semiconductor structure

Abstract

The semiconductor structure includes a transistor comprising a plurality of nanostructures on a substrate, a gate dielectric layer covering and situated on the nanostructures, and a gate on the gate dielectric layer, wherein a portion of the gate dielectric layer extending above the upper surface of the topmost nanostructure is thicker than a portion of the gate dielectric layer extending below the lower surface of the topmost nanostructure.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to semiconductor structures for adjusting the size of top channel components. Background Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (i.e., the number of interconnect devices per unit wafer area) typically increases as the geometry (i.e., the smallest component or circuit that the manufacturing process can produce) shrinks. Shrinking manufacturing processes generally facilitate increased production capacity and reduced associated costs.

[0003] Minimizing size also increases the complexity of processing and manufacturing integrated circuits. Integrated circuits comprise various circuit components such as transistors. Transistors with different configurations have different performance characteristics and are suitable for different circuit functions. While existing transistors and their fabrication methods are generally suitable for their intended purpose, they cannot meet all requirements. Utility Model Content

[0004] This utility model relates to a semiconductor structure. The semiconductor structure includes a transistor, which includes a plurality of nanostructures located on a substrate, a gate dielectric layer covering and located on the nanostructures, and a gate located on the gate dielectric layer, wherein a portion of the gate dielectric layer extending above the upper surface of the topmost nanostructure is thicker than a portion of the gate dielectric layer extending below the lower surface of the topmost nanostructure.

[0005] In some embodiments, the thickness of the topmost nanostructure of the plurality of nanostructures is less than the thickness of the bottommost nanostructure of the plurality of nanostructures, and the distance between the topmost nanostructure of the plurality of nanostructures and the nanostructure below the topmost nanostructure of the plurality of nanostructures is equal to the distance between the bottommost nanostructure of the plurality of nanostructures and the substrate.

[0006] In some embodiments, the width of the topmost nanostructure is smaller than the width of the bottommost nanostructure.

[0007] In some embodiments, the transistor is a p-type transistor, and the semiconductor structure further includes an n-type transistor, the n-type transistor including a plurality of other nanostructures located on the substrate, and the upper surface of the topmost nanostructure of the plurality of nanostructures being lower than the upper surface of the topmost nanostructure of the plurality of other nanostructures.

[0008] In some embodiments, the thickness of the topmost nanostructure of the plurality of nanostructures is less than the thickness of the topmost nanostructure of the plurality of other nanostructures.

[0009] In some embodiments, the width of the topmost nanostructure of the plurality of nanostructures is smaller than the width of the topmost nanostructure of the plurality of other nanostructures.

[0010] In some embodiments, the thickness of the topmost nanostructure of the plurality of other nanostructures is equal to the thickness of the bottommost nanostructure of the plurality of other nanostructures.

[0011] In some embodiments, the distance between the topmost nanostructure of the plurality of other nanostructures and a nanostructure below the topmost nanostructure of the plurality of other nanostructures is equal to the distance between the bottommost nanostructure of the plurality of other nanostructures and the substrate.

[0012] In some embodiments, the topmost nanostructure of the plurality of nanostructures has a rectangular shape with rounded corners.

[0013] In some embodiments, the topmost nanostructure of the plurality of nanostructures has a trapezoidal shape with rounded corners. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure in various embodiments of the present invention.

[0015] Figure 2 These are various embodiments of the present invention. Figure 1 A partial top view of the structure of the multiple stages in the method.

[0016] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 ,and Figure 21A These are various embodiments of the present invention. Figure 1 The structure in the multiple production stages of the method along Figure 2 The partial sectional view shown by section line A-A'.

[0017] Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19A , Figure 19B and Figure 20 These are various embodiments of the present invention. Figure 1The structure in the multiple production stages of the method along Figure 2 The partial sectional view shown by section line B-B'.

[0018] Figure 21B These are various embodiments of the present invention. Figure 1 The structure created by the method along Figure 2 The partial sectional view shown by section line C-C'.

[0019] Figure 22 This is a partial cross-sectional view of a first other structure in various embodiments of this utility model.

[0020] Figure 23A In various embodiments of this utility model, it contains Figure 1 An exemplary circuit diagram of the static random access memory cell structure fabricated using this method.

[0021] Figure 23B This is a partial layout diagram of a static random access memory cell in various embodiments of this utility model.

[0022] Figure 24A In various embodiments of this utility model, it contains Figure 1 The exemplary circuit diagram used to construct the NOR logic gate structure by the method described above.

[0023] Figure 24B This is a partial layout diagram of the NOR logic gate in various embodiments of this utility model.

[0024] Figure 25 In various embodiments of this utility model, the NOR logic gate along Figure 24B The partial sectional view shown by section line E-E'.

[0025] Figure 26 This is a partial cross-sectional view of a second other structure in various embodiments of this utility model.

[0026] Figure 27 In various embodiments of this utility model, it contains Figure 1 A simplified block diagram of a semiconductor structure (such as an integrated circuit package) fabricated using this method.

[0027] Figure 28 These are various embodiments of the present invention. Figure 27 A partial cross-sectional view of the semiconductor structure shown.

[0028] Figure 29 This is a partial cross-sectional view of a third other structure in various embodiments of this utility model.

[0029] List of reference numerals

[0030] A-A', B-B', C-C', D-D', E-E': hatching

[0031] BL: Bitline

[0032] BLB: Complementary Bit Line

[0033] IN1: First input signal

[0034] IN2: Second input signal

[0035] M1, M2: n-type field-effect transistors

[0036] M3, M4: p-type field-effect transistors

[0037] OUT: Output signal

[0038] PD-1, PD-2: Pull-down transistors

[0039] PG-1, PG-2: Through-gate transistors

[0040] PU-1, PU-2: Pull-up transistors

[0041] P1, P2: Vertical spacing

[0042] SNB1: Complementary First Storage Node

[0043] SN1: First storage node

[0044] S1, S2: Space

[0045] T0, T0', T1, T2, T2': Thickness

[0046] Vdd: Power supply voltage

[0047] Vss: Voltage

[0048] WL: Character Line

[0049] W1, W2, W2': Width

[0050] 100: Method

[0051] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128: Steps

[0052] 200, 300, 400, 500, 600, 700: Structure

[0053] 200A, 400A, 500A, 700A: First Device Area

[0054] 200B, 400B, 500B, 700B: Second Unit Area

[0055] 202: Substrate

[0056] 204: Isolation Structure

[0057] 205, 205a, 205b, 405a, 405b: Active Zone

[0058] 205C: Passage Area

[0059] 205SD: Source / Drain Region

[0060] 206: Sacrifice Layer

[0061] 207: Stacking

[0062] 208: Channel Layer

[0063] 208A, 208A1, 208A1', 208A2, 208A3, 208A4, 208B, 208B1, 208B1', 208B2, 208B3, 208B4: Channel Components

[0064] 208AS, 208BS, 208BS', 246s: Upper surface

[0065] 216: Dummy Gate Structure

[0066] 218: Gate spacer

[0067] 220: Source / Drain opening

[0068] 222: Space

[0069] 224: Virtual Layer

[0070] 226: Inner spacer structure

[0071] 228N, 228P: Source / Drain Structure

[0072] 230: Contact Etching Stop Layer

[0073] 232: Interlayer dielectric layer

[0074] 234: Gate trench

[0075] 236: Gate opening

[0076] 238: Gate dielectric layer

[0077] 240, 240a, 240a', 240a", 240b: Interface layer

[0078] 242: Dielectric layer with high dielectric constant

[0079] 244: Hard mask layer

[0080] 246: Protective layer

[0081] 248: Patterned photoresist layer

[0082] 250: Plasma processing

[0083] 254a, 254b: Gate

[0084] 256a, 256b, 310, 410: Metal gate structure

[0085] 260: Gate isolation structure

[0086] 305a: p-type fin

[0087] 305b: n-type fin

[0088] 600A: First box

[0089] 600B: Second box Detailed Implementation

[0090] The following detailed description, accompanied by accompanying drawings, will facilitate understanding of various aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be arbitrarily increased or decreased for clarity. It should also be emphasized that the drawings illustrate only general embodiments of this utility model and should not be considered as limiting the scope of the embodiments of this utility model, as the embodiments of this utility model are equally applicable to other embodiments.

[0091] The different embodiments or examples provided below can implement different structures of the present invention. The embodiments of specific components and arrangements are intended to simplify this disclosure and not to limit the present invention. For example, a description of forming a first component on a second component includes direct contact between the two, or the two being spaced apart by other additional components rather than in direct contact. Various embodiments of the present invention may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0092] In addition, spatial relative terms such as “below,” “lower,” “above,” “higher,” or similar terms are used to describe the relationship between some elements or structures in a diagram and another element or structure. These spatial relative terms include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned in a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used will also be interpreted according to the orientation after the turn.

[0093] Furthermore, when the description of a numerical value or range uses terms such as "about," "approximately," or similar expressions, it is intended to cover values ​​within a reasonable range, such as inherent variations arising during the manufacturing process, as considered by those skilled in the art. For example, based on known manufacturing tolerances related to the numerical value, the numerical value or range covers a reasonable range including the stated number, for example, within + / - 10% of the stated number. For example, when the thickness of the material layer is about 5 nm and the manufacturing tolerance for deposited material layers is known to those skilled in the art at 15%, the included size range is 4.25 nm to 5.75 nm. Furthermore, the same reference numerals may be used repeatedly in various embodiments of this invention for brevity, but elements with the same reference numerals in various embodiments and / or settings do not necessarily have the same correspondence. To avoid ambiguity, the X, Y, and Z directions in the figures are perpendicular to each other and aligned. In the following description, similar reference numerals are used to indicate similar structures unless otherwise stated.

[0094] N-type transistors, such as N-type field-effect transistors (FETs), consist of a pair of N-type doped source / drain structures, with electrons as the primary carriers. P-type transistors, such as P-type FETs, consist of a pair of P-type doped source / drain structures, with holes as the primary carriers. For N-type and P-type FETs with the same configuration (e.g., effective channel width, effective channel thickness, gate length), the performance of the P-type FET is superior to that of the N-type FET. Many efforts have been made in this field to balance the performance of N-type and P-type FETs. For example, one method is to adjust the threshold voltage of the N-type and P-type FETs. However, adjusting the threshold voltage may affect switching characteristics such as turn-on and / or turn-off operation or noise tolerance. Another method is to reduce the channel width of the P-type FET or increase the channel width of the N-type FET, so that the performance of the N-type FET can be comparable to that of the P-type FET. However, shrinking p-type field-effect transistors may increase manufacturing complexity, while enlarging n-type field-effect transistors may disadvantageously increase the number of pins.

[0095] In this embodiment of the invention, the n-type field-effect transistor (FET) and the p-type FET are fully wound gate transistors, each having multiple channel components as channels, and a gate structure covering the channel components. The transistors (n-type FETs and / or p-type FETs) in this embodiment may include partially oxidized topmost components to reduce parasitic capacitance. Reducing parasitic capacitance reduces resistance-capacitance delay and leakage current, thus reducing power consumption or increasing speed. In some embodiments, the channel components of the n-type and p-type FETs can be processed to provide the desired performance without adjusting the threshold voltage or channel width. For example, to balance the performance of the n-type and p-type FETs, the topmost channel component of the p-type FET may be at least partially oxidized. In some other suitable applications, the concept of partially oxidizing the topmost channel component to reduce parasitic capacitance can also be implemented in the n-type FET. Therefore, this embodiment of the invention can improve the performance of transistors and various circuits and chips containing transistors.

[0096] Various embodiments of this utility model will be further described in detail with reference to the accompanying drawings. In this regard... Figure 1 This is a flowchart of a method 100 for forming a semiconductor structure 200 according to an embodiment of the present invention. Method 100 will be combined with... Figures 2 to 21B The following diagrams are partial cross-sectional or top views of the structure of the embodiment at different manufacturing stages of method 100. Figures 22 to 29 These are other embodiments of this utility model.

[0097] like Figure 1 , Figure 2 ,and Figure 3 As shown, step 102 of method 100 receives structure 200. Figure 3 It is structure 200 along Figure 2 Partial sectional view along section line A-A' shown. Structure 200 along... Figure 2 The partial sectional view shown by section line C-C' is similar to... Figure 3 Similarly, this cross-sectional view can be omitted for simplicity. In this embodiment, structure 200 includes a first device region 200A for forming an n-type device (such as an n-type fully wound gate transistor) and a second device region 200B for forming a p-type device (such as a p-type fully wound gate transistor). Structure 200 includes a substrate 202 (such as...). Figure 3(As shown). In one embodiment, substrate 202 is a substrate silicon (i.e., including substrate single-crystal silicon). In various embodiments, substrate 202 may include other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide, gallium arsenide phosphide, or combinations thereof. In some other embodiments, substrate 202 may be a semiconductor-on-insulator substrate such as a silicon-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate, and may include a carrier, an insulating layer on the carrier, and a semiconductor layer on the insulating layer. Substrate 202 may include various doped regions provided according to the design requirements of semiconductor structure 200. p-type doped regions may include p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. n-type doped regions may include n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof. In some embodiments, substrate 202 includes doped regions formed by a combination of p-type and n-type dopants. For example, various doped regions can be directly formed on and / or within the substrate 202 to provide p-type well structures, n-type well structures, dual-well structures, raised structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form various doped regions.

[0098] Structure 200 also includes multiple active regions (such as active regions 205a and 205b) protruding from substrate 202. In these embodiments, active region 205a is formed in the first device region 200A of substrate 200 (e.g., Figure 2 As shown, the active region 205b is formed in the second device region 200B of the substrate 200. Active regions 205a and 205b can be considered as active regions 205 individually or together. Each active region 205 extends along the X-direction and is divided into a channel region 205C and a source / drain region 205SD. The source / drain regions can be considered as source regions or drain regions individually or together, depending on the context.

[0099] The active region 205 can be formed by the top of the substrate 202 and the vertical stacking 207 of interleaved semiconductor layers such as sacrificial layer 206 and channel layer 208 (e.g. Figure 3The process is as shown, and the formation method can employ a combination of photolithography and etching steps. In the embodiment described, the vertical stacking 207 of staggered semiconductor layers such as sacrificial layers 206 and channel layers 208 includes a plurality of staggered sacrificial layers 206 and a plurality of channel layers 208. Each channel layer 208 may comprise a semiconductor material such as silicon, germanium, silicon carbide, silicon-germanium, germanium-tin, silicon-germanium-tin, silicon-carbide-germanium-tin, other suitable semiconductor materials, or combinations thereof. Furthermore, the composition of each sacrificial layer 206 differs from the composition of the channel layers 208. In one embodiment, the channel layer 208 comprises silicon, and the sacrificial layer 206 comprises silicon-germanium. The channel layers 208 and sacrificial layers 206 can be epitaxially deposited on the substrate 202, and the deposition method can employ molecular beam epitaxy, vapor phase epitaxy, ultra-high vacuum chemical vapor deposition, and / or other suitable epitaxial growth processes. In this example, the active region 205 includes four staggered sacrificial layers 206 and four channel layers 208. In some other examples, the active area 205 may each include a total of three to ten pairs of staggered sacrificial layers 206 and channel layers 208, but other configurations may be implemented according to specific design requirements.

[0100] The substrate 202 also includes an isolation structure 204 (such as...) Figure 11 The isolation structure 204 (as shown) is formed on substrate 202 to isolate two adjacent active regions 205. The isolation structure 204 may include a shallow trench isolation structure, and therefore can also be considered as a shallow trench isolation structure. In some embodiments, the shallow trench isolation structure 204 may include silicon oxide, silicon oxynitride, fluorosilicate glass, a dielectric material with a low dielectric constant, a combination of the above, and / or other suitable materials. In some embodiments, the upper surface of the shallow trench isolation structure 204 is lower than the upper surface of the top of substrate 202. The upper surface of the shallow trench isolation structure 204 may be an arcuate (e.g., concave) surface, with its lowest point near the center.

[0101] like Figure 2 and Figure 3 As shown, structure 200 also includes a dummy gate structure 216 formed on the channel region 205C of the active region 205. The channel region 205C and the dummy gate structure 216 also define source / drain regions 205SD, which do not vertically overlap with the dummy gate structure 216. Each channel region 205C is located between the two source / drain regions 205SD along the X direction. Figure 2 Two dummy gate structures 216 are shown, but structure 200 may include other numbers of dummy gate structures. In this embodiment, a gate replacement process (or post-gate process) is used, wherein the dummy gate structures 216 serve as functional gate structures (e.g., Figure 20The placeholders used in the metal gate structures 256a and 256b shown are illustrated. Other processes used to form the functional gate structures are also possible. In these embodiments (although not shown), each of the dummy gate structures 216 includes a dummy gate dielectric layer (such as silicon oxide) and a dummy gate (such as polysilicon) located on the dummy gate dielectric layer. Structure 200 also includes gate spacers 218 extending along the sidewalls of the dummy gate structures 216. In some embodiments, the gate spacers 218 may include silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. The gate spacers 218 may be a single-layer structure or a multilayer structure.

[0102] like Figure 1 and Figure 4 As shown, step 104 of method 100 causes the source / drain region 205SD of the active region 205 to be recessed to form a source / drain opening 220. Figure 4 Display structure 200 along Figure 2 Partial sectional view along section line A-A' shown. Structure 200 along... Figure 2 The partial sectional view shown by section line C-C' is similar to Figure 4 Therefore, the details are omitted for simplicity. In some embodiments, the source / drain regions 205SD of the active region 205 not covered by the dummy gate structure 216 and gate spacer 218 are anisotropically etched using dry etching or a suitable etching process to form source / drain openings 220. Exemplary dry etching processes may employ oxygen-containing gases, hydrogen-containing gases, fluorine-containing gases (such as carbon tetrafluoride, sulfur hexafluoride, difluoromethane, fluoroform, and / or hexafluoroethane), chlorine-containing gases (such as chlorine, chloroform, carbon tetrachloride, and / or boron trichloride), bromine-containing gases (such as hydrogen bromide and / or bromoform), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. The source / drain openings 220 extend through the stack 207 of the channel layer 208 and the sacrificial layer 206 and extend into the substrate 202. Figure 4 As shown, the sidewalls of the channel layer 208 and the sacrificial layer 206 are exposed in the source / drain opening 220.

[0103] like Figure 1 , Figure 5 ,and Figure 6 As shown, in step 106 of method 100, the sacrificial layer 206 is replaced with a dummy layer 224. Figure 5 and Figure 6 It is structure 200 along Figure 2 Partial sectional view along section line A-A' shown. Structure 200 along... Figure 2 The partial sectional view shown is... Figure 4 and Figure 5 Similarly, it is omitted to simplify the content. For example... Figure 5As shown, after forming the source / drain opening 220, the sacrificial layer 206 interspersed with the channel layer 208 in the channel region 205C is selectively removed. Selective removal of the sacrificial layer 206 can release the channel layer 208 to form a channel assembly (channel release process). Depending on the design, the channel layer 208 can be in the form of nanowires, nanosheets, or other nanostructures. Selective removal of the sacrificial layer 206 can form spaces 222 between and around adjacent channel layers 208. The method for selectively removing the sacrificial layer 206 can be selective dry etching, selective wet etching, or other selective etching processes. Examples of selective dry etching processes may include using one or more fluorine-based etchants such as fluorine gas or hydrocarbons. Examples of selective wet etching processes may include mixtures of ammonia peroxide, hydrogen peroxide, and water.

[0104] like Figure 6 As shown, after selectively removing the sacrificial layer 206, an example of the process may be to deposit a dielectric material layer around the channel layer 208 and over the source / drain openings 220. The dielectric material layer fills the space 222 between the channel layers 208 and covers the end sidewalls of the channel layers 208. After depositing the dielectric material layer, an etching process is performed to selectively etch the dielectric material layer, thereby forming a dummy layer 224 interleaved with the channel layers 208. The dummy layer 224 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, a high dielectric constant dielectric material (such as alumina or hafnium oxide), other suitable materials, or combinations thereof, and its deposition method may employ plasma-assisted chemical vapor deposition, atomic layer deposition, or other suitable methods. In one embodiment, the dummy layer 224 includes silicon oxide.

[0105] like Figure 1 and Figure 7As shown, step 108 of method 100 forms the inner spacer structure 226. After forming the dummy layer 224, an etching process is performed to selectively recess the dummy layer 224 to form the inner spacer recess (currently filled with the inner spacer structure 226). The etching process selectively recesses a portion of the dummy layer 224 to form the inner spacer recess without significantly etching the exposed channel layer 208. In embodiments where the channel layer 208 is substantially composed of silicon and the dummy layer 224 is composed of silicon oxide, the method of selectively recessing the dummy layer 224 can employ a selective wet etching process or a selective dry etching process. The amount of recess in the dummy layer 224 can be controlled by the time of the etching process. In other embodiments, the steps of etching back the dielectric material layer to form the dummy layer 224 and selectively recessing a portion of the dummy layer 224 are the same etching process. The inner spacer structure 226 is then formed in the inner spacer recess. In this example of the process, after forming the inner spacer recess, an inner spacer material layer (not shown) can be deposited on structure 200, including deposition within the inner spacer recess. The deposited inner spacer material layer is then etched back to remove excess inner spacer material, forming inner spacer structure 226. The etch-back process in step 108 can be a dry etching process, similar to the dry etching process used to form the source / drain openings 220. The inner spacer structure 226 continues the shape of the corresponding inner spacer recess. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material.

[0106] like Figure 1 and Figure 8 As shown, step 110 of method 100 forms a source / drain structure (such as source / drain structures 228N and 228P) adjacent to the channel region 205C. The source / drain structure is formed in and / or on the source / drain region 205SD and coupled to the channel layer 208 in the channel region 205C. In these embodiments, the n-type source / drain structure 228N is formed in the first device region 200A, while the p-type source / drain structure 228P (such as source / drain structures 228N and 228P) is formed in the channel region 205C. Figure 21BThe n-type source / drain structure 228N (shown) is formed in the second device region 200B. An exemplary n-type source / drain structure 228N may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped by introducing n-type dopants such as phosphorus, arsenic, or antimony during epitaxial processing, or out-of-situ doped using a junction implantation process. An exemplary p-type source / drain structure 228P may include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and may be in-situ doped by introducing p-type dopants such as boron or gallium during epitaxial processing, or out-of-situ doped using a junction implantation process. In various embodiments, the upper surface of the source / drain structures 228N and / or 228P may be an uneven or arcuate surface, and the arcuate surface may be curved inward or outward (e.g., concave or convex). In some embodiments, the upper surfaces of the source / drain structures 228N and / or 228P are not coplanar with the upper surface of the topmost channel layer 208 of the channel layer 208.

[0107] like Figure 1 and Figures 9 to 11 As shown, in step 112 of method 100, the dummy gate structure 216 is selectively removed to form a gate trench 234, and the dummy layer 224 is selectively removed to form a gate opening 236. Figure 9 As shown, after forming the source / drain structures 228N and 228P, a contact etch stop layer 230 and an interlayer dielectric layer 232 can be formed on the structure 200. The contact etch stop layer 230 is configured to protect various underlying components during subsequent fabrication processes and may include silicon nitride, silicon oxynitride, and / or other suitable materials. Its formation method may be atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, and / or other suitable deposition or oxidation processes. Figure 9 As shown, a contact etch stop layer 230 can be formed on the upper surface of the source / drain structure (such as an n-type source / drain structure 228N) and on the sidewalls of the gate spacer 218. After depositing the contact etch stop layer 230, an interlayer dielectric layer 232 can be deposited on the structure 200 by chemical vapor deposition, plasma-assisted chemical vapor deposition, or other suitable deposition techniques. The interlayer dielectric layer 232 may include silicon oxide, a low dielectric constant dielectric material, an oxide of tetraethoxysilane, doped silicon oxide (such as borosilicate glass, fluorosilicate glass, phosphosilicate glass, borosilicate glass, or the like), other suitable dielectric materials, or combinations thereof. One or more chemical mechanical polishing processes can be performed to planarize the upper surface of the structure 200 and expose the dummy gate of the dummy gate structure 216.

[0108] like Figure 10As shown, dummy gate structure 216 is selectively removed to form gate trench 234 on channel region 205C. The etching process used for selectively removing dummy gate structure 216 may include any suitable process, such as dry etching, wet etching, or a combination thereof. After removing dummy gate structure 216, dummy layer 224 may be selectively removed to form gate opening 236. The method for selectively removing dummy layer 224 may be selective dry etching, selective wet etching, or other selective etching processes. Examples of selective wet etching processes may use diluted hydrofluoric acid, or a mixture of hydrofluoric acid and ammonium fluoride. Examples of selective dry etching processes may use anhydrous hydrofluoric acid vapor, trifluoromethane, nitrogen trifluoride, hydrogen, ammonia, carbon tetrafluoride, sulfur hexafluoride, or a combination thereof. In some embodiments, selective wet etching uses a mixture of ammonia peroxide, hydrogen peroxide, and water.

[0109] Figure 11 Display structure 200 along Figure 2 and Figure 10The diagram shows a cross-sectional view along section B-B'. For ease of explanation, the channel layer 208 in the first device region 200A is considered as channel assembly 208A, and the channel layer 208 in the second device region 200B is considered as channel assembly 208B. More specifically, in this example, channel assembly 208A includes a topmost channel assembly 208A1, a first intermediate channel assembly 208A2 below the topmost channel assembly 208A1, a second intermediate channel assembly 208A3 below the first intermediate channel assembly 208A2, and a bottommost channel assembly 208A4. Channel assemblies 208A1, 208A2, 208A3, and 208A4 can be considered as channel assembly 208A individually or together. Channel assemblies 208B1, 208B2, 208B3, and 208B4 can be considered as channel assembly 208B individually or together. In some embodiments, channel assembly 208A and channel assembly 208B may have the same dimensional configuration. For example, the width W1 of channel component 208A is substantially equal to the width W2 of channel component 208B, and the thickness T1 of channel component 208A is substantially equal to the thickness T2 of channel component 208B. The vertical spacing P1 of channel component 208A (such as center-to-center spacing or edge-to-edge spacing) is substantially equal to the vertical spacing P2 of channel component 208B. Two adjacent layers of channel component 208A may be separated by a space S1, and two adjacent layers of channel component 208B may be separated by a space S2, and space S2 may be substantially equal to space S1. The upper surface 208AS of the topmost channel component 208A1 and the upper surface 208BS of the topmost channel component 208B1 are substantially coplanar. In some other embodiments, the channel component 208A in the first device region 200A and the channel component 208B in the second device region 200B may have the same spacing (i.e., vertical spacing P1 = vertical spacing P2), the same space (i.e., space S1 = space S2), and the same thickness (i.e., thickness T1 = thickness T2), but different widths (i.e., width W1 is different from width W2) to further flexibly adjust the performance of p-type transistors and n-type transistors.

[0110] like Figure 1 and Figure 12 As shown, step 114 of method 100 forms a gate dielectric layer 238 on structure 200, including a gate trench 234 and a gate opening 236. In some embodiments, the gate dielectric layer 238 is a multilayer structure, including an interface layer 240 and a high-dielectric-constant dielectric layer 242 located on the interface layer 240. In this embodiment, the interface layer 240 is formed by thermal oxidation and may include silicon oxide. That is, the interface layer 240 is formed only along the exposed surfaces of the semiconductor structure (such as the top of the substrate 202 and the channel components 208A and 208B). The interface layer 240 may have a generally uniform thickness T0. Figure 22In some of the embodiments shown, the interface layer 240 may be compliantly deposited on the substrate 202, including deposited in the gate trench 234 and the gate opening 236 and on the shallow trench isolation structure 204, and the deposition process may be atomic layer deposition or chemical vapor deposition.

[0111] Next, a deposition process such as chemical vapor deposition or atomic layer deposition is performed to compliantly deposit a high-dielectric-constant dielectric layer 242 on structure 200, the thickness of which is substantially uniform on the upper surface of structure 200 to fill the gate trench 234 and gate opening 236. The term "compliant" is used herein for convenience in describing a layer with substantially uniform thickness in various regions. The high-dielectric-constant dielectric layer 242 may comprise a high-dielectric-constant dielectric material, the dielectric constant of which may be greater than that of silicon oxide. Exemplary high-dielectric-constant dielectric materials include hafnium, zirconium, tantalum, titanium, oxygen, nitrogen, other suitable compositions, or combinations thereof. In some embodiments, the high dielectric constant dielectric layer 242 may include a high dielectric constant dielectric material such as hafnium oxide, hafnium silicon oxide, hafnium oxysilicon, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, other suitable high dielectric constant dielectric materials, or combinations thereof.

[0112] like Figure 1 and Figure 13 As shown, step 116 of method 100 compliantly forms a hard mask layer 244 on substrate 202. The hard mask layer 244 is compliantly deposited on substrate 202 and has a substantially uniform thickness on the upper surface of structure 200. The hard mask layer 244 can be formed using any process described herein, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, other suitable processes, or combinations thereof. The thickness of the hard mask layer 244 is set to fill any remaining portion of the gate opening 236 between adjacent channel layers 208 in the first device region 200A and the second device region 200B. In these embodiments, the gate opening 236 is substantially filled after the hard mask layer 244 is deposited, while the gate trench 234 remains partially filled. The material comprising the hard mask layer 244 allows for high etch selectivity between the hard mask layer 244 and the high-dielectric-constant dielectric layer 242 during the etching process. For example, the etching process may selectively etch the hard mask layer 244 while minimizing or omitting the high-dielectric-constant dielectric layer 242, and the etching process may be a dry etching process or a wet etching process. In some embodiments, the etching selectivity is greater than or equal to 10:1. In other words, the etching process etches the hard mask layer 244 at a rate at least 10 times greater than the rate at which the high-dielectric-constant dielectric layer 242 is etched. In some embodiments, the hard mask layer 244 comprises alumina, silicon oxide, silicon nitride, lanthanum oxide, silicon (such as polysilicon), silicon carbonitride, silicon carbonitride, aluminum nitride, aluminum oxynitride, combinations thereof, or other suitable materials.

[0113] like Figure 1 and Figure 14 As shown, step 118 of method 100 forms a protective layer 246 on the substrate 202. In one embodiment, the protective layer 246 includes a base anti-reflective coating material, which provides a platform for coating and patterning photoresist. In one embodiment, the protective layer 246 is formed by spin-coating the base anti-reflective coating material onto the substrate 202 and into the gate trench 234, and baking the base anti-reflective coating material to crosslink it. The upper surface of the protective layer 246 is higher than the upper surface of the hard mask layer 244.

[0114] like Figure 1 , Figure 15 ,and Figure 16 As shown, step 120 of method 100 causes a portion of the protective layer 246 in the second device region 200B to be recessed. As... Figure 15 As shown, after the protective layer 246 is formed, a patterned photoresist layer 248 can be formed on the protective layer 246. In one example of the process, a photoresist layer can be deposited on the structure 200 in a blanket manner, including the protective layer 246 deposited in the first device region 200A and the second device region 200B. The photoresist layer is then exposed to rays passing through or reflected from the photomask, followed by a baking process to bake the photoresist layer and developing it with a developing solution to form the patterned photoresist layer 248, as shown. Figure 15 As shown. In the embodiment, a patterned photoresist layer 248 is formed in the first device region 200A and the second device region 200B.

[0115] like Figure 16 As shown, an etching process is performed to recess the protective layer 246, and a patterned photoresist layer 248 is used as an etching mask. The etching process may include an isotropic etching process or anisotropic etching process, and may be dry etching. In some embodiments, the amount of recess in the protective layer 246 may be controlled by the time of the etching process. After recessing the protective layer 246 in the second device region 200B, the patterned photoresist layer 248 may be selectively removed. In some examples, the patterned photoresist layer 248 may be removed during the etching process that recesses the protective layer 246.

[0116] exist Figure 16In the illustrated embodiment, the recessed protective layer 246 in the second device region 200B has an upper surface 246s. The height of the upper surface 246s may be between the upper surface 208BS of the topmost channel assembly 208B1 and the upper surface 208BS' of the first intermediate channel assembly 208B2, to facilitate processing of the topmost channel assembly 208B1 of the channel assembly 208B in the second device region 200B. That is, the upper surface 246s may be coplanar with the upper surface 208BS, lower than the upper surface 208BS and higher than the upper surface 208BS', or coplanar with the upper surface 208BS', so that the process of processing the topmost channel layer 208B1 does not substantially affect the channel assembly (such as the first intermediate channel assembly 208B2) directly below the topmost channel assembly 208B1. In this embodiment, the upper surface 246s may be coplanar with the lower surface of the topmost channel assembly 208B1 of the channel assembly 208B in the second device region 200B.

[0117] like Figure 1 and Figure 16 As shown, in step 122 of method 100, an etching process is performed to selectively remove a portion of the hard mask layer 244 exposed by the recessed protective layer 246. After the protective layer 246 is recessed, the recessed protective layer 246 is used as an etching mask, and an etching process is performed to selectively etch away portions of the hard mask layer 244 not covered by the recessed protective layer 246, thereby exposing a portion of the gate dielectric layer 238 (such as a high-dielectric-constant dielectric layer 242) in the second device region 200B that contacts the topmost channel assembly 208B1. The etching process can be a dry etching process, a wet etching process, or a suitable etching process.

[0118] like Figure 1 , Figure 17 ,and Figure 18 As shown, step 124 of method 100 partially oxidizes the topmost channel assembly 208B1 in the second device region 200B. Figure 18 Enlarged views of portions of structure 200 (such as topmost channel components 208A1 and 208B1 and first intermediate channel components 208A2 and 208B2). After exposing the gate dielectric layer 238 (such as a high-dielectric-constant dielectric layer 242) in the second device region 200B, a directional (e.g., anisotropic) plasma processing step 250 can be performed to oxidize at least a portion of the topmost channel component 208B1 from top to bottom, thereby increasing the thickness of portions of the interface layer 240 adjacent to and above the topmost channel component 208B1. In some embodiments, the directional plasma processing step 250 may employ a combination of nitrogen plasma and oxygen plasma.

[0119] After performing a directional plasma treatment process 250, for ease of explanation, the thickness (e.g.) Figure 18 The portion of interface layer 240 with increased thickness (T0') shown can be considered interface layer 240a, while the portion of interface layer 240 with substantially unchanged thickness (such as thickness T0) can be considered interface layer 240b. For example, the portion of interface layer 240 located below the topmost channel component 208B1 in the second device region 200B, and the portion of interface layer 240 located in the first device region 200A and protected by the hard mask layer 244, is not thickened, and these portions are considered interface layer 240b. Therefore, the interface layers in the second device region 200B have inconsistent thicknesses (such as thickness T0 or T0'). In one embodiment, the ratio of thickness T0' to thickness T0 can be greater than about 1.5. If the ratio is less than 1.5, the amount of oxidation of the topmost channel component 208B1 may be insufficient to adjust the transistor performance in the second device region 200B. In some embodiments, after a directional plasma processing 250, the composition of the topmost channel assembly 208B1 differs from that of the other channel assemblies (such as channel assemblies 208A1 to 208A4 and channel assemblies 208B2 to 208B4). For example, the oxygen concentration of the topmost channel assembly 208B1 is greater than that of the other channel assemblies (such as channel assemblies 208A1 to 208A4 and channel assemblies 208B2 to 208B4). The partially oxidized topmost channel assembly 208B1 can be considered as the topmost channel assembly 208B1'. Due to partial oxidation, the current thickness T2' of the topmost channel assembly 208B1' is less than the thickness T2. In one embodiment, the ratio of thickness T2' to thickness T2 is less than 0.8, which can adjust the transistor performance in the second device region 200B. The current width W2' of the topmost channel assembly 208B1' is less than the width W2. In one embodiment, the width W1 is equal to the width W2 and greater than the width W2'. In another embodiment, width W1 is greater than width W2 and width W2'. In some other embodiments, width W1 is less than width W2 and may be less than, equal to, or greater than width W2'. In one example, width W2 is between about 3 nm and about 6 nm, and width W2' is between about 0 and about 4 nm. Due to the oxidation of the topmost channel component 208B1' from top to bottom, the upper surface 208BS of the topmost channel component 208B1' is currently lower than the upper surface 208AS of the topmost channel component 208A1, while the lower surface of the topmost channel component 208B1' remains coplanar with the lower surface of the topmost channel component 208A1. Although the space S2 between the topmost channel component 208B1' and the first intermediate channel component 208B2 remains unchanged, the distance between the upper surface 208BS of the topmost channel component 208B1' and the first intermediate channel component 208B2, such as the vertical spacing P2, is reduced. This is because the vertical spacing of the channel components 208B is currently inconsistent.

[0120] Figure 19A and Figure 19BEach is a partial cross-sectional view of the channel assembly 208B in the second device area 200B. Figure 19A and Figure 19B The channel component 208B shown is similar to Figure 18 One difference between the channel component 208B shown is its different outline. More specifically, Figure 18 The topmost channel component 208B1' shown can resemble a rectangle with rounded corners, while Figure 19A The topmost channel assembly 208B1' shown can resemble a trapezoid with rounded corners. The profile can be related to various parameters of the plasma processing 250, to crystal planes, or to different channel widths. In the embodiment described, a portion of the interface layer 240a formed on the upper surface 208BS of the topmost channel assembly 208B1' can have a uniform thickness, while portions of the interface layer 240a laterally adjacent to the topmost channel assembly 208B1' can have inconsistent thicknesses that gradually increase from bottom to top. In the above embodiment, the channel assembly 208B prior to the plasma processing 250 can resemble a rectangle with rounded corners. Figure 19B In the illustrated embodiment, the channel assembly 208B prior to the plasma processing step 250 may resemble a spherical column. This profile may result from the release of the channel layer 208 as another mechanism of the channel assembly (excluding the mechanism for forming the dummy layer 224). Figure 19A and Figure 19B The size settings of the channel component 208B in the middle and Figure 18 The dimensions of the channel component 208B are substantially the same, and will not be repeated here for the sake of simplicity.

[0121] like Figure 1 and Figure 20 As shown, step 126 of method 100 selectively removes the hard mask layer 244 and the recessed protective layer 246. After plasma processing 250, one or more etching processes may be performed to selectively remove the protective layer 246 and the hard mask layer 244 without substantially etching the high-dielectric-constant dielectric layer 242. In some embodiments, the protective layer 246 may be slightly etched during plasma processing 250.

[0122] like Figure 1 , Figure 20 , Figure 21A ,and Figure 21BAs shown, step 128 of method 100 involves subsequent processes. These subsequent processes may include forming a gate 254a on a gate dielectric layer 238 in a first device region 200A and forming a gate 254b on a gate dielectric layer 238 in a second device region 200B to form metal gate structures 256a and 256b. Gates 254a and 254b may be multilayer structures, including at least one work function layer and a metal fill layer. For example, the at least one work function layer may include titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, or tantalum carbide. The gate 254a formed in the first device region 200A may include at least one n-type work function layer. The n-type work function layer may include a titanium aluminum-based metal such as titanium aluminum carbide or titanium aluminum. The gate 254b formed in the second device region 200B may include at least one p-type work function layer. The p-type work function layer may include titanium nitride, tungsten carbonitride, tantalum nitride, or molybdenum nitride. Gates 254a and 254b may also include metal filler materials such as aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, silicon tantalum nitride, copper, other refractory metals, other suitable metallic materials, or combinations thereof. In various embodiments, gates 254a and 254b are formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, planarization processes such as chemical mechanical polishing may be performed to remove excess material on the interlayer dielectric layer 232 to provide a substantially flat upper surface, which facilitates subsequent processes. Figure 21A Show a cross-sectional view of structure 200 along section line A-A' (e.g., first device area 200A), while Figure 21B Show a cross-sectional view of structure 200 along section line C-C' (e.g., second device area 200B). Figure 21B As shown, the interface layer 240b formed on the topmost channel assembly 208B1' is thicker than the interface layer 240a. Partial oxidation causes the topmost channel assembly 208B1' to have inconsistent thickness in the cross-sectional view along the X direction, such as... Figure 21B As shown.

[0123] Figure 22Other embodiments of the present invention are shown. In these other embodiments, a gate isolation structure 260 is formed to provide isolation between metal gate structures 256a and 256b. The gate isolation structure 260 may be formed before or after the metal gate structures 256a and 256b are formed. In the embodiments described, the gate isolation structure 260 extends into the shallow trench isolation structure 204. In other embodiments, the gate isolation structure 260 may terminate on the shallow trench isolation structure 204. The gate isolation structure 260 may be composed of any suitable dielectric material and may be a single-layer or multi-layer structure. In the above embodiments, the interface layer 240 is initially formed by thermal oxidation. In other embodiments, the interface layer 240 may be compliantly deposited over the entire structure 200, including deposition on the shallow trench isolation structure 204. Figure 22 As shown, after plasma processing 250, a portion of the interface layer 240b is located on the shallow trench isolation structure 204.

[0124] Method 100 can also be used to form integrated circuit structures with improved performance, such as those that increase speed, reduce power consumption, or reduce the performance difference between n-type and p-type field-effect transistors. Figure 23A and Figure 23B As shown, the integrated circuit structure includes at least one array of memory cells. The array may include static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, non-volatile random access memory (NRAM) cells, flash memory cells, other suitable memory cells, or combinations thereof. In one embodiment, the array includes several SRAM cells such as structure 300, which are typically capable of storing or storing reserved data when powered on. In these embodiments, each SRAM cell such as structure 300 includes one or more of the aforementioned fully wound gate transistors.

[0125] Figure 23AThis is an exemplary circuit diagram of a single-ended static random access memory (SRAM) cell, such as structure 300 (e.g., a 1-bit SRAM cell). The single-ended SRAM cell, such as structure 300, includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and bypass transistors PG-1 and PG-2. As shown in the circuit diagram, pull-up transistors PU-1 and PU-2 are p-type transistors, while bypass transistors PG-1 and PG-2 and pull-down transistors PD-1 and PD-2 are n-type transistors. The drains of pull-up transistors PU-1 and PD-1 are coupled together, and the drains of pull-up transistors PU-2 and PD-2 are coupled together. Pull-up transistors PU-1 and PD-1 are cross-coupled to pull-up transistors PU-2 and PD-2 to form a first data latch. The gates of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled together and to the drains of pull-up transistor PU-1 and pull-down transistor PD-1 to form a first storage node SN1. The gates of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled together and to the drains of pull-up transistor PU-2 and pull-down transistor PD-2 to form a complementary first storage node SNB1. The sources of pull-up transistors PU-1 and PU-2 are coupled to the power supply voltage Vdd, while the sources of pull-down transistors PD-1 and PD-2 are coupled to the voltage Vss. In some embodiments, the voltage Vss may be electrically grounded. The first data latch-up first storage node SN1 is coupled to the bit line BL via a through-gate transistor PG-1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB via a through-gate transistor PG-2. The first storage node SN1 and the complementary first storage node SNB1 are complementary nodes, typically representing opposite logic bits (logic high or logic low). The gates of the through-gate transistors PG-1 and PG-2 are coupled to the word line WL.

[0126] Figure 23BThis diagram shows a partial layout of a static random access memory (SRAM) cell, such as structure 300. The SRAM cell 300 includes p-type three-dimensional finned active regions, such as p-type fins 305a, each located within a p-type doped region, and n-type three-dimensional finned active regions, such as n-type fins 305b, each located within an n-type doped region. The p-type fins 305a after the channel release process can be similar to the active region 205a, and the n-type fins 305b after the channel release process can be similar to the active region 205b. The SRAM cell, such as structure 300, includes a metal gate structure 310 similar to metal gate structures 256a and / or 256b, with its length direction along the X direction and located on the p-type fins 305a and / or n-type fins 305b, to form various transistors, including pull-down transistors PD-1 and PD-2, pull-up transistors PU-1 and PU-2, and bypass transistors PG-1 and PG-2. Static random access memory cells, such as structure 300, are along... Figure 23B The sectional view shown by section line D-D' can be compared with... Figure 20 The structure 200 shown is essentially the same. By forming pull-up transistors PU-1 and PU-2 with partially oxidized topmost channel components 208B1', the performance difference between n-type fully wound gate transistors and p-type fully wound gate transistors can be reduced. In addition, the parasitic capacitance of static random access memory cells such as structure 300 can be reduced, and the performance balance between static random access memory cells such as structure 300 and integrated circuit structure can be improved.

[0127] In the above embodiment, the topmost channel component 208B1 in the second device region 200B used for p-type transistors is partially oxidized. In some other embodiments, the topmost channel component 208A1 in the first device region 200A used for n-type transistors is partially oxidized to improve the performance of other integrated circuit structures. For example, such as Figure 24A , Figure 24B ,and Figure 25 In another application shown, the integrated circuit structure includes at least one array of standard logic cells to provide a variety of standard logic devices such as inverters, AND, NAND, OR, XOR, NOR, other suitable devices, or combinations thereof. In the embodiment shown, the standard logic cell includes several NOR logic gates, the n-type transistors of which have a partially oxidized topmost channel component 208A1 in a first device region 200A.

[0128] Figure 24AThis diagram illustrates an exemplary circuit of a NOR logic gate, such as structure 400. The NOR logic gate, such as structure 400, includes two n-type field-effect transistors (e.g., n-type field-effect transistors M1 and M2) and two p-type field-effect transistors (e.g., p-type field-effect transistors M3 and M4). The two n-type field-effect transistors (e.g., n-type field-effect transistors M1 and M2) are connected in parallel, while the two p-type field-effect transistors (e.g., p-type field-effect transistors M3 and M4) are connected in series and connected in series with the two n-type field-effect transistors to form the NOR logic gate, such as structure 400. Figure 24A As shown. n-type field-effect transistor M1 and p-type field-effect transistor M4 are configured to receive the first input signal IN1, while n-type field-effect transistor M2 and p-type field-effect transistor M3 are configured to receive the second input signal IN2. The NOR logic gate, as shown in structure 400, provides an output signal OUT in response to the first input signal IN1 and the second input signal IN2.

[0129] Figure 24B This diagram shows a partial layout of a NOR logic gate, such as structure 400. The NOR logic gate, such as structure 400, includes active regions 405a and 405b and a metal gate structure 410 (similar to metal gate structures 256a and / or 256b). The gate structure 410 is oriented along the Y-direction and is located on the active regions 405a and 405b to form various transistors, such as two n-type field-effect transistors M1 and M2 and two p-type field-effect transistors M3 and M4. A path is defined as the route for transmitting signals in a circuit. A critical path is the location that primarily governs the circuit speed (or signal transmission speed), which depends on the specific circuit application. If the circuit speed varies significantly with transistor performance, the path can be considered a critical path. If the circuit speed is substantially unrelated to transistor performance, the path can be considered a non-critical path. For the NOR logic gate, such as structure 400, the two p-type field-effect transistors M3 and M4 are in the critical path, while the two n-type field-effect transistors M1 and M2 are in the non-critical path. The different configurations in the critical and non-critical paths help reduce power consumption and maintain satisfactory circuit speed during field operation. In this embodiment, the n-type field-effect transistors in the non-critical paths are configured as the topmost channel components with partial oxidation to achieve low power consumption. A cross-sectional view of the NOR logic gate, such as structure 400 along section line E-E', is shown below. Figure 25 As shown.

[0130] like Figure 25 As shown, the NOR logic gate, structure 400, includes a first device region 400A for forming n-type field-effect transistors (such as n-type field-effect transistors M1 and M2), and a second device region 400B for forming p-type field-effect transistors (such as p-type field-effect transistors M3 and M4). In an exemplary manufacturing process, a matching... Figures 1 to 14Steps 102 to 118 of method 100 described above are used to form channel assembly 208A in the first device region 400A and channel assembly 208B in the second device region 400B. Different from Figures 15 to 19B The illustrated embodiment (partial oxidation of the topmost channel component 208B1 to form the topmost channel component 208B1' and the thickened interface layer 240a) Figure 25 The example shown partially oxidizes the topmost channel component 208A1 to form the topmost channel component 208A1' and the thickened interface layer 240a'. For example, a patterned photoresist layer can be formed on the second device region 400B, exposing the first device region 400A. Then, steps 120 to 124 of method 100 are performed to partially recess the protective layer 246 in the first device region 400A. The hard mask layer 244 not covered by the recessed protective layer 246 is removed, and a plasma processing process 250 is performed to partially oxidize the topmost channel component 208A1. The relationship between the topmost channel component 208A1' and the interface layer 240a', and the matching... Figures 17 to 19B The relationship between the topmost channel component 208B1' and the interface layer 240a described above is substantially the same. The relationship between the topmost channel component 208A1' and other channel components (such as the topmost channel component 208B1 and the first intermediate channel component 208A2) is similar to that between the topmost channel component 208A1' and the interface layer 240a. Figures 17 to 19B The relationship between the topmost channel component 208B1' and the other channel components is essentially the same. This will not be repeated here for simplicity. Proceed to steps 126 and 128 to complete the fabrication of structure 400.

[0131] In the above embodiments, the structure (such as structure 200, 300, or 400) includes a p-type field-effect transistor containing the topmost channel component 208B1', or an n-type field-effect transistor containing the topmost channel component 208A1'. Figure 26In other embodiments shown, structure 500 includes a plurality of n-type field-effect transistors and a plurality of p-type field-effect transistors, at least one n-type field-effect transistor in a non-critical path including a topmost channel component 208A1', and at least one p-type field-effect transistor in a non-critical path including a topmost channel component 208B1'. For example, structure 500 includes a first device region 500A for forming n-type field-effect transistors and a second device region 500B for forming p-type field-effect transistors. First device region 500A includes a portion similar to first device region 200A and a portion similar to first device region 400A, while second device region 500B includes a portion similar to second device region 200B and a portion similar to second device region 400B. Details of first device regions 200A and 400A and second device regions 200B and 400B have been described above and will not be repeated here for simplicity. It is worth noting that structure 500 may include one or more gate isolation structures 260 configured to provide isolation between the metal gate structures of two adjacent transistors.

[0132] In the above embodiments, structures (such as structures 200, 300, 400, or 500) are formed in unit cells (such as memory cells or logic cells). In some other embodiments, the above method 100 can be used to form different blocks (or different wafers) to improve performance (e.g., reduce power loss or increase speed). Figure 27 The simplified structure 600 shown (such as an integrated circuit package) includes a first block 600A and a second block 600B, while Figure 28Cross-sectional views of the transistors in the first block 600A and the second block 600B are shown. The first block 600A and the second block 600B can be configured for different functions and / or for different applications. For example, the first block 600A may include a die that prioritizes speed over power consumption (e.g., a die with high current drive capability or suitable for efficient computing), while the second block 600B may include a die that prioritizes power consumption over speed (e.g., a die with low current drive capability). For ease of explanation, the first block 600A can be considered a high-efficiency computing block, and the second block 600B can be considered a low-power block. However, it should be understood that method 100 can also be applied to form other types of dies. In this embodiment of the invention, to improve performance, the high-efficiency computing block, such as the first block 600A, includes an n-type field-effect transistor with a topmost channel component 208A1, and a p-type field-effect transistor with a topmost channel component 208B1. The low-power blocks, such as the second block 600B, include n-type field-effect transistors with a partially oxidized topmost channel component 208A1', while the p-type field-effect transistors have a partially oxidized topmost channel component 208B1'. Therefore, both the n-type and p-type field-effect transistors in the high-efficiency computing blocks, such as the first block 600A, are driven by high current, while both the n-type and p-type field-effect transistors in the low-power blocks, such as the second block 600B, are driven by low power. Details of the n-type field-effect transistors with topmost channel components 208A1 or 208A1', and details of the p-type field-effect transistors with topmost channel components 208B1 or 208B1', have been described above and will not be repeated here for simplicity.

[0133] In the above embodiment, the topmost channel components 208A1' and 208B1' are partially oxidized. In another embodiment, the topmost channel components 208A1 or 208B1 can be completely oxidized during plasma processing 250. Figure 29 For example, structure 700 includes a first device region 700A containing an n-type field-effect transistor and a second device region 700B containing a p-type field-effect transistor, and the topmost channel component 208B1 is completely oxidized to form an interface layer 240a" on the first intermediate channel component 208B2. In another embodiment, the topmost channel component 208A1 can be completely oxidized during plasma processing 250. Figure 29 The two other embodiments shown can be applied to the other embodiments described above (such as...). Figures 19A to 28 Although not illustrated, method 100 can also be used to form transistors with other suitable numbers of channel components. For example, stack 207 may include three staggered channel layers 208 and three sacrificial layers 206, and the final transistor may include three channel components without plasma processing 250. Another final transistor may include three channel components, with the topmost channel component partially or completely oxidized.

[0134] One or more embodiments of this invention can provide numerous advantages to semiconductor devices and their formation methods, but are not limited thereto. In some embodiments, this invention provides a method for forming transistors with reduced parasitic capacitance and improved performance (e.g., reducing the performance difference between n-type and p-type field-effect transistors and reducing power consumption). For example, the width and thickness of the topmost channel assembly of a p-type field-effect transistor are smaller than the width and thickness of the bottommost channel assembly of a p-type field-effect transistor. The topmost channel assembly of a p-type field-effect transistor can be made smaller by performing a plasma processing process to partially oxidize the initial topmost channel assembly. In some embodiments, n-type and p-type field-effect transistors can be fabricated with different arrangements of their channel assemblies. For example, the channel assembly used for the n-type field-effect transistor is not subjected to a plasma processing process, but the channel assembly used for the p-type field-effect transistor can be subjected to a plasma processing process. The plasma processing process can be performed at the transistor level (e.g., within a cell) or at the die level (e.g., between two different dies). The desired transistor performance can be achieved by oxidizing the topmost channel assembly.

[0135] This invention provides many different embodiments. Semiconductor structures and their fabrication methods are disclosed herein. One embodiment of this invention relates to a method for forming a semiconductor structure. The method includes forming a plurality of nanostructures on a substrate; depositing a dielectric layer to encapsulate the nanostructures; forming a masking layer on the dielectric layer; etching back the masking layer so that the upper surface of the masking layer is flush with or lower than the upper surface of the topmost nanostructure of the nanostructures; performing a process to reduce the thickness of the topmost nanostructure of the nanostructures; selectively removing the masking layer after the process; and forming a gate on the dielectric layer to encapsulate the nanostructures.

[0136] In some embodiments, the processing steps may implement directional plasma, and the directional plasma includes oxygen-containing gas. In some embodiments, the dielectric layer may include an interface layer and a high-dielectric-constant dielectric layer located on the interface layer, and the processing steps may change the thickness of the interface layer. In some embodiments, after the processing steps, the ratio of the thickness of the topmost nanostructure to the thickness of the bottommost nanostructure of the nanostructure is less than 0.8. In some embodiments, after the processing steps, the width of the topmost nanostructure of the nanostructure is less than the width of the bottommost nanostructure of the nanostructure. In some embodiments, the steps of forming the nanostructure may include forming a plurality of interleaved channel layers and a plurality of sacrificial layers; selectively removing the sacrificial layers to form a plurality of openings; forming a plurality of dummy layers in the openings; and selectively removing the dummy layers to release the channel layers as a plurality of nanostructures, wherein the etch selectivity between the channel layers and the dummy layers is greater than the etch selectivity between the channel layers and the sacrificial layers. In some embodiments, after the etch-back step, the upper surface of the mask layer and the lower surface of the topmost nanostructure of the nanostructure may be substantially coplanar. In some embodiments, the method may also include forming a plurality of source / drain structures to couple to the nanostructure; and forming a plurality of inner spacer structures below the topmost nanostructure of the nanostructure to provide isolation between the source / drain structures and the gate, wherein the thickness of the topmost nanostructure of the nanostructure is inconsistent in a cross-sectional view through the source / drain structures and the nanostructure. In some embodiments, the source / drain structures include p-type dopants.

[0137] Another embodiment of this utility model relates to a method for forming a semiconductor structure. The method includes forming a plurality of first nanostructures on a first region of a substrate and forming a plurality of second nanostructures on a second region of the substrate, wherein the first nanostructures and the second nanostructures include the same number of nanostructures; partially oxidizing the topmost nanostructure of the second nanostructures from top to bottom; forming a dielectric layer to cover the first nanostructures and the second nanostructures; forming a first gate on the first nanostructures and covering the first nanostructures; and forming a second gate on the second nanostructures and covering the second nanostructures, wherein after the partial oxidation step, the upper surface of the topmost nanostructure of the second nanostructure is lower than the upper surface of the topmost nanostructure of the first nanostructure, and the lower surface of the topmost nanostructure of the second nanostructure is substantially coplanar with the lower surface of the topmost nanostructure of the first nanostructure.

[0138] In some embodiments, the method may also include forming a plurality of first-type source / drain structures to couple to a first nanostructure; and forming a plurality of second-type source / drain structures to couple to a second nanostructure, wherein the first-type source / drain structures and the second-type source / drain structures may include dopants with different doping polarities. In some embodiments, after the partial oxidation step, the lower surface of the topmost nanostructure of the second nanostructure may be substantially coplanar with the lower surface of the topmost nanostructure of the first nanostructure. In some embodiments, the width of the topmost nanostructure of the second nanostructure may be smaller than the width of the bottommost nanostructure of the second nanostructure. In some embodiments, a dielectric layer is formed prior to the partial oxidation step. In some embodiments, the step of forming the dielectric layer includes forming a first interface layer to cover the first nanostructure and forming a second interface layer to cover the second nanostructure; and compliantly depositing a high-dielectric-constant dielectric layer on the first interface layer and the second interface layer, wherein the step of partially oxidizing the topmost nanostructure of the second nanostructure increases the thickness of a portion of the second interface layer on the topmost nanostructure of the second nanostructure. In some embodiments, the step of partially oxidizing the top nanostructure of the second nanostructure from top to bottom may include forming a masking layer on a substrate; recessing a portion of the masking layer on a second region of the substrate, wherein the upper surface of the recessed portion of the masking layer is lower than the upper surface of the top nanostructure of the second nanostructure; and performing a directional plasma process to oxidize the top nanostructure of the second nanostructure.

[0139] Another embodiment of this utility model relates to a semiconductor structure. The semiconductor structure includes a transistor, which includes a plurality of nanostructures located on a substrate, a gate dielectric layer covering and located on the nanostructures, and a gate located on the gate dielectric layer, wherein a portion of the gate dielectric layer extending above the upper surface of the topmost nanostructure is thicker than a portion of the gate dielectric layer extending below the lower surface of the topmost nanostructure.

[0140] In some embodiments, the thickness of the topmost nanostructure of the nanostructure may be less than the thickness of the bottommost nanostructure of the nanostructure, and the distance between the topmost nanostructure of the nanostructure and a nanostructure below it may be equal to the distance between the bottommost nanostructure of the nanostructure and the substrate. In some embodiments, the width of the topmost nanostructure is less than the width of the bottommost nanostructure. In some embodiments, the transistor is a p-type transistor, and the semiconductor structure may also include an n-type transistor, the n-type transistor including a plurality of other nanostructures located on the substrate, and wherein the upper surface of the topmost nanostructure of the nanostructure may be lower than the upper surface of the topmost nanostructures of the other nanostructures. In some embodiments, the thickness of the topmost nanostructure of the nanostructure is less than the thickness of the topmost nanostructures of the other nanostructures. In some embodiments, the width of the topmost nanostructure of the nanostructure is less than the width of the topmost nanostructures of the other nanostructures. In some embodiments, the thickness of the topmost nanostructure of the other nanostructure is equal to the thickness of the bottommost nanostructure of the other nanostructure. In some embodiments, the distance between the topmost nanostructure of the other nanostructure and the nanostructures below it is equal to the distance between the bottommost nanostructure of the other nanostructure and the substrate. In some embodiments, the outline of the topmost nanostructure of the nanostructure is a rectangle with rounded corners. In some embodiments, the topmost nanostructure of the nanostructure has a trapezoidal shape with rounded corners.

[0141] The features of the above embodiments are beneficial for those skilled in the art to understand this utility model. Those skilled in the art should understand that this utility model can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this utility model, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this utility model. For example, by implementing bit line conductors and word line conductors of different thicknesses, conductors with different resistances can be achieved. However, other techniques can also be used to change the resistance of the metal conductor.

Claims

1. A semiconductor structure, characterized in that, include: A transistor, comprising: Multiple nanostructures are located on a substrate. A gate dielectric layer, covering and situated on the plurality of nanostructures, and A gate, located on the gate dielectric layer, A portion of the gate dielectric layer extending above the upper surface of the topmost nanostructure of the plurality of nanostructures is thicker than a portion of the gate dielectric layer extending below the lower surface of the topmost nanostructure of the plurality of nanostructures.

2. The semiconductor structure as described in claim 1, characterized in that, The thickness of the topmost nanostructure of the plurality of nanostructures is less than the thickness of the bottommost nanostructure of the plurality of nanostructures, and the distance between the topmost nanostructure of the plurality of nanostructures and the nanostructure below the topmost nanostructure of the plurality of nanostructures is equal to the distance between the bottommost nanostructure of the plurality of nanostructures and the substrate.

3. The semiconductor structure as described in claim 2, characterized in that, The width of the topmost nanostructure is smaller than the width of the bottommost nanostructure.

4. The semiconductor structure as described in claim 2, characterized in that, The transistor is a p-type transistor, and the semiconductor structure further includes an n-type transistor. The n-type transistor includes several other nanostructures located on the substrate, and The upper surface of the topmost nanostructure among the plurality of nanostructures is lower than the upper surface of the topmost nanostructure among the plurality of other nanostructures.

5. The semiconductor structure as described in claim 4, characterized in that, The thickness of the topmost nanostructure of the plurality of nanostructures is less than the thickness of the topmost nanostructure of the plurality of other nanostructures.

6. The semiconductor structure as described in claim 4, characterized in that, The width of the topmost nanostructure of the plurality of nanostructures is smaller than the width of the topmost nanostructure of the plurality of other nanostructures.

7. The semiconductor structure as described in claim 4, characterized in that, The thickness of the topmost nanostructure of the plurality of other nanostructures is equal to the thickness of the bottommost nanostructure of the plurality of other nanostructures.

8. The semiconductor structure as described in claim 7, characterized in that, The distance between the topmost nanostructure of the plurality of other nanostructures and the nanostructure below the topmost nanostructure of the plurality of other nanostructures is equal to the distance between the bottommost nanostructure of the plurality of other nanostructures and the substrate.

9. The semiconductor structure as described in claim 1, characterized in that, The topmost nanostructure of the multiple nanostructures has a rectangular outline with rounded corners.

10. The semiconductor structure as claimed in claim 1, characterized in that, The topmost nanostructure of the multiple nanostructures has a trapezoidal shape with rounded corners.

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