Semiconductor device
By embedding a three-dimensional MIM capacitor architecture in the back-side power rail of a semiconductor device, the problems of insufficient capacitance density and design flexibility in the prior art are solved, achieving high capacitance density and enhanced reliability, and it is applicable to a variety of transistor types.
Patent Information
- Application Number
- CN202522335982.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-11-26
- Filing Date
- 2025-11-04
- Publication Date
- 2026-11-06
- Estimated Expiration
- 2035-11-04
AI Technical Summary
As the integration density of semiconductor components increases, existing technologies struggle to effectively achieve higher capacitance density and design flexibility, especially in three-dimensional structures, particularly in the application of BEOL deep trench MIM structures.
A three-dimensional MIM capacitor architecture is adopted, which incorporates multilayer film stacks, including metal/dielectric/metal or metal/dielectric/metal/dielectric/metal structures, into the back-side power rails of the semiconductor device, combined with a curved profile to improve reliability and flexibility.
It achieves high capacitance density and design flexibility, suitable for various transistor types, including metal-oxide-semiconductor devices, fin field-effect transistors, and gate-all-around devices, enhancing the reliability and flexibility of capacitors.
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Figure CN224948032U_ABST
Abstract
Description
Technical Field
[0001] Some embodiments of this disclosure provide semiconductor devices. Background Technology
[0002] The semiconductor industry is experiencing rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area. Utility Model Content
[0003] Some embodiments of this disclosure provide a semiconductor device comprising a first substrate, a second substrate, a first metal layer, a second metal layer, a dielectric layer, and a bonding layer. The first substrate includes a first side and a second side opposite to each other. A plurality of epitaxial structures and at least one gate structure are formed on the first side of the first substrate. The second substrate includes a first side and a second side opposite to each other. A first metal layer is formed on the first side of the second substrate. A second metal layer is formed on the first side of the second substrate. A dielectric layer is inserted between the first metal layer and the second metal layer. A bonding layer is inserted between the second side of the first substrate and the second side of the second substrate. The first metal layer, the second metal layer, and the dielectric layer are operatively configured to form a capacitor on the first side of the second substrate, the capacitor being coupled to at least one of the epitaxial structures on the first side of the first substrate, wherein each of the first metal layer, the dielectric layer, and the second metal layer includes at least one vertical portion extending toward or away from the first substrate.
[0004] Some embodiments of this disclosure provide a semiconductor device including a substrate, a plurality of transistors, a first metal layer, a second metal layer, and a dielectric layer. The substrate includes a first side and a second side opposite to each other. A plurality of transistors are formed on the first side of the substrate. The first metal layer is formed on the second side of the substrate. The second metal layer is formed on the second side of the substrate. The dielectric layer is inserted between the first metal layer and the second metal layer. Each of the first metal layer, the dielectric layer, and the second metal layer includes a vertical portion extending toward or away from the first side of the substrate and a lateral portion connected to the vertical portion.
[0005] In another embodiment disclosed herein, a semiconductor device is provided, comprising a first substrate, a second substrate, a first metal layer, a second metal layer, a dielectric layer, and a bonding layer. The first substrate includes a first side and a second side opposite to each other. A plurality of epitaxial structures and at least one gate structure are formed on the first side of the first substrate. The second substrate includes a first side and a second side opposite to each other. A first metal layer is formed on the first side of the second substrate. A second metal layer is formed on the first side of the second substrate. The first metal layer is disposed in one of the first metal layers, which are formed in a plurality of metallization layers on the first side of the second substrate, and the second metal layer is disposed in a second of these metallization layers. A dielectric layer is inserted between the first metal layer and the second metal layer. A bonding layer is inserted between the second side of the first substrate and the second side of the second substrate. Each of the first metal layer, the dielectric layer, and the second metal layer includes at least one vertical portion extending toward or away from the first substrate. Attached Figure Description
[0006] When with attachment Figure 1 When reading this document, it is best to understand the specifications as described below. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for ease of discussion, the dimensions of the various features may be arbitrarily increased or decreased.
[0007] Figure 1 A cross-sectional view of a semiconductor device according to some embodiments is shown;
[0008] Figure 2 A flowchart illustrating an example method for manufacturing a semiconductor device according to some embodiments;
[0009] Figure 3A , Figure 3B , Figure 3C and Figure 3D A flowchart illustrating an example method for manufacturing a semiconductor device according to some embodiments;
[0010] Figure 4 A cross-sectional view of a semiconductor device according to some embodiments is shown;
[0011] Figure 5 A flowchart illustrating an example method for manufacturing a semiconductor device according to some embodiments;
[0012] Figure 6A , Figure 6B , Figure 6C and Figure 6D A flowchart illustrating an example method for manufacturing a semiconductor device according to some embodiments;
[0013] Figure 7A , Figure 7B and Figure 7C A cross-sectional view of a semiconductor device according to some embodiments is shown;
[0014] Figure 8A and Figure 8B A cross-sectional view of a semiconductor device according to some embodiments is shown;
[0015] Figure 9 A top view of a semiconductor device according to some embodiments is shown;
[0016] Figure 10 A top view of a semiconductor device according to some embodiments is shown;
[0017] Figure 11 A cross-sectional view of a semiconductor device according to some embodiments is shown.
[0018] [Symbol Explanation]
[0019] 100: Semiconductor devices
[0020] 110: First substrate
[0021] 111: First side
[0022] 112: Second side
[0023] 120: Second substrate
[0024] 121: First side
[0025] 122: Second side
[0026] 130: Epitaxial structure
[0027] 135: Bonding layer
[0028] 140: Gate structure
[0029] 150: Metallization layer
[0030] 150A: Metallization layer
[0031] 150B: Metallization layer
[0032] 160: Capacitor
[0033] 161: First metal layer
[0034] 161L: Lateral section
[0035] 161V: Vertical section
[0036] 162: Second metal layer
[0037] 162L: Lateral section
[0038] 162V: Vertical section
[0039] 167: Dielectric layer
[0040] 167L: Lateral section
[0041] 167V: Vertical section
[0042] 200: Method
[0043] 210: Operation
[0044] 220: Operation
[0045] 230: Operation
[0046] 300: Semiconductor Devices
[0047] 301: First substrate
[0048] 302: Second substrate
[0049] 330: Epitaxial structure
[0050] 361: First metal layer
[0051] 362: Second metal layer
[0052] 367: Dielectric layer
[0053] 380: Hat Layer
[0054] 390: Interlayer dielectric
[0055] 391: Passivation structure
[0056] 400: Semiconductor Devices
[0057] 410: First substrate
[0058] 411: First side
[0059] 412: Second side
[0060] 420: Second substrate
[0061] 421: First side
[0062] 422: Second side
[0063] 430: Epitaxial structure
[0064] 435: Bonding layer
[0065] 440: Gate structure
[0066] 450: Metallization layer
[0067] 450A: Metallization layer
[0068] 450B: Metallization layer
[0069] 460: Capacitor
[0070] 461: First metal layer
[0071] 461L: Lateral section
[0072] 461V: Vertical section
[0073] 462: Second metal layer
[0074] 462L: Lateral section
[0075] 462V: Vertical section
[0076] 467: Dielectric layer
[0077] 467L: Lateral section
[0078] 467V: Vertical section
[0079] 500: Methods
[0080] 510: Operation
[0081] 520: Operation
[0082] 530: Operation
[0083] 600: Semiconductor Devices
[0084] 601: First substrate
[0085] 602: Second substrate
[0086] 630: Epitaxial structure
[0087] 661: First metal layer
[0088] 662: Second metal layer
[0089] 667: Dielectric layer
[0090] 690: Interlayer Dielectric
[0091] 700: Semiconductor Devices
[0092] 760: Capacitor
[0093] 760V: Porosity
[0094] 761: First metal layer
[0095] 762: Second metal layer
[0096] 767: Dielectric layer
[0097] 800: Semiconductor Device
[0098] 860: Capacitor
[0099] 861: First metal layer
[0100] 862: Second metal layer
[0101] 863: Third metal layer
[0102] 867: Dielectric layer
[0103] 868: Dielectric layer / First dielectric layer
[0104] 869: Dielectric layer / Second dielectric layer
[0105] 910: Semiconductor Device
[0106] 920: Semiconductor device
[0107] 930: Semiconductor Device
[0108] 940: Semiconductor device
[0109] 950: Semiconductor device
[0110] 960: Semiconductor Device
[0111] 970: Semiconductor Device
[0112] 980: Semiconductor Device
[0113] 1010: Semiconductor Devices
[0114] 1020: Semiconductor Devices
[0115] 1030: Semiconductor Devices
[0116] 1040: Semiconductor device
[0117] 1050: Semiconductor device
[0118] 1060: Semiconductor Device
[0119] 1070: Semiconductor Device
[0120] 1080: Semiconductor device
[0121] 1110: Semiconductor Devices
[0122] 1120: Semiconductor Device
[0123] 1130: Semiconductor Devices
[0124] 1140: Semiconductor Device
[0125] 1150: Semiconductor Devices
[0126] 1160: Semiconductor Devices
[0127] 1170: Semiconductor Devices
[0128] 1180: Semiconductor Device
[0129] CT: Contact Structure
[0130] EPI: Epitaxial Structure
[0131] FEOL: Front-end process
[0132] ILD1: Interlayer dielectric structure
[0133] MG: Gate structure
[0134] TD: Depth
[0135] TW: Width
[0136] VB: Through-hole structure
[0137] VB-1: Through-hole structure
[0138] VB-2: Through-hole structure
[0139] VB-3: Through-hole structure
[0140] VD: Depth
[0141] VP: Position
[0142] VW: Width Detailed Implementation
[0143] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.
[0144] Furthermore, for ease of description, spatial relative terms such as “below,” “lower,” “lower,” “higher,” “upper,” “top,” “bottom,” and the like are used herein to describe the relationship between one element or feature as illustrated in the accompanying drawings and another element or feature(s). In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.
[0145] Continuous innovation in semiconductor process technology is enabling higher integration densities and device scale. As the semiconductor industry moves towards smaller technology nodes, planar and non-planar field-effect transistor (FET) device structures must be scaled down to smaller dimensions to provide increased device width per coverage area. In this regard, nanostructures (e.g., nanosheets, nanowires, or other gate-all-around (GAA) FET devices are considered a viable option for continued scaling of complementary metal-oxide-semiconductor (CMOS). Generally, various structures can be incorporated into semiconductor devices. For example, metal-insulator-metal (MIM) capacitors can be provided on the back-end-of-line (BEOL) side for high-capacitance applications (e.g., full exposure).
[0146] This disclosure provides a MIM capacitor embedded in the back-side power rail of a semiconductor device to achieve high capacitance. The techniques disclosed herein utilize a three-dimensional (3D) MIM architecture that integrates multilayer film stacks (e.g., metal / dielectric / metal, or metal / dielectric / metal / dielectric / metal) while providing enhanced capacitance and design flexibility. In some embodiments, curved profiles can be used, for example, by introducing vias to improve reliability and flexibility. The techniques disclosed herein can be applied to various transistor types, including but not limited to metal-oxide-semiconductor devices, fin field-effect transistor devices, gate-all-around devices, etc., regardless of the BEOL deep trench MIM structure.
[0147] Figure 1A cross-sectional view of a semiconductor device 100 according to some embodiments is illustrated. The semiconductor device 100 includes: a first substrate 110 including a first side 111 and a second side 112 opposite to each other; and a second substrate 120 including a first side 121 and a second side 122. In some embodiments, the first substrate 110 may be a front-end-of-line (FEOL) side. In some embodiments, the second substrate 120 may be a back-side (B / S) power rail.
[0148] In some embodiments, the semiconductor device 100 includes a plurality of transistors formed on a first substrate 110. The semiconductor device 100 may include a plurality of epitaxial layers (EPIs) 130 and gate structures (MGs) 140 formed on a first side 111 of the first substrate 110. The semiconductor device 100 may include source and drain (S / D) structures, contact structures (CTs), etc., formed on the first substrate 110. The semiconductor device 100 may include one or more interlayer dielectric structures (e.g., ILD1).
[0149] In some embodiments, the semiconductor device 100 includes a plurality of metallization layers 150 (e.g., metallization layers 150A, 150B, etc.) formed on a second substrate 120. In some embodiments, the semiconductor device 100 includes a first metal layer 161 formed on the second substrate 120, a second metal layer 162 formed on the second substrate 120, and a dielectric layer 167 inserted between the first metal layer 161 and the second metal layer 162. The first metal layer 161, the second metal layer 162, and the dielectric layer 167 can be operatively configured to form a capacitor on a first side 121 of the second substrate 120, the capacitor being coupled to at least one of a plurality of epitaxial structures 130 on the first side 111 of the first substrate 110. Each of the first metal layer 161, the dielectric layer 167, and the second metal layer 162 includes an orientation (e.g., ...). Figure 1 (as shown) or far away (as shown) Figure 4As shown, at least one vertical portion (e.g., vertical portions 161V, 167V, 162V, etc.) extends from the first substrate 110. In some embodiments, each of the first metal layer 161, dielectric layer 167, and second metal layer 162 may include at least one lateral portion (e.g., lateral portions 161L, 167L, 162L, etc.) connected to the corresponding vertical portion. In some embodiments, the semiconductor device 100 may include a bonding layer 135. The bonding layer 135 may be inserted between a second side 112 of the first substrate 110 and a second side 122 of the second substrate 120. In some embodiments, the bonding layer 135 may be formed on the second side 122 of the second substrate 120, as shown. In some embodiments, the bonding layer 135 may be formed on the second side 112 of the first substrate 110. The bonding layer 135 can be used to bond both the first substrate 110 and the second substrate 120. In some embodiments, the bonding layer 135 may be formed of materials including but not limited to dielectrics (e.g., silicon dioxide, silicon nitride, silicon carbide), epitaxial films (e.g., silicon germanium, silicon phosphorus), metal oxides (e.g., aluminum oxide, zirconium oxide, hafnium oxide), etc.
[0150] In some embodiments, a first metal layer 161 is disposed in a first metallization layer 150 (e.g., metallization layer 150B formed on a second substrate 120), and a second metal layer 162 is formed in a second metallization layer 150 (e.g., metallization layer 150A). For example, as shown, the first metal layer 161 may be electrically coupled to a metal structure (e.g., BS metal-1) in metallization layer 150A. The second metal layer 162 may be electrically coupled to a metal structure (e.g., BS metal-2) in metallization layer 150B via a via structure (e.g., VB-2), a dielectric layer (e.g., dielectric layer 167), or a metal layer (e.g., metal layer 161). In some embodiments, the first metal layer 161 may be electrically coupled to a first epitaxial structure 130 (e.g., a first S / D epitaxial structure), and the second metal layer 162 may be electrically coupled to a second epitaxial structure 130 (e.g., a second S / D epitaxial structure). For example, as shown in the figure, a first metal layer 161 may be electrically coupled to a first epitaxial structure 130 via a metal structure (e.g., BS metal-1) and a via structure (e.g., VB-1), and a second metal layer 162 may be electrically coupled to a second epitaxial structure 130 via a via structure (e.g., VB-2) and a metal structure (e.g., BS metal-2). In some embodiments, as shown in the figure, a plurality of epitaxial structures 130 may be laterally disposed on the side surface of the gate structure 140.
[0151] In some embodiments, the first metallization layer 150A and the second metallization layer 150B may be vertically adjacent to each other without any other metallization layer inserted between them. In some embodiments, the first metallization layer 150A and the second metallization layer 150B may be vertically adjacent to each other with at least one of the metallization layers 150 inserted between them.
[0152] In some embodiments, the first metal layer 161, dielectric layer 167, and second metal layer 162 can operatively form a capacitor 160. In some embodiments, dielectric layer 167 comprises a high-k dielectric material (e.g., zirconium oxide, aluminum oxide, hafnium oxide, etc.). In some embodiments, dielectric layer 167 may comprise or be formed of any material with a dielectric constant greater than 10. In some embodiments, dielectric layer 167 comprises a ferroelectric material. In some embodiments, the first metal layer 161 and the second metal layer 162 each comprise copper. In some embodiments, the first metal layer 161 and the second metal layer 162 each comprise aluminum. In some embodiments, the first metal layer 161 and the second metal layer 162 may comprise titanium nitride (TiN), titanium, tantalum nitride (TaN), tantalum, copper (Cu), cobalt (Co), aluminum (Al), etc. In some embodiments, each of the first metal layer 161 and the second metal layer 162 may be or comprise different materials.
[0153] In some embodiments, capacitor 160 may include a third metal layer (e.g., formed within dielectric layer 167 between first metal layer 161 and second metal layer 162) Figure 8B (as shown in the diagram). In some embodiments, the first metal layer 161, the second metal layer 162, the third metal layer located within the dielectric layer 167, and the dielectric layer 167 may form a capacitor connected in parallel with each other.
[0154] It should be understood that Figure 1 The semiconductor device 100 described herein is a non-limiting example and is simplified for illustrative purposes; therefore, the semiconductor device 100 may include any of a variety of other components or structures, while remaining within the scope of this disclosure. In some embodiments, the semiconductor device 100 may include more than Figure 1 As shown or relative to Figure 1 The accompanying drawings describe more, fewer, or different components. For clarity, these reference cross-sections are shown in the following figures.
[0155] Figure 2 A flowchart illustrating an example method 200 for manufacturing a semiconductor device according to some embodiments is shown. For example, at least some of the operations (or steps) in method 200 may form Figure 1 The semiconductor device 100 or similar shown is illustrated. It should be noted that method 200 is a non-limiting example. Therefore, in Figure 2Additional operations may be provided before, during, and after method 200, and only some of these additional operations may be briefly described herein. In some embodiments, the operation of method 200 may be related to... Figure 3A , Figure 3B , Figure 3C and Figure 3D The example semiconductor devices shown at various manufacturing stages are associated with each other and will be discussed in further detail below. In some embodiments, Figure 3A , Figure 3B , Figure 3C and Figure 3D The flowchart shown can be associated with the operation of method 200.
[0156] In summary, method 200 begins with operation 210, which forms a plurality of transistors on the front side of a first substrate, wherein each of the plurality of transistors includes at least one epitaxial structure. Method 200 continues to operation 220, which forms a first metal layer, a second metal layer, and a dielectric layer inserted between the first and second metal layers on the front side of a second substrate, wherein each of the first metal layer, the dielectric layer, and the second metal layer includes a vertical portion extending toward or away from the second substrate. Method 200 continues to operation 230, which bonds the first substrate to the second substrate, wherein the back side of the first substrate faces the back side of the second substrate. Figure 3A , Figure 3B , Figure 3C and Figure 3D Each can be drawn in Figure 2 A portion of the semiconductor device 100 at each manufacturing stage of method 200.
[0157] Corresponding to Figure 2 Operation 210, Figure 3AThis is a cross-sectional view of a semiconductor device 300 including a first substrate 301 and a second substrate 302. In some embodiments, each of the first substrate 301 and the second substrate 302 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. In some embodiments, each of the first substrate 301 and the second substrate 302 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of each of the first substrate 301 and the second substrate 302 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.
[0158] At operation 210, a plurality of transistors may be formed on the front side of the first substrate 301. In some embodiments, each of the plurality of transistors may include at least one epitaxial structure (e.g., EPI; S / D structure) 330. In some embodiments, the epitaxial structure 330 may be doped. For example, when the semiconductor device 300 is configured as n-type (and operates in enhancement mode), each of the epitaxial structures 330 may be silicon doped with a p-type dopant, such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the semiconductor device 300 is configured as p-type (and operates in enhancement mode), each of the epitaxial structures 330 may be silicon doped with an n-type dopant, such as phosphorus (P), arsenic (As), and antimony (Sb). The epitaxial structure 330 may include materials such as compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. The epitaxial structure 330 may be epitaxially grown on the front side of the first substrate 301 using, for example, molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD, MOCVD), and / or other suitable epitaxial growth processes. At operation 210, via structures (e.g., VB-1) and metal structures (e.g., BS metal-1) may be formed on the second substrate 302 using techniques such as photolithography and etching. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), may form the top surface of the second substrate 302.
[0159] Corresponding to Figure 2 Operation 220, Figure 3B This is a cross-sectional view of a semiconductor device 300, wherein a first metal layer 361, a second metal layer 362, and a dielectric layer 367 inserted between the first metal layer 361 and the second metal layer 362 are formed on the front side of the second substrate 302. Each of the first metal layer 361, the dielectric layer 367, and the second metal layer 362 includes a vertical portion extending toward or away from the second substrate 302.
[0160] At operation 220, an interlayer dielectric 390 may be formed over the front side of the second substrate 302. In some embodiments, the interlayer dielectric 390 may be deposited using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). The interlayer dielectric 390 may then be etched to form trenches (or openings). For example, a photoresist material may be used to pattern the interlayer dielectric 390 to form a patterned mask. The patterned mask may then be used to pattern the exposed portions of the interlayer dielectric 390 to form trenches in which a first metal layer 361, a second metal layer 362, and a dielectric layer 367 may be formed. In some embodiments, the trenches may be formed using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or similar methods or combinations thereof. The etching process may be anisotropic.
[0161] Then, each of the first metal layer 361, the second metal layer 362, and the dielectric layer 367 may be formed. In some embodiments, each of the first metal layer 361, the second metal layer 362, and the dielectric layer 367 may be deposited onto the deep trench region using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, a metal material may be deposited to at least line the trench, thereby forming the first metal layer 361. Then, a dielectric material may be deposited to at least line the trench (e.g., with the first metal layer 361), thereby forming the dielectric layer 367. A metal material may be deposited to fill the trench, thereby forming the second metal layer 362. In some embodiments, a cap layer (e.g., silicon nitride) 380 may be deposited on a portion of the first metal layer 361, the second metal layer 362, and the dielectric layer 367. In some embodiments, various other structures may be formed at operation 220, including through-hole structures (e.g., VB-2), metallic structures (e.g., BS metal-2), passivated structures (e.g., passivated structure 391), etc., for example, such as Figure 3C As shown in the figure. In some embodiments, the passivation structure 391 may include a dielectric material (e.g., silicon dioxide, silicon nitride, silicon carbide), etc.
[0162] Corresponding to Figure 2 Operation 230, Figure 3D This is a cross-sectional view of a semiconductor device 300, wherein a first substrate 301 is bonded to a second substrate 302, with the back side of the first substrate 301 facing the back side of the second substrate 302. The first substrate 301 and the second substrate 302 can be coupled or bonded to each other using any suitable wafer bonding process (e.g., based on...). Figure 1 (135) bonding layer.
[0163] Figure 4 A cross-sectional view of a semiconductor device 400 according to some embodiments is illustrated. The semiconductor device 400 includes: a first substrate 410 including a first side 411 and a second side 412 opposite to each other; and a second substrate 420 including a first side 421 and a second side 422. In some embodiments, the first substrate 410 may be a front-end-of-line (FEOL) side. In some embodiments, the second substrate 420 may be a back-side (B / S) power rail. As shown, the semiconductor device 400 may be substantially similar to and / or incorporate features of the semiconductor device 100. For example, the semiconductor device 400 may include a capacitor whose orientation (e.g., orientation toward or away from a vertically extending portion of the substrate) is opposite to that of the capacitor 160 of the semiconductor device 100.
[0164] In some embodiments, the semiconductor device 400 includes a plurality of transistors formed on a first substrate 410. The semiconductor device 400 may include a plurality of epitaxial layers (EPIs) 430 and gate structures (MGs) 440 formed on a first side 411 of the first substrate 410. The semiconductor device 400 may include source and drain (S / D) structures, contact structures (CTs), etc., formed on the first substrate 410. The semiconductor device 400 may include one or more interlayer dielectric structures (e.g., ILD1).
[0165] Semiconductor device 400 includes a plurality of metallization layers 450 (e.g., metallization layers 450A, 450B, etc.) formed on a second substrate 420. Semiconductor device 400 includes a first metal layer 461 formed on the second substrate 420, a second metal layer 462 formed on the second substrate 420, and a dielectric layer 467 inserted between the first metal layer 461 and the second metal layer 462. The first metal layer 461, the second metal layer 462, and the dielectric layer 467 can be operatively used to form a capacitor on the second substrate 420, which is coupled to at least one of a plurality of epitaxial structures 430 on a first side 411 of the first substrate 410. One of the first metal layer 461, the dielectric layer 467, and the second metal layer 462 includes an orientation (e.g., ...). Figure 1 (as shown) or far away (as shown) Figure 4(As shown) At least one vertical portion extending from the first substrate 410 (e.g., vertical portions 461V, 467V, 462V, etc.). In some embodiments, each of the first metal layer 461, dielectric layer 467, and second metal layer 462 may include at least one lateral portion connected to the corresponding vertical portion (e.g., lateral portions 461L, 467L, 462L, etc.). In some embodiments, the semiconductor device 400 may include a bonding layer 435. The bonding layer 435 may be inserted between a second side 412 of the first substrate 410 and a second side 422 of the second substrate 420. In some embodiments, the bonding layer 435 may be formed on the second side 422 of the second substrate 420. In some embodiments, the bonding layer 435 may be formed on the second side 412 of the first substrate 410. The bonding layer 435 may be used to bond the first substrate 410 and the second substrate 420.
[0166] In some embodiments, a first metal layer 461 is electrically coupled to and / or disposed in a first metallization layer 450 (e.g., metallization layer 450A formed on the second substrate 420), and a second metal layer 462 is electrically coupled to and / or disposed in a second metallization layer 450 (e.g., metallization layer 450B). For example, as shown, the first metal layer 461 may be electrically coupled to a metal structure (e.g., BS metal-1) in metallization layer 450A via a metal structure (e.g., BS metal-1). The second metal layer 462 may be electrically coupled to a metal structure (e.g., BS metal-2) in metallization layer 450B. In some embodiments, the first metal layer 461 may be electrically coupled to a first epitaxial structure 430 (e.g., a first S / D epitaxial structure), and the second metal layer 462 may be electrically coupled to a second epitaxial structure 430 (e.g., a second S / D epitaxial structure). For example, as shown in the figure, a first metal layer 461 may be electrically coupled to a first epitaxial structure 430 via a metal structure (e.g., BS metal-1) and a via structure (e.g., VB-1, VB-2), and a second metal layer 462 may be electrically coupled to a second epitaxial structure 430 via a via structure (e.g., VB-3) and a metal structure (e.g., BS metal-2). In some embodiments, as shown in the figure, a plurality of epitaxial structures 430 may be laterally disposed on the side surface of the gate structure 440.
[0167] In some embodiments, the first metallization layer 450A and the second metallization layer 450B may be vertically adjacent to each other without any other metallization layer inserted between them. In some embodiments, the first metallization layer 450A and the second metallization layer 450B may be vertically adjacent to each other with at least one of the metallization layers 450 inserted between them.
[0168] In some embodiments, the first metal layer 461, the dielectric layer 467, and the second metal layer 462 can operatively form a capacitor 460. In some embodiments, the dielectric layer 467 comprises a high-k dielectric material (e.g., zirconium oxide, aluminum oxide, hafnium oxide, etc.). In some embodiments, the dielectric layer 467 comprises a ferroelectric material. In some embodiments, the first metal layer 461 and the second metal layer 462 each comprise copper. In some embodiments, the first metal layer 461 and the second metal layer 462 each comprise aluminum. In some embodiments, the first metal layer 461 and the second metal layer 462 may comprise titanium nitride, titanium, tantalum nitride, tantalum, etc.
[0169] In some embodiments, capacitor 460 may include a third metal layer (e.g., formed within dielectric layer 467 between first metal layer 461 and second metal layer 162) Figure 8B (as shown in the diagram). In some embodiments, the first metal layer 461, the second metal layer 462, the third metal layer located within the dielectric layer 467, and the dielectric layer 467 may form a capacitor connected in parallel with each other.
[0170] It should be understood that Figure 4 The semiconductor device 400 is a non-limiting example and is simplified for illustrative purposes; therefore, the semiconductor device 400 may include any of a variety of other components or structures, while remaining within the scope of this disclosure. In some embodiments, the semiconductor device 400 may include more than Figure 4 As shown or relative to Figure 1 The accompanying drawings describe more, fewer, or different components. For clarity, these reference cross-sections are shown in the following figures.
[0171] Figure 5 A flowchart illustrating an example method 500 for manufacturing a semiconductor device according to some embodiments is shown. For example, at least some of the operations (or steps) in method 500 may form Figure 4 The semiconductor device 400 or similar shown is illustrated. It should be noted that method 500 is a non-limiting example. Therefore, in Figure 5 Additional operations may be provided before, during, and after method 500, and only some of these additional operations may be briefly described herein. In some embodiments, the operation of method 500 may be related to... Figure 6A , Figure 6B , Figure 6C and Figure 6D The example semiconductor devices shown at various manufacturing stages are associated with each other and will be discussed in further detail below. In some embodiments, Figure 6A , Figure 6B , Figure 6C and Figure 6D The flowchart shown can be associated with the operation of method 500.
[0172] In summary, method 500 begins with operation 510, which forms a plurality of transistors on the front side of a first substrate, wherein each of the plurality of transistors includes at least one epitaxial structure. Method 500 continues to operation 520, which forms a first metal layer, a second metal layer, and a dielectric layer inserted between the first and second metal layers on the front side of a second substrate, wherein each of the first metal layer, the dielectric layer, and the second metal layer includes a vertical portion extending toward or away from the second substrate. Method 500 continues to operation 530, which bonds the first substrate to the second substrate, wherein the back side of the first substrate faces the back side of the second substrate. Figure 6A , Figure 6B , Figure 6C and Figure 6D Each can be drawn in Figure 5 The semiconductor device 400 is part of the various manufacturing stages of method 500.
[0173] Corresponding to Figure 5 Operation 510, Figure 6A This is a cross-sectional view of a semiconductor device 600 including a first substrate 601 and a second substrate 602. In some embodiments, each of the first substrate 601 and the second substrate 602 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. In some embodiments, each of the first substrate 601 and the second substrate 602 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of each of the first substrate 601 and the second substrate 602 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.
[0174] At operation 510, a plurality of transistors may be formed on the front side of the first substrate 601. In some embodiments, each of the plurality of transistors may include at least one epitaxial structure (e.g., EPI; S / D structure) 630. In some embodiments, the epitaxial structure 630 may be doped. For example, when the semiconductor device 600 is configured as n-type (and operates in enhancement mode), each of the epitaxial structures 630 may be silicon doped with a p-type dopant, such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the semiconductor device 600 is configured as p-type (and operates in enhancement mode), each of the epitaxial structures 630 may be silicon doped with an n-type dopant, such as phosphorus (P), arsenic (As), and antimony (Sb). The epitaxial structure 630 may include materials such as compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. The epitaxial structure 630 may be epitaxially grown on the front side of the first substrate 601 using, for example, molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD (MOCVD)), and / or other suitable epitaxial growth processes. At operation 510, via structures (e.g., VB-1) and metal structures (e.g., BS metal-1) may be formed on the second substrate 602 using techniques such as photolithography and etching. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), may form the top surface of the second substrate 602.
[0175] Corresponding to Figure 5 Operation 520, Figure 6B This is a cross-sectional view of a semiconductor device 600, wherein a first metal layer 661, a second metal layer 662, and a dielectric layer 667 inserted between the first metal layer 661 and the second metal layer 662 are formed on the front side of the second substrate 602. Each of the first metal layer 661, the dielectric layer 667, and the second metal layer 662 includes a vertical portion extending toward or away from the second substrate 602.
[0176] At operation 520, each of a first metal layer 661, a second metal layer 662, and a dielectric layer 667 may be formed. In some embodiments, each of the first metal layer 661, the second metal layer 662, and the dielectric layer 667 may be deposited over the second substrate 602 using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, a metal material may be deposited over the front side of the second substrate 602 and then etched to form the first metal layer 661. A dielectric material may then be deposited to back the first metal layer 661 to form the dielectric layer 667. A metal material may be deposited to back the dielectric layer 667 to form the second metal layer 662. In some embodiments, although not shown, a capping layer (e.g., silicon nitride) may be deposited on a portion of the first metal layer 661, the second metal layer 662, and the dielectric layer 667. Then, an interlayer dielectric 690 may be formed over the first metal layer 661, the second metal layer 662, and the dielectric layer 667. In some embodiments, the interlayer dielectric 690 may be deposited using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, at operation 520, various other structures may be formed, including via structures (e.g., VB-3), metallic structures (e.g., BS metal-2), passivation structures, etc., for example, such as Figure 6C As shown in the image.
[0177] Corresponding to Figure 5 Operation 530, Figure 6D This is a cross-sectional view of a semiconductor device 600, wherein a first substrate 601 is bonded to a second substrate 602, with the back side of the first substrate 601 facing the back side of the second substrate 602. The first substrate 601 and the second substrate 602 can be coupled or bonded to each other by any suitable wafer bonding process.
[0178] Figure 7A , Figure 7B and Figure 7C A cross-sectional view of a semiconductor device 700 according to some embodiments is illustrated. The figures show non-limiting examples. In some embodiments, the semiconductor device 700 may include more, fewer, or different components than shown or described in the figures. In some embodiments, the semiconductor device 700 may be substantially similar to or incorporate features of semiconductor devices 100, 400, etc. For example, as shown in the figures, the semiconductor device 700 includes a capacitor 760 comprising a first metal layer 761, a second metal layer 762, and a dielectric layer 767. As shown, the capacitor 760 includes a vertical portion extending toward the bottom side of a substrate. Although not shown, in some embodiments, the capacitor 760 may include a vertical portion extending away from the bottom side of the substrate.
[0179] Unlike semiconductor devices 100 and 400, semiconductor device 700 may include an aperture 760V. For example... Figure 7A , Figure 7B and Figure 7C As shown, capacitor 760 may include apertures 760V within the first metal layer 761. Figure 7A In the semiconductor device 700, an aperture 760V is located at the top of a trench; Figure 7B In the semiconductor device 700, an aperture 760V is located at the middle portion of a trench; and in Figure 7C In this embodiment, the semiconductor device 700 includes an aperture 760V at the bottom of a trench. The depth of the aperture 760V can be defined as VD; the width of the aperture 760V can be defined as VW; the width of the trench can be defined as TW; and the location of the aperture 760V can be defined as VP. In some embodiments, the width VW of the aperture 760V can be 1% to 20% of the trench width TW, and the depth VD of the aperture 760V can be 10% to 50% of the trench depth TD. In some embodiments, the location VP of the aperture 760V (e.g., from the top of the trench to the center of the aperture) can be located at 2% to 50% of the trench depth TD, at a midpoint, or at the bottom (e.g., 50% to 98% of the trench depth TD). The aperture 760V allows for a curved profile as shown in the figure, which relieves stress, especially when the semiconductor device is used as an array (e.g., a three-dimensional MIM capacitor for an image sensor application).
[0180] It should be understood that Figure 7A , Figure 7B and Figure 7C The semiconductor device 700 is a non-limiting example and is simplified for illustrative purposes; therefore, the semiconductor device 700 may include any of a variety of other components or structures, while remaining within the scope of this disclosure. In some embodiments, the semiconductor device 700 may include more than Figure 7A , Figure 7B and Figure 7C As shown or relative to Figure 7A , Figure 7B and Figure 7C The components described include more, fewer, or different components.
[0181] Figure 8A and Figure 8B A cross-sectional view of a semiconductor device 800 according to some embodiments is illustrated. The figures show non-limiting examples. In some embodiments, the semiconductor device 800 may include more, fewer, or different components than shown or described with respect to the figures. In some embodiments, the semiconductor device 800 may be substantially similar to or incorporate features of semiconductor devices 100, 400, etc. For example, such as Figure 8AAs shown, the semiconductor device 800 includes a capacitor 860, which includes a first metal layer 861, a second metal layer 862, and a dielectric layer 867. The capacitor 860 may include a vertical portion extending toward the bottom side of the substrate. Although not shown, in some embodiments, the capacitor 860 may include a vertical portion extending away from the bottom side of the substrate.
[0182] With semiconductor devices 100, 400 or Figure 8A The semiconductor device 800 shown is the opposite. Figure 8B The semiconductor device 800 shown may include in Figure 8A Within dielectric layer 867 (or between first dielectric layer 868 and second dielectric layer 869, such as...) Figure 8B As shown in the figure, a third metal layer 863 is formed between the first metal layer 861 and the second metal layer 862. In some embodiments, the first metal layer 861, the second metal layer 862, the third metal layer 863, and the dielectric layers 868 and 869 form a capacitor connected in parallel with each other. In some embodiments, as shown in the figure, the third metal layer 863 may be connected via a via structure VB (e.g., to an epitaxial structure).
[0183] In some embodiments, the first metal layer 861, the second metal layer 862, and the third metal layer 863 may be different. For example, one of the first metal layer 861, the second metal layer 862, and the third metal layer 863 may include different materials. Each of the first metal layer 861, the second metal layer 862, and the third metal layer 863 may be or include different materials. In some embodiments, the dielectric layer 868 and the dielectric layer 869 may be different. For example, each of the dielectric layer 868 and the dielectric layer 869 may be or include different dielectric materials.
[0184] It should be understood that Figure 8A and Figure 8B The semiconductor device 800 described herein is a non-limiting example and is simplified for illustrative purposes; therefore, the semiconductor device 800 may include any of a variety of other components or structures, while remaining within the scope of this disclosure. In some embodiments, the semiconductor device 800 may include more than Figure 8A and Figure 8B As shown or relative to Figure 8A and Figure 8B The components described include more, fewer, or different components.
[0185] Figure 9The accompanying drawings illustrate top views of semiconductor devices 910, 920, 930, 940, 950, 960, 970, and 980 according to some embodiments. The drawings illustrate non-limiting examples. In some embodiments, semiconductor devices 910, 920, 930, 940, 950, 960, 970, and 980 may include more, fewer, or different components than shown in or relative to the drawings. In some embodiments, semiconductor devices 910, 920, 930, 940, 950, 960, 970, and 980 may be substantially similar to semiconductor devices 100, 400, ... Figure 8A Semiconductor devices 800, etc., may incorporate their own features. For example, semiconductor devices 910, 920, 930, 940, 950, 960, 970, and 980 may be top views of semiconductor devices 100, 400, etc. Each of semiconductor devices 910, 920, 930, 940, 950, 960, 970, and 980 includes a capacitor, which includes a first metal layer, a second metal layer, and a dielectric layer, these layers forming MIM trenches electrically connected (e.g., to an epitaxial structure) via a via structure.
[0186] like Figure 9 As shown, the geometry and dimensions of the MIM trenches, first metal layer, second metal layer, and dielectric layer can vary. In some embodiments, with respect to semiconductor device 910, capacitors can be arranged in parallel. As shown in semiconductor device 950, each of the array capacitors can have multiple MIM trench structures. As shown in semiconductor devices 920 and 960, capacitors can be arranged in various orientations. Although shown as parallel arrangements (e.g., semiconductor devices 910, 920, 950, 960), capacitors can be arranged or configured in flexible ways. As shown in semiconductor devices 930, 940, 970, and 980, the geometry and dimensions of the MIM trench structures can vary. For example, MIM trenches can have shapes such as cross-shaped, rectangular, or combinations thereof.
[0187] It should be understood that Figure 9 The semiconductor device described herein is a non-limiting example and is simplified for illustrative purposes; therefore, it may include any of a variety of other components or structures while remaining within the scope of this disclosure. In some embodiments, the semiconductor device 800 may include more than Figure 9 As shown or relative to Figure 9 The components described include more, fewer, or different components.
[0188] Figure 10A top view of a semiconductor device according to some embodiments is illustrated. The accompanying drawings show non-limiting examples. In some embodiments, semiconductor devices 1010, 1020, 1030, 1040, 1050, 1060, 1070, and 1080 may include more, fewer, or different components than shown in or relative to the drawings. In some embodiments, semiconductor devices 1010, 1020, 1030, 1040, 1050, 1060, 1070, and 1080 may be substantially similar to semiconductor devices 100, 400, ... Figure 8B Semiconductor devices 800, etc., may incorporate their features. For example, semiconductor devices 1010, 1020, 1030, 1040, 1050, 1060, 1070, and 1080 may be top views of semiconductor devices 100, 400, etc. Each of semiconductor devices 1010, 1020, 1030, 1040, 1050, 1060, 1070, and 1080 includes a capacitor, which includes a first metal layer, a second metal layer, and a dielectric layer, these layers forming MIMIM trenches electrically connected via multiple via structures (e.g., multiple epitaxial structures).
[0189] like Figure 10 As shown, the geometry and dimensions of the MIMIM trenches, first metal layer, second metal layer, and dielectric layer can vary. In some embodiments, with respect to semiconductor device 1010, capacitors can be connected in parallel. As shown in semiconductor device 1050, each of the array capacitors can have multiple MIMIM trench structures. As shown in semiconductor devices 1020 and 1060, capacitors can be arranged in various orientations. Although shown as parallel arrangements (e.g., semiconductor devices 1010, 1020, 1050, 1060), capacitors can be arranged or configured in flexible ways. As shown in semiconductor devices 1030, 1040, 1070, and 1080, the geometry and dimensions of the MIMIM trench structures can vary. For example, MIMIM trenches can have shapes such as cross-shaped, rectangular, or combinations thereof.
[0190] As discussed above, the semiconductor device disclosed herein may include various features, such as whether the vertical portions of the metal and dielectric layers extend toward or away from the substrate; whether the semiconductor device includes a third metal layer (e.g., third metal layer 863); whether the semiconductor device includes apertures (e.g., aperture 760V), etc. Based on these features, the semiconductor device can be designed in various ways. For example, refer to... Figure 11 Non-limiting examples of semiconductor devices are summarized in Table 1 below. Figure 11 Cross-sectional views of semiconductor devices 1110, 1120, 1130, 1140, 1150, 1160, 1170 and 1180 according to some embodiments are shown.
[0191] Table 1
[0192]
[0193]
[0194] For example, semiconductor device 1110 includes a vertical portion extending toward a first substrate (or top) having a MIM trench, and semiconductor device 1120 further includes an aperture with a curved profile. Semiconductor device 1130 includes a vertical portion extending toward a first substrate (or top) having a MIM trench (because semiconductor device 1130 includes a third metal layer), and semiconductor device 1140 further includes an aperture with a curved profile. Similarly, semiconductor device 1150 includes a vertical portion extending away from the first substrate (or top) having a MIM trench, and semiconductor device 1160 further includes an aperture with a curved profile. Semiconductor device 1170 includes a vertical portion extending toward a first substrate (or top) having a MIM trench (because semiconductor device 1170 includes a third metal layer), and semiconductor device 1180 further includes an aperture with a curved profile.
[0195] It should be understood that Figure 11 The semiconductor device described is a non-limiting example and is simplified for illustrative purposes; therefore, it may include any of a variety of other components or structures while remaining within the scope of this disclosure. In some embodiments, Figure 11 The semiconductor device may include more Figure 11 As shown or relative to Figure 11 The components described include more, fewer, or different components.
[0196] In one embodiment of this disclosure, a semiconductor device is disclosed. The semiconductor device includes a first substrate, which includes a first side and a second side opposite to each other. The semiconductor device includes: a plurality of epitaxial structures and at least one gate structure formed on the first side of the first substrate; a second substrate, including the first side and the second side opposite to each other; a first metal layer formed on the first side of the second substrate; a second metal layer formed on the first side of the second substrate; a dielectric layer inserted between the first metal layer and the second metal layer; and a bonding layer inserted between the second side of the first substrate and the second side of the second substrate. The first metal layer, the second metal layer, and the dielectric layer are operatively configured to form a capacitor on the first side of the second substrate, the capacitor being coupled to at least one of the plurality of epitaxial structures on the first side of the first substrate. Each of the first metal layer, the dielectric layer, and the second metal layer includes at least one vertical portion extending toward or away from the first substrate.
[0197] In some embodiments, a first metal layer is disposed in a first metallization layer formed in a plurality of metallization layers on a first side of a second substrate, and a second metal layer is disposed in a second of these metallization layers. In some embodiments, the first and second metallization layers are vertically adjacent to each other without any other metallization layers inserted between them. In some embodiments, the first and second metallization layers are vertically adjacent to each other with at least one other metallization layer inserted between them. In some embodiments, the dielectric layer comprises a high-k dielectric material. In some embodiments, the dielectric layer comprises a ferroelectric material. In some embodiments, the first metal layer is electrically coupled to a first of these epitaxial structures, and the second metal layer is electrically coupled to a second of these epitaxial structures. In some embodiments, these epitaxial structures are laterally disposed on a plurality of sides of at least one gate structure. In some embodiments, the first and second metal layers each comprise copper or aluminum. In some embodiments, the first and second metal layers comprise a variety of different materials. In some embodiments, each of the first metal layer, the dielectric layer, and the second metal layer includes one or more lateral portions connected to the corresponding at least one vertical portion.
[0198] In another embodiment of this disclosure, a semiconductor device is disclosed. The semiconductor device includes: a substrate including a first side and a second side opposite to each other; a plurality of transistors formed on the first side of the substrate; a first metal layer formed on the second side of the substrate; a second metal layer formed on the second side of the substrate; and a dielectric layer inserted between the first metal layer and the second metal layer. Each of the first metal layer, the dielectric layer, and the second metal layer includes a vertical portion extending toward or away from the first side of the substrate and a lateral portion connected to the vertical portion.
[0199] In some embodiments, the first metal layer, the dielectric layer, and the second metal layer operatively form a capacitor. In some embodiments, the dielectric layer comprises either a ferroelectric material or a high-k dielectric material. In some embodiments, the first metal layer and the second metal layer each comprise copper or aluminum. In some embodiments, the semiconductor device further includes a third metal layer formed within the dielectric layer between the first and second metal layers. In some embodiments, the first metal layer, the dielectric layer, and the second metal layer operatively form a capacitor. In some embodiments, the dielectric layer comprises either a ferroelectric material or a high-k dielectric material. In some embodiments, the first metal layer and the second metal layer each comprise copper or aluminum. In some embodiments, the semiconductor device further includes a third metal layer formed within the dielectric layer between the first and second metal layers. In some embodiments, the first metal layer, the second metal layer, the third metal layer located within the dielectric layer, and the dielectric layer form a plurality of capacitors connected in parallel with each other.
[0200] In another embodiment of this disclosure, a method for forming a semiconductor device is disclosed. This method includes: forming a plurality of transistors on the front side of a first substrate, wherein each of the plurality of transistors includes at least one epitaxial structure; forming a first metal layer, a second metal layer, and a dielectric layer inserted between the first metal layer and the second metal layer on the front side of a second substrate, wherein each of the first metal layer, the dielectric layer, and the second metal layer includes a vertical portion extending toward or away from the second substrate; and bonding the first substrate to the second substrate, wherein the back side of the first substrate faces the back side of the second substrate.
[0201] In some embodiments, the method further includes forming an interlayer dielectric over the front side of the second substrate; etching the interlayer dielectric to form a trench; depositing a metal material to at least line the trench, thereby forming a first metal layer; depositing a dielectric material to at least line the trench, thereby forming a dielectric layer; and depositing a metal material to fill the trench, thereby forming a second metal layer; wherein the metal material is copper. In some embodiments, the method further includes: depositing a metal material over the front side of the second substrate; etching the metal material to form a first metal layer; depositing a dielectric material to line the first metal layer, thereby forming a dielectric layer; and depositing a metal material to line the dielectric layer, thereby forming a second metal layer; wherein the metal material is aluminum.
[0202] In another embodiment disclosed herein, a semiconductor device is provided, comprising a first substrate, a second substrate, a first metal layer, a second metal layer, a dielectric layer, and a bonding layer. The first substrate includes a first side and a second side opposite to each other. A plurality of epitaxial structures and at least one gate structure are formed on the first side of the first substrate. The second substrate includes a first side and a second side opposite to each other. A first metal layer is formed on the first side of the second substrate. A second metal layer is formed on the first side of the second substrate. The first metal layer is disposed in one of the first metal layers, which are formed in a plurality of metallization layers on the first side of the second substrate, and the second metal layer is disposed in a second of these metallization layers. A dielectric layer is inserted between the first metal layer and the second metal layer. A bonding layer is inserted between the second side of the first substrate and the second side of the second substrate. Each of the first metal layer, the dielectric layer, and the second metal layer includes at least one vertical portion extending toward or away from the first substrate.
[0203] As used herein, the terms “about” and “approximately” generally indicate the value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term “about” may indicate, for example, the value of a given quantity that varies within 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).
[0204] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.
Claims
1. A semiconductor device, characterized in that, Include: A first substrate includes a first side and a second side that are opposite to each other; Multiple epitaxial structures and at least one gate structure are formed on the first side of the first substrate; A second substrate includes a first side and a second side that are opposite to each other; A first metal layer is formed on the first side of the second substrate; A second metal layer is formed on the first side of the second substrate; A dielectric layer is inserted between the first metal layer and the second metal layer; and A bonding layer is inserted between the second side of the first substrate and the second side of the second substrate; The first metal layer, the second metal layer, and the dielectric layer are operably configured to form a capacitor on the first side of the second substrate, the capacitor being coupled to at least one of the plurality of epitaxial structures on the first side of the first substrate, and each of the first metal layer, the dielectric layer, and the second metal layer includes at least one vertical portion extending toward or away from the first substrate.
2. The semiconductor device as claimed in claim 1, characterized in that, The first metal layer is electrically coupled to a first of the plurality of epitaxial structures, and the second metal layer is electrically coupled to a second of the plurality of epitaxial structures.
3. The semiconductor device as claimed in claim 1, characterized in that, The plurality of epitaxial structures are laterally disposed on a plurality of sides of the at least one gate structure.
4. The semiconductor device as claimed in claim 1, characterized in that, Each of the first metal layer, the dielectric layer, and the second metal layer includes one or more lateral portions connected to the corresponding at least one vertical portion.
5. A semiconductor device, characterized in that, Include: A substrate, including a first side and a second side opposite to each other; Multiple transistors are formed on the first side of the substrate; A first metal layer is formed on the second side of the substrate; A second metal layer is formed on the second side of the substrate; and A dielectric layer is inserted between the first metal layer and the second metal layer; Each of the first metal layer, the dielectric layer, and the second metal layer includes a vertical portion extending toward or away from the first side of the substrate and a lateral portion connected to the vertical portion.
6. The semiconductor device as claimed in claim 5, characterized in that, It further includes a third metal layer formed within the dielectric layer between the first metal layer and the second metal layer.
7. The semiconductor device as claimed in claim 6, characterized in that, The first metal layer, the second metal layer, the third metal layer located within the dielectric layer, and the dielectric layer form a plurality of capacitors connected in parallel to each other.
8. A semiconductor device, characterized in that, Include: A first substrate includes a first side and a second side that are opposite to each other; Multiple epitaxial structures and at least one gate structure are formed on the first side of the first substrate; A second substrate includes a first side and a second side that are opposite to each other; A first metal layer is formed on the first side of the second substrate; A second metal layer is formed on the first side of the second substrate, wherein the first metal layer is disposed in a first one, the first one is formed in a plurality of metallization layers on the first side of the second substrate, and the second metal layer is disposed in a second one of the plurality of metallization layers. A dielectric layer is inserted between the first metal layer and the second metal layer; and A bonding layer is inserted between the second side of the first substrate and the second side of the second substrate; Each of the first metal layer, the dielectric layer, and the second metal layer includes at least one vertical portion extending toward or away from the first substrate.
9. The semiconductor device as claimed in claim 8, characterized in that, One of the first metallization layers and one of the second metallization layers are vertically adjacent to each other, without any other metallization layers inserted between them.
10. The semiconductor device as claimed in claim 8, characterized in that, One of the first metallization layers and one of the second metallization layers are arranged vertically adjacent to each other, with at least one of the plurality of metallization layers inserted between them.