Power Module

Abstract

This disclosure provides a power module, including: a silicon carbide chip; a substrate including an upper copper layer; a buffer layer located between the silicon carbide chip and the upper copper layer; and a first connection layer and a second connection layer. The silicon carbide chip and the buffer layer are connected through the first connection layer, and the buffer layer and the upper copper layer are connected through the second connection layer. The buffer layer is a copper-molybdenum alloy layer with a thermal expansion coefficient between that of the silicon carbide chip and the upper copper layer. The copper-molybdenum alloy buffer layer forms a dual-interface stress buffer structure between the silicon carbide chip and the upper copper layer, thereby significantly improving the thermal fatigue life of the first connection layer and the second connection layer, thus balancing the reliability and heat dissipation performance of the power module.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and more specifically, to a power module. Background Technology

[0002] With the increasing prevalence of silicon carbide (SiC) devices in high-voltage, high-temperature, and high-frequency applications, their packaging reliability has become a prominent issue. When the packaging structure of traditional silicon-based power modules is directly applied to SiC chips, the significant difference in the coefficient of thermal expansion (CTE) between SiC and copper makes the solder layer prone to cracking during power cycling, leading to increased thermal resistance and even device failure. Existing technologies attempt to alleviate thermal stress by thickening the solder layer, but increasing the solder layer thickness reduces thermal conductivity. Therefore, there is an urgent need for a packaging structure that can effectively mitigate the CTE mismatch between the SiC chip and the copper substrate while balancing thermal performance and reliability. Utility Model Content

[0003] This disclosure addresses the aforementioned problem by proposing a power module that effectively mitigates the CTE mismatch between the silicon carbide chip and the copper substrate by setting a molybdenum-copper alloy buffer layer between the silicon carbide chip and the copper layer on the substrate.

[0004] A power module provided according to an embodiment of this disclosure includes:

[0005] Silicon carbide chips;

[0006] Substrate, the substrate including an upper copper layer;

[0007] A buffer layer is located between the silicon carbide chip and the upper copper layer; and

[0008] A first interconnect layer and a second interconnect layer are provided. The silicon carbide chip is connected to the buffer layer via the first interconnect layer, and the buffer layer is connected to the upper copper layer via the second interconnect layer.

[0009] The buffer layer is a copper-molybdenum alloy layer, and its coefficient of thermal expansion is between that of the silicon carbide chip and the upper copper layer.

[0010] Optionally, the first connecting layer and / or the second connecting layer are silver sintered layers.

[0011] Optionally, the thickness of the buffer layer ranges from 0.1 to 0.3 mm.

[0012] Optionally, the substrate further includes a lower copper layer and an insulating layer, the insulating layer being sandwiched between the upper copper layer and the lower copper layer.

[0013] Optionally, it also includes a base plate and a third connecting layer, wherein the base plate and the lower copper layer are connected by the third connecting layer.

[0014] Optionally, it also includes an encapsulation layer covering the silicon carbide chip, buffer layer, substrate, first interconnect layer, second interconnect layer and third interconnect layer.

[0015] Optionally, the encapsulation layer is a silicone gel layer or an epoxy resin layer.

[0016] Optionally, the coefficient of thermal expansion of the buffer layer ranges from 5.3 to 16.5 ppm, and its value forms a continuous gradient transition between the coefficients of thermal expansion of the silicon carbide chip and the upper copper layer.

[0017] Optionally, the molybdenum content in the copper-molybdenum alloy layer is 50% to 80%.

[0018] Optionally, the molybdenum content in the copper-molybdenum alloy layer is 50%, 60%, 70%, or 80%.

[0019] One of the above technical solutions has the following beneficial effects:

[0020] By introducing a copper-molybdenum alloy buffer layer between the silicon carbide chip and the upper copper layer, a dual-interface stress buffer structure is constructed, significantly improving the reliability of the power module under high temperature and temperature cycling conditions. Experimental data show that when the buffer layer uses a 0.2mm thick Cu-80%Mo alloy, the fatigue life of the connection layer at the bottom of the chip (the first connection layer) can reach 5100 cycles, which is about 12 times better than the solution without a buffer layer; while when using a 0.3mm thick Cu-50%Mo alloy, the life of the connection layer at the bottom of the chip reaches 1700 cycles, and the life of the connection layer at the bottom of the buffer layer (the second connection layer) remains at 5200 cycles, achieving a synergistic improvement in the reliability of the interfaces on both sides of the chip and the substrate. This gradient design method, which adjusts the molybdenum content (range 5.3–16.5 ppm) and buffer layer thickness (0.1–0.3 mm) in the copper-molybdenum alloy, ensures a continuous transitional matching of the coefficient of thermal expansion and maintains heat dissipation performance through the high thermal conductivity of the material itself (the thermal conductivity of copper-molybdenum alloy can reach 150–300 W / (m·K)). This solves the contradiction between thermal matching and thermal conductivity in traditional single-material buffer layers.

[0021] Specifically designed for applications requiring drastic temperature variations, such as automotive OBCs and photovoltaic inverters, the use of Cu-50%Mo or Cu-80%Mo alloys as the buffer layer material allows for a chip bottom interconnect layer lifetime exceeding 1000 cycles while maintaining the buffer layer's bottom interconnect layer lifetime at over 5000 cycles—a 3-12 times improvement over traditional solutions. This significantly extends the power module's lifespan under high junction temperature conditions. This packaging method, based on the synergistic optimization of material and structural parameters, provides a systematic solution for the high reliability applications of third-generation semiconductor devices.

[0022] Furthermore, the first and second connecting layers can be formed using a silver sintering process to achieve higher interfacial strength. The encapsulation layer can be made of silicone gel or epoxy resin, and its main functions are moisture protection, oxidation protection, and buffering against minor mechanical shocks.

[0023] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this disclosure. Attached Figure Description

[0024] Figure 1 A three-dimensional structural schematic diagram of a power module according to an embodiment of the present disclosure is shown.

[0025] Figure 2 It shows along Figure 1 A cross-sectional view of the section cut by line AA.

[0026] Figure 3 The fatigue life curves of the first and second connecting layers as the molybdenum content in the molybdenum-copper alloy are shown.

[0027] Figure 4 The fatigue life curves of the first and second connecting layers as the thickness of the buffer layer are shown. Detailed Implementation

[0028] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0029] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0030] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0031] In this description, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in this description, unless otherwise stated, "multiple" means two or more.

[0032] The following will combine Figure 1 and Figure 2The power module structure of the embodiments of this disclosure will be described in detail, wherein, in order to more clearly show the positional relationship between the various structures, Figure 1 The encapsulation layer is not shown.

[0033] like Figure 1 and Figure 2 As shown, the power module of this embodiment includes: a base plate 100, a substrate 200, a buffer layer 300, a chip 400, a first connection layer 10, a second connection layer 20, a third connection layer 30, and a bonding wire 40.

[0034] A substrate 200 is disposed on a base plate 100, wherein the substrate 200 includes an upper copper layer 210, a lower copper layer 220, and an insulating layer 201 sandwiched between the upper copper layer 210 and the lower copper layer 220. The upper copper layer 210 is used to form various wiring patterns to constitute a power main circuit. For example, the upper copper layer 210 includes source wiring 211, drain wiring 212, and gate wiring 213 separated from each other. Of course, those skilled in the art can make other settings for the wiring pattern in the upper copper layer 210 as needed. The lower copper layer 220 is used for heat dissipation and is connected to the base plate 100 through a third connection layer 30.

[0035] The substrate 200 may be, for example, a direct-bonded copper (DBC) substrate, a direct-bonded aluminum (DAB) substrate, an active metal bonded (AMB) substrate, or an insulated metal substrate (IMS). The insulating layer 201 may be made of ceramic materials, such as Al2O3, AlN, BeO, or Si3N4.

[0036] In this embodiment, the insulating layer 201 is preferably a silicon nitride ceramic substrate with a thermal expansion coefficient of 3.2 ppm, which has good matching with the 4.5 ppm of the silicon carbide chip.

[0037] A buffer layer 300 is located between the silicon carbide chip 400 and the upper copper layer 210. The silicon carbide chip 400 and the buffer layer 300 are connected by a first connecting layer 10, and the buffer layer 300 and the upper copper layer 210 are connected by a second connecting layer 20. The buffer layer 300 is a copper-molybdenum alloy layer, and its coefficient of thermal expansion is between that of the silicon carbide chip 400 and the upper copper layer 210.

[0038] The chip 400 disclosed herein may include a diode, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a JFET (Junction Field-Effect Transistor), a HEMT (High Electron Mobility Transistor), or any other suitable controllable or uncontrollable semiconductor device.

[0039] In some specific embodiments, taking a MOSFET silicon carbide chip as an example, a drain electrode is formed on the lower surface of the silicon carbide chip 400, and a gate electrode and a source electrode are formed on the upper surface. The buffer layer 300 is located on the drain wiring 212 of the upper copper layer 210. The source electrode of the silicon carbide chip 400 is connected to the source wiring 211 through the bonding line 40, and the gate electrode of the silicon carbide chip 400 is connected to the gate wiring 213 through the bonding line 40.

[0040] In some embodiments, the first connecting layer 10 and the second connecting layer 20 may be silver sintered layers.

[0041] In some embodiments, the thickness of the buffer layer 300 ranges from 0.1 to 0.3 mm.

[0042] The encapsulation layer 500 covers the silicon carbide chip 400, the buffer layer 300, the substrate 200, the first interconnect layer 10, the second interconnect layer 20, and the third interconnect layer 30. The encapsulation layer 500 may be, for example, a silicone gel layer or epoxy resin.

[0043] In this embodiment of the disclosure, the thickness of the buffer layer 300 and the molybdenum content in the molybdenum-copper alloy can be selected from the material group composed of copper-X%molybdenum (Cu-X%Mo) alloy according to the priority relationship between heat dissipation requirements and reliability requirements of the application scenario. The coefficient of thermal expansion (CTE) of pure copper is about 16.5ppm and the thermal conductivity is about 395W / (mk). The CTE of molybdenum is about 5.3ppm and the thermal conductivity is about 138W / (mk), while the CTE of SiC is about 4.5ppm.

[0044] To better match the CTE between the silicon carbide chip 400 and the upper copper layer 210, while also considering thermal conductivity, when the heat dissipation performance of the power module is required to be high, i.e., when the fatigue life of the second connection layer 20 is required to be high, a copper-molybdenum alloy layer with a low percentage of Mo content can be selected as the buffer layer 300; when the reliability of the power module is required to be high, i.e., when the fatigue life of the first connection layer 10 is required to be high, a copper-molybdenum alloy layer with a high percentage of Mo content can be selected as the buffer layer 300; when both the heat dissipation performance and reliability of the power module need to be considered, a copper-molybdenum alloy layer with a Cu-50% Mo content can be selected as the buffer layer 300.

[0045] Figure 3The fatigue life curves of the first and second connecting layers as the molybdenum content in the molybdenum-copper alloy are shown when the thickness of the buffer layer 300 is 0.2 mm.

[0046] Without the buffer layer 300, the chip 400 would be directly connected to the upper copper layer 210 via the interconnect layer (a sintered silver layer). Since the CTE of the silicon carbide chip 400 is approximately 4.5 ppm, while the CTE of the upper copper layer 210 is approximately 16.5-17 ppm, the CTE mismatch is severe, causing the interconnect layer to experience significant thermal stress under high-temperature conditions. In this case, the fatigue life of the interconnect layer is approximately 420 cycles. Figure 3 As shown:

[0047] When the thickness of the buffer layer 300 is 0.2 mm and a (Cu-20%Mo) molybdenum-copper alloy layer is used, the fatigue life of the first connecting layer 10 is about 300 cycles and the fatigue life of the second connecting layer 20 is about 30,000 cycles.

[0048] When the thickness of the buffer layer 300 is 0.2 mm and a (Cu-50%Mo) molybdenum-copper alloy layer is used, the fatigue life of the first connecting layer 10 is about 1350 cycles and the fatigue life of the second connecting layer 20 is about 7500 cycles.

[0049] When the thickness of the buffer layer 300 is 0.2 mm and a (Cu-60%Mo) molybdenum-copper alloy layer is used, the fatigue life of the first connecting layer 10 is about 2400 cycles and the fatigue life of the second connecting layer 20 is about 4290 cycles.

[0050] When the thickness of the buffer layer 300 is 0.2 mm and a (Cu-70%Mo) molybdenum-copper alloy layer is used, the fatigue life of the first connecting layer 10 is about 3940 cycles and the fatigue life of the second connecting layer 20 is about 2850 cycles.

[0051] When the thickness of the buffer layer 300 is 0.2 mm and a (Cu-80%Mo) molybdenum-copper alloy layer is used, the fatigue life of the first connecting layer 10 is about 5100 cycles and the fatigue life of the second connecting layer 20 is about 2050 cycles.

[0052] When the thickness of the buffer layer 300 is 0.2 mm and a pure molybdenum layer of (100% Mo) is used, the fatigue life of the first connecting layer 10 is about 7200 cycles and the fatigue life of the second connecting layer 20 is about 700 cycles.

[0053] Depend on Figure 3Simulation data shows that the fatigue life of the chip side (first interconnect layer 10) increases with the increase of molybdenum content in the molybdenum-copper alloy, and can be increased to a maximum of about 7200 cycles; the fatigue life of the buffer layer side (second interconnect layer 20) decreases with the increase of molybdenum content in the molybdenum-copper alloy, and can be reduced to a maximum of about 700 cycles. This is because the gap between the buffer layer CTE and the upper copper layer 210 widens, and the stress is transferred upward.

[0054] When the molybdenum content is 50%–80%, the chip-side lifetime is 3–12 times higher than that of the buffer-less scheme (420 cycles), while the buffer-side lifetime is still maintained at over 2000 cycles, thus balancing the reliability of both sides.

[0055] Therefore, under a thickness of 0.2 mm, Cu-50%Mo or Cu-80%Mo can preferably achieve a fatigue life of 1350–5100 cycles on the chip side, while the life on the buffer layer side remains in the range of 2000–7500 cycles.

[0056] Figure 4 The fatigue life curves of the first and second connecting layers as a function of the buffer layer thickness are shown when the buffer layer 300 is made of a (Cu-50%Mo) molybdenum-copper alloy layer.

[0057] like Figure 4 As shown:

[0058] When the thickness of the buffer layer 300 is 0.1 mm and a (Cu-50%Mo) molybdenum-copper alloy layer is used, the fatigue life of the first connecting layer 10 is about 900 cycles and the fatigue life of the second connecting layer 20 is about 13,000 cycles.

[0059] When the thickness of the buffer layer 300 is 0.2 mm and a (Cu-50%Mo) molybdenum-copper alloy layer is used, the fatigue life of the first connecting layer 10 is about 1350 cycles and the fatigue life of the second connecting layer 20 is about 7500 cycles.

[0060] When the thickness of the buffer layer 300 is 0.3 mm and a (Cu-50%Mo) molybdenum-copper alloy layer is used, the fatigue life of the first connecting layer 10 is about 1700 cycles and the fatigue life of the second connecting layer 20 is about 5200 cycles.

[0061] Depend on Figure 4 Simulation data shows that the fatigue life of the first connecting layer 10 increases with the increase of the thickness of the buffer layer 300, while the fatigue life of the second connecting layer 20 decreases with the increase of the thickness of the buffer layer 300.

[0062] Combination Figure 3 and Figure 4Simulation data shows that the molybdenum content and thickness of the copper-molybdenum alloy buffer layer 300 have a significant regulatory effect on the interface fatigue life between the first connecting layer 10 and the second connecting layer 20.

[0063] In some embodiments, the buffer layer 300 may be selected as a molybdenum-copper alloy layer with a molybdenum content of 50%–80%, thereby simultaneously improving the fatigue life of the first connecting layer 10 and the second connecting layer 20, while taking into account both thermal performance and reliability.

[0064] In some preferred embodiments, the buffer layer 300 may be selected as a molybdenum-copper alloy layer with a molybdenum content of 50%, 60%, 70%, or 80%.

[0065] When the molybdenum content increases from 20% to 80%, the coefficient of thermal expansion of the buffer layer 300 gradually decreases from 13.8 ppm to 7.2 ppm, approaching the coefficient of thermal expansion of the silicon carbide chip 400 (4.5 ppm), while forming a smoother transition gradient with the upper copper layer 210 (16.5 ppm). This gradient design allows thermal stress to exhibit stratified attenuation characteristics in the three-layer structure of chip 400-buffer layer 300-upper copper layer 210, avoiding early failure caused by concentrated stress at a single interface. For example, when using a Cu-80%Mo alloy, the fatigue life of the first interconnect layer 10 (chip-buffer layer) increases to 5100 cycles, 12 times higher than the solution without a buffer layer, while the life of the second interconnect layer 20 (buffer layer-upper copper layer), although reduced to 2050 cycles, is still significantly better than the reliability level of a traditional single solder layer.

[0066] Furthermore, the synergistic effect of the thickness of the buffer layer 300 and the molybdenum content has a nonlinear influence on the thermal stress distribution. When the thickness of the buffer layer 300 increases from 0.1 mm to 0.3 mm, the fatigue life of the first connecting layer 10 shows an approximately linear increase, while the life of the second connecting layer 20 decreases with increasing thickness. This is because the thicker buffer layer 300 generates a larger amount of strain energy absorption during thermal cycling, causing the stress distribution to shift to the second connecting layer 20. Therefore, in applications such as on-board chargers (OBCs) that require withstanding severe temperature shocks, a 0.2mm thick Cu-50%Mo alloy with a CTE of 10.9ppm is preferred. This allows the first connection layer 10 to achieve a lifespan of 1350 cycles while maintaining the stability of the second connection layer 20 for 7500 cycles. In scenarios such as photovoltaic inverters where long-term high-temperature durability is paramount, a 0.3mm thick Cu-50%Mo alloy is used. By adding a buffer layer of 300 cubic meters to further disperse thermal stress, the lifespan of the first connection layer 10 reaches 1700 cycles, while the lifespan of the second connection layer 20 remains at 5200 cycles. This application-scenario-based parameter optimization method, through dual-dimensional control of material CTE and structural thickness, achieves a balance of reliability for the power module under extreme operating conditions, solving the technical bottleneck of balancing heat dissipation performance and mechanical stability in traditional packaging structures.

Claims

1. A power module, characterized in that, include: Silicon carbide chips; Substrate, the substrate including an upper copper layer; A buffer layer is located between the silicon carbide chip and the upper copper layer; as well as A first interconnect layer and a second interconnect layer are connected, wherein the silicon carbide chip and the buffer layer are connected through the first interconnect layer, and the buffer layer and the upper copper layer are connected through the second interconnect layer. The buffer layer is a copper-molybdenum alloy layer.

2. The power module according to claim 1, characterized in that, The first connecting layer and / or the second connecting layer are silver sintered layers.

3. The power module according to claim 1, characterized in that, The thickness of the buffer layer ranges from 0.1 to 0.3 mm.

4. The power module according to claim 1, characterized in that, The coefficient of thermal expansion of the buffer layer ranges from 5.3 to 16.5 ppm, and its value forms a continuous gradient transition between the coefficient of thermal expansion of the silicon carbide chip and the upper copper layer.

5. The power module according to any one of claims 1 to 4, characterized in that, The substrate further includes a lower copper layer and an insulating layer, with the insulating layer sandwiched between the upper copper layer and the lower copper layer.

6. The power module according to claim 5, characterized in that, It also includes a base plate and a third connecting layer, wherein the base plate and the lower copper layer are connected by the third connecting layer.

7. The power module according to claim 6, characterized in that, It also includes an encapsulation layer that covers the silicon carbide chip, buffer layer, substrate, first interconnect layer, second interconnect layer and third interconnect layer.

8. The power module according to claim 7, characterized in that, The encapsulation layer is a silicone gel layer or an epoxy resin layer.

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