Packaging framework and packaging structure

Abstract

A packaging frame and packaging structure are disclosed. The packaging frame includes a first base island and a second base island. The first base island includes a first base island body and a first notch located at a first corner of the first base island body. The first base island body includes a first device mounting surface located on a first plane. The second base island has its orthographic projection on the first surface located at the first notch. The second base island includes a second device mounting surface located on a second plane different from the first plane. This packaging frame is compatible with power chips at different potentials and ensures sufficient insulation spacing between power chips at different potentials.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a packaging framework and packaging structure. Background Technology

[0002] With the development of integrated circuits, integrated circuits are becoming smaller and smaller. Based on the packaging requirements of low cost and high packaging quantity, multi-chip integrated packaging has become the development trend of packaging.

[0003] In the packaging framework of multi-chip integrated packaging, the base island design that carries the chip mostly adopts a single or two base island design. This design can package a small number of chips, making it difficult to achieve the overall packaging of power chips with different potentials. In addition, the framework conducts heat quickly, resulting in poor chip heat dissipation and high manufacturing cost. Utility Model Content

[0004] At least one embodiment of this disclosure provides a packaging frame including a first base island and a second base island. The first base island includes a first base island body and a first notch located at a first corner of the first base island body. The first base island body includes a first device mounting surface, which is located on a first plane. The second base island is projected onto the first surface at the first notch. The second base island includes a second device mounting surface, which is located on a second plane different from the first plane.

[0005] For example, in the packaging framework provided in at least one embodiment of this disclosure, the first base island further includes a second clearance notch located at a second corner of the first base island body, and the packaging framework further includes: a third base island spaced apart from the first base island body, the orthographic projection of which is located on the first surface at the second notch, wherein the third base island includes a third device mounting surface, and the third device mounting surface is located on the second plane.

[0006] For example, in the packaging framework provided in at least one embodiment of this disclosure, the area of ​​the first device mounting surface is greater than the sum of the areas of the second device mounting surface and the third device mounting surface.

[0007] For example, in the packaging framework provided in at least one embodiment of this disclosure, the area of ​​the second device mounting surface is the same as the area of ​​the third device mounting surface, and the second base island and the third base island are symmetrically arranged.

[0008] For example, in the packaging framework provided in at least one embodiment of this disclosure, the orthographic projection of the second base island on the first surface does not overlap with the first device mounting surface, and the orthographic projection of the third base island on the first surface does not overlap with the second device mounting surface.

[0009] For example, at least one embodiment of the present disclosure provides a packaging framework that further includes: a plurality of first pins, at least one second pin, and at least one third pin; the plurality of first pins include a first pin portion disposed on a first side of the first base island body and a second pin portion disposed on a second side of the first base island body, wherein the first side is opposite to the second side, at least one second pin is disposed on the first side, integrally connected to the second base island, and disposed in parallel with the first pin portion, and at least one third pin is disposed on the second side, integrally connected to the third base island, and disposed in parallel with the second pin portion.

[0010] For example, in the packaging framework provided in at least one embodiment of this disclosure, the plurality of first pins are spaced apart from the first base island body.

[0011] For example, in the packaging framework provided by at least one embodiment of this disclosure, each of the plurality of first pins includes a first pin body and a first pin end located at the end of the first pin body. The first pin body is located in the second plane, and the first pin end is located in the third plane by bending. The third plane is different from the first plane and the second plane.

[0012] For example, in the packaging framework provided by at least one embodiment of this disclosure, each of the at least one second pin includes a second pin body and a second pin end located at the end of the second pin body, the second pin body being located in the second plane and integrally connected to the second base island, and the second pin end being located in the third plane by bending. Each of the at least one third pin includes a third pin body and a third pin end located at the end of the third pin body, the third pin body being located in the second plane and integrally connected to the third base island, and the third pin end being located in the third plane by bending.

[0013] For example, in the packaging framework provided in at least one embodiment of this disclosure, the thickness of the first base island body is greater than or equal to the thickness of the second base island and greater than or equal to the thickness of the third base island.

[0014] For example, in at least one embodiment of the present disclosure, the first plane is parallel to the second plane in the encapsulation framework.

[0015] For example, in the packaging frame provided in at least one embodiment of this disclosure, on a fourth plane perpendicular to the first plane, the orthographic projection of the first base island does not overlap with the orthographic projection of the second base island, nor with the orthographic projection of the third base island; or, the orthographic projection of the first base island is connected to the orthographic projection of the second base island, and is connected to the orthographic projection of the third base island.

[0016] For example, in the packaging framework provided in at least one embodiment of this disclosure, the first base island further includes a third notch located at the third corner of the first base island body, and the packaging framework further includes: a fourth base island spaced apart from the first base island body, the orthographic projection of which is located on the first surface at the third notch, wherein the fourth base island includes a fourth device mounting surface, and the fourth device mounting surface is located in the second plane.

[0017] For example, in the packaging framework provided in at least one embodiment of this disclosure, the area of ​​the first device mounting surface is greater than the sum of the areas of the second device mounting surface, the third device mounting surface, and the fourth device mounting surface.

[0018] For example, in the packaging framework provided in at least one embodiment of this disclosure, the first base island further includes a fourth notch located at the fourth corner of the first base island body, and the packaging framework further includes: a fifth base island spaced apart from the first base island body, the orthographic projection of which is located on the first surface at the fourth notch, wherein the fifth base island includes a fifth device mounting surface, and the fifth device mounting surface is located in the second plane.

[0019] For example, in the packaging framework provided in at least one embodiment of this disclosure, the area of ​​the first device mounting surface is greater than the sum of the areas of the second device mounting surface, the third device mounting surface, the fourth device mounting surface, and the fifth device mounting surface.

[0020] For example, in the encapsulation framework provided in at least one embodiment of this disclosure, the first base island body includes a plurality of protruding connecting ribs, and at least a portion of the edges of the plurality of protruding connecting ribs are configured to form the first notch and the second notch.

[0021] At least one embodiment of this disclosure also provides a packaging structure, which includes: a packaging frame, a first chip, a second chip, and a packaging material provided in the embodiments of this disclosure; wherein, the first base island body further includes a first back surface opposite to the first device mounting surface, the first chip is mounted on the first device mounting surface, the second chip is mounted on the second device mounting surface, the power of the first chip is greater than the power of the second chip, the packaging material encapsulates the packaging frame, exposes the pin ends of a plurality of pins of the packaging frame, and exposes the first back surface.

[0022] For example, in the packaging structure provided in at least one embodiment of this disclosure, the first chip has a voltage withstand range of 400V-1300V and a current range of 50A-200A.

[0023] In the packaging framework provided in this embodiment, the first surface where the first device mounting surface of the first base island is located is different from the second plane where the second device mounting surface of the second base island is located, thereby creating a height difference. This increases the insulation distance between the chip mounted on the first base island and the chip mounted on the second base island, extending the creepage distance. The first device mounting surface of the first base island can be used to mount high-power chips, while the second base island at its corners can be used to mount low-power chips. This allows the packaging framework to be compatible with power chips at different potentials. Furthermore, the first base island, located at the center, can primarily serve a heat dissipation function, improving heat dissipation efficiency. At the same time, the first base island and the second base island at its corners form a regular structure, which helps to reduce the space occupied and makes the structure more compact while ensuring device reliability. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0025] Figures 1-3 The three-dimensional structural diagrams of the packaging frame provided in at least one embodiment of this disclosure along different directions are shown.

[0026] Figure 4 for Figures 1-3 Top view of the encapsulation framework in the image;

[0027] Figure 5 for Figures 1-3 Side view of the encapsulation frame in the middle;

[0028] Figure 6 for Figures 1-3 Another view of the encapsulation frame in the middle;

[0029] Figure 7 A top view of another encapsulation frame provided for at least one embodiment of this disclosure;

[0030] Figure 8 A top view of another encapsulation framework provided in at least one embodiment of this disclosure;

[0031] Figure 9 A top view of another encapsulation frame provided for at least one embodiment of this disclosure;

[0032] Figure 10 A top view of another encapsulation frame provided for at least one embodiment of this disclosure;

[0033] Figure 11 This is a top view of the packaging structure provided in at least one embodiment of the present disclosure;

[0034] Figure 12A side view of the packaging structure provided in at least one embodiment of this disclosure;

[0035] Figure 13 A top view of another packaging structure provided in at least one embodiment of this disclosure;

[0036] Figure 14 A top view of another packaging structure provided in at least one embodiment of this disclosure;

[0037] Figure 15 A top view of another packaging structure provided in at least one embodiment of this disclosure;

[0038] Figure 16 A top view of another packaging structure provided in at least one embodiment of this disclosure;

[0039] Figure 17 A circuit diagram of a plurality of chips provided for at least one embodiment of this disclosure. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0042] As mentioned above, in the packaging framework of multi-chip integrated packaging, the base island design that carries the chip mostly adopts a single or two base island design. This design can only package a small number of chips, often only one or two chips, and it is difficult to achieve the overall packaging of power chips with different potentials (e.g., different bottom potentials).

[0043] In some implementations, a substrate, such as a ceramic substrate, can be added to the bottom of the chip to isolate the potentials of power chips at different potentials; however, adding a substrate increases the process, increases costs, and increases thermal resistance. For example, the JC thermal resistance (junction-to-case thermal resistance) will increase by about 2 times. For instance, when using an alumina ceramic substrate for potential isolation, the thermal resistance within the package will be significantly increased, resulting in poor chip heat dissipation.

[0044] In some implementations, the problem of incompatibility between chips with different bottom potentials on the package base island can be solved by splitting the thermal pad, for example, by forming multiple electrically isolated areas on the circuit board. However, this method will cause different potentials in different areas on the circuit board. In this case, using a non-conductive TIM (thermal interface material) to connect different areas will lead to increased thermal resistance and poor chip heat dissipation.

[0045] In addition, the creepage distance between different potentials is also a key factor limiting package size, which needs to be considered in the package frame design, thus increasing the design difficulty.

[0046] At least one embodiment of this disclosure provides a packaging frame, which includes a first base island and a second base island. The first base island includes a first base island body and a first notch located at a first corner of the first base island body. The first base island body includes a first device mounting surface, which is located on a first plane. The second base island is projected onto the first surface at the first notch. The second base island includes a second device mounting surface, which is located on a second plane different from the first plane.

[0047] In the packaging framework provided in this embodiment, the first surface where the first device mounting surface of the first base island is located is different from the second plane where the second device mounting surface of the second base island is located, thereby creating a height difference. This increases the insulation distance between the chip mounted on the first base island and the chip mounted on the second base island, extending the creepage distance. The first device mounting surface of the first base island can be used to mount high-power chips, while the second base island at its corners can be used to mount low-power chips. This allows the packaging framework to be compatible with power chips at different potentials. Furthermore, the first base island, located at the center, can primarily serve a heat dissipation function, improving heat dissipation efficiency. At the same time, the first base island and the second base island at its corners form a regular structure, which helps to reduce the space occupied and makes the structure more compact while ensuring device reliability.

[0048] At least one embodiment of this disclosure provides a packaging structure, which includes a packaging frame, a first chip, a second chip, and a packaging material provided in the embodiments of this disclosure; wherein, the first base island body also includes a first back surface opposite to the first device mounting surface, the first chip is mounted on the first device mounting surface, the second chip is mounted on the second device mounting surface, the power of the first chip is greater than the power of the second chip, the packaging material encapsulates the packaging frame, exposes the pin ends of a plurality of pins of the packaging frame, and exposes the first back surface.

[0049] In the packaging structure provided in this embodiment, after the chip is packaged using a packaging material, such as a plastic mold, the pin ends of multiple pins are exposed, enabling electrical connection with the device. The first back side of the first base island is exposed, allowing direct connection / contact with the device to improve heat dissipation efficiency.

[0050] The encapsulation framework and encapsulation structure of this disclosure will be described below through several specific embodiments.

[0051] At least one embodiment of this disclosure provides an encapsulation framework. Figures 1-3 The diagrams show the three-dimensional structure of the packaging frame along different directions. Figure 4 It shows Figures 1-3 Top view of the encapsulation framework in the middle. Figure 5 It shows Figures 1-3 A side view of the encapsulation framework in the image, such as... Figures 1-4 As shown, the packaging frame includes a first base island 10 and a second base island 20. The first base island 10 includes a first base island body 11 and a first notch 12 located at a first corner of the first base island body 11, as shown. Figure 5 As shown, the first base island body 11 includes a first device setting surface S1, which is located on a first plane P1; for example, the first device setting surface S1 is configured to set a first chip, which may be a high-power chip.

[0052] refer to Figure 4 The second base island 20 can be spaced apart from the first base island body 11. The orthographic projection of the second base island 20 on the first surface is located at the first notch 12, for reference. Figure 5 The second base island 20 includes a second device setting surface S2; for example, the second device setting surface S2 is configured to set a second chip, which may be a low-power chip.

[0053] refer to Figure 4 The packaging frame may also include a third base island 30, and the first base island 10 may also include a second notch 13 located at a second corner of the first base island body 11, for example, referring to Figure 4 The third base island 30 can be spaced apart from the main body 11 of the first base island. The orthographic projection of the third base island 30 on the first surface is located at the second notch 13, for reference. Figure 5 The third base island 30 includes a third device setting surface S3; for example, the third device setting surface S3 is configured to set a third chip, which may be a low-power chip.

[0054] refer to Figure 5 The second device mounting surface S2 and the third device mounting surface S3 are located on a second plane P2, which is different from the first plane P1. Therefore, the first chip mounted on the first device mounting surface S1 can be at a different height and spaced further apart from the second chip mounted on the second device mounting surface S2 and the third chip mounted on the third device mounting surface S3. This solves the problem of potential incompatibility at the bottom of different chips, avoids thermal resistance loss caused by adding other dielectric materials such as substrates in some embodiments, and ensures sufficient insulating spacing between chips at different potentials. Furthermore, the second base island 20 and the third base island 30 are respectively located at notches at different corners of the first base island 10, giving the packaging frame formed by the first base island 10, second base island 20, and third base island 30 a regular shape, facilitating arrangement and reducing space occupation. In addition, the first base island located in the middle can primarily serve a heat dissipation function, improving heat dissipation efficiency.

[0055] In the embodiments of this disclosure, since there is a height difference between the first plane P1 and the second plane P2, the bottoms of the second base island 20 and the third base island 30 are empty. In the packaging process, a jig can be used to support the second base island 20 and the third base island 30.

[0056] For example, in Figures 1-5 In the embodiments, reference Figure 4 The first notch 12 and the second notch 13 are located at the upper left and upper right corners of the main body 11 of the first base island, respectively. The first base island 10 is generally rectangular in shape, and the first notch 12 and the second notch 13 are arranged along the short side of the rectangle. For example, in some other embodiments, the first notch 12 and the second notch 13 may also be located at different corners than those in the above embodiments, such as the upper left and lower left corners of the main body 11 of the first base island, or the upper left and lower right corners, or the upper right and lower right corners, or the upper right and lower left corners, etc., which will be described in detail later.

[0057] For example, in some embodiments, such as Figure 5 As shown, the first plane P1 is parallel to the second plane P2. This ensures that the packaged structure formed after chip packaging has a relatively thin thickness. It should be noted that during the manufacturing or use process, there may be errors between the first plane P1 and the second plane P2, resulting in a small angle between them. In this case, the angle between the first plane P1 and the second plane P2 is less than or equal to 10 degrees, which falls under the category of the first plane P1 being parallel to the second plane P2 as described above.

[0058] For example, in some embodiments, such as Figure 5 As shown, the area of ​​the first device mounting surface S1 is greater than the sum of the areas of the second device mounting surface S2 and the third device mounting surface S3. Therefore, the first device mounting surface S1 can accommodate larger high-power chips and helps improve the heat dissipation efficiency of high-power chips.

[0059] For example, in some embodiments, such as Figure 4 As shown, the areas of the second device mounting surface S2 and the third device mounting surface S3 are basically the same, and the second base island 20 and the third base island 30 are symmetrically arranged. This can improve the stress balance of the overall packaging frame after packaging and enhance packaging reliability.

[0060] For example, the symmetry settings described above can include axial symmetry settings and central symmetry settings. Figures 1-4 In the embodiments, reference Figure 4 The second base island 20 and the third base island 30 are along the vertical centerline of the first base island 10. Figure 4 The dotted lines in the diagram are arranged symmetrically along an axis. In other embodiments, the second base island 20 and the third base island 30 may also be arranged symmetrically along the horizontal center line of the first base island 10, or centrally symmetrically along the center point of the first base island 10, which will be described in detail later.

[0061] For example, in other embodiments, the area of ​​the second device setting surface S2 and the area of ​​the third device setting surface S3 may also be different to suit different power chips.

[0062] For example, in some embodiments, reference Figure 4 and Figure 5 The projection of the second base island 20 onto the first surface S1 does not overlap with the first device mounting surface S1, and the projection of the third base island 30 onto the first surface S1 does not overlap with the second device mounting surface S2. This ensures that the first base island 10 is spatially separated from the second base island 20 and the third base island 30, allowing the first chip mounted on the first base island 10 to be spaced further away from the second chip mounted on the second base island 20 and the third chip mounted on the third base island 30. This extends the creepage distance and prevents short circuits, signal crosstalk, and other adverse phenomena between different chips.

[0063] For example, in some embodiments, such as Figure 5As shown, the thickness H1 of the first base island body 11 (i.e., the dimension in the direction perpendicular to the first plane P1) can be greater than or equal to the thickness H2 of the second base island 20 (i.e., the dimension in the direction perpendicular to the first plane P1) and greater than or equal to the thickness H3 of the third base island 30 (i.e., the dimension in the direction perpendicular to the first plane P1). For example, in some examples, the thickness H1 of the first base island body 11 can be greater than the thickness H2 of the second base island 20 and greater than the thickness H3 of the third base island 30. Thus, the thicker first base island body 11 helps to improve the heat dissipation efficiency of the first base island 10.

[0064] For example, in some embodiments, the thickness H2 of the second base island 20 can be substantially the same as the thickness H3 of the third base island 30. During fabrication, the second base island 20 and the third base island 30 can be manufactured using substantially the same standards, thereby simplifying the fabrication process.

[0065] For example, in some embodiments, such as Figure 5 As shown, on the fourth plane perpendicular to the first plane P1, the orthographic projection of the first base island 10 does not overlap with the orthographic projection of the second base island 20, and the orthographic projection of the first base island 10 also does not overlap with the orthographic projection of the third base island 30. Therefore, the entirety of the first base island 10 is at a completely different height from the entirety of the second base island 20 and the third base island 30, and the entirety of the first base island 10 is spaced apart from the entirety of the second base island 20 and the third base island 30 in a direction perpendicular to the first plane P1. Figure 5 This is manifested in the fact that the lower surfaces of the second base island 20 and the third base island 30 are spaced from the first device mounting surface S1 of the first base island 10, which helps to increase the insulation distance between the chip mounted on the first base island 10 and the chip mounted on the second base island 20 and the third base island 30, and extend the creepage distance.

[0066] Alternatively, in other embodiments, such as Figure 6 As shown, on the fourth plane perpendicular to the first plane P1, the orthographic projection of the first base island 10 is in contact with the orthographic projection of the second base island 20 (i.e., exactly at the edge), and the orthographic projection of the first base island 10 is also in contact with the orthographic projection of the third base island 30 (i.e., exactly at the edge). At this time, the entire first base island 10 is at a completely different height from the entire second base island 20 and the third base island 30, which can ensure a certain insulation distance / creep distance and reduce the overall thickness of the packaging frame.

[0067] For example, in some embodiments, such as Figures 1-4As shown, the package frame also includes multiple pins L1 / L2 / L3, which are used to connect the chips disposed on the first base island 10, the second base island 20, and the third base island 30 to other devices, such as circuit boards (PCBs). For example, the package frame includes multiple first pins L1, at least one second pin L2, and at least one third pin L3.

[0068] For example, refer to Figure 4 Multiple first pins L1 include those disposed on the first side of the first base island body 11 ( Figure 4 The first pin portion LP1 (on the left side) and the second side of the first base island body 11 (on the left side) Figure 4 The second pin portion LP2 (right side of the image), the first pin portion LP1 and the second pin portion LP2 each include at least one first pin L1, for example, each includes multiple first pins L1. The multiple first pins L1 are spaced apart from the first base island body 11. For example, the chip disposed on the first base island body 11 can be connected to the multiple first pins L1 by leads.

[0069] The first side of the main body 11 of the first base island is opposite to the second side. Figures 1-4 In the example, the first side is the left side of the first base island body 11, and the second side is the right side of the first base island body 11. In other embodiments, the first side may also be the upper side of the first base island body 11, and the second side may be the lower side of the first base island body 11. The embodiments disclosed herein do not specifically limit this.

[0070] For example, such as Figure 4 As shown, the second pin L2 is located on the first side, integrally connected with the second base island 20, and arranged in parallel with the first pin portion LP1. That is, the second pin L2 and the multiple first pins L1 of the first pin portion LP1 are arranged in a row. The third pin L3 is located on the second side, integrally connected with the third base island 30, and arranged in parallel with the second pin portion LP2. That is, the third pin L3 and the multiple first pins L1 of the second pin portion LP2 are arranged in a row.

[0071] For example, in some examples, the chip disposed on the second base island 20 can be connected to a portion of the first pin L1 in the first pin portion LP1 via a lead wire, and is integrally connected to the second pin L2; the chip disposed on the third base island 30 can be connected to a portion of the first pin L1 in the second pin portion LP2 via a lead wire, and is integrally connected to the third pin L3.

[0072] Therefore, multiple pins of the first base island 10, the second base island 20, and the third base island 30 are respectively arranged on opposite sides of the first base island body 11, for example, only on opposite sides of the first base island body 11. Figure 4(As shown in the diagram, on the left and right sides), so that the chips set on the base island can be connected to other devices (such as circuit boards) from the opposite sides of the first base island body 11, making the connection structure more concentrated, regular, and occupying less space.

[0073] For example, the first base island 10 is roughly rectangular in shape, and the aforementioned pins are arranged in a row along the long side of the rectangle, thereby allowing for a greater number of pins to be arranged to facilitate device connection.

[0074] For example, in Figures 1-4 In the example, the first pin portion LP1 includes 10 first pins L1. In other examples, the number of first pins L1 included in the first pin portion LP1 may be more or less, for example, 8, 9, 11, 12, 15, 20, etc. The embodiments of this disclosure do not specifically limit this; Figures 1-4 In the example, the second pin portion LP2 includes 10 first pins L1. In other examples, the number of first pins L1 included in the second pin portion LP2 may be more or less, such as 8, 9, 11, 12, 15, 20, etc. The embodiments disclosed herein do not specifically limit this. The number of first pins L1 included in the first pin portion LP1 may be the same as or different from the number of first pins L1 included in the second pin portion LP2.

[0075] For example, in Figures 1-4 In the example, the number of second pins L2 is one. In other examples, the number of second pins L2 can also be multiple, such as 2, 3, 4, 5, 6, etc. The embodiments of this disclosure do not specifically limit this. Figures 1-4 In the example, the number of third pins L3 is one. In other examples, the number of third pins L3 can also be multiple, such as 2, 3, 4, 5, 6, etc. The embodiments of this disclosure do not specifically limit this. The number of second pins L2 and the number of third pins L3 can be the same or different.

[0076] For example, by connecting the second pin L2 to the second base island 20 as a whole, and the third pin L3 to the third base island 30 as a whole, the structural stability can be improved.

[0077] For example, such as Figure 5 and Figure 6 As shown, the thickness H4 of the second pin L2 is basically the same as the thickness H2 of the second base island 20, so as to facilitate integral formation, and the thickness H5 of the third pin L3 is basically the same as the thickness H3 of the third base island 30, so as to facilitate integral formation.

[0078] For example, such as Figures 1-4As shown, each first pin L1 includes a first pin body L11 and a first pin end L12 located at the end of the first pin body L11. The first pin body L11 is located on a second plane P2, and the second plane P2 has a height difference with the first plane P1. The first pin body L11 can be configured to be connected to a chip disposed on the first base island body 11 via a lead, such as... Figure 5 and Figure 6 As shown, the first pin end L12 is bent into the third plane P3. The third plane P3 is different from the first plane P1 and the second plane P2, for example, it is parallel to the first plane P1 and the second plane P2. The first pin end L12, which is bent into the third plane P3, is more convenient to connect with other devices, such as circuit boards.

[0079] For example, such as Figures 1-4 As shown, each second pin L2 includes a second pin body L21 and a second pin end L22 located at the end of the second pin body L21. The second pin body L21 is located on the second plane P2 and is integrally connected to the second base island 20. Since the second base island 20 is also located on the second plane P2, the integrally connected second pin body L21 and second base island 20 form a flat whole, as shown. Figure 5 and Figure 6 As shown, the second pin end L22 is bent into the third plane P3. The second pin end L22, which is bent into the third plane P3, is more convenient to connect with other devices, such as circuit boards.

[0080] Similarly, such as Figures 1-4 As shown, each third pin L3 includes a third pin body L31 and a third pin end L32 located at the end of the third pin body L31. The third pin body L31 is located on the second plane P2 and is integrally connected to the third base island 30. Since the third base island 30 is also located on the second plane P2, the integrally connected third pin end L32 and the third base island 30 form a flat whole, as shown. Figure 5 and Figure 6 As shown, the third pin end L32 is bent into the third plane P3. The bending of the third pin end L32 into the third plane P3 makes it easier to connect with other devices, such as circuit boards.

[0081] For example, in some embodiments, such as Figures 1-4 As shown, the first base island body 11 includes a plurality of protruding connecting ribs 14, at least a portion of the edges of the plurality of protruding connecting ribs 14 being configured to form a first notch 12 and a second notch 13, that is, at least a portion of the edges of the plurality of protruding connecting ribs 14 being configured to form sidewalls of the first notch 12 and the second notch 13. Figure 4In the example shown, the vertical edges of the two connecting ribs 14 located on the upper side of the first base island body 11 form the sidewalls of the first notch 12 and the second notch 13, respectively, and the edge of the first base island body 11 forms the other sidewall of the first notch 12 and the second notch 13. At this time, the connecting ribs 14 are arranged adjacent to the notches, and the connecting ribs 14 can play a connecting and supporting role during the preparation or use process.

[0082] For example, in Figures 1-4 In the example, there are four connecting ribs 14, which are respectively set on the opposite sides of the first base island body 11, shown as the upper and lower sides in the figure; in other examples, the number of connecting ribs 14 can be more or less, which can be set according to the needs.

[0083] For example, in some embodiments, such as Figures 1-4 As shown, the first base island body 11 may further include multiple support members 18. Two support members 18 arranged opposite each other are shown in the figure as an example. During preparation or use, the support members 18 can provide support for the first base island 10. For example, the support members 18 can be respectively arranged between two adjacent connecting ribs 14. The embodiments of this disclosure do not limit the specific arrangement of the support members 18.

[0084] For example, Figure 7 This illustration shows a top view of another packaging frame provided in at least one embodiment of the present disclosure, which, in other embodiments, is similar to the one described above. Figures 1-6 The embodiments differ from those, such as Figure 7 As shown, the second base island 20 and the third base island 30 can be arranged in a centrally symmetrical manner, that is, the second base island 20 and the third base island 30 are arranged in a centrally symmetrical manner along the center point O of the first base island 10. At this time, the first notch 12 and the second notch 13 are located at the lower left corner and the upper right corner of the main body 11 of the first base island, respectively (or in other examples, they are located at the upper left corner and the lower right corner).

[0085] For example, the first base island 10 is roughly rectangular in shape, and the first notch 12 and the second notch 13 are set along the diagonal of the rectangle.

[0086] for Figure 7 Other structural designs of the packaging framework, such as the first base island, second base island, third base island, multiple pins, connecting ribs, and support components, can be found in [reference needed]. Figures 1-6 The specific implementation examples are not described here.

[0087] For example, Figure 8 A top view of another encapsulation framework provided in at least one embodiment of the present disclosure is shown, which in some other embodiments is similar to the one described above. Figures 1-6 The embodiments differ from those, such as Figure 8 As shown, the second base island 20 and the third base island 30 can be along the horizontal centerline of the first base island ( Figure 8 The dashed lines in the diagram are arranged symmetrically. At this time, the first gap 12 and the second gap 13 are located at the upper right corner and the lower right corner of the first base island body 11, respectively (or in other examples, they are located at the upper left corner and the lower left corner).

[0088] For example, the first base island 10 is roughly rectangular in shape, and the first notch 12 and the second notch 13 are set along the long side of the rectangle.

[0089] At this point, the arrangement of multiple pins is similar to... Figures 1-6 The embodiments are slightly different. For example... Figure 8 As shown, in this embodiment, the second pin L2 and the third pin L3 are disposed on the same side of the first base island body 11. For example, the second pin L2 and the third pin L3 are disposed in parallel with the second pin portion LP2 (or in other examples, they are disposed in parallel with the first pin portion LP1). That is, the second pin L2 and the third pin L3 are arranged in a column with the second pin portion LP2, and the second pin L2 and the third pin L3 are respectively disposed on opposite sides of the second pin portion LP2 (the upper and lower sides in the figure). The first pin portion LP1 is arranged in a separate column, and the number of multiple first pins L1 included in the first pin portion LP1 may be different from the number of multiple first pins L1 included in the second pin portion LP2.

[0090] for Figure 8 Other structural designs of the encapsulation frame, such as the first base island, second base island, third base island, connecting ribs, and supporting components, can be found in [reference needed]. Figures 1-6 The specific implementation examples are not described here.

[0091] exist Figures 1-8 In the embodiments described, the packaging frame includes "one large and two small" base islands to accommodate different power chips. In other embodiments, the packaging frame may also include more base islands to accommodate more chips.

[0092] For example, Figure 9 A top view of another encapsulation frame provided in at least one embodiment of the present disclosure is shown, which in some other embodiments is similar to the one described above. Figures 1-6 The embodiments differ from those, such as Figure 9 As shown, the first base island 10 also includes a third notch 15 located at the third corner of the first base island body 11. The packaging frame also includes a fourth base island 40, which is spaced from the first base island body 11. The orthographic projection of the fourth base island 40 onto the first surface P1 is located at the third notch 15. For example, the orthographic projection of the fourth base island 40 onto the first surface P1 is spaced from the first device mounting surface S1 of the first base island 10. The fourth base island 40 includes a fourth device mounting surface, which is located on the second plane P2.

[0093] For example, in Figure 9 In the example, the second base island 20, the third base island 30, and the fourth base island 40 can be located at any three corners of the main body 11 of the first base island. Figure 9 The top left, top right, and bottom left corners are shown. In other examples, they can also be set at the top left, top right, and bottom right corners, or the top left, top left, and bottom right corners, etc. The embodiments disclosed herein do not specifically limit this.

[0094] For example, the specific structure and arrangement of the fourth base island 40 can be basically the same as those of the second base island 20 and the third base island 30, as can be seen in the design of the second base island 20 and the third base island 30. For example, the area of ​​the fourth device mounting surface is basically the same as the area of ​​the second device mounting surface S2 and the area of ​​the third device mounting surface S3, so as to balance the stress of the entire packaging frame after packaging and improve the packaging reliability; or, the area of ​​the fourth device mounting surface is slightly the same as the area of ​​the second device mounting surface S2 and the area of ​​the third device mounting surface S3, so as to be suitable for different power chips.

[0095] For example, the area of ​​the first device mounting surface S1 is greater than the sum of the areas of the second device mounting surface S2, the third device mounting surface S3, and the fourth device mounting surface. In this case, the area of ​​the first device mounting surface S1 is large enough to accommodate larger high-power chips and helps improve the heat dissipation efficiency of high-power chips.

[0096] For example, such as Figure 9 As shown, the package frame includes at least one fourth pin L4 for the fourth base island 40. One fourth pin L4 is shown in the figure as an example. In other embodiments, the fourth pin L4 may be other numbers.

[0097] For example, refer to Figure 9 The fourth pin L4 is located on the first side of the first base island body 11 and is configured to be connected to the fourth base island 40, for example, integrally connected, and arranged in parallel with the first pin portion LP1. That is, the fourth pin L4 and the multiple first pins L1 of the first pin portion LP1 are arranged in a row. For example, the fourth pin L4 and the third pin L3 are respectively located on opposite sides of the first pin portion LP1 (the upper and lower sides in the figure). The fourth pin L4 and the third pin L3 have basically the same structure and can be arranged symmetrically.

[0098] For example, in other examples, when the fourth base island 40 is located at the lower right corner of the first base island body 11, the fourth pin L4 is set on the second side of the first base island body 11 and is arranged in parallel with the second pin portion LP2. That is, the fourth pin L4 and the multiple first pins L1 of the second pin portion LP2 are arranged in a row. At this time, the fourth pin L4 and the second pin L2 are respectively set on opposite sides of the first pin portion LP1. The structures of the fourth pin L4 and the second pin L2 are basically the same and can be arranged symmetrically.

[0099] thus, Figure 9 The packaging framework in this embodiment includes one large and three small base islands to accommodate different power chips. In other embodiments, the packaging framework may also include more base islands to accommodate more chips.

[0100] For example, Figure 10 A top view of another encapsulation frame provided by at least one embodiment of the present disclosure is shown. In some other embodiments, unlike the embodiment described in 9 above, such as... Figure 10 As shown, the first base island 10 also includes a fourth notch 16 located at the fourth corner of the first base island body 11. The packaging frame also includes a fifth base island 50, which is spaced apart from the first base island body 11. The orthographic projection of the fifth base island 50 on the first surface P1 is located at the fourth notch 16. For example, the orthographic projection of the fifth base island 50 on the first surface P1 is spaced apart from the first device mounting surface S1 of the first base island 10. The fifth base island 50 includes a fifth device mounting surface, which is located on the second plane P2.

[0101] For example, such as Figure 10 As shown, the second base island 20, the third base island 30, the fourth base island 40, and the fifth base island 50 are located at the four corners of the first base island body 11. For example, the specific structure and arrangement of the fifth base island 50 can be basically the same as that of the second base island 20 and the third base island 30, as can be seen in the design of the second base island 20 and the third base island 30. For example, the area of ​​the fifth device mounting surface can be basically the same as the area of ​​the second device mounting surface S2, the third device mounting surface S3, and the fourth device mounting surface, so as to balance the stress of the entire packaging frame after packaging and improve the packaging reliability; or, the area of ​​the fifth device mounting surface can be slightly different from the area of ​​the second device mounting surface S2, the third device mounting surface S3, and the fourth device mounting surface, to suit different power chips.

[0102] For example, the area of ​​the first device mounting surface S1 is greater than the sum of the areas of the second device mounting surface S2, the third device mounting surface S3, the fourth device mounting surface, and the fifth device mounting surface. In this case, the area of ​​the first device mounting surface S1 is large enough to accommodate larger high-power chips and helps improve the heat dissipation efficiency of the high-power chips.

[0103] For example, such as Figure 10 As shown, the package frame includes at least one fifth pin L5 for the fifth base island 50. One fifth pin L5 is shown in the figure as an example. In other embodiments, the fifth pin L5 may be other numbers.

[0104] For example, refer to Figure 10 The fifth pin L5 is located on the second side of the first base island body 11 and is configured to be connected to the fifth base island 50, for example, integrally connected, and arranged in parallel with the second pin portion LP2. That is, the fifth pin L5 and the multiple first pins L1 of the second pin portion LP2 are arranged in a row. For example, the fifth pin L5 and the second pin L2 are respectively located on opposite sides of the second pin portion LP2 (shown as the upper and lower sides in the figure). The structures of the fifth pin L5 and the second pin L2 are basically the same and can be arranged symmetrically.

[0105] For example, refer to Figure 10 The fourth pin L4 is located on the first side of the first base island body 11 and is configured to be connected to the fourth base island 40, for example, integrally connected, and arranged in parallel with the first pin portion LP1. That is, the fourth pin L4 and the multiple first pins L1 of the first pin portion LP1 are arranged in a row. For example, the fourth pin L4 and the third pin L3 are respectively located on opposite sides of the first pin portion LP1 (shown as the upper and lower sides in the figure). The fourth pin L4 and the third pin L3 have basically the same structure and can be arranged symmetrically.

[0106] thus, Figure 10 The packaging framework in the embodiment includes a “one large and four small” base islands to accommodate different power chips, making it suitable for a wider range of chip applications.

[0107] In the various packaging frames provided in the embodiments of this disclosure, the first surface where the first device placement surface of the first base island is located is different from the second plane where the second device placement surface of the second base island and the third device placement surface of the third base island are located. This creates a height difference, which increases the insulation distance between the chip on the first base island and the chips on the second and third base islands, thus extending the creepage distance. The first device placement surface of the first base island can be used to place high-power chips, while the second and third base islands at its corners can be used to place low-power chips. This allows the packaging frame to be compatible with power chips at different potentials. Furthermore, the first base island, located at the center, can primarily serve a heat dissipation function, improving heat dissipation efficiency. At the same time, the first base island and the second and third base islands at its corners form a regular structure, which helps to reduce the space occupied and makes the structure more compact while ensuring device reliability.

[0108] At least one embodiment of this disclosure also provides a packaging structure. Figure 11 A top view of the packaging structure is shown. Figure 2 A side view of the packaging structure is shown, as follows: Figure 11 and Figure 12 As shown, the packaging structure includes a packaging frame, a first chip 1, a second chip 2, and a packaging material 60 provided in this embodiment; Reference Figure 5 and Figure 6 The first base island body 11 of the packaging frame also includes a first back surface S10 opposite to the first device mounting surface S1, as shown in the reference. Figure 11 and Figure 12 The first chip 1 is disposed on the first device placement surface S1, the second chip 2 is disposed on the second device placement surface S2, the encapsulation material 60 is configured to encapsulate the encapsulation frame, for example, at least encapsulating the chips 1 / 2 / 3, and the encapsulation material 60 exposes the pin ends L12 / L22 / L32 of a plurality of pins of the encapsulation frame and exposes the first back surface S10.

[0109] For example, such as Figure 11 and Figure 12 As shown, the packaging frame also includes a third base island 30, and the packaging structure also includes a third chip 3, which is disposed on the third device placement surface S3 of the third base island 30.

[0110] It should be noted that, Figure 11 and Figure 12 The dashed lines in the middle indicate the approximate locations of chips 1 / 2 / 3. However, the locations of chips 1 / 2 / 3 are not limited to those shown. The locations can be adjusted according to the specific characteristics of the chips, such as their size.

[0111] For example, the encapsulation material 60 can be a plastic encapsulation or other encapsulation form, which can encapsulate the chip set on the first device setting surface S1, the second device setting surface S2 and the third device setting surface S3, and expose the pin ends L12 / L22 / L32 of multiple pins and the first back surface S10. Thus, after the chip is encapsulated using the encapsulation material 60, the pin ends L12 / L22 / L32 of multiple pins are exposed, which can realize electrical connection with the device (e.g., circuit board). The first back surface S10 of the first base island 10 is exposed, which can directly connect / contact with the device (e.g., circuit board) to improve heat dissipation efficiency.

[0112] For example, in some embodiments, the package structure may include two chips, namely a first chip 1 and a second chip 2. The power of the first chip 1 is greater than that of the second chip 2. In this case, the potential of the first chip 1 is greater than that of the second chip 2. For example, the potential difference between the bottom of the first chip 1 and the bottom of the second chip 2 is approximately 600V to 800V. The first chip 1 is disposed on a first device mounting surface S1, and the second chip 2 is disposed on a second device mounting surface S2. In this case, the first chip 1 and the second chip 2 have sufficient spacing to ensure their normal operation.

[0113] For example, in some embodiments, reference Figure 11 and Figure 12 The package structure may include three chips: a first chip 1, a second chip 2, and a third chip 3. The power of the first chip 1 is greater than that of the second chip 2, and the power of the third chip 3 is also greater than that of the third chip 3. The first chip 1 is disposed on a first device mounting surface S1, the second chip 2 is disposed on a second device mounting surface S2, and the third chip 3 is disposed on a third device mounting surface S3. At this time, the first chip 1 has sufficient spacing from the second chip 2 / third chip 3, while the second chip 2 and third chip 3 are further apart to ensure their normal operation.

[0114] For example, the first chip 1 is a high-power chip, with a voltage rating of 400V-1300V and a current rating of 50A-200A. For example, the first chip 1 includes gallium nitride devices.

[0115] For example, Figure 17 A circuit diagram of multiple chips provided in at least one embodiment of this disclosure, such as Figure 17 As shown, the first chip 1 includes gallium nitride devices T1 and T2, the second chip 2 includes a first driving circuit, and the third chip 3 includes a second driving circuit. The gallium nitride devices T1 and T2, the first driving circuit, and the second driving circuit have the following characteristics: Figure 17The connection relationships shown are as follows: the gate G1 of gallium nitride device T1 is connected to the first end of the first driving circuit (the right end of the first driving circuit in the figure); the gate G2 of gallium nitride device T2 is connected to the first end of the second driving circuit (the right end of the second driving circuit in the figure); the source S1 of gallium nitride device T1 is connected to the drain D2 of gallium nitride device T2; the drain D1 of gallium nitride device T1 is connected to pin IN3; the source S2 of gallium nitride device T2 is connected to pin IN4; pins IN3 and IN4 can be implemented as the first pin mentioned above; the second end of the first driving circuit (the left end of the first driving circuit in the figure) is connected to pin IN1; pin IN1 can be implemented as the second pin mentioned above; and the second end of the second driving circuit (the left end of the second driving circuit in the figure) is connected to pin IN2; pin IN2 can be implemented as the third pin mentioned above.

[0116] For example, Figure 11 and Figure 12 The packaging structure shown uses Figures 1-6 The encapsulation framework shown can be used in other examples as well. Figures 7-10 Encapsulation frameworks, for example, Figure 13 The packaging structure provided in at least one embodiment of this disclosure is shown to employ... Figure 7 The top view of the encapsulation frame shown. Figure 14 The packaging structure provided in at least one embodiment of this disclosure is shown to employ... Figure 8 The top view of the encapsulation frame shown is in Figures 11-14 The packaging framework shown includes one large and two small base islands; for example, when the device requires more chips, a larger array can be used. Figure 9 The packaging frame shown includes one large and three small base islands. The resulting packaging structure is as follows: Figure 15 As shown, the package structure also includes chip 4, which may include, for example, a substrate control circuit; or, it may employ, as shown in the diagram. Figure 10 The packaging frame shown includes one large and four small base islands. The resulting packaging structure is as follows: Figure 16 As shown, the package structure also includes chip 4 and chip 5, which, for example, include substrate control circuits; thus, the package structure can be compatible with more chips.

[0117] In the packaging structure provided in this embodiment, the first chip disposed on the first base island can be at a different height and a greater distance from the second chip disposed on the second base island. This can solve the problem of potential incompatibility at the bottom of different chips, avoid the thermal resistance loss caused by adding other dielectric materials such as substrates in some embodiments, and ensure sufficient insulation spacing between chips with different potentials. In addition, the smaller second base island (which in some embodiments also includes a third / fourth / fifth base island) is disposed at the notches at different corners of the first base island, so that the packaging frame formed by the first base island and the second base island (which in some embodiments also includes a third / fourth / fifth base island) has a regular shape, which facilitates arrangement and helps to reduce the space occupied. Furthermore, the first base island located in the middle position can mainly play a heat dissipation role, improve heat dissipation efficiency, and thus improve the overall heat dissipation effect of the packaging structure.

[0118] The following points also need to be explained:

[0119] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0120] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0121] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0122] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A packaging framework, characterized in that, include: The first base island includes a first base island body and a first notch located at a first corner of the first base island body. The first base island body includes a first device mounting surface, which is situated on a first plane. The second base island, whose orthographic projection onto the first plane is located at the first notch, includes a second device mounting surface. The second device is disposed on a second plane that is different from the first plane.

2. The packaging frame according to claim 1, characterized in that, The first base island also includes a second notch located at the second corner of the main body of the first base island. The encapsulation framework also includes: The third base island is spaced apart from the main body of the first base island, and its orthographic projection on the first plane is located at the second notch. The third base island includes a third device mounting surface, which is located on the second plane.

3. The packaging frame according to claim 2, characterized in that, The area of ​​the first device surface is greater than the sum of the areas of the second device surface and the third device surface.

4. The packaging frame according to claim 2 or 3, characterized in that, The area of ​​the surface on which the second device is mounted is the same as the area of ​​the surface on which the third device is mounted. The second base island and the third base island are arranged symmetrically.

5. The packaging frame according to claim 2 or 3, characterized in that, The orthographic projection of the second base island onto the first plane does not overlap with the surface on which the first device is mounted, and the orthographic projection of the third base island onto the first plane does not overlap with the surface on which the second device is mounted.

6. The packaging frame according to claim 2 or 3, characterized in that, Also includes: A plurality of first pins, including a first pin portion disposed on a first side of the first base island body and a second pin portion disposed on a second side of the first base island body, wherein the first side and the second side are opposite to each other. At least one second pin is disposed on the first side, integrally connected to the second base island, and arranged side-by-side with the first pin portion. At least one third pin is disposed on the second side, integrally connected to the third base island, and disposed in parallel with the second pin portion.

7. The encapsulation frame according to claim 6, characterized in that, The plurality of first pins are spaced apart from the first base island body.

8. The packaging frame according to claim 7, characterized in that, Each of the plurality of first pins includes a first pin body and a first pin end located at the end of the first pin body. The first pin body is located in the second plane. The end of the first pin is bent into a third plane, which is different from the first plane and the second plane.

9. The packaging frame according to claim 8, characterized in that, Each of the at least one second pin includes a second pin body and a second pin end located at the end of the second pin body, the second pin body being situated in the second plane and integrally connected to the second base island, and the second pin end being situated in the third plane by bending. Each of the at least one third pin includes a third pin body and a third pin end located at the end of the third pin body, the third pin body being situated in the second plane and integrally connected to the third base island, and the third pin end being situated in the third plane by bending.

10. The packaging frame according to claim 2 or 3, characterized in that, The thickness of the first base island body is greater than or equal to the thickness of the second base island and greater than or equal to the thickness of the third base island.

11. The packaging frame according to claim 2 or 3, characterized in that, The first plane is parallel to the second plane.

12. The packaging frame according to claim 2 or 3, characterized in that, On a fourth plane perpendicular to the first plane, the orthographic projection of the first base island does not overlap with the orthographic projection of the second base island, nor with the orthographic projection of the third base island. or The orthographic projection of the first base island is connected to the orthographic projection of the second base island, and is also connected to the orthographic projection of the third base island.

13. The packaging frame according to claim 2 or 3, characterized in that, The first base island also includes a third notch located at the third corner of the main body of the first base island. The encapsulation framework also includes: The fourth base island is spaced apart from the main body of the first base island, and its orthographic projection on the first plane is located at the third notch. The fourth base island includes a fourth device mounting surface, which is located on the second plane.

14. The packaging frame according to claim 13, characterized in that, The area of ​​the first device mounting surface is greater than the sum of the areas of the second device mounting surface, the third device mounting surface, and the fourth device mounting surface.

15. The packaging frame according to claim 13, characterized in that, The first base island also includes a fourth notch located at the fourth corner of the main body of the first base island. The encapsulation framework also includes: The fifth base island is spaced apart from the main body of the first base island, and its orthographic projection on the first plane is located at the fourth notch. The fifth base island includes a fifth device mounting surface, which is located on the second plane.

16. The packaging frame according to claim 15, characterized in that, The area of ​​the first device mounting surface is greater than the sum of the areas of the second device mounting surface, the third device mounting surface, the fourth device mounting surface, and the fifth device mounting surface.

17. The encapsulation frame according to claim 2, characterized in that, The first base island body includes a plurality of protruding connecting ribs, at least a portion of the edges of the plurality of protruding connecting ribs being configured to form the first notch and the second notch.

18. A packaging structure, characterized in that, include: The packaging frame according to any one of claims 1-17, wherein the first base island body further includes a first back surface opposite to the surface on which the first device is disposed. The first chip is disposed on the surface of the first device. A second chip is disposed on the surface of the second device, wherein the power of the first chip is greater than the power of the second chip, and The encapsulation material encapsulates the encapsulation frame, exposing the pin ends of a plurality of pins of the encapsulation frame, and exposing the first back side.

19. The packaging structure according to claim 18, characterized in that, The first chip has a voltage rating of 400V-1300V and a current rating of 50A-200A.

Images