Semiconductor device packaging structure

Abstract

This utility model relates to the field of semiconductor technology, specifically to a packaging structure for a semiconductor device. The packaging structure includes: a substrate on which a chip is disposed; a buffer layer sintered to the source region of the chip; and a bonding member, wherein a first lead of the bonding member is connected to the substrate, and a second lead of the bonding member is connected to the buffer layer. The second lead of the bonding member has an arc-shaped portion at its edge, forming a first angle with the buffer layer. The arc-shaped portion is connected to the buffer layer via a bonding pad. The thermal expansion coefficient of the bonding member matches that of the buffer layer. Introducing a buffer layer between the chip and the bonding member, and ensuring that the thermal expansion coefficients of the bonding member and the buffer layer match, reduces the stress on the bonding pad and improves its reliability. Furthermore, the arc-shaped portion effectively increases the thickness of the bonding pad at the arc-shaped portion, thereby enhancing reliability.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and specifically to a packaging structure for a semiconductor device. Background Technology

[0002] In existing power semiconductor device packaging structures, copper clips are widely used in semiconductor packaging due to their advantages over traditional bonding. Currently, in terms of process, copper clips are generally connected to chips and substrates through reflow soldering or silver sintering to achieve electrical transmission between chips, between chips and substrates, and between substrates.

[0003] However, compared to traditional bonding copper wires, copper clips are significantly larger. In actual operating conditions, when subjected to temperature changes, the thermal expansion volume is less compatible with the thermal expansion of the chip, resulting in greater stress on the bonding layer between the copper clip and the chip. Prolonged exposure to this high stress causes more severe plastic strain in the bonding layer, making it more prone to cracking and leading to premature failure. Utility Model Content

[0004] In view of this, the present invention provides a packaging structure for semiconductor devices to solve the problem that the connection layer between the copper clip and the chip is subjected to large stress, which leads to premature failure of the connection layer.

[0005] In a first aspect, the present invention provides a packaging structure for a semiconductor device, the packaging structure comprising: A substrate, on which chips are mounted; A buffer layer is sintered into the source region of the chip; A bonding component, wherein a first pin of the bonding component is connected to the substrate, and a second pin of the bonding component is connected to the buffer layer; and the second pin of the bonding component is provided with an arc-shaped portion at the edge position, the arc-shaped portion and the buffer layer forming a first included angle, and the arc-shaped portion is connected to the buffer layer through a connecting solder layer. The coefficient of thermal expansion of the bonding element matches that of the buffer layer.

[0006] Beneficial Effects: In this embodiment, the buffer layer is sintered to the source region of the chip. Compared to traditional direct sintering of bonding components, the buffer layer has better surface flatness, resulting in more uniform pressure during sintering and making the process easier to implement, thus significantly reducing the process difficulty. Simultaneously, the introduction of a buffer layer between the chip and the bonding component, with the thermal expansion coefficient of the bonding component matching that of the buffer layer, reduces the difference in thermal expansion coefficients between the upper and lower layers of the bonding layer, thereby reducing the stress on the bonding layer and improving its reliability. Furthermore, this embodiment incorporates an arc-initiating section. During welding, the bonding layer climbs upwards along the surface of the arc-initiating section, effectively increasing the thickness of the bonding layer at the arc-initiating section without changing the process conditions, thereby improving reliability. Furthermore, the arc-initiating section can also be provided on both sides of the side welding surface of the buffer layer, further improving the reliability of the copper-clad buffer layer side welding layer.

[0007] In one alternative embodiment, the buffer layer is made of silver, copper-molybdenum alloy, copper-molybdenum-copper, or other materials whose coefficient of thermal expansion matches that of the bonding element.

[0008] In one alternative implementation, the buffer layer is sintered to the source region of the chip using silver paste or silver film.

[0009] In one alternative implementation, the thickness of the buffer layer is within a predetermined range.

[0010] Beneficial Effects: This embodiment sets a certain thickness for the buffer layer, allowing it to more effectively absorb thermal stress caused by temperature changes and reduce mechanical stress in the solder layer caused by the difference in expansion between the upper and lower layers, thereby reducing the risk of cracking. A thicker buffer layer can disperse the stress borne by the solder layer, avoiding stress concentration and delaying solder layer fatigue failure. Increasing the buffer layer thickness helps form a smoother surface during sintering, providing a uniform contact interface for subsequent reflow soldering, reducing welding defects, and improving solder layer integrity. Furthermore, the solder layer between the buffer layer and the bonded component is formed through a reflow soldering process, used to fix the bonded component with the arc-starting section onto the buffer layer. The reliability of the arc-starting section directly affects the electrical connection and mechanical stability between the bonded component and the chip. Therefore, a thicker buffer layer can improve the reliability of the reflow soldering layer.

[0011] In one alternative embodiment, the bonding member includes a first support plate, a second support plate, and a third support plate connected in sequence.

[0012] In one alternative embodiment, the first support plate has a first foot at one end, the third support plate has a second foot at one end, and the second support plate is parallel to the substrate.

[0013] In one optional embodiment, a second included angle is provided between the first support plate and the second support plate, and a third included angle is provided between the third support plate and the second support plate.

[0014] In one alternative embodiment, the widths of both the first and third support plates gradually increase along the direction approaching the second support plate.

[0015] Beneficial effects: By widening the width of the first support plate and the second support plate, this embodiment can increase the overall current flow capacity of the bonded component and increase the overall heat dissipation area of ​​the bonded component without affecting the welding surface.

[0016] In one alternative embodiment, a chip bonding layer is provided on the substrate, and the chip is connected to the substrate through the chip bonding layer.

[0017] In one alternative embodiment, a sintering layer is disposed on the source region of the chip, and the buffer layer is disposed on the sintering layer. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this utility model, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a front view of the packaging structure of the semiconductor device in an embodiment of this utility model; Figure 2 for Figure 1 Top view of the packaging structure shown; Figure 3 for Figure 1 The side view of the packaging structure shown; Figure 4 This is a schematic diagram showing that the first included angle of the arc portion in an embodiment of this utility model is 40°; Figure 5 This is a schematic diagram showing that the first included angle of the arc portion in an embodiment of this utility model is 10°; Figure 6 This is a schematic diagram showing that the arc-starting part is provided on both sides of the welding surface on the buffer layer side in an embodiment of this utility model; Figure 7 This is a schematic diagram showing that the bonding component in this embodiment of the present invention has a ramp. Figure 8 This is a schematic diagram showing the increased width of the bonding component in an embodiment of this utility model.

[0020] Explanation of reference numerals in the attached figures: 1. Substrate; 11. Copper-clad substrate; 12. Ceramic substrate; 2. Chip; 3. Bonding component; 31. First pin; 32. First support plate; 33. Second support plate; 34. Third support plate; 35. Second pin; 36. Arc starting part; 4. Chip solder layer; 5. Sintering layer; 6. Buffer layer; 7. Connecting solder layer. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0022] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0024] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0025] A power module is a modular electronic component that integrates power semiconductor devices, drive circuits, and protection circuits. Its main function is to convert DC power into electrical energy suitable for various electronic power devices. Over the past few decades, power modules have experienced rapid development and widespread application, continuously evolving towards higher power density, high-frequency switching characteristics, and smaller size. This, in turn, places higher demands on the electrical signal transmission capabilities within the module.

[0026] In existing power semiconductor device packaging structures, wire bonding is typically used to achieve electrical connections between chip 2 and substrate 1, and between chips 2 and each other. Common bonding methods include: thick aluminum wire bonding, copper wire bonding, aluminum-clad copper wire bonding, aluminum strip bonding, etc.

[0027] Compared to traditional bonding methods, bonding components 3, such as copper clips, have advantages in high power density and high-frequency switching modules: 1. It has better conductivity, which can reduce on-resistance and power loss. In addition, since the copper clip and chip 2 can achieve a larger contact area, the contact resistance between conductors can also be reduced. 2. It has better thermal conductivity and a larger contact area with chip 2, providing additional heat dissipation pathways. It can also be combined with a top heatsink for natural convection or forced air cooling, allowing the device to consume more power while maintaining the same maximum junction temperature. 3. It has better current carrying capacity. Under the same package type and area conditions, the current carrying capacity of the copper clip is equivalent to that of multiple copper wires. Furthermore, the copper clip allows the current path to be located above chip 2, saving space on substrate 1 and enabling applications in smaller package sizes. 4. Reduce parasitic inductance. Parasitic inductance is related to the permeability and shape of the conductor itself. The longer the bonding wire and the more leads there are, the more parasitic inductance is introduced, limiting the application of devices in high-frequency switches. Compared with leads, copper clips have lower parasitic inductance under the same DC or AC modes. In addition, the distribution of parasitic inductance can be controlled by changing the shape of the copper clip.

[0028] 5. Improve production efficiency. Copper clips can be stamped into the designed shape, offering greater flexibility in horizontal layout and effectively increasing production capacity.

[0029] Therefore, copper clips play a crucial role in packaging applications that meet the requirements of low total device resistance (RDS(on),) high power density, and high-frequency switching. Currently, copper clips are typically connected to chip 2 and substrate 1 via reflow soldering or silver sintering to achieve electrical transmission between chips 2, between chips 2 and substrate 1, and between substrates 1.

[0030] Compared to copper wire, copper clips are significantly larger. In actual working conditions, when subjected to temperature changes, the thermal expansion volume is more mismatched with the thermal expansion of chip 2, resulting in the connection layer bearing greater stress. Long-term exposure to greater stress causes more severe plastic strain in the connection layer, making it prone to cracking and leading to premature failure of the connection layer.

[0031] Currently, silver sintering is commonly used instead of reflow soldering to connect the copper clips and the chip 2. Compared to soldering, the silver sintered layer 5 has higher electrical and thermal conductivity. However, since the copper clips are formed by direct stamping, the processing precision is relatively low. During the pressurized silver sintering process, insufficient flatness of the copper clip surface may lead to uneven pressure from the pressure head, affecting the welding effect. This process is difficult to implement in mass production due to its high complexity. Furthermore, the number of pressure heads is limited, restricting the number of copper clips that can be welded to each pressure head. For multiple complex-shaped copper clips, multiple pressure heads need to work simultaneously during mass production, resulting in low production efficiency and impacting capacity. In addition, the processing time and material costs of silver sintering are significantly higher than reflow soldering, compressing the product's profit margin.

[0032] In view of this, the present invention provides a packaging structure for a semiconductor device to solve the problem that the connection layer between the copper clip and the chip 2 is subjected to large stress, resulting in premature failure of the connection layer.

[0033] The following is combined with Figures 1 to 8 The following describes embodiments of the present invention.

[0034] According to an embodiment of the present invention, in one aspect, a packaging structure for a semiconductor device is provided, the packaging structure including a substrate 1, a chip 2, a buffer layer 6, and a bonding member 3.

[0035] Specifically, in this embodiment, the substrate 1 is typically composed of a copper-clad substrate 11 and a ceramic substrate 12, and a chip 2 is disposed on the substrate 1. For the connection method of the chip 2, solder paste can be added to the pads of the substrate 1 using a dispensing machine or stencil, or solder pads can be placed, and the chip 2 can be placed on top of the substrate 1. The chip 2 is then soldered through four stages: preheating, thermal activation, reflow, and cooling. Alternatively, a silver film or silver paste can be placed at the pads of the substrate 1 using a silver sintering method, achieving the connection between the chip 2 and the substrate 1 under high temperature and high pressure.

[0036] Furthermore, in this embodiment, the buffer layer 6 is sintered to the source region of the chip 2. The solder can be silver paste or silver film. Here, the buffer layer 6 can also be made of silver, copper-molybdenum alloy, copper-molybdenum-copper structure, or other materials whose coefficient of thermal expansion matches that of the bonding element 3.

[0037] Furthermore, in this embodiment, the first pin 31 of the bonding component 3 is connected to the substrate 1, and the second pin 35 of the bonding component 3 is connected to the buffer layer 6. Solder paste is printed on the substrate 1, the soldering position corresponding to the first pin 31 of the bonding component 3, and the buffer layer 6, or solder pads are placed thereon. The bonding component 3 is precisely mounted on the solder. Here, the bonding component 3 may have stress-relieving structures such as grooves, arches, and holes, or it may be made of silver, copper-molybdenum alloy, copper-molybdenum-copper, or other materials with a coefficient of thermal expansion matching that of the buffer layer 6. The mounted bonding component 3 is placed in a soldering device to complete vacuum reflow soldering.

[0038] Furthermore, in this embodiment, the second pin 35 of the bonding member 3 has an arc-shaped portion 36 at its edge. The arc-shaped portion 36 is inclined upward, forming a first angle between the arc-shaped portion 36 and the buffer layer 6. The second pin 35 and the arc-shaped portion 36 of the bonding member 3 are connected to the buffer layer 6 via a connecting solder layer 7. The first pin 31 of the bonding member 3 is connected to the substrate 1 via the connecting solder layer 7.

[0039] In this configuration, the buffer layer 6 is sintered to the source region of the chip 2. Compared to the traditional direct sintering of the bonding component 3, the buffer layer 6 has a better surface flatness, resulting in more uniform pressure during sintering and making the process easier to implement, thus significantly reducing the process difficulty. Simultaneously, the introduction of the buffer layer 6 between the chip 2 and the bonding component 3, with the thermal expansion coefficient of the bonding component 3 matching that of the buffer layer 6, reduces the difference in thermal expansion coefficients between the upper and lower layers of the connecting solder layer 7, thereby reducing the stress on the connecting solder layer 7 and improving its reliability. Furthermore, this embodiment includes an arc-starting portion 36. During welding, the connecting solder layer 7 rises upwards along the surface of the arc-starting portion 36, effectively increasing the solder layer thickness of the arc-starting portion 36 without changing the process conditions, thereby improving reliability. Furthermore, the arc-starting portion 36 can also be provided on both sides of the side welding surface of the buffer layer 6, further improving the reliability of the side solder layer of the copper-clad buffer layer 6.

[0040] Furthermore, in an optional embodiment, the buffer layer 6 is composed of one of silver, copper-molybdenum alloy, or copper-molybdenum-copper layered composite material. Of course, this embodiment is merely an example illustrating the specific material type of the buffer layer 6, and is not intended to limit it. Those skilled in the art can modify it according to actual circumstances, as long as the same technical effect is achieved.

[0041] Furthermore, in an alternative embodiment, the buffer layer 6 is sintered to the source region of the chip 2 using silver paste or silver film.

[0042] Furthermore, in an optional embodiment, the thickness of the buffer layer 6 is within a predetermined range.

[0043] In this embodiment, the buffer layer 6 is configured with a certain thickness, allowing it to more effectively absorb thermal stress caused by temperature changes and reduce mechanical stress in the solder layer due to the difference in expansion between the upper and lower layers, thereby reducing the risk of cracking. A thicker buffer layer 6 can disperse the stress borne by the solder layer, preventing stress concentration and delaying solder layer fatigue failure. The increased thickness of the buffer layer 6 helps form a smoother surface during sintering, providing a uniform contact interface for subsequent reflow soldering, reducing welding defects, and improving solder layer integrity. Furthermore, the solder layer between the buffer layer 6 and the bonding component 3 is formed through a reflow soldering process, used to fix the bonding component 3 with the arc-starting portion 36 onto the buffer layer 6. The reliability of the arc-starting portion 36 directly affects the electrical connection and mechanical stability between the bonding component 3 and the chip 2. Therefore, a thicker buffer layer 6 can improve the reliability of the reflow soldering layer.

[0044] Further, in an optional embodiment, the bonding member 3 includes a first support plate 32, a second support plate 33 and a third support plate 34 connected in sequence. The other end of the first support plate 32 is provided with a first foot 31, the other end of the third support plate 34 is provided with a second foot 35, and the second support plate 33 is parallel to the substrate 1.

[0045] Further, in an optional embodiment, a second included angle is provided between the first support plate 32 and the second support plate 33, and a third included angle is provided between the third support plate 34 and the second support plate 33. The bonding member 3 can be designed at the rising portion as follows: Figure 7 The slope shown is the slope formed by the first support plate 32 and the third support plate 34. The larger the slope angle, the higher the reliability of the weld layer.

[0046] Furthermore, in an alternative implementation, such as Figure 8 As shown, along the direction close to the second support plate 33, the widths of both the first support plate 32 and the third support plate 34 gradually increase.

[0047] With this configuration, this embodiment can increase the overall flow capacity of the bonding component 3 and increase the overall heat dissipation area of ​​the bonding component 3 by widening the width of the first support plate 32 and the second support plate 33 without affecting the welding surface.

[0048] Furthermore, in an optional embodiment, a chip bonding layer 4 is provided on the substrate 1, and the chip 2 is connected to the substrate 1 through the chip bonding layer 4.

[0049] Furthermore, in an optional embodiment, a sintering layer 5 is disposed on the source region of the chip 2, and the buffer layer 6 is disposed on the sintering layer 5.

[0050] In summary, this utility model adds a buffer layer 6 to the welded structure, which combines the high reliability of silver sintering with the advantage of reflow soldering in easily achieving complex structures. Specifically, this is reflected in the following points: 1. Reduced process difficulty: The buffer layer 6 is a flat thin sheet without a complex structure, which makes it easy to apply pressure and position during sintering. Compared with the bonded part 3 with a complex three-dimensional structure, the process difficulty is greatly reduced. 2. Increased reliability: The upper and lower layers of the connecting weld layer 7 are made of the same material with the same coefficient of thermal expansion. The stress caused by the difference in thermal expansion volume is small, which greatly improves the life of the connecting weld layer 7. At the same time, the thickness of the weld layer at the easy failure point is increased by the arc initiation part 36 without changing the process, which further improves the reliability of the connecting weld layer 7.

[0051] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A packaging structure for a semiconductor device, characterized in that, include: A substrate (1) is provided with a chip (2); A buffer layer (6) is sintered into the source region of the chip (2); A bonding component (3) is provided with its first pin (31) connected to the substrate (1) and its second pin (35) connected to the buffer layer (6). The second pin (35) of the bonding component (3) is provided with an arc-shaped portion (36) at its edge position. The arc-shaped portion (36) and the buffer layer (6) form a first included angle. The arc-shaped portion (36) is connected to the buffer layer (6) through a connecting solder layer (7). The coefficient of thermal expansion of the bonding element (3) matches that of the buffer layer (6).

2. The packaging structure of the semiconductor device according to claim 1, characterized in that, The buffer layer (6) is made of silver, copper-molybdenum alloy, copper-molybdenum-copper or other materials whose coefficient of thermal expansion matches that of the bonding element (3).

3. The packaging structure of the semiconductor device according to claim 2, characterized in that, The buffer layer (6) is sintered to the source region of the chip (2) using silver paste or silver film.

4. The packaging structure of the semiconductor device according to claim 3, characterized in that, The thickness of the buffer layer (6) is within a predetermined range.

5. The packaging structure of the semiconductor device according to any one of claims 1 to 4, characterized in that, The bonding component (3) includes a first support plate (32), a second support plate (33), and a third support plate (34) connected in sequence.

6. The packaging structure of the semiconductor device according to claim 5, characterized in that, The first support plate (32) has a first foot (31) at one end, and the third support plate (34) has a second foot (35) at one end. The second support plate (33) is parallel to the substrate (1).

7. The packaging structure of the semiconductor device according to claim 6, characterized in that, A second included angle is provided between the first support plate (32) and the second support plate (33), and a third included angle is provided between the third support plate (34) and the second support plate (33).

8. The packaging structure of the semiconductor device according to claim 7, characterized in that, Along the direction close to the second support plate (33), the width of both the first support plate (32) and the third support plate (34) gradually increases.

9. The packaging structure of the semiconductor device according to any one of claims 1 to 4, characterized in that, A chip bonding layer (4) is provided on the substrate (1), and the chip (2) is connected to the substrate (1) through the chip bonding layer (4).

10. The packaging structure of the semiconductor device according to any one of claims 1 to 4, characterized in that, A sintered layer (5) is provided on the source region of the chip (2), and a buffer layer (6) is provided on the sintered layer (5).

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