Cipb embedded power device structure with low parasitic capacitance inductance

Abstract

This invention discloses a CIPB embedded power device structure with low parasitic capacitance and inductance, comprising: a ceramic layer formed in a prepreg layer; a first copper layer formed in the prepreg layer, located on the upper surface of the ceramic layer; a second copper layer formed in the prepreg layer, located on the lower surface of the ceramic layer; a chip formed in the prepreg layer and sintered on the first copper layer; a first metal shielding layer formed in the prepreg layer above the chip; a second metal shielding layer formed in the prepreg layer below the chip; a third copper layer formed on the upper surface of the prepreg layer; a fourth copper layer formed on the lower surface of the prepreg layer; and a connection hole connecting to the chip from the third copper layer. This invention can reduce parasitic capacitance and inductance, and improve product performance.

Description

Technical Field

[0001] This utility model relates to a CIPB embedded power device structure with low parasitic capacitance and inductance. Background Technology

[0002] With the trends of miniaturization, high frequency, and cost reduction in new energy vehicles and electronic products, traditional module packaging suffers from high parasitic inductance and cost, gradually reaching a bottleneck for power chips. Therefore, both internationally and domestically, there is an increasing development of CIPB (Chip-In-Layer Power Board) embedded power device structures with low parasitic capacitance and inductance. CIPB is a new packaging technology that directly embeds power semiconductor chips within a multi-layer PCB (printed circuit board), aiming to overcome the performance bottlenecks of traditional power modules in high-voltage, high-frequency, and high-power-density scenarios. It is particularly suitable for new energy vehicles, electric drive inverters, and other fields.

[0003] In the structure of CIPB embedded power devices with low parasitic capacitance and inductance, a large number of vertical vias are required to carry high currents. However, an increase in the number of vertical vias introduces parasitic capacitance and inductance, affecting device performance.

[0004] Therefore, there is an urgent need for a CIPB embedded power device structure with low parasitic capacitance and inductance that can reduce parasitic capacitance and inductance and improve product performance. Utility Model Content

[0005] The utility model description section introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This utility model description section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by this utility model is to provide a CIPB embedded power device structure with low parasitic capacitance and inductance, which can reduce parasitic capacitance and inductance.

[0007] To solve the above-mentioned technical problems, the present invention provides a CIPB embedded power device structure with low parasitic capacitance and inductance, comprising:

[0008] Ceramic layer 1 is formed in prepreg layer 2;

[0009] The first copper layer 3 is formed in the prepreg layer 2 and is located on the upper surface of the ceramic layer 1;

[0010] The second copper layer 4 is formed in the prepreg layer 2 and is located on the lower surface of the ceramic layer 1;

[0011] Chip 5, which is formed in prepreg layer 2 and sintered on first copper layer 3;

[0012] A first metal shielding layer 6 is formed in the prepreg layer 2 above the chip 5;

[0013] The second metal shielding layer 7 is formed in the prepreg layer 2 below the chip 5;

[0014] The third copper layer 8 is formed on the upper surface of the prepreg layer 2;

[0015] The fourth copper layer 9 is formed on the lower surface of the prepreg layer 2;

[0016] Connection hole 10, which connects to chip 5 from the third copper layer 8.

[0017] In CIPB (Chip-in-PCB) embedded power devices, the prepreg layer is one of the key materials for building the module package. Its role is not only to achieve electrical isolation and mechanical support for the multi-layer PCB structure, but also to undertake multiple functions such as thermal management, electrical insulation, and chip protection. Especially in embedded power device packaging, its performance directly affects the module's reliability, thermal stability, and electrical performance. Prepreg is a composite material made by impregnating glass fiber cloth with partially cured (B-stage) epoxy resin. Under heating and pressurization conditions, it can soften, flow, and re-cure to form a stable insulating layer.

[0018] Preferably, in a further improved CIPB embedded power device structure with low parasitic capacitance and inductance, the first copper layer 3 and the second copper layer 4 have the same thickness, the first metal shielding layer 6 and the second metal shielding layer 7 have the same thickness, and the third copper layer 8 has a thickness less than the fourth copper layer 9.

[0019] Preferably, in a further improved CIPB embedded power device structure with low parasitic capacitance and inductance, the thickness of the first copper layer 3 is in the range of 300um to 340um; for example, 300um, 310um, 320um, 330um or 340um.

[0020] Preferably, in the further improved CIPB embedded power device structure with low parasitic capacitance and inductance, the thickness of the second copper layer 4 is in the range of 300um to 340um; for example, 300um, 310um, 320um, 330um or 340um.

[0021] Preferably, the thickness of the ceramic layer 1 in the further improved CIPB embedded power device structure with low parasitic capacitance and inductance is in the range of 280um to 320um; for example, 280um, 290um, 300um, 310um or 320um.

[0022] Preferably, in a further improved CIPB embedded power device structure with low parasitic capacitance and inductance, the thickness of the first metal shielding layer 6 is in the range of 280um to 320um; for example, 280um, 290um, 300um, 310um or 320um.

[0023] Preferably, in a further improved CIPB embedded power device structure with low parasitic capacitance and inductance, the thickness of the second metal shielding layer 7 is in the range of 280um to 320um; for example, 280um, 290um, 300um, 310um or 320um.

[0024] Preferably, in the further improved CIPB embedded power device structure with low parasitic capacitance and inductance, the thickness of the third copper layer 8 is in the range of 150um to 200um; for example, 1500um, 160um, 170um, 180um, 190um or 200um.

[0025] Preferably, in the further improved CIPB embedded power device structure with low parasitic capacitance and inductance, the thickness of the fourth copper layer 9 is in the range of 300um to 350um; for example, 300um, 310um, 320um, 330um, 340um or 350um.

[0026] The working principle of this utility model is explained as follows;

[0027] The main design concept of this utility model is to optimize the current path and electric field distribution by introducing a "Shielded MetalLayer SML layer, namely the first metal shielding layer and the second metal shielding layer" into the CIPB structure, thereby suppressing the generation of parasitic capacitance and parasitic inductance.

[0028] A first metal shielding layer and a second metal shielding layer are embedded in the multilayer PCB structure to shield electric field interference and optimize the signal return path; the first metal shielding layer and the second metal shielding layer serve as key metal layers to form a low-impedance, low-coupling current loop.

[0029] This utility model can achieve at least the following technical effects;

[0030] This invention can reduce parasitic capacitance: the first metal shielding layer and the second metal shielding layer can isolate the electric field coupling between the upper and lower layers, effectively reduce the interlayer parasitic capacitance, reduce the interlayer electric field coupling, reduce the C value, and improve high-frequency performance.

[0031] This invention can reduce parasitic inductance: the first metal shielding layer and the second metal shielding layer can serve as a reference ground, providing a low-impedance return path for high-speed signals, reducing the loop area, thereby reducing parasitic inductance, optimizing the current return path, reducing the magnetic flux loop area, and reducing the L value.

[0032] This invention can improve device performance: reduce switching losses, suppress voltage overshoot and EMI, and improve system stability.

[0033] This invention can maintain high current capacity: while reducing parasitic parameters, it still retains a large number of through holes to carry large currents.

[0034] The first metal shielding layer and the second metal shielding layer of this invention form a symmetrical or differential structure, which can actively control the direction of current and the distribution of magnetic field; by using the symmetrical or differential structure, the magnetic flux cancels each other out, further reducing the equivalent inductance. Attached Figure Description

[0035] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the present invention, supplementing the description in the specification. However, the accompanying drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The accompanying drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by the exemplary embodiments of the present invention. The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0036] Figure 1 This is a schematic diagram of the structure of this utility model.

[0037] Explanation of reference numerals in the attached figures:

[0038] Ceramic layer 1;

[0039] Prepreg layer 2;

[0040] First copper layer 3;

[0041] Second copper layer 4;

[0042] Chip 5;

[0043] First metallic shielding layer 6;

[0044] Second metal shielding layer 7;

[0045] Third copper layer 8;

[0046] Fourth copper layer 9;

[0047] Connection hole 10. Detailed Implementation

[0048] The following specific embodiments illustrate the implementation of this utility model. Those skilled in the art can fully understand other advantages and technical effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the utility model. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of this utility model can be implemented in many different forms and should not be construed as limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of this utility model thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0049] Example

[0050] refer to Figure 1 As shown, this utility model provides a CIPB embedded power device structure with low parasitic capacitance and inductance, comprising:

[0051] Ceramic layer 1 is formed in prepreg layer 2;

[0052] The first copper layer 3 is formed in the prepreg layer 2 and is located on the upper surface of the ceramic layer 1;

[0053] The second copper layer 4 is formed in the prepreg layer 2 and is located on the lower surface of the ceramic layer 1;

[0054] Chip 5, which is formed in prepreg layer 2 and sintered on first copper layer 3;

[0055] A first metal shielding layer 6 is formed in the prepreg layer 2 above the chip 5;

[0056] The second metal shielding layer 7 is formed in the prepreg layer 2 below the chip 5;

[0057] The third copper layer 8 is formed on the upper surface of the prepreg layer 2;

[0058] The fourth copper layer 9 is formed on the lower surface of the prepreg layer 2;

[0059] Connecting hole 10 connects to chip 5 from the third copper layer 8.

[0060] The thickness of the first copper layer 3 ranges from 300um to 340um, preferably 320um; the thickness of the second copper layer 4 ranges from 300um to 340um, preferably 320um; the thickness of the ceramic layer 1 ranges from 280um to 320um, preferably 300um; the thickness of the first metal shielding layer 6 ranges from 280um to 320um, preferably 300um; the thickness of the second metal shielding layer 7 ranges from 280um to 320um, preferably 300um; the thickness of the third copper layer 8 ranges from 150um to 200um, preferably 180um; and the thickness of the fourth copper layer 9 ranges from 300um to 350um, preferably 320um or 330um.

[0061] Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of exemplary embodiments according to this utility model, the first element, component, region, layer, or portion discussed below may also be referred to as the second element, component, region, layer, or portion.

[0062] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0063] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the present invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the present invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A CIPB embedded power device structure with low parasitic capacitance and inductance, characterized in that, include: A ceramic layer (1) is formed in the prepreg layer (2); A first copper layer (3) is formed in the prepreg layer (2) and is located on the upper surface of the ceramic layer (1); A second copper layer (4) is formed in the prepreg layer (2) and is located on the lower surface of the ceramic layer (1); Chip (5), which is formed in a prepreg layer (2) and sintered on a first copper layer (3); A first metal shielding layer (6) is formed in the prepreg layer (2) above the chip (5); A second metal shielding layer (7) is formed in the prepreg layer (2) below the chip (5); A third copper layer (8) is formed on the upper surface of the prepreg layer (2); A fourth copper layer (9) is formed on the lower surface of the prepreg layer (2); A connection hole (10) is connected to the chip (5) from the third copper layer (8).

2. The CIPB embedded power device structure with low parasitic capacitance and inductance as described in claim 1, characterized in that: The first copper layer (3) and the second copper layer (4) have the same thickness, the first metal shielding layer (6) and the second metal shielding layer (7) have the same thickness, and the third copper layer (8) has a thickness less than the fourth copper layer (9).

3. The CIPB embedded power device structure with low parasitic capacitance and inductance as described in claim 1, characterized in that: The thickness of the first copper layer (3) ranges from 300um to 340um.

4. The CIPB embedded power device structure with low parasitic capacitance and inductance as described in claim 1, characterized in that: The thickness of the second copper layer (4) ranges from 300um to 340um.

5. The CIPB embedded power device structure with low parasitic capacitance and inductance as described in claim 1, characterized in that: The thickness of the ceramic layer (1) ranges from 280um to 320um.

6. The CIPB embedded power device structure with low parasitic capacitance and inductance as described in claim 1, characterized in that: The thickness of the first metal shielding layer (6) ranges from 280um to 320um.

7. The CIPB embedded power device structure with low parasitic capacitance and inductance as described in claim 1, characterized in that: The thickness of the second metal shielding layer (7) ranges from 280um to 320um.

8. The CIPB embedded power device structure with low parasitic capacitance and inductance as described in claim 1, characterized in that: The thickness of the third copper layer (8) ranges from 150um to 200um.

9. The CIPB embedded power device structure with low parasitic capacitance and inductance as described in claim 1, characterized in that: The thickness of the fourth copper layer (9) ranges from 300um to 350um.

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