Wafer test analysis graphical user interface for electronic devices

CN309204809SActive Publication Date: 2025-03-28SEMITRONIX
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Patent Information

Application Number
CN202430331683.3
Authority / Receiving Office
CN · China
Patent Type
Designs(China)
Current Assignee / Owner
Filing Date
2024-05-31
Publication Date
2025-03-28
Estimated Expiration
2039-05-31

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Abstract

1. The name of the product of this design: Graphical user interface for wafer test analysis for electronic equipment. 2. Purpose of this design product: This design product is used for an electronic device. 3. The key design point of this appearance design product lies in the graphical user interface. 4. The picture or photo that best illustrates the key points of the design: Main view of Design 1. 5. Designate Design 1 as the base design. 6. Purpose of the graphical user interface: This appearance design product is used to view the correlation analysis between wafer testing and yield; interface interaction process: the correlation analysis chart on the upper left side of the main view of Design 1, the box plot on the middle left side, the CDF chart on the middle right side, the wafer yield stacking chart on the upper right side and the line chart on the lower side. ×-out the box plot on the middle left side of the main view of Design 1, and jump to Design 1 change state diagram 1; ×-out the CDF chart on the middle left side of Design 1 change state diagram 1, and jump to Design 1 change state diagram 2; ×-out the wafer yield stacking chart on the upper right side of Design 1 change state diagram 2, and jump to Design 1 change state diagram 3; the interaction method and purpose of Design 2 are similar to those of Design 1, the only difference is that the wafer yield stacking chart on the upper right side of the main view of Design 2 is ×-out, and jump to Design 2 change state diagram 1; ×-out the CDF chart in the middle of Design 2 change state diagram 1, and jump to Design 2 change state diagram 2.
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