Wafer defect pattern analysis graphical user interface for electronic devices

CN310163104SActive Publication Date: 2026-08-21SEMITRONIX
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Patent Information

Application Number
CN202530780265.7
Authority / Receiving Office
CN · China
Patent Type
Designs(China)
Current Assignee / Owner
Filing Date
2025-12-31
Publication Date
2026-08-21
Estimated Expiration
2040-12-31

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Abstract

1. The name of the design product: wafer defect pattern analysis graphical user interface for electronic equipment. 2. The use of the design product: wafer defect pattern classification / clustering and user interaction thereof. 3. The design points of the design product: in the graphical user interface. 4. The picture or photo that best indicates the design points: design 1 front view. 5. The electronic equipment is a conventional design, and other views of each design are omitted. 6. Design 1 is designated as the basic design. 7. The use of the graphical user interface: the design product is used for matching wafer defect patterns; the interface interaction process: based on the design 1 front view, click the "Classification" button in the upper left corner to display design 1 interface change state diagram 1, click "OK" after selecting the model to display design 1 interface change state diagram 2, and display design 1 interface change state diagram 3 after the matching is loaded; based on the design 2 front view, click the "Cluster" button in the upper left corner to display design 2 interface change state diagram 1, click "OK" after selecting the model to display design 2 interface change state diagram 2, and display design 2 interface change state diagram 3 after the clustering is loaded.
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