Multi-level memory and method for operating the same

Abstract

A multi-level memory comprising a memory structure (21, 31, 22, 32, 23; 230) arranged between a first electrode (11; 251) and a second electrode (12; 252), wherein a distribution density of a resistance level of the memory structure (21, 31, 22, 32, 23; 230) is higher at its minimum value than at its maximum value, and wherein the memory structure (21, 31, 22, 32, 23; 230) is arranged on a substrate (10; 200) and has a plurality of phase change structures (21, 22, 23; 232, 234, 236) which differ in terms of a distance of their bottom surface from an upper surface of the substrate (10; 200).

Description

BACKGROUND TECHNICAL AREA

[0001] The present invention relates to a semiconductor memory, in particular to a multi-level memory and a method for operating the same. DESCRIPTION OF RELATED TECHNOLOGY

[0002] A phase-change layer has a property of variable electrical resistance depending on its crystalline state, and the same can be used to store data in a multi-level memory. The electrical resistance of the phase-change layer is low in a crystalline state (i.e., a set state) and high in an amorphous state (i.e., a reset state). The crystalline state of the phase-change layer corresponding to the stored data can therefore be verified by measuring the electrical resistance of the phase-change layer.

[0003] The crystalline state of the phase change layer can be controlled by time and temperature.

[0004] Fig. Figure 1 is a graph illustrating the variation of the crystalline state of the phase-change layer with time and temperature. In the graph, the x-axis represents time (T) and the y-axis represents temperature (TMP).

[0005] Referring to Fig.1, when the phase change layer is heated to a temperature higher than the melting temperature (Tm) for a first period (T1) and then cooled, the phase change layer assumes an amorphous state 1. Further, when the phase change layer is heated to a temperature lower than the melting temperature (Tm) and higher than the crystallization temperature (Tc) for a second period (T2) and then cooled, the phase change layer assumes a crystalline state 2. Here, the second period (T2) is a longer period than the first period T1.

[0006] Recently, to meet the increased demand for storage capacity in semiconductor memories, a multi-level cell that stores a plurality of data in a single memory cell has been introduced. Such a multi-level memory is known, for example, from document US 2006 / 0077706 A1. To realize such a multi-level cell in a multi-level memory, a method for controlling a volume of the crystallized region in the phase-change layer is introduced. As described above, since each phase-change layer has a different resistance according to its crystalline state, the overall resistance level of the phase-change memory cell of this method is determined by the volume fraction of the amorphous or crystalline region of the phase-change layer. Therefore, to realize the multi-level cell, discrete control of the volume of the region in which the crystalline state changes is required.However, since the crystallization of the phase change layer depends on temperature, which is a spatially difficult parameter to control, discrete control of the volume of the phase-changeable region is difficult to achieve.

[0007] Furthermore, since the resistance level of the phase change memory cell according to this method is mainly determined by the resistance level of the amorphous region, there is another problem that it is difficult to realize the multi-level cell. Fig. Figure 2 illustrates in detail the relationship between the volume of the phase-changeable region and the resistance level of the phase-change memory cell. For clarity of description, it is assumed that the phase-change layer has three different phase-changeable regions P1, P2, and P3.

[0008] Referring to Fig.2, since the phase-changeable regions P1, P2 and P3 are connected in series, the total resistance level (R) of the phase-change layer is equal to a sum of R1, R2 and R3, which denote the resistance of the phase-changeable regions P1, P2 and P3 respectively, as follows: R=R1+R2+R3

[0009] To show an example of numerical analysis, assume that the resistance of each phase-changeable region is 1 kΩ in a tuned state (i.e., a crystalline state) and 100 kΩ in a retuned state (i.e., an amorphous state). [Table 1] State (resistance) R1 Adjustment (1kΩ) Readjustment (100kΩ) Readjustment (100kΩ) Readjustment (100kΩ) R2 Adjustment (1kΩ) Adjustment (1kΩ) Readjustment (100kΩ) Readjustment (100kΩ) R3 Adjustment (1kΩ) Adjustment (1kΩ) Adjustment (1kΩ) Readjustment (100kΩ) R 3kΩ(~0kΩ) 102kΩ(~100kΩ) 201kΩ(~200kΩ) 300kΩ Data 00 01 10 11

[0010] As shown in the previous Table 1, the resistance level R of the entire phase change layer can have four different data states (00, 01, 10, 11) according to the crystalline states of the respective phase changeable regions P1, P2 and P3, and the data state depends on the number of phase changeable regions in the reset state.

[0011] However, according to recent research, how in Fig. 3, the resistance level in the reset state changes with time (D. Ielmini et al., IEEE Transactions on Electron Devices, 2007, Vol. 54, 308-315). As shown in Fig.As shown in Figure 4, the drift of such a resistor results in a change in the resistance level of the phase-change memory cells, and furthermore, the resistance level window required to distinguish the data states may disappear. In particular, in a configuration where the phase-changeable regions are connected in series, since the time-dependent drift of a resistor is also given by Equation 1, the change in the resistance of the data states increases proportionally to the number of phase-changeable regions in the reset state.

[0012] An object of the present invention is to provide an improved multi-level memory. SUMMARY

[0013] The object is achieved by a multi-level memory according to claim 1 and a multi-level memory according to claim 16. Further developments of the invention are defined in the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The foregoing and other objects, features, and advantages of the invention will become apparent from the more particular description of preferred aspects of the invention as illustrated in the accompanying drawings, in which like reference characters refer to the same parts throughout the several views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Fig. 1 is a graph showing various characteristics of a crystalline state of a phase change layer according to a temperature and a time period. Fig.Figure 2 illustrates the relationship between the volume of a phase-changeable region and the resistance level of a phase-change memory cell. Fig. 3 is a graphical representation showing a time-dependent drift effect of the resistance level. Fig. 4 is a graph for illustrating a variation in the resistance levels of phase change memory cells caused by a resistance drift. Fig. 5 is a circuit diagram showing a unit cell of a multi-level memory cell according to the present invention. Fig. 6 is a circuit diagram illustrating a unit cell of a multi-level memory cell according to an exemplary embodiment of the present invention. Fig. 7A to 7D are timing charts for illustrating a method of operating a multi-level memory cell according to the present invention. Fig.8A and Fig. 8B illustrate multi-level memories according to exemplary embodiments of the present invention, wherein the Fig. 8B is not covered by the claims. Fig. 9A to 12A are plan views for illustrating a method of manufacturing a multi-level memory according to an exemplary embodiment of the present invention. Fig. 9B to 12B are cross-sectional views for illustrating a method of manufacturing a multi-level memory according to an exemplary embodiment of the present invention. Fig. 13A to 17A are plan views for illustrating a method of manufacturing a multi-level memory according to another exemplary embodiment of the present invention. Fig.13B to 17B are cross-sectional views for illustrating a method of manufacturing a multi-level memory according to another exemplary embodiment of the present invention, which is not covered by the claims. Fig. 18A is a circuit diagram illustrating a multi-level memory having a diode according to the present invention. Fig. 18B is a circuit diagram illustrating a multi-level memory having a selection transistor according to the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0015] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numerals refer to like elements throughout.

[0016] It is understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0017] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used merely to distinguish one element, component, region, layer, or portion from another region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below could be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0018] Spatially related terms such as "beneath," "under," "lowermost," "lower," "above," "topmost," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the drawings. It is understood that the spatially related terms are intended to encompass different orientations of the device being used or operated in addition to the orientation illustrated in the drawings. For example, if the device illustrated in the drawings were turned over, elements described as being "below" or "below" other element(s) or feature(s) would then be oriented "above" the other elements or features. The exemplary term "below" can thus encompass an orientation both above and below.The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. Furthermore, "lateral," as used herein, refers to a direction substantially orthogonal to a vertical direction.

[0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "comprises" and / or "comprises," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0020] Exemplary embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations are to be expected as a result of, for example, manufacturing processes and / or tolerances. Embodiments of the present invention should thus not be construed as limited to the specific shapes of regions illustrated herein, but are intended to encompass deviations from shapes resulting, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from an implanted to a non-implanted region.Likewise, a buried region formed by implantation may result in an implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions depicted in the drawings are schematic in nature, and their shapes are not intended to represent the actual shape of a region of a device and are not intended to limit the scope of the present invention.

[0021] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as that commonly understood by one of ordinary skill in the art to which this invention belongs. Accordingly, these terms may include equivalent terms created after such time. It is further understood that terms such as those defined in commonly used dictionaries should be construed to have a meaning consistent with their meaning in the present specification and in the context of the relevant art, and are not to be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0022] Fig.5 is a circuit diagram illustrating a unit cell of a multi-level memory according to an embodiment of the present invention.

[0023] Referring to Fig. 5, the unit cell 100 of the multi-level memory according to the present invention comprises a first electrode 11, a second electrode 12, and a plurality of memory elements M1-Mn arranged between the first and second electrodes 11 and 12, forming a memory structure. The respective memory elements M1-Mn may have a variable resistive structure capable of varying their crystalline state by changing a temperature condition. Here, the variable resistive structures of each of the memory elements M1-Mn may be made of a material selected from a group of chalcogen compounds including antimony (Sb), tellurium (Te), and selenium (Se).

[0024] The multi-level memory comprising the chalcogen compound is at least one of the technical fields to which the technical idea of ​​the present invention can be applied. However, the technical idea of ​​the present invention is not limited to such a technical field, but can be applied to various other memories for multi-level cells.

[0025] According to the present invention, the memory elements M1-Mn are configured such that the first and second electrodes 11 and 12 are connected in parallel. In this case, the resistance level R of the memory structure can be determined by 1R=∑i=1n1Ri where Ri denotes a resistance of the memory element Mi. For example, assume that the unit cell has three memory elements M1, M2, and M3, and a resistance of each of the memory elements is 1 kΩ in a set state (i.e., a crystalline state) and 100 kΩ in a reset state (i.e., an amorphous state). In this case, the total resistance level R of the memory elements can be given by the following table. [Table 2] State (resistance) R1 Adjustment (1kΩ) Readjustment (100kΩ) Readjustment (100kΩ) Readjustment (100kΩ) R2 Adjustment (1kΩ) Adjustment (1kΩ) Readjustment (100kΩ) Readjustment (100kΩ) R3 Adjustment (1kΩ) Adjustment (1kΩ) Adjustment (1kΩ) Readjustment (100kΩ) R ~0.33kΩ ~0.50kΩ ~0.98kΩ ~33.33kΩ Relationship R 00 1,49 R 00 2,94 R 00 100 R 00 Data 00 01 10 11

[0026] As can be seen from Table 2, if the memory elements M1-Mn are connected in parallel, the resistance level R of the memory structure is predominantly determined by the number of memory elements in a set state. That is, the total resistance level of the memory elements is essentially determined by the number of memory elements in states with a low resistance level (i.e., set states). The resistance level of the memory structure is essentially inversely proportional to the number of memory elements in states with a low resistance level (i.e., set states).

[0027] According to another aspect of the present invention, it can be said that the resistance level of the memory structure, except for its maximum value 33.33kΩ, is increased by its minimum value R 00More specifically, in Table 2, resistance levels of 0.33 kΩ, 0.50 kΩ, 0.98 kΩ in data states 00, 01, and 10 have smaller differences from the minimum value (i.e., the resistance level of 0.33 kΩ in data state 00) than differences from the maximum value (i.e., the resistance level of 33.33 kΩ in data state 11). Here, from the arithmetic relationship shown by the example in Table 2, it is clear that the resistance characteristics with respect to a difference between the maximum values ​​and the minimum values ​​are independent of a number of memory elements. Furthermore, as can be seen from Table 2, the resistance level of a memory structure is always smaller than a predetermined average resistance level except for the maximum value of 33.33 kΩ. According to Table 2, the average resistance level may be about 1 kΩ. However, according to modified embodiments of the present invention, this average resistance level may be a level between (Rmax - R min ) / 30 and the maximum value (e.g. 33.33kΩ). (R max and R min are the maximum and minimum values ​​of a resistance level of the memory structure.)

[0028] In this respect, the traditional problems related to Fig. 3 describe how time-dependent drift of a reset resistor and narrowing of a resistance level window are overcome in the multi-level memory comprising the parallel-connected memory elements of the present invention.

[0029] In case the memory elements M1-Mn are connected between the first and second electrodes 11 and 12, a method capable of selectively varying the crystalline states of the variable resistive structure is required to identify the data states of the unit cell. Fig.6 is a circuit diagram illustrating an embodiment of the present invention capable of realizing this.

[0030] Referring to Fig. 6, the variable-resistance structures of the respective memory elements M1-Mn can be made of materials each having different crystallization temperatures Tx1, Tx2, ..., Txn. For example, the memory elements M1-Mn can each comprise a different type of phase-change material. More specifically, the variable-resistance structures of the respective memory elements M1-Mn can be made of the chalcogen compounds described above, which have a different component ratio of antimony-tellurium-selenium.

[0031] Fig.7A to 7D are timing charts illustrating an operation method of a multi-level memory according to the present invention. For this exemplary description, it is assumed that the unit cell 100 has three memory elements M1, M2, and M3, and the crystallization temperatures of the variable resistive structures of the respective memory elements Tx1, Tx2( <Tx1) und Tx3(<Tx2) sind. Fig. 7A to 7D are timing diagrams for respectively realizing data states (11, 10, 01, 00) in Table 2.

[0032] Referring to Fig.7A, all variable-resistance structures are heated to a temperature above their melting point and then rapidly cooled. The rapid cooling step involves rapidly cooling the variable-resistance structures to a temperature below Tx3 for a duration shorter than the minimum crystallization time of the variable-resistance structures. (Here, the crystallization time is the duration of a temperature condition above the crystallization temperature required to crystallize the corresponding variable-resistance structure.) In this case, all variable-resistance structures assume amorphous states, and their memory cells assume a data state (11).

[0033] Referring to Fig.7B, all variable-resistance structures are heated to a temperature above the melting point and then very rapidly cooled to a temperature between Tx3 and Tx2. A temperature condition above Tx3 is then maintained for a period longer than the crystallization time required to crystallize memory element M3. In this case, memory elements M1 and M2 assume amorphous states, and memory element M3 assumes a crystalline state. The memory cell undergoing such thermal processes assumes a data state (10).

[0034] Referring to Fig.7C, all variable-resistance structures are heated to a temperature above the melting point and then very rapidly cooled to a temperature between Tx2 and Tx1. In this case, the memory element M1 assumes an amorphous state. Then, for a period t2 longer than the crystallization time required to crystallize the memory element M2, a temperature condition higher than Tx2 is maintained, and the variable-resistance structures are cooled to a temperature between Tx3 and Tx2. In such a case, the memory elements M2 assume crystalline states. Subsequently, a temperature condition above Tx3 is maintained for the period t3, and they are cooled to a temperature below Tx3. The memory elements M3 assume crystalline states. The memory cell undergoing such a thermal process results in a data state (01).

[0035] Referring to Fig.7D, all variable resistive structures are heated to a temperature above the melting point, then slowly cooled to a temperature between Tx2 and Tx1. This step may comprise cooling the variable resistive structures at a temperature condition between Tx1 and the melting point Tm for a time period t1 that is longer than a crystallization time required to crystallize the memory element M1. In this case, the memory element M1 assumes a crystalline state. A description of the crystallization of the memory elements M2 and M3 will not be repeated, since it is identical to the previous description with reference to Fig. 7C. After such a thermal process, the memory cell results in a data state (00).

[0036] The cooling condition (e.g., a variation rate of temperature with time) of the thermal process described above can be modified and designed in various other forms. Furthermore, the present invention is not limited to the variable resistive structures being made of chalcogen compounds, and therefore, the method for producing a difference in crystallization temperatures is not limited to a method using different types of a material or a combination. That is, the idea that the crystallization states of the parallel-connected variable resistive structures can be selectively changed by using a difference in crystallization temperatures of the variable resistive structures is not limited to the foregoing, with reference to Fig.7A to 7D and may be modified to utilize various other components. Furthermore, according to the present invention, a multi-level memory cell can be switched to a desired data state without reference to the initial state through a single thermal process.

[0037] According to one aspect of the present invention, in a writing step in which a resistance level of a memory structure is changed, all resistance levels of the memory structure except the maximum value are changed to a resistance level at which the difference from the minimum value is smaller than the difference from the maximum value. More specifically, all resistance levels of the memory structure except the maximum value are smaller than a predetermined average resistance level. Here, the average resistance level may be a value between (R max - R min ) / 30 and R max be (R max= the maximum value of resistance levels of the memory structure, R min = the minimum value of resistance levels of the memory structure).

[0038] The memory structure may comprise a plurality of variable resistive structures, as described above. In this case, the resistance level of the memory structure switched by the write step is substantially inversely proportional to the number of variable resistive structures with a low resistance level.

[0039] According to the present invention, the writing step switches the resistance level of the memory structure to a predetermined single resistance level. The write operation condition required to switch the resistance level of the variable resistive structure may be different for each of the variable resistive structures, and the writing step may comprise selectively switching the resistance levels of the variable resistive structures by using each different write operation condition for each of the variable resistive structures.

[0040] Fig. 8A and Fig. 8B illustrate multi-level memories according to embodiments of the present invention. For clarity of description, repeated descriptions may be omitted in the two embodiments.

[0041] Referring to Fig.8A, a lower conductive structure 41 and a first electrode 11 connected to the lower conductive structure 41 are arranged on a substrate 10. An upper conductive structure 42 and a second electrode 12 connected to the upper conductive structure 42 are arranged on the first electrode 11. According to one embodiment, main planes of the first electrode 11 and the second electrode 12 are opposite to each other and are formed vertically with respect to the upper surface of the substrate 10 (the main planes of the first and second electrodes 11 and 12 are their largest surfaces). The first and second electrodes 11 and 12 may be connected to the upper surface of the lower conductive structure 41 and the lower surface of the upper conductive structure 42, respectively.

[0042] Successively stacked variable resistive structures 21, 22, and 23 are arranged between the first electrode 11 and the second electrode 12, and separation layer structures 31 and 32 are arranged between the variable resistive structures 21, 22, and 23. The variable resistive structures 21, 22, and 23 may each be formed at different levels with respect to the substrate 10. According to this embodiment, sidewalls of the variable resistive structures 21, 22, and 23 are configured to contact the main planes of the first and second electrodes 11 and 12. As a result, the variable resistive structures 21, 22, and 23 are connected in parallel between the first and second electrodes 11 and 12.

[0043] The variable resistive structures 21, 22, and 23 may be made of a material selected from the chalcogen compounds described above. According to one embodiment, the chalcogen compound may be a compound of tellurium (Te) with a concentration of approximately 20 to 80 atomic percent, antimony (Sb) with a concentration of 5 to 50 atomic percent, and germanium (Ge) with a concentration of the remaining atomic percent. According to the present invention, the variable resistive structures 21, 22, and 23 may comprise different types of phase-change materials from one another. For example, the variable resistive structures 21, 22, and 23 may be made of a material having a different component ratio of antimony-tellurium-selenium.

[0044] Referring to Fig.8B, the variable resistive structures 21, 22, and 23 are connected in parallel at a substantially equal distance from the substrate 10 between the first and second electrodes 11 and 12. The main planes of the first and second electrodes 11 and 12 may be formed to be parallel to the upper surface of the substrate 10. As in the previous embodiment, the variable resistive structures 21, 22, and 23 may be made of different types of phase-change materials or made of chalcogen compounds with a different component ratio of antimony-tellurium-selenium.

[0045] Fig. 9A, Fig. 10A, Fig. 11A and Fig. 12A are plan views illustrating a method of forming a multi-level memory according to an embodiment of the present invention. Fig. 9B, Fig. 10B, Fig. 11B, Fig.12B contain two cross-sectional views along lines II' and II-II' of Fig. 9A, Fig. 10A, Fig. 11A and 12A, respectively, illustrating a method of forming the multi-level memory according to the embodiment of the present invention.

[0046] Referring to Fig. 9A and Fig. 9B, lower conductive structures 210 are formed on a substrate 200, and a memory layer 220 comprising a plurality of variable resistive layers 222, 224, and 226 and separation layers 223 and 225 therebetween is formed on the resulting structure.

[0047] The variable resistive layers 222, 224, and 226 can be made from materials that have different crystallization temperatures. The variable resistive layers 222, 224, and 226 can be made from different types of phase-change materials. For example, the variable resistive layers 222, 224, and 226 can be made from a selected one of chalcogen compounds comprising tellurium (Te) at a concentration of about 20 to 80 atomic percent, antimony (Sb) at a concentration of 5 to 50 atomic percent, and germanium (Ge) at a concentration of the remaining atomic percent. The antimony-tellurium-selenium component ratios of all variable resistive layers can differ from one another.The variable resistive layers 222, 224 and 226 may be formed using either a chemical vapor deposition or a physical vapor deposition process, and thicknesses of the variable resistive layers 222, 224 and 226 may be different from each other.

[0048] The separation layers 223 and 225 may be made of at least one material selected from insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. According to the present invention, the storage layer 220 may further include a cap layer 227 formed on the uppermost variable resistive layer 226 or a lower separation layer 221 formed below the lowermost variable resistive layer 222. The cap layer 227 may be made of at least one material selected from silicon oxide or silicon nitride, and its thickness may be between about 100 and 5000 Å. The lower separation layer 221 electrically separates the lower conductive structure 210 and the lowermost variable resistive layer 222 and may be formed with a thickness between 50 and 500 Å.

[0049] The lower conductive structures 210 may be plugs arranged two-dimensionally on the substrate 200. According to one embodiment, word lines 205 arranged in one direction on the substrate 200 may further be formed prior to forming the lower conductive structures 210. The lower conductive structures 210 extend through a lower interlayer dielectric 215 to be connected to the word lines 205 thereunder. Furthermore, a diode, as in Fig. 18A, between the lower conductive structures 210 and the word lines 205.

[0050] According to a modified embodiment of the present invention, the lower conductive structure 210 may be connected to a drain electrode of a selection transistor, as shown in Fig. 18B, and a gate electrode of the selection transistor may be connected to a word line.

[0051] Referring to Fig. 10A and Fig. 10B, the memory layer 220 is patterned to form memory structures 230 comprising successively stacked variable resistive structures 232, 234, and 236 and separation layer structures 223 and 225 therebetween.

[0052] According to the present invention, the memory structures 230 may be formed parallel along one direction. For example, the memory structures 230 may be formed parallel to the wordlines 205, as shown. However, in another embodiment, the memory structures 230 may be formed to cross the wordlines 205. The memory structures 230 may further be formed such that their centers are laterally offset from the center of the lower conductive structure 210. According to this embodiment, the memory structures 230 expose a portion of a top surface of the lower conductive structure 210, as shown.

[0053] Conductive spacers 240 (or first and second electrode structures) are formed on both sidewalls of the memory structures 230. Forming the conductive spacers 240 includes conformally forming an electrode layer on the resulting structure where the memory structures 230 are formed, and then anisotropically etching the electrode layer to expose a top surface of the memory structure 230.

[0054] According to the present invention, the conductive spacers 240 may be made of a material selected from nitrides comprising metal elements, oxynitrides comprising metal elements, carbon (C), titanium (Ti), tantalum (Ta), aluminum titanium (TiAl), zirconium (Zr), hafnium (Hf), molybdenum (Mo), aluminum (Al), aluminum-copper (Al-Cu), aluminum-copper-silicon (Al-Cu-Si), copper (Cu), tungsten (W), tungsten titanium (TiW), and tungsten silicide (WSix). The nitrides comprising the metal elements may include TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN and / or TaAlN, and the oxynitrides comprising the metal elements may include TiON, TiAlON, WON and TaON.

[0055] The memory structure 230 may further include a capping structure 237 and a lower isolation layer structure 231 formed by patterning the capping layer 227 and the lower isolation layer 221. This exemplary embodiment is described as having three variable resistive structures, but the number of variable resistive structures and / or the number of isolation layer structures may be increased or decreased as needed.

[0056] Referring to Fig. 11A and Fig. 11B, the memory structures 230 and mask structures 260 crossing the conductive spacers 240 are formed on the resulting structure where the conductive spacers 240 are formed. First electrodes 251 and second electrodes 252 are formed on both sidewalls of the memory structure 230 by etching the conductive spacers 240 using the mask structure 260 as an etching mask.

[0057] The mask patterns 260 may be photoresist patterns formed using photolithography. Since the width of the conductive spacers 240 is smaller than their height, if the conductive spacers 240 are etched using anisotropic etching, the components located under the conductive spacers 240 (e.g., the bottom conductive pattern 210) may be damaged by etching. It is therefore desirable to etch the conductive spacers 240 using isotropic etching. In this case, the first and second electrodes 251 and 252 may have smaller widths than the mask pattern 240, as shown.

[0058] The first electrodes 251 are arranged on one sidewall of the memory structures 230, and the second electrodes 252 are formed on the other sidewall of the memory structures 230. Furthermore, all of the first electrodes 251 and all of the second electrodes 252 are formed two-dimensionally on the substrate 200 and are separated from each other as a result of the etching process. According to this embodiment, since the first and second electrodes 251 and 252 are structures resulting from etching the conductive spacers 240, the structure characteristics, such as a type of material or a width, can be identical.

[0059] According to a modified embodiment of the present invention, an order of the steps for anisotropic etching of the electrode layer and etching by using the mask pattern 260 may be reversed. After the electrode layer is formed to conformally cover the resulting structure where the memory structures 230 are formed, the mask patterns 260 may be formed to cross the memory structures 230. By performing anisotropic etching or isotropic etching on the electrode layer by using the mask pattern 260 as an etching mask, electrode patterns may be formed to cross the memory structures 230. Then, after the mask pattern is removed, the first and second electrodes 251 and 252 are formed by performing anisotropic etching on the electrode structures to expose a top surface of the memory structures.

[0060] Referring to Fig. 12A and Fig. 12B, after upper interlayer dielectrics 272 are formed on the resulting structure where the first and second electrodes 251 and 252 are formed, the upper interlayer dielectrics 272 are patterned to form contact holes 275 configured to expose the second electrodes 252. Subsequently, contact plugs 280 filling the contact holes 275 and bit lines 290 connecting the contact plugs 280 are formed.

[0061] The step of forming the contact holes 275 includes performing an anisotropic etch on the upper interlayer dielectrics 272 until the second electrodes 252 are exposed. The capping structure 237 is formed from a material having etch selectivity with respect to the upper interlayer dielectrics 272 to prevent the variable resistive structure 236 from being exposed through the contact hole 275. Furthermore, in another embodiment of the present invention, before the upper layers of the interlayer dielectrics 272 are formed, etch stop layers 271 may be further formed as shown, wherein the etch stop layers 271 are configured to conformally cover the resulting structure in which the first and second electrodes 251 and 252 are formed.The etch stop layers 271 may be made of a material having etch selectivity with respect to the upper layers of the interlayer dielectrics 272, for example silicon nitride.

[0062] Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A and Fig. 17A are plan views illustrating a method of forming a multi-level memory according to another embodiment of the present invention. Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B and Fig. 17B are process plan views illustrating a method of forming the multi-level memory according to another embodiment of the present invention. More specifically, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B and Fig. 17B contain cross-sectional views along lines III-III' and IV-IV' of Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A or 17A.

[0063] Referring to Fig. 13A and Fig. 13B, after device isolation layer structures 305 defining active regions AKT are formed on a substrate 300, gate structures 310 are formed crossing the active regions AKT. Impurity regions 315, which are used as source / drain electrodes of a transistor, are formed in the active regions AKT on both sides of the gate structures 310.

[0064] According to one embodiment, two gate structures 310 cross one of the active regions AKT. Therefore, in an active region AKT, one impurity region 315 is formed between the gate structures 310 and used as the common source electrode, and two impurity regions 315 are formed, each formed outside the gate structures and used as drain electrodes.

[0065] Subsequently, an interlayer dielectric 320 is formed to cover the gate structures 310, and contact plugs 325 coupled to the impurity regions 315 are formed to penetrate the interlayer dielectric 320. Then, contact pads 330 and a source line 335 are formed to be coupled to the contact plugs 325. The contact pads 330 are formed at each of the impurity regions used as a drain electrode, and the source line 335 is formed to connect the impurity regions used as a common source electrode.

[0066] Referring to Fig. 14A and Fig.14B, after insulating layers filling the contact pads 330 and the source line 335 have been formed, a first mold structure 340 is formed on the resulting structure. The first mold structure 340 is arranged on the source line 335 so that it crosses the active regions AKT and exposes portions of the upper surfaces of the contact pads 330. Conductive spacer structures 345 are then formed on both sides of the first mold structure 340.

[0067] The step of forming the conductive spacer structures 345 may include, after forming a conductive spacer layer on the resulting assembly in which the first mold structure 340 is formed, performing anisotropic etching on the conductive spacer layer to expose a top surface of the first mold structure 340. The conductive spacer structures 345 may be made of at least one selected from nitrides comprising metal elements, oxynitrides comprising metal elements, carbon (C), titanium (Ti), tantalum (Ta), aluminum-titanium (TiAl), zirconium (Zr), hafnium (Hf), molybdenum (Mo), aluminum (Al), aluminum-copper (Al-Cu), aluminum-copper-silicon (Al-Cu-Si), copper (Cu), tungsten (W), tungsten-titanium (TiW), and tungsten silicide (WSix).The nitrides comprising the metal elements may include TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, and / or TaAlN, and the oxynitrides comprising the metal elements may include TiON, TiAlON, WON, and TaON. Alternatively, the first mold structure 340 may be made of an insulating material, such as silicon nitride or silicon oxynitride.

[0068] Referring to Fig. 15A and Fig. 15B, the conductive spacer structures 345 are patterned to form first electrodes 347 arranged on sidewalls of the first mold structure 340.

[0069] This step may include, after the mask pattern intersecting the first mold pattern 340 has been formed at the contact pads 330, etching the conductive spacer structures 345 using the mask pattern as an etch mask. Accordingly, the first electrodes 347 are formed at each of the contact pads 330. The etching of the conductive spacer structures 345 may be performed using a wet or dry etching process.

[0070] Referring to Fig. 16A and Fig.16B, a second mold structure 350 is formed on the first mold structure 340 and the first electrodes 347. According to this embodiment, the second mold structure 350 is formed in a direction intersecting the first mold structure 340 and the source line 335 so as to cover the region between the first electrodes 347. Accordingly, the upper surfaces of the first electrodes 347 are exposed by the second mold structure 350. Further, the second mold structure 350 may be made of an insulating material, for example, silicon nitride or silicon oxynitride, and the thickness may be between about 200 to 500 Å.

[0071] Memory structures 360 are formed on both sidewalls of the second mold structure 350. The memory structures 360 include a plurality of variable resistive structures 362, 364, and 366 and separation layer structures 363 and 365 disposed between the variable resistive structures 362, 364, and 366. Consequently, the memory structures 360 are connected to the upper surfaces of the first electrodes 347 exposed on both sides of the second mold structure 350.

[0072] The variable resistive structures 362, 364, and 366 and the separation layer structures 363 and 365 can be formed by repeatedly performing a conventional spacer formation process, which may include thin film deposition and anisotropic etching steps. In this embodiment, three variable resistive structures are described as examples, but the number of variable resistive structures 362, 364, 366 and the separation layer structures 363 and 365 can be varied as needed. Meanwhile, mold spacers 361 can be further formed on sidewalls of the second mold structure 350 before the variable resistive structures 362, 364, and 366 are formed.

[0073] According to this embodiment, the variable resistive structures 362, 364, and 366 may be made from materials each having a different crystallization temperature. For example, the variable resistive structures 362, 364, and 366 may each be made from a different phase-change material. More specifically, the variable resistive structures 362, 364, and 366 may be made from a selected one of chalcogen compounds comprising tellurium (Te) at a concentration of about 20 to 80 atomic percent, antimony (Sb) at a concentration of 5 to 50 atomic percent, and germanium (Ge) at a concentration of the remaining atomic percent. The antimony-tellurium-selenium component ratio of each variable resistive layer may be different.

[0074] Furthermore, the widths of the variable resistive structures 362, 364, and 366 may differ from each other. In other words, each of the variable resistive structures 362, 364, and 366 may have a different cross-sectional area in the plane parallel to the substrate 300.

[0075] Referring to Fig. 17A and Fig. 17B, ​​second electrodes 370 are formed on the memory structures 360. The second electrodes 370 may include top electrode structures 371 and metal structures 372, which are respectively stacked. The second electrodes 370 may be used as bit lines for selecting a memory cell. The second electrodes 370 may be formed to intersect the gate structures 310, which are used as word lines.

[0076] The upper electrode structures 371 may be made of at least one selected from nitrides comprising metal elements, oxynitrides comprising metal elements, carbon (C), titanium (Ti), tantalum (Ta), aluminum-titanium (TiAl), zirconium (Zr), hafnium (Hf), molybdenum (Mo), aluminum (Al), aluminum-copper (Al-Cu), aluminum-copper-silicon (Al-Cu-Si), copper (Cu), tungsten (W), tungsten-titanium (TiW), and tungsten silicide (WSix). The nitrides comprising the metal elements may include TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, and / or TaAlN, and the oxynitrides comprising the metal elements may include TiON, TiAlON, WON, and TaON. Alternatively, the metal structure 372 may be made of a metallic material, such as aluminum, copper, and tungsten.

[0077] According to the previous exemplary embodiment, the variable resistive structures 362, 364 and 366 are connected in parallel between the first and second electrodes 347 and 370, and in contrast to the embodiments described with reference to Fig. 9 to 12, the variable resistive structures 362, 364 and 366 are formed at a substantially equal height above the top surface of the substrate 300.

[0078] According to the present invention, variable resistive structures connected in parallel between two electrodes are provided. By arranging the variable resistive structures in parallel, the resistance level of the memory cell having the same is determined by a set resistance of the variable resistive structures and is free from a resistance drift problem. Accordingly, the resistance drift problem that may occur over time does not occur or is reduced in the multi-level memory of the present invention. As a result, a multi-level cell having stable electrical characteristics can be realized. Furthermore, according to the present invention, the multi-level memory cell can be set to a data state by a single thermal process without reference to the initial state.

[0079] Although the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

[1] A multi-level memory comprising a memory structure (21, 31, 22, 32, 23; 230) arranged between a first electrode (11; 251) and a second electrode (12; 252), wherein a distribution density of a resistance level of the memory structure (21, 31, 22, 32, 23; 230) is higher at the minimum value thereof than at the maximum value thereof, and wherein the memory structure (21, 31, 22, 32, 23; 230) is arranged on a substrate (10; 200) and has a plurality of phase change structures (21, 22, 23; 232, 234, 236) which differ in a distance of their bottom surface from an upper surface of the substrate (10; 200). [2] A multi-level memory according to claim 1, wherein all resistance levels of the memory structure (21, 31, 22, 32, 23; 230) except the maximum value are closer to the minimum value of the resistance level than to the maximum value thereof. [3] A multi-level memory according to claim 1, wherein all resistance levels of the memory structure (21, 31, 22, 32, 23; 230) except the maximum value are less than a predetermined average resistance level, and the average resistance level is a value in the range between (R max - R min ) / 30 and R max is (where R max = the maximum value of the resistance level of the memory structure (21, 31, 22, 32, 23; 230), R min = the minimum value of the resistance level of the memory structure (21, 31, 22, 32, 23; 230)). [4] A multi-level memory according to claim 1, wherein the memory structure (21, 31, 22, 32, 23; 230) comprises a plurality of variable resistive structures (21, 22, 23; 232, 234, 236) and the resistance levels of the memory structure (21, 31, 22, 32, 23; 230) are substantially determined by a number of the variable resistive structures (21, 22, 23; 232, 234, 236) in a low resistance level state. [5] A multi-level memory according to claim 4, wherein the resistance levels of the memory structure (21, 31, 22, 32, 23; 230) are substantially inversely proportional to the number of variable resistive structures (21, 22, 23; 232, 234, 236) in a low resistance level state. [6] Multi-level memory according to claim 4, wherein the variable resistive structures (21, 22, 23; 232, 234, 236) are connected in parallel between the first electrode (11; 251) and the second electrode (12; 252). [7] Multi-level memory according to claim 4, wherein the resistance level R of the memory structure (21, 31, 22, 32, 23; 230) is given by the following equation: 1R=∑i=1n1Ri, (R i is a resistor of the variable resistive structure (21, 22, 23; 232, 234, 236), n is the number of variable resistive structures (21, 22, 23; 232, 234, 236) in the memory structure (21, 31, 22, 32, 23; 230).) [8] A multi-level memory according to claim 4, wherein the variable resistive structure (21, 22, 23; 232, 234, 236) comprises a material having temperature-dependent resistance level characteristics. [9] A multi-level memory according to claim 4, wherein respective variable resistive structures (21, 22, 23; 232, 234, 236) are configured to be capable of changing a resistance level by different write operation conditions. [10] A multi-level memory according to claim 4, wherein the variable resistive structures (21, 22, 23; 232, 234, 236) comprise a chalcogen compound selected from a group comprising at least one of antimony (Sb), tellurium (Te) and selenium (Se), and the antimony-tellurium-selenium component ratios of all the variable resistive structures (21, 22, 23; 232, 234, 236) differ from each other. [11] Multi-level memory according to claim 1, further comprising: a word line (205) arranged under the first electrode (251); a diode between the word line (205) and the first electrode (11; 251); and a bit line (290) connected to the second electrode (12; 252) to cross the word line (205). [12] Multi-level memory according to claim 1, further comprising: a selection transistor arranged under the first electrode (251) and having a gate electrode, a source electrode and a drain electrode; a plug (280) connecting the drain electrode of the selection transistor and the first electrode (251); and a bit line (290) connected to the second electrode (12; 252), wherein the gate electrode of the selection transistor is coupled to the word line (205) crossing the bit line (290). [13] The multi-level memory of claim 1, wherein at least one of the phase change structures (21, 22, 23; 232, 234, 236) is configured to be in contact with sidewalls of the first and second electrodes (11, 12; 251, 252). [14] Multi-level memory according to claim 1, wherein the phase change structures (21, 22, 23; 232, 234, 236) have different crystallization temperatures. [15] A multi-level memory according to claim 1, wherein the phase change structures (21, 22, 23; 232, 234, 236) differ from each other with respect to an antimony-tellurium-selenium component ratio. [16] Multi-level memory comprising: a substrate (10; 200); a storage structure (21, 31, 22, 32, 23; 230) between a first electrode (11; 251) and a second electrode (12; 252), the storage structure (21, 31, 22, 32, 23; 230) comprising: a first phase change structure (21, 22, 23, 232, 234, 236) having a bottom surface disposed a first distance above a top surface of the substrate (10, 200); and a second phase change structure (21, 22, 23, 232, 234, 236) whose bottom surface is arranged at a second distance above the upper surface of the substrate (10, 200), the second distance and the first distance being different, wherein the first and second phase change structures (21, 22, 23, 232, 234, 236) are connected in parallel between the first electrode (11; 251) and the second electrode (12; 252). [17] Multi-level memory according to claim 16, wherein the phase change structures (21, 22, 23; 232, 234, 236) are made of different materials. [18] A multi-level memory according to claim 16, wherein the phase change structures (21, 22, 23; 232, 234, 236) comprise a material selected from a group of chalcogen compounds comprising at least one of antimony (Sb), tellurium (Te) and selenium (Se). [19] Multi-level memory according to claim 18, wherein the phase change structures (21, 22, 23; 232, 234, 236) differ from each other with respect to an antimony-tellurium-selenium component ratio. [20] A multi-level memory according to claim 16, wherein the phase change structures (21, 22, 23; 232, 234, 236) differ from each other with respect to an area contacting the first electrode (11; 251) or the second electrode (12; 252). [21] Multi-level memory according to claim 16, wherein the phase change structures (21, 22, 23; 232, 234, 236) differ from one another with regard to a thickness or a cross-sectional area. [22] A multi-level memory according to claim 16, wherein the substrate (10; 200) is arranged under the first electrode (11; 251). [23] The multi-level memory of claim 22, wherein at least one of the phase change structures (21, 22, 23; 232, 234, 236) is configured to be in contact with sidewalls of the first and second electrodes (11, 12; 251, 252). [24] Multi-level memory according to claim 16, further comprising: a word line (205) under the first electrode (251); a diode arranged between the word line (205) and the first electrode (251); and a bit line (290) connected to the second electrode (252) to cross the word line (205). [25] Multi-level memory according to claim 16, further comprising: a selection transistor under the first electrode (251), the selection transistor having a gate electrode, a source electrode and a drain electrode; a plug (280) configured to connect the drain electrode of the selection transistor and the first electrode (251); and a bit line (290) connected to the second electrode (252), wherein the gate electrode of the selection transistor is connected to a word line (205) crossing the bit line.

Images