System and method for improving semiconductor drive performance using a programmable bus arbiter, and a storage medium for carrying out the method

Abstract

A storage medium (400) containing content which, when executed by an accessing machine, causes the accessing machine to: to delay a request from a semiconductor drive to access an interface for a period of time to allow a host to access the interface and transmit a command to the semiconductor drive; and to temporarily delay the request from a semiconductor drive to access an interface when there is less than a threshold number of commands pending in the semiconductor drive.

Description

FIELD OF THE INVENTION

[0001] Embodiments of the present invention relate generally to the field of data storage, and more particularly to a system and method for improving solid-state drive performance using a programmable bus arbiter, and a storage medium for performing the method. BACKGROUND OF THE INVENTION

[0002] Modern solid-state disk (SSD) drives have such high performance that they can saturate an interface, such as a Serial Advanced Technology Attachment (SATA) interface, in a very bursty manner. Because of these large bursts of data, new commands from a host may be prevented from being sent to the SSD until the SSD is idle for a period of time. As a result, an SSD may not be able to utilize the full concurrency of the NAND devices under very large pending workloads. New commands to the SSD may be blocked for several hundred microseconds, as the SSD is likely to obtain SATA bus arbitration while it has data ready to be sent to the host. This is not a problem with conventional spinning-disk drives, as they cannot fetch data for multiple commands in parallel. However, with SSDs, this can prevent the full utilization of multiple cooperating NAND channels.

[0003] US 2008 / 0140883 A1 discloses a priority or arbitration scheme. It discloses a bus arbiter for determining priority among a number of processes or units competing for access to a bus.

[0004] US 2009 / 0031073 A1 discloses a similar situation. There, a large number of controllers compete for access. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like reference numerals are used to refer to similar elements and in which: Fig. 1 is a graphical representation of an exemplary solid-state drive and host interface, according to an exemplary embodiment of the invention; Fig. 2 is a block diagram of an exemplary electronic device suitable for implementing the disclosed methods according to an exemplary embodiment of the invention; Fig. 3 is a flow diagram of an exemplary method for improving solid-state drive performance using a programmable bus arbiter according to an exemplary embodiment of the invention; and Fig. 4 is a block diagram of an exemplary article of manufacture including content that, when accessed by a device, causes the device to implement one or more aspects of one or more embodiments of the invention. DETAILED DESCRIPTION

[0006] In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be obvious to one skilled in the art that the invention may be practiced without these specific details. In other instances, structures and devices are shown in block diagram form so as not to obscure the invention.

[0007] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the use of the phrase "in one embodiment" in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0008] Fig. 1 is a graphical representation of an exemplary solid-state drive and host interface according to an exemplary embodiment of the invention. According to the illustrated exemplary embodiment, system 100 may include a host 102 and a solid-state drive (SSD) 104 communicating over and contending for access to interface 116. Host 102 may include host queue 106 to store pending commands 110, such as read requests, to be sent to SSD 104 when host 102 can access interface 116. SSD 104 may include disk queue 108 to store results 112, such as read access executions, to be sent to host 102 when SSD 104 can access interface 116.

[0009] Host 102 and SSD 104 may arbitrate for access to interface 116. In one embodiment, where SSD 104 submits access request 118 before host 102 submits access request 120, SSD 104 has access to interface 116 for access time 122 to transfer a stored result 112. When SSD 104 is finished transferring after access time 122, SSD 104 may be ready to submit another access request at time 124. However, SSD 104 may be used as part of a method for optimizing solid-state drive performance using a programmable bus arbiter, as described below with reference to Fig. 3, instead delaying a request to access interface 116 for a delay time 126 to allow host 102 to submit the access request 128 and transmit a command 110 to SSD 104 via interface 116 during the access time 130.

[0010] Delay time 126 may be initiated periodically or only when certain conditions are met. In one embodiment, delay time 126 is introduced to delay SSD 104 from requesting access to interface 116 when it is detected that host 102 has lost to SSD 104 in an attempt to access interface 116, such as in the case of access request 120. In one embodiment, delay time 126 is only introduced when there are fewer than threshold 114 results 112 stored in disk queue 108, for example, when it would be advantageous to allow host 102 to submit additional commands 110. Other methods or conditions for when to introduce delay time 126 may occur to one of ordinary skill in the art and are considered part of the spirit of embodiments of the invention. In one embodiment, delay time 126 comprises approximately 1 microsecond.

[0011] Fig. Figure 2 is a block diagram of an exemplary electronic device suitable for implementing the disclosed methods according to an exemplary embodiment of the invention. The electronic device 200 is intended to represent any of a wide variety of conventional and non-conventional electronic devices, laptops, desktop computers, mobile phones, wireless communication subscriber devices, wireless telephony infrastructure elements, personal digital assistants (PDAs), set-top boxes, or any other electrical device to which the teachings of the invention may be applied. According to the illustrated exemplary embodiment, the system 200 may include one or more processors 202, memory controller 204, system memory 206, input / output controller 208, network controller 210, input / output device(s) 212, solid-state drive 214, interconnect 216, and arbiter 218 coupled as shown in Fig. 2. In one embodiment, solid-state drive 214 includes flash memory, such as NAND flash memory, and interacts with I / O controller 208, while SSD 104 interacts with host 102. In one embodiment, arbiter 218 may introduce a delay 126 into SSD interconnect access requests as part of a method to improve solid-state drive performance, as described in more detail with reference to Fig. 3 described.

[0012] The processor(s) 202 may represent any of a wide variety of control logic components, including, but not limited to, one or more microprocessors, a programmable logic device (PLD), a programmable logic array (PLA), an application-specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this regard. In one embodiment, the processor(s) 202 are Intel®-compatible processors. The processor(s) 202 may have an instruction set that includes a plurality of machine-level instructions that may be called, for example, by an application or an operating system.

[0013] The memory controller 204 may represent any type of chipset or control logic that connects the system memory 206 to the other components of the electronic device 200. In one embodiment, the connection between the processor(s) 202 and the memory controller 204 may be a serial point-to-point link. In another embodiment, the memory controller 204 may be referred to as a northbridge.

[0014] System memory 206 may represent any type of memory device used to store data and instructions that may have been used or may be used in the future by processor(s) 202. System memory 206 typically consists of dynamic random access memory (DRAM), although the invention is not limited in this regard. In one embodiment, system memory 206 may consist of Rambus DRAM (RDRAM). In one embodiment, system memory 206 may consist of double data rate synchronous DRAM (DDRSDRAM).

[0015] The input / output (I / O) controller 208 may represent any type of chipset or control logic that connects the I / O devices 212 to the other components of the electronic device 200. In one embodiment, the I / O controller 208 may be referred to as a southbridge. In another embodiment, the I / O controller 208 may be a controller compliant with the PCI Special Interest Group's Peripheral Component Interconnect (PCI) Express™ Base Specification 1.0a, dated April 15, 2003.

[0016] Network controller 210 may represent any type of device that enables electronic device 200 to communicate with other electronic devices or apparatus. In one embodiment, network controller 210 may conform to the Institute of Electrical and Electronics Engineers, Inc. (IEEE) standard 802.11b (approved September 16, 1999, as an appendix to ANSI / IEEE Std 802.11, 1999 Edition). In another embodiment, network controller 210 may be an Ethernet network interface card.

[0017] I / O device(s) 212 may represent any type of device, peripheral, or component that provides input to or processes output from the electronic device 200.

[0018] Coupling structure 216 is shown as coupling solid-state drive 214 to I / O controller 208, however, solid-state drive 214 may be coupled to other components of electronic device 200. In one embodiment, coupling structure 216 represents a SATA bus.

[0019] While arbiter 218 is shown as part of solid-state drive 214, it may be included in another component of electronic device 200, such as I / O controller 208. In one embodiment, arbiter 218 may be software or a combination of software and hardware. In one embodiment, arbiter 218 represents an operating system (OS) application.

[0020] Fig. Figure 3 is a flow diagram of an exemplary method for improving solid-state drive performance using a programmable bus arbiter according to an exemplary embodiment of the invention. It will be readily apparent to those skilled in the art that, although the following operations may be described as a sequential process, many of the operations may actually be performed in parallel or cooperatively. Furthermore, the order of the operations may be rearranged without departing from the spirit of embodiments of the invention.

[0021] In one embodiment, method 300 begins with SSD 214 processing (302) a recently received request for data from I / O controller 208. In an exemplary embodiment, a command 110 may include a virtual address for data to be read from flash memory.

[0022] SSD 214 would then retrieve the requested data from flash memory (304). In one embodiment, SSD 214 would store the results in disk queue 108.

[0023] Method 300 continues with arbiter 218 determining (306) whether I / O controller 208 lost in an attempt to access interconnect 216. In one embodiment, arbiter 218 sets a flag or increments a counter when a losing access request 120 is detected.

[0024] Arbiter 218 may then delay (308) a request by SSD 214 to access interconnect 216 if certain conditions are met. In one exemplary embodiment, a delay time 126 is introduced when a losing access request 120 is detected. In one embodiment, arbiter 218 introduces delay time 126 when a formula based at least in part on the number of stored results 112 and / or a count of losing access requests 120 indicates that a delay would improve disk performance.

[0025] Then, method 300 may complete with SSD 214 requesting (310) access to interconnect 216 to transfer retrieved data, such as a stored result 112.

[0026] Fig.4 illustrates a block diagram of an exemplary storage medium including content that, when accessed, causes an electronic device to implement one or more aspects of the disclosed method 300. In this regard, storage medium 400 includes content 402 (e.g., instructions, data, or any combination thereof) that, when executed, causes the device to implement one or more aspects of the method described above.

[0027] The machine-readable (storage) medium 400 may include, but is not limited to, floppy disks, optical disks, CD-ROMs and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, flash memory, or other types of media / machine-readable medium suitable for storing electronic instructions. For example, the present invention may also be downloaded as a computer program product, where the program may be transmitted from a remote computer to a requesting computer using data signals embodied in a carrier wave or other propagation medium over a communications link (e.g., a modem, radio, or network connection).

[0028] In the foregoing description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention.

[0029] However, it will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0030] Embodiments of the present invention may be used in a variety of applications. Although the present invention is not limited in this respect, the invention disclosed herein may be used in microcontrollers, general-purpose microprocessors, digital signal processors (DSPs), reduced instruction-set computing (RISC), and complex instruction-set computing (CISC), among other electronic devices. However, it should be understood that the scope of the present invention is not limited to these examples.

[0031] Embodiments of the present invention may also be incorporated into integrated circuit blocks referred to as core memory, cache memory, or other types of memory that store electronic instructions to be executed by the microprocessor or that store data that can be used in arithmetic operations. In general, an embodiment utilizing multi-stage domino logic according to the claimed subject matter may provide an advantage for microprocessors and, in particular, may be incorporated into an address decoder for a memory device. It should be noted that the embodiments may be integrated into radio systems or portable devices, particularly when devices depend on reduced power consumption.Therefore, laptops, mobile radio telephone communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDAs), cameras and other products are intended to be included within the scope of the present invention.

[0032] The present invention encompasses various operations. These operations of the present invention may be performed by hardware components or implemented in machine-executable content (e.g., instructions) that can be used to cause a general-purpose or special-purpose processor or logic circuitry programmed with the instructions to perform the processes. Alternatively, the operations may be performed by a combination of hardware and software. Furthermore, although the invention has been described in the context of a computing device, those skilled in the art will recognize that such functionality may well be embodied in any number of alternative embodiments, such as integrated within a communications device (e.g., a cellular telephone).

[0033] Many of the methods are described in their most basic form; however, operations may be added to or removed from any of the methods, and information may be added to or removed from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept are anticipated within the scope and spirit of the present invention. In this regard, the specific exemplary embodiments illustrated are not provided to limit the invention, but only to illustrate it. The scope of the present invention is not determined by the specific examples listed above, but only by the following claims.

Claims

[1] A storage medium (400) comprising content that, when executed by an accessing machine, causes the accessing machine to: delaying a request from a solid-state drive to access an interface for a period of time to allow a host to access the interface and transmit a command to the solid-state drive; and temporarily delaying the request from a solid-state drive to access an interface when there are fewer than a threshold number of commands pending in the solid-state drive. [2] The storage medium (400) of claim 1, further comprising content that, when executed by an accessing machine, causes the accessing machine to detect whether the host has lost to the solid-state drive in an attempt to access the interface, and if it is detected that the host has lost, to initiate a delay time for a subsequent request from the solid-state drive to access the interface. [3] The storage medium (400) of claim 2, wherein the interface comprises a SATA interface. [4] The storage medium (400) of claim 3, wherein the semiconductor drive comprises NAND flash memory. [5] The storage medium (400) of claim 4, wherein the delay time comprises approximately 1 microsecond. [6] The storage medium (400) of claim 1, further comprising content that, when executed by an accessing machine, causes the accessing machine to delay periodic requests from the solid-state drive for access to the interface. [7] System (100; 200), comprising: a processor (202); a network controller (210), an interface host (102); and a semiconductor drive (104; 214), the semiconductor drive comprising an arbiter (218) for delaying a request from the semiconductor drive to access an interface (116) for some time to allow the interface host to access the interface and transmit a command to the semiconductor drive, and the arbiter for delaying a request from the semiconductor drive to access an interface only when there are fewer than a threshold number of commands pending in the semiconductor drive. [8] The system (200) of claim 7, further comprising an I / O controller (208) to determine whether the interface host (102) has lost to the solid-state drive (104; 214) in an attempt to access the interface (116) and to delay a subsequent request from the solid-state drive to access the interface (116). [9] The system (200) of claim 8, wherein the interface comprises a SATA interface. [10] The system (200) of claim 9, wherein the semiconductor drive (214) comprises NAND flash memory. [11] The system (100; 200) of claim 10, wherein the delay time comprises approximately 1 microsecond. [12] The system (200) of claim 7, further comprising the arbiter (218) to delay periodic requests from the solid-state drive to access the interface. [13] Method comprising: receiving a request for data at a solid-state drive; accessing the requested data on the semiconductor drive in response to the request; delaying an attempt to access an interface to transfer the requested data for some time to allow a host to access the interface and transfer a command to the solid-state drive, and temporarily delay a request from a solid-state drive to access an interface when there are fewer than a threshold number of commands pending in the solid-state drive. [14] The method of claim 13, further comprising determining whether the I / O controller lost to the solid-state drive in an attempt to access the interface, and delaying a subsequent request from the solid-state drive to access the interface. [15] The method of claim 14, wherein the interface comprises a SATA interface. [16] The method of claim 15, wherein the semiconductor drive comprises NAND flash memory. [17] The method of claim 16, wherein the delay time comprises approximately 1 microsecond. [18] The method of claim 13, further comprising delaying periodic requests from the solid-state drive to access the interface.

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