Method for manufacturing an optoelectronic semiconductor device

Abstract

Method for manufacturing an optoelectronic semiconductor device (200) comprising at least the following steps: - Providing a support arrangement (1) comprising a support body (11), an intermediate layer (12) arranged on an outer surface (111) of the support body (11) and a working layer (13) arranged on an outer surface (121) of the intermediate layer (12) facing away from the support body (11); wherein - the material of the intermediate layer (12) is different from the material of the wear layer (13), - Introducing at least two openings (4) spaced apart from each other in the lateral direction (L) into the working layer (13) via an outer surface (131) of the working layer (13) facing away from the support body (11), wherein the openings extend completely through the working layer (13) in the vertical direction (V); - Electrical insulation of the side surfaces (41) of the openings (4) and the outer surface (131) of the wear layer (13) facing away from the carrier body (11); - Arranging electrically conductive material (6) at least partially in the openings (4), wherein - after completion of the optoelectronic semiconductor device (200) the electrically conductive material (6) in its course along the outer surface (131) of the functional layer (13) has at least one interruption (U) between adjacent openings (4) - at least a polishing stop layer (7) is applied at least partially to the outer surface (131) of the wear layer (13) facing away from the carrier body (11), wherein the electrically conductive material (6) together with an outer surface of the polishing stop layer (7) facing away from the carrier body (11) forms a flat surface, and - Arranging at least one optoelectronic semiconductor body (8) on the outer surface (131) of the functional layer (13), wherein the optoelectronic semiconductor body (8) comprises at least one active zone (81) suitable for generating or detecting electromagnetic radiation and is electrically connected to the electrically conductive material (6).

Description

[0001] A method for manufacturing an electrical connection carrier, a method for manufacturing an optoelectronic semiconductor component, an electrical connection carrier, and an optoelectronic semiconductor component are described.

[0002] Documents US 7 714 345 B2, US 2002 / 0 135 069 A1, US 2008 / 0 272 497 A1, WO 2010 / 059 118 A1, US 2006 / 0 105 496 A1 and US 2007 / 0 290 329 A1 disclose methods for manufacturing an electrical connector, methods for manufacturing an optoelectronic semiconductor device, an electrical connector and an optoelectronic semiconductor device.

[0003] One problem to be solved is to specify a method for manufacturing an electrical contact carrier for an optoelectronic semiconductor body, in which material damage to the manufactured contact carrier is avoided.

[0004] In the first step of the process, a support structure is provided. This support structure can be a mechanically stable beam on whose outer surfaces, for example, components can be arranged and attached. In other words, the support structure is self-supporting and provides a stable mounting and / or support base for the components. The support structure can be designed in the form of a disk. Preferably, the lateral extent of the support structure is greater than its vertical extent. This means, for example, that the lateral extent of the support structure is at least five times greater than its vertical extent. In this context, "lateral direction" means a direction parallel to the main direction of extension of the support structure."Vertical direction" refers to a direction perpendicular to the main extension direction of the support assembly, for example, the thickness of the support assembly. The support assembly comprises a support body, with an intermediate layer arranged on one outer surface of the support body. Furthermore, a functional layer is arranged on an outer surface of the intermediate layer facing away from the support body. In this context, "functional layer" means that at least this layer remains in the finished electrical connector and, for example, performs an electrical and / or mechanical function when the electrical connector is integrated into an optoelectronic component.

[0005] The material of the intermediate layer differs from the material of the functional layer. In this case, the material of the functional layer is not identical to the material of the intermediate layer. For example, the intermediate layer is electrically insulating. The functional layer and the intermediate layer can differ from each other, at least in their chemical and / or physical properties.

[0006] In a further step of the process, at least two openings, spaced apart from each other in the laterally direction, are introduced into the functional layer via an outer surface of the functional layer facing away from the substrate, with the openings extending completely through the functional layer in the vertical direction. For example, the openings are introduced into the functional layer by means of at least one dry and / or wet chemical etching process. For example, the intermediate layer is essentially non-etchable compared to the functional layer when using the same etchant. In this context, "essentially non-etchable" means that the intermediate layer, when using an etchant, has an etch rate that is at most 20%, preferably less than 10%, of the etch rate of the functional layer when using the same etchant.In other words, in this case, the etching process occurs through the active layer, and the etching process is halted in the intermediate layer due to the material properties and the resulting low or non-existent etch rate. The intermediate layer in this case acts as an etch stop layer. In other words, creating openings in the active layer results in a highly selective etching process between the active layer and the intermediate layer. Alternatively or additionally, the etching process in the intermediate layer can also be interrupted or terminated by means of an etch endpoint detection system. This can be particularly useful when the active layer and the intermediate layer have similar or identical etch rates, as the etching process in this case does not necessarily stop spontaneously within the intermediate layer but must be interrupted or terminated externally.For example, the decay of an (etching) signal correlated with the working layer and / or the etching process, or the increase of an (etching) signal related to the intermediate layer and / or the etching process, could be used to interrupt and / or stop the etching process in time.

[0007] For example, each opening has at least one continuous and contiguous side surface, a bottom surface, and an opening opposite the bottom surface. The bottom surface can be formed entirely by the intermediate layer, while the side surface is formed at least partially by the surface layer.

[0008] In the next step, the side surfaces of the openings and the outer surface of the wear layer facing away from the substrate are electrically insulated. This means that no electric current can flow directly on the side surfaces of the openings or on the outer surface of the wear layer facing away from the substrate.

[0009] In the next step, electrically conductive material is placed at least partially within the openings. Once the connection carrier is complete, the electrically conductive material has at least one interruption in the lateral direction between adjacent openings along the outer surface of the functional layer. In other words, the electrically conductive material does not continuously connect adjacent openings in the lateral direction. For example, the openings are completely filled with the electrically conductive material. The interruption in the lateral direction, for instance, isolates electrically conductive material adjacent to each other within the openings.

[0010] According to at least one embodiment of the method, in a first step a carrier arrangement is provided, comprising a carrier body, an intermediate layer arranged on an outer surface of the carrier body, and a functional layer arranged on an outer surface of the intermediate layer facing away from the carrier body. In a next step, at least two laterally spaced openings are provided in the functional layer via an outer surface of the functional layer facing away from the carrier body, the openings extending completely through the functional layer in a vertical direction. In a further step, the side surfaces of the openings and the outer surface of the functional layer facing away from the carrier body are electrically insulated.In a further step, electrically conductive material is arranged at least partially in the openings, whereby, after completion of the connection carrier, the electrically conductive material has at least one interruption in its course along the outer surface of the working layer in the lateral direction between adjacent openings.

[0011] The method described here for manufacturing an electrical connection carrier is based, among other things, on the understanding that creating openings in a carrier body, which can serve for the subsequent electrical contacting of an optoelectronic component, can lead to damage to or within the carrier body. If the openings are created in the carrier using an etching process, for example, such an etching process can cause material damage in the carrier body, particularly in the area of ​​the openings' base surfaces. Since such a carrier body can remain part of the subsequent optoelectronic component, the optoelectronic component also exhibits such damage to its carrier body. For example, this can lead to an optoelectronic component whose optical output power and / or power handling capacity is reduced during operation.

[0012] To describe a method for manufacturing an electrical connector carrier that avoids such material damage in the carrier body, the method outlined here utilizes, among other things, the idea of ​​first placing an intermediate layer on the carrier body and then a functional layer on top of this intermediate layer. In other words, the intermediate layer is positioned between the functional layer and the carrier body. The intermediate layer can therefore act as a buffer and / or spacer between the carrier body and the functional layer. If openings are then introduced into the functional layer, for example, using an etching process, the intermediate layer can act as an etch stop, halting the etching process.In other words, the intermediate layer acts as the etch seal (also called a blind hole seal), so that any damage, for example, to the bottom surfaces of the openings, which might be caused by the etch seal, is caused only in the intermediate layer by the etching process, instead of in the functional layer. In other words, damage to the functional layer is avoided. To make the functional layer suitable for use in a later optoelectronic component, the next step involves electrically insulating the side surfaces of the openings and an outer surface of the functional layer facing away from the substrate. A semiconductor body of the later optoelectronic semiconductor component is then deposited on this outer surface, with the semiconductor body being electrically contacted via the electrically conductive material arranged in the openings.

[0013] According to at least one embodiment of the method, electrical insulation is carried out by means of at least one thermal oxidation process. Using such a process, the side surfaces of the openings and the outer surface of the wear layer facing away from the substrate can be electrically insulated particularly easily and cost-effectively. For example, the side surfaces of the openings and the outer surface are heated so that, for instance, the material of the wear layer is surface-oxidized.

[0014] According to at least one embodiment, the substrate is formed with silicon and the intermediate layer with a silicon oxide and / or a silicon nitride. For example, such a substrate is described in the publication "Silicon-on-insulator: materials aspects and applications, Andreas Plössl, Gertrud Kräuter, Solid-State Electronics layer 44 (2000) 775-782", the disclosure of which is hereby incorporated by reference.

[0015] According to at least one embodiment of the method, the wear layer is formed with or contains at least one of the materials Si, N, GaN, Ge, or GaAs. For example, the wear layer and the support body are formed with the same material, such as Si. In this case, such a support arrangement is particularly cost-effective. If the wear layer is formed with GaN, the intermediate layer and / or the support body can be formed with Si, for example. Advantageously, GaN and Si have similar coefficients of thermal expansion, so that the tensile and / or compressive stresses within the support arrangement are as low as possible, for example, during heating. Sapphire can also be used as the material for the support body and / or the intermediate layer instead of Si.Similarly, the intermediate layer can be formed with one or more sublayers, each composed of, for example, SiN. In this case, a further intermediate layer, composed of, for example, SiO2, can be placed on top of the intermediate layer. If the functional layer is composed of, for example, Ge, Ge, GaAs, or sapphire can be used as the material for the substrate and / or the intermediate layer. In this case, the electrical insulation of the side surfaces can be achieved not by thermal oxidation, but by depositing at least one electrically insulating layer onto the side surfaces of the functional layer.

[0016] According to at least one embodiment of the method, the electrically conductive material is introduced into the openings in the form of a melt and subsequently hardened, wherein the electrically conductive material is formed with or contains at least one of the materials Al, Zn, Cu, Ag, Si, Cd, Ga, In, Tl, Sn, Pb, Bi, Po, or AuSn. For example, such an introduction of electrically conductive material into the openings is described for Zn in the publication "Zinc and Tin-Zinc Via Filling for the Formation of Through-Silicon Vias in a System-in-Package," Journal of ELECTRONIC MATERIALS, Vol. 38, No. 5, 2009, the disclosure of which is hereby incorporated by reference. If the electrically conductive material is formed with a semiconductor material, it may be doped.

[0017] The electrically conductive material can also be alloys and / or electrically conductive metal pastes. If the electrically conductive material is in the form of a metal paste, the curing of the metal paste can occur isothermally.

[0018] Desired physical and / or technical properties of the electrically conductive material include high electrical and thermal conductivity, the closest possible match to the thermal expansion properties of the wear layer, and the best possible adhesion to the wear layer. Further criteria for selecting the appropriate material may include viscosity, surface tension, reactivity, or susceptibility to oxidation.

[0019] If the functional layer is installed together with the electrically conductive material in a semiconductor device, the highest possible electrical and thermal conductivity can help to avoid energy losses in the current supply within the semiconductor device and to ensure the most effective possible removal of power loss from the semiconductor device.

[0020] The table below compares the individual physical and / or technical properties of zinc and aluminum: aluminum zinc Melting point [°C] 660,4 419,6 Viscosity [mPa s] 1,2 3,5 Surface energy [J / m 2 ] 1,07 0,8 Specific electrical 2,7 6,0 Resistance [µΩ cm] Thermal conductivity [W / m K] 235 120 Linear thermal coefficient of expansion [10 -6 K - 1 ] 23,1 30,2

[0021] For example, copper and silver exhibit high electrical and thermal conductivity. If the electrically conductive material is formed with zinc, silicon, cadmium, gallium, indium, tungsten, tin, lead, bicarbonate, phosphate, or ferrous sulfate, it has a low melting point, which minimizes heat damage to the functional layer, for example, during filling the openings. On the other hand, the melting point is high enough that the electrically conductive material does not melt when the functional layer is incorporated into a later semiconductor device, for example, during a soldering process.

[0022] According to at least one embodiment, the electrically conductive material is an electrically conductive adhesive. For example, the adhesive is formed with a matrix material into which metal particles or other electrically conductive particles are incorporated, wherein the matrix material can harden after being poured into the openings.

[0023] According to at least one embodiment of the method, after curing, the electrically conductive material projects vertically beyond the wear layer. This means that the electrically conductive material protrudes vertically from the wear layer and is raised above it. In this case, the openings can be overfilled with the electrically conductive material, and the excess electrically conductive material emerging from the openings can be in direct contact with the outer surface of the wear layer facing away from the substrate.

[0024] Alternatively, the openings may only be partially filled with the electrically conductive material. In other words, the openings are underfilled in this case. This means that the functional layer extends vertically beyond the electrically conductive material. Such underfilling can be avoided or corrected by ensuring that the vertical extent of the functional layer and / or the intermediate layer is sufficiently small, or by selectively etching the functional layer and / or the intermediate layer back to the level of the electrically conductive material.

[0025] In a next step, at least a polishing stop layer is applied, at least partially, to the outer surface of the wear layer facing away from the substrate. The outer surfaces of the electrically conductive material facing away from the substrate may be at least partially free of the polishing stop layer, and the polishing stop layer may be formed with, for example, at least one of the following materials: SiO₂, Si₃N₄, SrO₂, HfO₂, HfO₂, ZrO₂, or at least contain one of these materials. For example, the polishing stop layer is applied only to the exposed outer surface of the wear layer. In a top view of the outer surface of the wear layer, the polishing stop layer may completely surround and enclose the electrically conductive material. For example, after the polishing stop layer has been applied to the outer surface of the wear layer, the electrically conductive material may also extend vertically beyond the polishing stop layer.In other words, in this case too, the electrically conductive material protrudes vertically from the polishing stop layer. It is also possible that the polishing stop layer is applied, at least partially, to the outer surface of the wear layer facing away from the substrate before the openings are created in the wear layer and / or before the electrically conductive material is applied. In this context, "polishing stop layer" means that, compared to the electrically conductive material, the polishing stop layer is significantly more difficult or even impossible to remove and / or polish using a chemical and / or mechanical polishing process. For example, after the polishing process, only the electrically conductive material shows traces of material removal.

[0026] After at least one polishing step has been applied to the electrically conductive material, the electrically conductive material does not extend beyond the polishing stop layer in the vertical direction. The electrically conductive material, together with an outer surface of the polishing stop layer facing away from the substrate, forms a flat surface. Advantageously, this avoids electrical and / or mechanical connection problems of the semiconductor body to the electrically conductive material when subsequently depositing it onto the polishing stop layer and the electrically conductive material.

[0027] According to at least one embodiment, after the electrically conductive material has been applied, the carrier body is removed from the intermediate layer. For example, the carrier body is removed by irradiating the intermediate layer with high-energy laser light, which at least partially destroys it (also known as laser lift-off). It is also conceivable that the carrier body is removed by etching and / or mechanically grinding the intermediate layer and / or the carrier body itself, at least in certain areas. Additionally, it is conceivable that any remaining traces of the intermediate layer after the carrier body has been removed are removed from the functional layer by further polishing. After the removal of the carrier body and, if applicable, the intermediate layer, only the functional layer remains in the finished connector carrier as the substrate material for the electrical connector.

[0028] Furthermore, a method for manufacturing an optoelectronic semiconductor device is described.

[0029] According to at least one embodiment of the method, in a first step an electrical connector is provided, which is manufactured by a method as described in one or more of the embodiments described herein. That is to say, the features implemented for the method described herein for manufacturing the electrical connector are also disclosed for the method described herein for manufacturing the optoelectronic semiconductor device, and vice versa.

[0030] In a further step, at least one semiconductor body is arranged on the outer surface of the functional layer. This semiconductor body comprises at least one active zone suitable for generating or detecting electromagnetic radiation and is electrically connected to the electrically conductive material. For example, at least two laterally adjacent openings, in which the electrically conductive material is located, are associated with each semiconductor body. In this case, the semiconductor body can have electrical contact points that are electrically connected to the outer surfaces of the electrically conductive material facing away from the substrate.

[0031] According to at least one embodiment, the semiconductor body is based on a III nitride semiconductor material. In this context, "III nitride semiconductor material" means that the semiconductor body is a nitride semiconductor material, preferably Al. n Ga m In 1-n-m N has or consists of it, where 0 ≤ m ≤ 1, 0 ≤ n ≤ 1 and m + n ≤ 1.

[0032] According to at least one embodiment, at least one protective diode structure is formed in the functional layer and electrically connected to the semiconductor body. For example, the protective diode structure is integrated into the functional layer. In this case, the outer surface of the functional layer facing away from the substrate, together with an outer surface of the protective diode structure, forms a flat surface. In other words, the protective diode structure does not protrude vertically from the functional layer. The protective diode structure protects the semiconductor body from electrostatic discharge. An electrical voltage, generated, for example, due to electrostatic charging, which is reverse-biased relative to the forward direction of the active zone, can dissipate via the protective diode structure. This prevents damage to the semiconductor body in the subsequent optoelectronic device.

[0033] Furthermore, an electrical connection carrier is specified.

[0034] For example, the electrical connection carrier can be manufactured using the method described here, as described in connection with one or more of the embodiments mentioned above. That is to say, the features implemented for the method described here are also disclosed for the electrical connection carrier described here, and vice versa.

[0035] According to at least one embodiment, the electrical connection carrier comprises at least one functional layer having an outer surface and a contact surface opposite the outer surface. The contact surface is part of the outer surface area of ​​the functional layer and faces a contact carrier—for example, a printed circuit board—when the electrical connection carrier is mounted. In other words, the contact surface is a mounting surface that can be used to mount the electrical connection carrier onto the contact carrier. For example, the contact surface is formed locally by the electrically conductive material. The outer surface and the contact surface are connected to each other via side surfaces of the connection carrier. For example, the side surfaces of the connection carrier extend vertically, i.e., perpendicular to the main direction of extension of the electrical connection carrier.

[0036] According to at least one embodiment, the electrical connection carrier comprises at least two openings arranged laterally apart from each other in the working layer, which are introduced into the working layer via the outer surface of the working layer.

[0037] According to at least one embodiment, the electrical connection carrier comprises electrically conductive material which is arranged at least partially in the openings, wherein the openings extend completely through the functional layer from the outer surface towards the contact surface.

[0038] The side surfaces of the openings and the outer surface of the wear layer are electrically insulating, with the electrically conductive material having at least one interruption in its course along the outer surface between laterally adjacent openings.

[0039] Furthermore, an optoelectronic semiconductor device is specified.

[0040] For example, the optoelectronic semiconductor device can be manufactured using the method described here, as described in conjunction with one or more of the embodiments mentioned above. That is to say, the features described for the method described here are also disclosed for the optoelectronic semiconductor device described here, and vice versa.

[0041] According to at least one embodiment, the optoelectronic semiconductor device comprises a terminal carrier as described in the embodiment described above. That is, the features implemented for the electrical terminal carrier are also disclosed for the optoelectronic semiconductor device described here, and vice versa.

[0042] According to at least one embodiment, the optoelectronic semiconductor device comprises at least one optoelectronic semiconductor body arranged on the outer surface of the functional layer, wherein the optoelectronic semiconductor body comprises at least one active zone suitable for generating or detecting electromagnetic radiation.

[0043] According to at least one embodiment, the optoelectronic semiconductor device comprises at least one protective diode structure formed in the functional layer, which is electrically interconnected with the semiconductor body.

[0044] The following section explains in more detail the method described here, as well as an electrical connection carrier and an optoelectronic semiconductor device described here, using exemplary embodiments and the corresponding figures. The Fig. 1A, Fig. 1B, Fig. 1C, Fig. 1D, Fig. 1E and Fig.Figure 1F shows individual manufacturing steps for the production of an embodiment of an optoelectronic semiconductor device described herein by a method described herein, wherein the Fig. Figure 1F shows a schematic side view of an embodiment of an optoelectronic semiconductor device described herein, comprising an embodiment of an electrical connection carrier described herein.

[0045] In the exemplary embodiments and figures, identical or similarly functioning components are each designated with the same reference numerals. The elements shown are not to scale; rather, individual elements may be exaggerated for clarity.

[0046] The Fig.Figure 1A shows a schematic side view of a support arrangement 1. The support arrangement 1 comprises a support body 11, an intermediate layer 12 arranged on an outer surface 111 of the support body 11, and a utility layer 13 arranged on an outer surface 121 of the intermediate layer 12 facing away from the support body 11. In particular, the support body 11 can be formed with silicon and the intermediate layer with an oxide of silicon and / or a nitride of silicon. The utility layer 13 is formed with or contains at least one of the materials Si, N, GaN, Ge, GaAs. For example, the utility layer 13 has a thickness of at least 30 µm to at most 250 µm, preferably at least 50 µm to at most 200 µm. In this context, "thickness" means a maximum extent of the utility layer 13 in the vertical direction V.

[0047] Furthermore, in the Fig.Figure 1B, a schematic side view of the support arrangement 1, shows that openings 4 are spaced apart from one another in the lateral direction L in the working layer 13 via an outer surface 131 of the working layer 13 facing away from the support 11, with the side surfaces 41 of the openings 4 being completely formed by the working layer 13. The openings 4 are formed in the working layer 13, for example, by means of at least one dry and / or wet chemical etching process. In other words, etching occurs in the vertical direction V through the working layer 13 during etching, with the etching process ending in the intermediate layer 12 and / or being stopped by the material of the intermediate layer 12. This means that the intermediate layer 12 is essentially not etchable compared to the working layer 13 when using the same etchant. The bottom surfaces 42 of the openings 4 are completely formed by the intermediate layer 12.

[0048] Furthermore, in the Fig. Figure 1B shows that a protective diode structure 9 is formed in the functional layer 13. The outer surface 131 and an outer surface 190 of the protective diode structure 9 form a flat surface.

[0049] Furthermore, the Fig. Figure 1B shows a thermal oxidation process 5 by means of which at least the side surfaces 41 and the outer surface 131 of the functional layer 13 facing away from the support body 11 are electrically insulated. In other words, no electric current will flow or be conducted directly on the oxidized areas of the outer surface 131 and the side surfaces 41 of the openings 4.

[0050] In the Fig.Figure 1C shows a schematic side view illustrating how, in a subsequent step, electrically conductive material 6 is introduced into the openings 4, for example, by filling them completely. This means that the electrically conductive material 6 fully fills the openings 4 and extends vertically beyond the working layer 13. For this purpose, the electrically conductive material 6 is introduced into the openings 4, for example, as a melt or by means of an electroplating process. After being introduced into the openings 4, the electrically conductive material 6 can harden within them. For example, underfilling of the openings 4 after and / or during the hardening and / or cooling of the electrically conductive material 6 within the openings 4 can be caused by volume contraction of the electrically conductive material 6.If attempts are made to remedy the underfill by thinning the functional layer 13, electrical insulation at an upper edge of the groove layer 13 may be damaged, potentially leading to operational and / or safety risks when the functional layer 13 is used in a semiconductor device. Overfilling and subsequent material removal, for example, protect this edge and any barrier and / or insulating layers applied to the outer surface 131 of the functional layer 13. Such barrier and insulating layers can be applied, for example, by chemical vapor deposition (CVD) and / or atomic layer deposition (ALD). Similarly, the intermediate layer 12 allows for opening and / or electrical connection of the electrically conductive material 6 by locally exposing and / or opening the electrically conductive material 6, without compromising the edge insulation of the openings 4.For example, the electrically conductive material 6 is formed with or contains at least one of the materials Al, Zn, Cu, Ag, Si, Cd, Ga, In, Tl, Sn, Pb, Bi, Po, AuSn. Furthermore, the . Fig. It can be deduced from Figure 1C that the electrically conductive material 6 has a break U in the lateral direction L along the outer surface 131 of the wear layer 13. This means that there is no electrically conductive connection between the openings 4 and the electrically conductive material 6 arranged in the openings 4. In other words, the electrically conductive material 6 arranged in the openings 4 is electrically isolated from each other.

[0051] In the Fig.Figure 1D shows a schematic side view illustrating how, in a subsequent step, a polishing stop layer 7 is applied to the outer surface 131, wherein the outer surfaces 61 of the electrically conductive material 6 facing away from the carrier body 11 are partially free of the polishing stop layer 7. In this case, the Fig. In step 1D, a polishing step has already been applied to the electrically conductive material 6, such that an outer surface 71 of the polishing stop layer 7 facing away from the carrier body 11 and the outer surfaces 61 of the electrically conductive material 6 form a flat surface. The polishing stop layer is formed with or contains at least one of the materials SiO2, Si3N4, SrO, HfO, HfO2, ZrO, ZrO2.

[0052] In the schematic side view of the Fig.Figure 1E shows in a further step how a semiconductor body 8 is applied to the outer surface 71 of the polishing stop layer 7 and the outer surfaces 61 of the electrically conductive material 6, wherein the semiconductor body 8 comprises at least one active zone 81 suitable for generating electromagnetic radiation. For example, the semiconductor body 8 is based on a III nitride semiconductor material. The semiconductor body 8 is electrically connected to the electrically conductive material 6. For this purpose, the semiconductor body 8 can have contact points which rest on the outer surfaces 61 of the electrically conductive material 6 and are, for example, in direct contact with them. In particular, the protective diode structure 9 can be electrically connected to the semiconductor body 8, thereby protecting the semiconductor body 8 from electrostatic discharge.

[0053] In the schematic side view of the Fig.Figure 1F shows that both the substrate 11 and the intermediate layer 12 have been completely removed from the functional layer 13, and that after the removal of the substrate 11 and the intermediate layer 12, an optoelectronic semiconductor device 200 comprising an electrical contact carrier 100 has been produced. For example, the removal can be carried out by applying high-energy laser light to the intermediate layer 12, which is at least partially destroyed by the laser light. Any remaining traces of the intermediate layer 12 can be removed from the functional layer 13 by at least one chemical and / or mechanical polishing step. The optoelectronic semiconductor device 200 has a contact surface 132 opposite the outer surface 131. In this case, the contact surface 132 is formed in places by outer surfaces of the electrically conductive material 6.The openings 4 extend from the outer surface 131 towards the contact surface 132 completely through the wear layer 13.

Claims

[1] Method for manufacturing an optoelectronic semiconductor device (200) comprising at least the following steps: - Providing a support arrangement (1) comprising a support body (11), an intermediate layer (12) arranged on an outer surface (111) of the support body (11) and a working layer (13) arranged on an outer surface (121) of the intermediate layer (12) facing away from the support body (11); wherein - the material of the intermediate layer (12) is different from the material of the wear layer (13), - Introducing at least two openings (4) spaced apart from each other in the lateral direction (L) into the working layer (13) via an outer surface (131) of the working layer (13) facing away from the support body (11), wherein the openings extend completely through the working layer (13) in the vertical direction (V); - Electrical insulation of the side surfaces (41) of the openings (4) and the outer surface (131) of the wear layer (13) facing away from the carrier body (11); - Arranging electrically conductive material (6) at least partially in the openings (4), wherein - after completion of the optoelectronic semiconductor device (200) the electrically conductive material (6) in its course along the outer surface (131) of the functional layer (13) has at least one interruption (U) between adjacent openings (4) - at least a polishing stop layer (7) is applied at least partially to the outer surface (131) of the wear layer (13) facing away from the carrier body (11), wherein the electrically conductive material (6) together with an outer surface of the polishing stop layer (7) facing away from the carrier body (11) forms a flat surface, and - Arranging at least one optoelectronic semiconductor body (8) on the outer surface (131) of the functional layer (13), wherein the optoelectronic semiconductor body (8) comprises at least one active zone (81) suitable for generating or detecting electromagnetic radiation and is electrically connected to the electrically conductive material (6). [2] Method according to claim 1, wherein the support body (11) is formed with silicon and the intermediate layer (12) is formed with an oxide of silicon and / or a nitride of silicon. [3] Method according to any of the preceding claims, wherein the wear layer (13) is formed with or contains at least one of the materials: Si, N, GaN, Ge, GaAs. [4] Method according to any of the preceding claims, wherein the electrical insulation is carried out by means of at least one thermal oxidation process (5). [5] Method according to any of the preceding claims, wherein the electrically conductive material (6) is introduced into the openings (4) in the form of a melt and subsequently hardens, wherein the electrically conductive material (6) is formed with or contains at least one of the following materials: Al, Zn, Cu, Ag, Si, Cd, Ga, In, Tl, Sn, Pb, Bi, Po, AuSn. [6] Method according to one of the preceding claims, wherein after curing the electrically conductive material (6) extends beyond the wear layer (13) in a vertical direction (V). [7] Method according to one of the preceding claims, wherein outer surfaces (61) of the electrically conductive material (6) facing away from the carrier body (11) are at least partially free of the polishing stop layer (7) and the polishing stop layer (7) is formed with at least one of the following materials or contains at least one of the following materials: SiO2, Si3N4, SrO, HfO, HfO2, ZrO, ZrO2. [8] Method according to one of the preceding claims, wherein after arranging the electrically conductive material (6) the carrier body (11) is removed from the intermediate layer (12). [9] Method according to any of the preceding claims, wherein the functional layer (13) of the carrier body (11) has a thickness of at least 30 µm and at most 250 µm. [10] Method according to the preceding claim, wherein at least one protection diode structure (9) is formed in the functional layer (13) which is electrically connected to the semiconductor body (8).

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