Event system and timing for a battery management and battery protection system

Abstract

Battery management and battery protection system comprising: a plurality of modules (204, 206, 208), at least one of which determines whether an operating characteristic of a battery (100) is within a predetermined range when the battery (100) is coupled to the system; a central processing unit (202); and a timer (240) for generating a set of events, each having a corresponding frequency F / n1, F / n2... F / nm, where n are integers, wherein each of the modules (204, 206, 208) receives one or more of the events, wherein the generation of the events and the transmission of the events to the modules (204, 206, 208) are independent of the central processing unit (202), and wherein the results trigger the execution of one or more actions by the modules (204, 206, 208).

Description

Some modern portable devices (e.g., laptop computers, mobile phones, digital cameras, video cameras, media players, PDAs, game consoles) contain battery packs. A battery pack contains one or more battery cells connected to one or more integrated circuit (IC) chips. These chips typically include a controller (e.g., a microcontroller) and circuitry, and perform functions such as battery cell management and protection. Some battery packs contain a lithium-ion (Li-ion) battery cell, which essentially involves a volatile chemical reaction within a cylinder or other container. Potential energy is stored in each cell. If the battery cell is exposed to environmental conditions outside its specifications, it can overheat, catch fire, or explode. Some battery packs configured with such volatile cells include a protective circuitry to detect hazardous conditions (e.g., overcurrent charging or discharging, short circuits) and to take corrective action to prevent damage to the battery cell and / or the device and to protect the end user. Details of one or more implementations of the invention are described below with reference to the accompanying drawings. According to one aspect, the operation of a battery management and protection system involves generating a set of events, each with a frequency F / n1, F / n2... F / nm, where ni are integers. One or more events are passed to one or more modules in the system. These events, generated independently of a central processing unit and passed to the modules, trigger specific actions by the modules. Some implementations offer one or more of the following advantages. For example, the specified techniques and event system enable the automation of critical and non-critical tasks in a battery management and protection system without requiring firmware involvement (i.e., independent of the CPU 202). For instance, the techniques and event system can help provide safe and predictable handling and response times for critical tasks, thus reducing firmware qualification requirements. The techniques and event system can also help reduce power consumption. However, implementations may also be realized that offer not all or none of the advantages mentioned here. Other aspects, features, and advantages of the invention are clarified by the following description, the drawings, and the claims. Fig. 1 is a schematic view of an application including a battery pack. Fig. 2 is a schematic view of a battery pack operating circuit. Fig. 3 is a block diagram showing various modules of a battery management and battery protection system. Fig. 4 illustrates some features of the system with respect to battery protection. Fig. 5 illustrates further features of a battery measurement subsystem. Fig. 6 illustrates some features of the system with respect to an event system for communication between the modules. Fig. 7A shows exemplary clock signals generated by a timer in the event system. Fig. 7B shows exemplary time signals generated by the timer to trigger an oscillator calibration. Fig. 8 is a flowchart showing an example of a sleepwalking function. The following description refers to a single-chip battery management and protection system, in which a microcontroller, non-volatile memory, and other circuit components are integrated into a single integrated circuit. However, the system can also be implemented in a multi-chip solution. As described below, the battery management and protection system includes autonomous safety and measurement functions and can be used, for example, in a management and protection system for lithium-ion or other batteries. As shown in Fig. 1, a battery pack 100 can be connected to a device 102 or a charger 104. When the battery pack 100 is connected to the charger 104, terminals (e.g., positive and negative terminals and a communication terminal) of the battery pack 100 are connected via a medium 106 to corresponding terminals (i.e., positive and negative terminals and communication terminals) of the charger 104 in order to charge the cell(s) associated with the battery pack 100. The medium 106 can be wires, connectors, pins, or other electrical connections. When the battery pack 100 is connected to the device 102, the terminals (i.e., positive and negative terminals and communication terminals) of the battery pack 100 are connected via a medium 108 to corresponding terminals (i.e., positive and negative terminals and communication terminals) of the device 102 to enable the operation of the device 102. The medium 108 can be wires, connectors, pins, or other electrical connections. In some implementations, the battery pack 100 is also connected to the device 102 and the charger 104 at corresponding communication terminals to allow the transmission of information (for commands and control) between the device 102 / charger 104 and the battery pack 100. An example of the information to be transmitted is the battery charge level (i.e., the capacity). As shown in Fig. 2, the battery pack 100 comprises one or more battery cells 120, discrete transistors 110, 112, a sensing resistor 114, and a battery management and protection system 130. The system 130 contains various components, as explained below, which can be integrated into a single package (i.e., integrated into a single integrated circuit) or packaged separately. Discrete transistors 110, 112 can be provided separately from the system 130 and contained in a separate package, or they can be packaged together with other system components. Discrete transistors 110 and 112 are used as switches to disconnect the battery cells 120 from the external battery pack terminals (the external positive and negative battery pack terminals 140 and 150). The implementation shown comprises two discrete transistors, which can be implemented, for example, as field-effect transistors (FETs). Other transistor technologies can also be used, but FETs offer advantages in terms of process, performance (e.g., on-resistance), cost, and size. The two transistors in the implementation shown are a charging transistor 110 and a separate discharging transistor 112. The charging transistor 110 is used for safely charging the battery cells 120. The discharging transistor 112 is used for safely discharging the battery cells 120. As shown in Fig. 2, the charging and discharging transistors 110 and 112 are coupled in series. In some implementations, two N-channel FETs (NFETs) are used, coupled drain-to-drain in a series configuration. In other implementations, two P-channel FETs (PFETs) may be used. In a PFET solution, additional diodes may be required to provide power to system 130. In the implementation shown, the charge and discharge transistors 110 and 112 are coupled in a high-side configuration (i.e., the series transistors are coupled to the high side, rather than the low side, of the battery cell). In this high-side configuration, one terminal (e.g., the source) of the charge transistor 110 is coupled to the positive terminal of the battery cell 120. One terminal (e.g., the source) of the discharge transistor 112 is coupled to the external positive battery pack terminal 150. Corresponding second terminals of the charge and discharge transistors 110 and 112 are coupled to each other (forming a drain-drain junction). The gates of the charge transistor 110 and the discharge transistor 112 are coupled to the system 130 at their respective inputs OC and OD. The junction between FET transistors 110 and 112 is coupled to system 130 at an input (VFET) that provides operating power for system 130. An on-chip low-dropout voltage regulator (LDO) regulates the voltage at the VFET input to provide a suitable voltage supply (e.g., 2.2 V) for the internal logic, I / O lines, and analog circuitry. The regulated voltage is also supplied to an external pin, VREG. Battery cell 120 is a rechargeable lithium-ion (Li-ion) or lithium-polymer (Li-polymer) battery. However, other battery technologies can also be used. If multiple cells are used, they can be connected in series, parallel, or in a series / parallel combination. In the implementation shown, the positive terminal of battery cell 120 is connected to system 130 (e.g., to detect the battery voltage level at input PV1) and to one of the discrete transistors (e.g., the charging transistor 110). The negative terminal of battery cell 120 is also connected to system 130 (e.g., to detect the battery voltage level at input NV) and to a terminal of the detection resistor 114. The detection resistor 114 is connected to system 130 (to allow measurement of the current flow through the detection resistor 114 at input PI).The second terminal of the resistance sensor is connected to the local ground (the local ground of a smart battery), system 130 (to measure the current flow through the sensing resistor 114 at input NI), and to the external negative battery pack terminal 140 of battery pack 100. An implementation with only one battery cell is shown here, but battery pack 100 can contain any other number of battery cells. In some implementations, battery pack 100 also includes a circuit assembly 116 that acts as a fuse. Certain battery technologies can lead to dangerous situations if not used correctly. For example, lithium-ion and lithium-polymer batteries can overheat, explode, or ignite if overcharged or discharged too quickly. Dangerous situations can also arise if the battery is discharged too deeply. Furthermore, lithium-ion and lithium-polymer batteries can lose a significant portion of their charge capacity when deeply discharged. System 130 includes monitoring electronics to ensure reliable operation. Among other things, System 130 helps ensure current flow to and from battery cell 120 and maintain battery cell 120's voltage and temperature within safe limits. Various aspects of System 130 are explained in more detail below. As shown in Figures 3 and 4, a battery management and protection system 130 comprises a software-based central processing unit (CPU) 202, which can be implemented, for example, as a low-power 8-bit CMOS microcontroller based on a RISC architecture. The CPU 202 ensures correct program execution and can access memory, perform calculations, and control other modules in the system. A memory (e.g., flash memory) 214 stores instructions that can be executed by the CPU 202. The battery management system 130 shown also includes a RAM 210 and an EEPROM 212 as additional memory. Some implementations may also include other types of memory. In the example shown, the aforementioned on-chip LDO regulator for regulating the VFET connection voltage can be provided as part of the voltage regulator 248 to provide a suitable supply voltage for the internal logic, the I / O lines, and the analog circuitry. The regulated voltage will also be available at the VREG pin (Fig. 2). System 130 contains various modules that provide battery measurement and protection. These modules include a voltage analog-to-digital converter (V-ADC) module 204, a current analog-to-digital converter (C-ADC) module 206, and a current protection module 208. These modules, which contain circuitry and logic, are explained in greater detail below. The V-ADC module 204 can be implemented, for example, as a 16-bit sigma-delta analog-to-digital converter optimized for measuring voltage and temperature. It includes multiple selectable input channels for, say, a scaled battery cell voltage, general-purpose inputs (e.g., for use as an external temperature sensor), an internal temperature sensor, a scaled battery voltage (BATT), and diagnostic functions. The V-ADC 204 can perform single conversions or channel sampling under firmware control (i.e., under the control of a CPU 202). The V-ADC module 204 can also perform automatic battery protection sampling. In the case of sampling for single conversion / channel sampling mode, the CPU 202 selects the channels and begins sampling. In contrast, automatic protection sampling is performed independently of the firmware (i.e., independently of the CPU 202).As explained in more detail below, the automatic protection sampling is configured with automatically loaded values ​​during system 130 startup. The V-ADC module 204 performs an automatic sampling and compares the measured values ​​(e.g., battery cell voltage and / or temperature) with automatically loaded trip values. These features allow the V-ADC module 204 to provide accurate, yet configurable, protection values ​​for battery cell voltage and temperature. The C-ADC module 206 is configured to measure the current flow through an external sensing resistor (e.g., the sensing resistor 114 in Fig. 2). In the implementation shown, the C-ADC module 206 provides both instantaneous and accumulated outputs. The instantaneous current value can be useful for various critical battery management tasks, such as monitoring the charging current during undervoltage recovery and fast charging, monitoring the battery pack state (e.g., standby or discharge), providing accurate overcurrent protection, and performing impedance calculations. The C-ADC module 206 can include a window comparator 207 to determine whether the battery voltage is within a user-programmable range. This feature can be used, for example, when a charger is connected or disconnected and to detect the presence of excessive charging or discharging currents.The comparator 207 can generate a break signal or other event if the instantaneous current is outside the specified range for a user-programmable number of samples. In some implementations, the comparator 207 is configured to generate an "event" when the current is too high and to generate a break signal when the current is low. This and other "events" are explained in greater detail below in connection with the event system (see Fig. 6). The system 130 shown includes a voltage reference module 244, which provides a very accurate reference voltage (e.g., 1100 V) and an internal temperature reference for the V-ADC module 204. An example of the connections between the modules that form the battery measurement subsystem is shown in Fig. 5. The reference voltage is also supplied to pin VREF (Fig. 2). The current protection module 208 samples the voltage across the sensing resistor 114 at user-programmable intervals and compares the voltage to several programmable values. The protection values ​​are configured by programming specific locations of the flash memory 214 (or EEPROMs 212) with the desired protection values. As explained in more detail below, registers are automatically loaded from these flash memory locations during system 130 startup. Violation counters enable time-based filtering of overcurrent and short-circuit current. In some implementations, the current protection module 208 is configured to generate an "event" when the current falls outside a specified range. This and other "events" are explained in more detail below in connection with the event system (see Fig. 6). The battery management system 130 also includes a module 216 for controlling the FET transistors 110 and 112. In the implementation shown, the FET controller 216 includes several outputs (e.g., OC, OD) that are coupled to external devices which can be configured by the FET controller 216 to control the current flow between the battery cell 120 and a device or charger. The FET controller 216 includes circuitry and logic for generating voltages at the OC and OD outputs. In some implementations, the OC output is a high-voltage output coupled to the gate of a charging FET (e.g., the charging transistor 110) to allow or partially restrict current flow during a charging event. The OD output is a high-voltage output coupled to the gate of the discharging FET (e.g., the charging transistor 110).of the discharge transistor 112) is coupled to allow or prevent the current flow during a charging event by the discharge FET completely or partially. The CPU 202 and other modules send and receive signals via one or more buses 218 (Fig. 3). One bus is an input / output bus 218A (Fig. 4). Another bus 218B is used for loading safety and other parameters from the flash memory 214 during system startup. The system also includes an interrupt bus 218C for communicating interrupt signals to / from the CPU 202 or another module. Furthermore, a dedicated control network 219 allows "events" to be passed between certain modules independently of the CPU 202, which is explained in more detail below with reference to the event system (see Fig. 6). As shown in Fig. 3, System 130 also includes a sleep / power module 246, which is explained below. Other components and modules that may be included in the implementation 130 shown are oscillators 250, a wake-up timer (WUT) 252, a watchdog timer (WDT) 254, a universal asynchronous sender / receiver (UART) 256, a two-wire bidirectional (TWI) bus 258, an on-chip debug (OCD) module 260, an interrupt control device 262, and an oscillator / clock control device 264. A practical implementation of System 130 may also include other components, modules, and subsystems not shown in Fig. 3 for the sake of simplicity. Furthermore, some implementations need not include all of the components, modules, and subsystems shown in the example of Fig. 3. To improve the safe operation of the System 130, various safety and calibration parameters are automatically loaded from non-volatile memory to dedicated input / output registers in one or more of the modules during system startup. Safety parameters can be used by the system to determine the safety functions of the battery 120. In one implementation, user-programmable safety parameters are stored in dedicated locations in the flash memory 214. During system startup, these parameters are automatically loaded from the flash memory 214 to dedicated registers 215 by the reset control unit 220 (Fig. 3). The bus 218B (Fig. 4) is used to transfer the safety parameters from the flash memory 214 to the dedicated registers 215. The CPU 202 can read the registers 215 but cannot write to them. The safety parameters stored in the dedicated registers 215 cannot be changed during operation. By automatically loading battery protection and calibration parameters from predefined locations during the startup cycle, independently of the CPU 202 and the firmware (e.g.,(during a reset cycle), the safe operation of the System 130 can be improved. The 215 registers can be distributed across various modules for implementing critical safety functions. For example, the 215 registers in the V-ADC module 204 can store information for determining the channels used in a protection scan, determining the protection scan frequency, and specifying the thresholds for cell voltage comparators. The 215 registers in the current protection module 208 can, for example, store information on current protection control, short-circuit protection timing, overcurrent protection timing, short-circuit detection values, discharge overcurrent detection values, and charge overcurrent detection values.The registers 215 in the FET controller 216 can, for example, store information about an action to be taken when a signal is received indicating one of the following events: a short-circuit protection event, a discharge overcurrent protection event, a charge overcurrent protection event, a cell overvoltage protection event, a cell undervoltage protection event, an internal temperature overvoltage protection event, and an internal temperature undervoltage protection event. Other safety parameters can also be loaded during startup and automatically stored in dedicated registers 215 in this or other modules of the system 130. The parameters used for calibrating various aspects of System 130 can also be automatically loaded during startup (e.g., during reset) from non-volatile memory 214 into dedicated input / output registers, as described above for the safety parameters. Examples of such parameters include parameters for calibrating voltage references and parameters for calibrating oscillators. In some implementations, calibration values ​​can be stored in the non-volatile memory 214, for example, during chip manufacturing or by a customer. Some customers prefer to use the factory default values ​​provided by the manufacturer to reduce testing costs, while others prefer to choose the calibration parameters themselves for greater accuracy.Some implementations allow the customer to choose whether the parameters are loaded from a first location containing values ​​stored by the manufacturer or from a second location containing the customer's own values. Non-volatile memory can be used to enable this choice for the customer. In some implementations, the system is reset by a reset request and held in the reset state as long as the request is active. Once all reset requests have been canceled, System 130 goes through several stages before the internal reset is canceled and system operation begins. In some implementations, before the internal reset is canceled, a counter delay is reset and started, oscillators are started, the counter delay expires, and the safety and calibration parameters are loaded from non-volatile memory 214 as described above. Other operations can also be performed during the startup (e.g., reset) of System 130, such as setting input / output registers to their corresponding output values. Although much communication in System 130 takes place via the CPU 202, System 130 also includes an event system for certain communication between modules. The event system allows a state change in one module of the system to automatically trigger an action in one or more other modules of the system, independently of the CPU 202. Such a notification of a change in a module is called an "event." Events are transmitted between modules using a dedicated control network 219 (Figs. 3 and 4). The module that generates the event is sometimes called the event generator, while the module that uses the event is sometimes called the event user. The action triggered by the event is sometimes called the event action.Some event users can receive events from one or more event creators and can initiate the same or different event actions. As shown in Fig. 6, one such event generator is a timer 240, which is part of the event control unit 222 (see Fig. 3). The timer 240 acts as a centralized timer that controls when certain events occur and is directly coupled via the dedicated control network 219 to some of the modules, such as the V-ADC module 204, the C-ADC module 206, and the current protection module 208. A timer 308 generates events (e.g., pulse signals) that, in turn, trigger clock activation events. In some implementations, the event signals can be used directly as clock signals. The timer 308 can generate a set of divided event signals. For example, in the implementation shown, the timer 240 includes a prescaler that takes an event signal (clk) and generates power-of-two divisions of the output signal. The timer 240 generates a set of divided signals, each with a corresponding frequency clk / 2 ...exhibiting clk / 2'', where n is an integer. In one particular implementation, the timer 240 generates a first event signal with a frequency clk / 2, a second event signal with a frequency clk / 4, a third event signal with a frequency clk / 8, and a fourth event signal with a frequency clk / 16 (Fig. 7A). In some implementations, the timer 240 generates additional or other synchronous event signals. For example, in some implementations, a second event signal is divided from the first event signal, the third event signal is divided from the second event signal, and so on. If a slow event signal has an active edge, the faster event signals also have an active edge. In other situations, the division factors can be any series of integers (e.g., clk / 2, clk / 3, clk / 4).In general, the timer 240 generates a set of divided signals, each with a corresponding frequency F / n1, F / n2... F / nm, where ni are integers. Timer 240 is used to generate events for the modules connected to it. Each module can individually select its desired clock division (e.g., based on information automatically loaded into register 215 during startup). For example, one module (e.g., the V-ADC module 204) can be programmed to clk / 32, a second module (e.g., the C-ADC module 206) can be programmed to clk / 128, and a third module (e.g., the current protection module 208) can be programmed to clk / 32. In this example, the first and third modules, 204 and 208, receive events simultaneously, while the second module, 206, receives events at 1 / 4 of the frequency. In this example, the timer events for all modules are synchronized. When the second module receives events, the first and third modules receive them simultaneously.For example, timer events can be used to trigger measurements and detect safety issues. The timer 240 acts as an initiator for several event sequences. The timer outputs events at regular intervals to trigger actions in other modules (e.g., the V-ADC module 204, the C-ADC module 206, and the current protection module 208). Event sequences for protection events that can be configured during operation are initiated by the timer 240 and trigger event actions, for example, in the C-ADC module 206. In the example shown, event sequences for automatically loaded protection events are also initiated by the timer 240 and trigger event actions in the V-ADC module 204 and the current protection module 208.Examples of actions that can be set to be triggered by the timer 240 at regular events include: a protection scan by the V-ADC module, a current measurement by the C-ADC module, a detection of regular current, a detection of high charging / discharging currents, measurements by the current protection module, a detection of a short-circuit current, and a detection of charging / discharging overcurrents. The V-ADC module 204, the C-ADC module 206, and the current protection module 208 can each act as an event generator. For example, events generated by the C-ADC module 206 can trigger one or more event actions in the FET controller 216. For this purpose, the C-ADC module 206 is connected to the FET controller 216 via a dedicated control network 219, allowing events to be communicated directly from the C-ADC module 206 to the FET controller 216, independently of the CPU 202. Similarly, the V-ADC module 204 and the current protection module 208 can each trigger one or more event actions in the FET controller 216. For this purpose, the V-ADC module 204 and the current protection module 208 are also connected to the FET controller 216 via the dedicated control network 219, so that such events can be communicated directly and independently of the CPU 202 from the V-ADC module 204 or the current protection module 208 to the FET controller 216. An example of an action that can be triggered based on events from the aforementioned modules is the deactivation of FETs 110 and 112. For example, FETs 110 and 112 can be automatically deactivated based on one or more of the following events: an over / undervoltage of the V-ADC channel, an over / undertemperature of the V-ADC channel, a high charge / discharge current of the C-ADC, a detection of a C-ADC discharge current at low voltages, a charge / discharge overcurrent of the current protection module, and a short circuit of the current protection module. The event system enables the automation of critical and non-critical tasks within a battery management and protection system without involving the firmware (i.e., independently of the CPU 202). For example, the event system can help ensure safe and predictable handling and response times for critical tasks, thus reducing firmware qualification requirements. Simultaneously, the battery management and protection system offers flexibility by allowing users to program certain safety parameters, as described above. For non-critical tasks, the event system can help reduce the time the CPU 202 needs to be in active mode, thereby also contributing to lower power consumption. The event system can still be used to support other events that are not critical for battery protection event loops. For example, events from timer 240 can be used to increment a timer / counter 242 (Fig. 3 and Fig. 5). The event system can also be used to trigger various system calibrations at regular intervals, independently of the CPU 202. Using the event system allows calibration to be triggered simultaneously with other events. When events occur concurrently, measurements triggered by event signals from the timer can also be performed synchronously to reduce the time the central modules are active. This, in turn, reduces overall power consumption. For example, events generated by the timer 240 can help ensure that the calibration of oscillators 250 is performed at regular intervals without the involvement of the CPU 202. Because calibration can be performed simultaneously with other activities that share the same resources, power consumption can be reduced.Therefore, system calibration can be initiated during operation based on one or more timer events. For example, high-precision oscillators consume a considerable amount of power. Therefore, in some implementations, a reference oscillator is only switched on at regular time intervals. This time interval can be based, for example, on a parameter automatically loaded from non-volatile memory 214 into a dedicated register 215 during startup. Temperature variations in the oscillator can be eliminated, for example, by calibrating the oscillator against a measured temperature at regular time intervals. In some implementations, the system 130 is configured to calibrate the oscillator by calculating a target cycle ratio between the reference oscillator and the target oscillator, partly based on the last temperature reading by the V-ADC module 204.The use of the timer 240 to trigger the temperature readings and the subsequent calibration allow the various actions to be carried out simultaneously at precisely determined times, as shown in the example of Fig. 7B. If a 240 timer is not included in some implementations, various other modules must be implemented, each with its own prescaler, which increases the overall cost of System 130. Cost savings can be achieved by including a centralized 240 timer in System 130. Furthermore, ensuring synchronous operation without the centralized timer can be complicated. As mentioned above, various modules perform battery measurement functions. The measurement subsystem automatically conducts controlled safety measurements of the battery as well as CPU-controlled measurements of the battery's state of charge and health. The modules of the battery measurement subsystem include the V-ADC module 204, the C-ADC module 206, the current protection module 208, and the voltage reference module 248. As previously explained, these modules contain dedicated registers 215 into which safety parameters are automatically loaded when the system 130 starts, independently of the CPU 202. Furthermore, critical safety measurements are triggered by events generated by the timer 240 and communicated via the event management network 219, independently of the CPU 202. Thus, the same modules that perform the firmware-controlled measurements involving the CPU 202 also perform the battery safety measurements independently of the CPU 202. Therefore, by using the same hardware modules for both types of battery measurements, the size and cost of the system 130 can be reduced in some cases. A sleep / power management control module 246 (Fig. 3) allows the battery management system 130 to enter one or more sleep modes (with low power consumption) to reduce power consumption. Sleep modes can be entered from an active mode in which the CPU 202 executes application code. The application code determines when to enter a sleep mode and which sleep mode to enter. Interrupt signals from activated modules and activated reset sources can reset the CPU 202 from sleep mode to active mode. A sleep mode type available in some implementations is called an idle mode, in which the operations of the CPU 202 and the non-volatile memory are stopped. In idle mode, other modules, including the event control device 222 (explained above) and the interrupt control device 262 (see Fig. 3), continue to operate if enabled. Interrupt requests from enabled interrupt signals wake up the system 130. To reduce power consumption in idle mode, unused modules can be disabled. Some implementations may also support additional or alternative low-power or sleep modes in which some of the modules in the System 130 are inactive. For example, some implementations include a power-saving mode in which various modules (e.g., the V-ADC module 204 and the C-ADC module 206) cannot normally operate, even if they are enabled. To minimize power consumption in power-saving mode, modules driven by enabled oscillators that are not in use should be disabled. This stops the clocks for the modules, resulting in a significantly reduced power consumption. The modules connected to the event system support "sleepwalking." Situations may arise where the system 130 is in a sleep mode, but a specific module in the event system needs to send an event to another module. If the target module is sleep-deprived (i.e., in a low-power mode), the event automatically triggers an event request to the target module so that the target module can process the event and then return to sleep mode. The dedicated event routing network 219 can be used to communicate the event request to the target module. Modules that do not normally operate in sleep mode can still operate in sleep mode by being triggered by the sleepwalking function. The sleepwalking function allows modules in the event system (e.g., the timer 240, the V-ADC module 204, the C-ADC module 206, and the power protection module 208) to continue performing critical safety or other functions even when the system 130 is in a low-power mode (e.g., sleep mode). Thus, if, as shown in Fig. 8, the timer 240 attempts to send an event to the V-ADC module 204, the C-ADC module 206, or the power protection module 208 while the target module is in low-power mode (block 302), the event automatically triggers an activation request to the target module (block 304). In response to receiving the activation request, the target module processes the event and then returns to sleep mode (block 306).Certain modules are activated to perform specified tasks even when the System 130 is in a sleep or low-power mode, in which these modules could not operate without the sleepwalking function. Furthermore, the sleepwalking function operates independently of the CPU 202. Therefore, certain tasks can be performed without waking the CPU 202. An example of how the sleepwalking function can be used in the implementation shown is as follows. The C-ADC module 206 has a programmable sampling mode, allowing it to perform an immediate conversion for a measured battery current value. The timer 240 triggers events so that the C-ADC module 206 samples battery current values ​​at regular intervals. If the C-ADC module 206 is in a sleep mode when sampling is due to occur, the sleepwalking function allows the C-ADC module 206 to be woken up and perform the immediate conversion. If, accordingly, the V-ADC module 204, the C-ADC module 206 or the current protection module 208 attempts to send an event to the FET controller 216 while the FET controller is in a low-power mode, the event automatically triggers an activation request to the FET controller, so that the FET controller processes the event and then returns to sleep mode. In some implementations, the timer 240 is connected to a timer / counter 242 (Fig. 3 and Fig. 5), which can be used, for example, to track time. If the system 130 is in a low-power mode when a timer event is triggered, the sleepwalking function can be used to increment the counter value of the timer / counter 242. To provide greater safety, some implementations of the battery management and battery protection system include 130 diagnostic functions that can be used to ensure the correct operation of the system. As explained below, various analog signals and values ​​at external pins of the battery management system 130 can be checked by the CPU 202. If a diagnostic function is outside the expected range, the CPU 202 can cause the FET controller 216 to disable FETs 110 and 112 (see Fig. 2) to maintain battery safety. For example, the voltage reference module 244 can include a window comparator that continuously monitors the VREF pin (see Fig. 2) to detect whether the reference voltage is short-circuited to ground or to a power supply (VDD). If a short-circuit condition occurs, the CPU 202 can cause FETs 110 and 112 to be disabled to protect the system. The CPU 202 can also perform various diagnostic tests in conjunction with the V-ADC module 204, which includes a dedicated battery channel (BATT) for detecting FET failures, faulty chargers, and disconnected pins. The CPU 202 can perform one or more diagnostic tests using signals on the battery channel. For example, when FETs 110 and 112 are fully activated, the voltage drop between the battery side and the charger / load side should be close to zero. After FETs 110 and 112 are activated, the difference between the battery channel voltage and the cell voltage can be calculated to determine if the FET is correctly switched on. If the measured voltage is outside the expected range, the CPU 202 can deactivate the FETs. A FET failure can also be detected by separate differential channels that directly measure the FET voltage drop. If a charger is connected to the battery management system (see Fig. 1), the battery channel can be used to check whether the charging voltage is within an acceptable range before FETs 110 and 112 are activated. Furthermore, measuring the battery channel while FETs 110 and 112 are active can reveal if the battery pin is not properly connected to a circuit board. If the result differs significantly from the battery cell voltage, the CPU 202 can deactivate the FETs. The CPU 202 can also perform diagnostic tests on the PV1 and NV pins of the V-ADC module 204 (see Fig. 2 and Fig. 5). For example, the CPU 202 can activate an internal pull-down resistor for the PV1 pin to determine whether the CPU 202 has a good connection to the positive cell terminal. If the result is significantly lower than expected while the pull-down resistor is activated, the CPU 202 determines that there is a poor connection. For the NV pin, the CPU 202 can activate an internal pull-up resistor to detect a poor connection to the negative cell resistor. With the pull-up resistor activated, the voltage difference between the NV and PV pins increases significantly if there is a poor connection to the cell. Conversely, if there is a good connection, the voltage difference is small.If any of the results are outside the expected range, the CPU 202 can disable FETs 110 and 112. In some implementations, if a protection scan is initiated while these diagnostic functions are being performed, the pull-up and pull-down resistors are automatically disabled to ensure a correct result from the protection scan. The CPU 202 can also perform diagnostic checks on pins PI and NI of the C-ADC module 206 (see Fig. 2 and Fig. 5), both of which have internal pull-up resistors for detecting a poor connection with the detection resistor 114. If the pull-up resistor for pin PI or pin NI is activated and the pin has a poor connection, the conversion result saturates to a maximum conversion value. In some implementations, if a protection scan is initiated while these diagnostic functions are running, the pull-up and pull-down resistors are automatically deactivated to ensure a correct result from the protection scan. Several advantages of some System 130 implementations are discussed above. Some System 130 implementations may include other advantages in addition to or as alternatives to those discussed above. For example, the firmware (i.e., the CPU 202) can control an initial configuration to adapt to specific application requirements, allowing the system to then run autonomously. Because the firmware only handles the initial configuration, the overhead for verifying a correct configuration is relatively low. Once the configuration is established, the hardware automatically handles critical safety functions without involving the firmware. The firmware can optionally lock the configuration registers from further CPU write access to ensure that safe operation is not compromised by firmware errors. The system can simplify product qualification for the customer by eliminating firmware errors that could compromise system safety. This reduces the effort required to qualify the system for various safety approvals. Improved system accuracy can also reduce the likelihood of undetected, unsafe operating conditions of a lithium-ion battery in some implementations, thereby enhancing battery safety. Due to the system's improved accuracy, developers can charge more energy into the battery pack without exceeding the battery cell's safety limits. This increased battery capacity makes more energy available to the user per unit charge. Furthermore, the improved accuracy allows for a more accurate estimate of remaining battery life. This prevents situations where the reported battery capacity suddenly and rapidly drops from indicating sufficient remaining capacity to indicating very low remaining capacity, prompting system shutdown. As previously explained, some features of the System 130 can help reduce power consumption. Reduced power consumption allows for a longer lifespan for new battery packs. Furthermore, it can reduce the risk of accidentally discharging a battery cell to an unsafe and dangerous level. Other implementations within the scope of the invention defined by the claims are also possible.

Claims

Battery management and battery protection system comprising: a plurality of modules (204, 206, 208), at least one of which determines whether an operating characteristic of a battery (100) is within a predetermined range when the battery (100) is coupled to the system; a central processing unit (202); and a timer (240) for generating a set of events, each having a corresponding frequency F / n1, F / n2... F / nm, where n are integers, wherein each of the modules (204, 206, 208) receives one or more of the events, wherein the generation of the events and the transmission of the events to the modules (204, 206, 208) are independent of the central processing unit (202), and wherein the results trigger the execution of one or more actions by the modules (204, 206, 208). System according to claim 1, characterized in that the set of events comprises pulse signals which are divided from one another. System according to claim 1, characterized in that the set of events comprises pulse signals which are divided from each other by powers of two. System according to claim 3, characterized in that the pulse signals comprise a first pulse signal with a frequency F, a second pulse signal with a frequency F / 2, a third pulse signal with a frequency F / 4, a fourth pulse signal with a frequency F / 8 and a fifth signal with a frequency F / 16. System according to claim 1, characterized in that the events are synchronous. System according to claim 1, characterized in that at least one of the modules (204, 206, 208) is arranged to monitor the voltage, current and / or temperature of a battery (100) when the battery (100) is coupled to the system, and that at least one of the events triggers an action in connection with the monitoring of the at least one module (204, 206, 208). System according to claim 6, characterized in that at least one of the modules (204, 206, 208) is arranged to use one or more of the events for sampling measurements of battery operating characteristics and for triggering reactions to the sampling. System according to claim 1, further characterized by a dedicated guidance network (219) for guiding corresponding events from the timer (240) to corresponding modules (204, 206, 208). System according to claim 8, characterized in that the dedicated control network (219) directs the corresponding events from the timer (240) to the corresponding modules (204, 206, 208). System according to claim 8, characterized in that the dedicated control network (219) directs the corresponding events from the timer (240) to the corresponding modules (204, 206, 208) independently of the central processing unit (202). System according to claim 8, characterized in that one or more of the modules (204, 206, 208) that receive an event from the timer (240) are arranged to receive signals indicating the voltage, current and / or temperature of a battery (100) when the battery (100) is coupled to the system. System according to claim 8, characterized in that the dedicated guidance network (219) is arranged to guide an event from a first module (204, 206, 208) to another module (204, 206, 208), wherein the event indicates a change of state detected by the first module (204, 206, 208). System according to claim 1, characterized in that the system is a battery management and battery protection system for a Li-ion battery. System according to claim 1, characterized in that the system has one or more low-power sleep modes in which the modules (204, 206, 208) can be operated to receive and respond to events from the timer, even when the modules (204, 206, 208) are in a low-power sleep mode. Method for operating a battery management and battery protection system comprising a central processing unit, wherein the method comprises the following steps: Generating, independently of the central processing unit, a set of events, each having a frequency F / n1, F / n2... F / nm, where n are integers, and providing, independently of the central processing unit, one or more events to one or more modules in the system, wherein the events trigger the execution of corresponding actions by the modules. Method according to claim 15, characterized in that the set of events comprises pulse signals that are divided from one another. Method according to claim 16, characterized in that the set of events comprises pulse signals which are each divided from each other by powers of two. Method according to claim 16, characterized in that the pulse signals comprise a first pulse signal with a frequency F, a second pulse signal with a frequency F / 2, a third pulse signal with a frequency F / 4, a fourth pulse signal with a frequency F / 8 and a fifth signal with a frequency F / 16. The method according to claim 15, characterized in that the events are synchronous. Method according to claim 15, wherein the modules receive the events and perform one or more actions even when the modules are in a low-power sleep mode. Battery management and battery protection system comprising: a module (204, 206, 208) for determining whether an operating characteristic of a battery (100) is within a predetermined range when the battery (100) is coupled to the system, a central processing unit (202), a timer (240) for generating a set of divided pulse signals, each having a frequency F / n1, F / n2... F / nm, where n are integers, and a dedicated control network (219) that directs one or more of the pulse signals to the module (204, 206, 208) independently of the central processing unit (202), wherein the pulse signals received by the module (204, 206, 208) trigger the execution of one or more actions by the module (204, 206, 208). System according to claim 21, wherein the set of pulse signals consists of pulse signals which are each divided by powers of two with respect to each other. System according to claim 21, wherein the pulse signals are synchronous.

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