Optoelectronic semiconductor device and method for its manufacture

Abstract

Optoelectronic semiconductor device comprising a substrate (2) and at least one semiconductor chip (1) arranged thereon, wherein: - the semiconductor chip (1) has an active layer (1a) suitable for generating radiation, - conductive traces for electrical contacting the semiconductor chip (1) are arranged on the substrate (2), - the semiconductor chip (1) is encapsulated with a potting material (5), and - the potting material (5) has at least a first potting layer (5a), a second potting layer (5b) and a third potting layer (5c), wherein: - the first potting layer (5a), the second potting layer (5b) and the third potting layer (5c) differ from each other in at least one of the following properties: their material composition, their optical properties, their chemical properties, and - in the second potting layer (5b), which is arranged on the side of the first potting layer (5a) facing away from the substrate (2),The pigments are included, which increase the reflectivity of the second potting layer (5b).

Description

The invention relates to an optoelectronic semiconductor device comprising a substrate and a semiconductor chip mounted thereon. The present invention further relates to a method for manufacturing such a semiconductor device. Semiconductor devices, which consist of a substrate and a semiconductor chip mounted on it, often also feature a potting compound that encapsulates the semiconductor chip. Common potting compounds include silicone and epoxy. However, silicone is permeable to gases, which means that gases present in the vicinity of the semiconductor device can pass through the potting compound to the substrate and, for example, reach the conductive traces located there. This can lead to corrosion of the conductive traces. Epoxy as a potting material, on the other hand, exhibits good gas tightness, thus preventing the penetration of harmful gases into the epoxy potting compound. However, epoxy is disadvantageously not light-stable. In particular, epoxy potting compounds can yellow and / or crack due to exposure to UV light. Documents US 2006 / 0 091 788 A1 , US 2008 / 0 218 072 A1 , US 2009 / 0 256 166 A1 and US 2009 / 0 278 147 A1 describe light-emitting components. Document US 2009 / 0 001 390 A1 describes a matrix material with particles for light-emitting components. The publication US 2008 / 0 231 181 A1 describes a phosphor-converted LED. It is an object of the present invention to provide a semiconductor device that avoids the aforementioned disadvantages, advantageously resulting in an age-stable semiconductor device that, in particular, comprises a potting material characterized by improved gas tightness and simultaneously by improved light stability. Furthermore, it is an object of the present invention to provide a manufacturing process for such an improved semiconductor device. These problems are solved by a semiconductor device having the features of claim 1. Furthermore, these problems are solved by a manufacturing process having the features of claim 10. Advantageous embodiments of the semiconductor device and the manufacturing process are the subject of the dependent claims. The optoelectronic semiconductor device comprises a substrate and at least one semiconductor chip mounted on it. The semiconductor chip has an active layer suitable for radiation generation. Conductive traces are arranged on the substrate for electrical contacting the semiconductor chip. The semiconductor chip is encapsulated with a potting material that has at least a first, a second, and a third potting layer. The potting layers of the material differ from one another in their material composition and / or in their optical and / or chemical properties. The conductive traces can, for example, be a body or a layer formed with a metal prone to corrosion, such as silver. Thus, the substrate can, for example, be designed as a conductor frame consisting of the metal or having a layer of this metal. The potting compound thus consists of several layers, the materials of which are selected according to the desired properties. This advantageously makes it possible to create a potting compound with a multitude of desired properties, which is conventionally not possible with a single-piece potting compound due to the limited material selection. For example, the use of such a triple-layer potting compound combines the advantages of the gas tightness of an epoxy potting compound with the light stability of a silicone potting compound. The conductive traces of the substrate usually contain silver. However, silver is susceptible to silver corrosion due to sulfur-containing compounds and corrosive gases that can penetrate a silicone potting compound. Triple-layer potting, by using different materials with varying properties, can advantageously prevent silver corrosion of the conductive traces, as one of the potting layers is gas-tight. The layers of the potting compound may have different matrix materials, such as silicone or epoxy. Additionally or alternatively, the layers may differ due to particles or pigments incorporated into the matrix material. For example, one layer of the potting compound may contain an additional pigment, while the other layers do not. The semiconductor device is an optoelectronic semiconductor device that enables the conversion of electronically generated data or energy into light emission, or vice versa. For example, the optoelectronic semiconductor device comprises a semiconductor chip, preferably a radiation-emitting semiconductor chip, such as an LED. The active layer of the semiconductor chip preferably contains a pn junction, a double heterostructure, a single quantum well (SQW), or a multi quantum well (MQW) for radiation generation. The term "quantum well structure" here has no bearing on the dimensionality of the quantization. It includes, among other things, quantum wells, quantum wires, and quantum dots, and any combination of these structures. The semiconductor chip preferably comprises a sequence of semiconductor layers made of semiconductor material. In particular, the semiconductor chip, especially the active layer, preferably contains a III / V semiconductor material. III / V semiconductor materials are particularly suitable for generating radiation in the ultraviolet, visible, and infrared spectral ranges. The semiconductor chip has a plurality of epitaxially deposited semiconductor layers in which the active layer is arranged. For example, the layers of the semiconductor chip are grown on a substrate that has subsequently been at least partially or completely removed. According to at least one embodiment, the potting layers of the potting material are arranged vertically one above the other. The potting material thus comprises a stack of different potting layers. The height of each individual potting layer in the vertical direction can be adapted to the desired properties. For example, the first potting layer is applied directly to the substrate and at least partially encloses the semiconductor chip. The semiconductor chip is thus located within the first potting layer, with its height being greater than the height of the first potting layer. The second potting layer can be applied directly to the first and also at least partially enclose the semiconductor chip. In this case, the combined height of the first and second potting layers can be less than the height of the semiconductor chip, so that the semiconductor chip extends vertically beyond both layers. The third potting layer can be applied to the second and completely enclose the semiconductor chip.The combined height of the first potting layer, the second potting layer, and the third potting layer therefore exceeds the height of the semiconductor chip, so that the semiconductor chip is completely enclosed by the first potting layer, the second potting layer, and the third potting layer. According to at least one embodiment, the first potting layer facing the substrate is designed as a gas barrier. This allows for a potting material that is at least partially gas-tight. The first potting layer is directly adjacent to the substrate. Advantageously, the first potting layer protects the conductor tracks of the substrate from corrosion. The first potting layer thus advantageously prevents the diffusion and penetration of gases occurring in the environment to the conductor tracks of the substrate. Preferably, the first potting layer exhibits a gas impermeability to harmful gases of over 80%, more preferably over 90%, and most preferably over 95%. According to at least one embodiment, the first potting layer is an epoxy layer. An epoxy layer is characterized by particularly good gas tightness but exhibits low light stability. By forming a first epoxy potting layer on the substrate, followed by a second and third potting layer, the advantages of such an epoxy layer can be exploited. At the same time, the epoxy layer is not exposed to the radiation-emitting side of the semiconductor chip, as it is only located on the side surfaces of the semiconductor chip, thus preventing yellowing or cracking of the epoxy layer. According to at least one embodiment, the second potting layer, which is arranged on the side of the first potting layer facing away from the substrate, contains pigments that increase the reflectivity of the second potting layer. The increased reflectivity of the second potting layer advantageously protects the underlying epoxy layer from light-induced yellowing and cracking. In particular, the second potting layer protects the first potting layer from degradation that can occur, for example, due to reflected radiation. Advantageously, the second potting layer has a reflectivity of 60% for radiation in the visible wavelength range, preferably 80%, preferably 90%. According to at least one embodiment, the pigments are white pigments. White pigments introduced in this way are particularly advantageous for increasing reflectivity. According to at least one embodiment, the second potting layer is a silicone layer. A silicone layer is characterized in particular by its light stability for radiation in the UV and visible wavelength ranges. Gases passing through the silicone layer are prevented from reaching the substrate and the conductor tracks applied to it by the first epoxy potting layer, thus ensuring sufficient protection against corrosion. According to at least one embodiment, the third potting layer, which is arranged on the side of the second potting layer facing away from the first potting layer, comprises a highly transparent, light-stable material. In particular, the third potting layer is located downstream of a radiation-emitting side of the semiconductor chip, such that the radiation generated in the semiconductor chip is coupled out of the semiconductor device by the third potting layer. Due to the highly transparent and light-stable material of the third potting layer, efficient light extraction from the device and an age-resistant device can be achieved. The third potting layer also protects the semiconductor chip from the environment. The term "highly transparent" means in particular that the material of the third potting layer is preferably 80%, preferably 90%, and especially preferably 95% transparent to radiation in the UV or visible spectral range. Light stability means, in particular, that the material of the third potting layer exhibits no or minimal yellowing or cracking effects when exposed to UV light for a certain period of time. Preferably, the material of the third potting layer is UV stable. According to at least one embodiment, the third potting layer is a silicone layer. For example, the third potting layer is a clear potting compound, preferably containing no pigments or particles. According to at least one embodiment, the semiconductor device comprises a housing with a cavity in which the semiconductor chip is arranged, wherein the potting material is placed in the cavity and surrounds the semiconductor chip. The housing, for example, encloses the substrate at least partially, so that a bottom surface of the cavity is formed by the substrate or by the conductor tracks of the substrate. The substrate is preferably a metal support, for example a lead frame, which consists, for example, of a copper substrate with at least one layer of a precious metal, which may be silver, for example. Alternatively, the substrate may be a printed circuit board (PCB). The potting material preferably completely encloses the semiconductor chip. Preferably, the potting material completely fills the cavity of the housing, so that a surface of the housing is flush with a surface of the potting material. A method for manufacturing a semiconductor device comprises the following process steps: - providing a substrate with conductive traces applied to it, - applying and electrically contacting a semiconductor chip on the substrate, - applying a first potting layer to the substrate, which at least partially encloses the semiconductor chip, - applying a second potting layer to the first potting layer, which at least partially encloses the semiconductor chip, and - applying a third potting layer to the second potting layer, which at least partially encloses the semiconductor chip, wherein the first potting layer, the second potting layer and the third potting layer differ from each other in their material composition and / or in their optical and / or chemical properties. The features and advantages mentioned in connection with the semiconductor device also apply to the manufacturing process and vice versa. A semiconductor device manufactured in this way is characterized by a triple encapsulation that combines the advantages of epoxy and silicone encapsulation. In particular, this method yields an encapsulation material that exhibits suitable gas tightness and light stability. For this process, a semiconductor chip is successively encapsulated with the different materials of the individual encapsulation layers. The different materials are applied one on top of the other in a vertical direction. According to at least one embodiment, the semiconductor device has a housing with a cavity, wherein the semiconductor chip and the potting compounds are placed into the cavity. Preferably, the potting compound completely encloses the semiconductor chip and flushly seals the cavity of the housing. Further advantages and advantageous developments of the invention will become apparent from the exemplary embodiments described below in conjunction with Fig. 1 and Fig. 2. Figures 1A and 1B each show a schematic cross-section of an embodiment of a semiconductor device according to the invention in the manufacturing process, and Figure 2 shows a schematic cross-section of a semiconductor device according to the prior art. In the figures, identical or similarly functioning components may be labeled with the same reference symbols. The depicted components and their relative sizes are not to be considered to scale. Rather, individual components such as layers, structures, parts, and areas may be exaggeratedly thick or large for clarity and / or better understanding. Figure 2 shows a cross-section of a semiconductor device comprising a semiconductor chip 1 in a housing 4. The housing 4 has, in particular, a cavity 4a in which the semiconductor chip 1 is arranged. One base of the cavity 4a is formed by a substrate 2 on which conductive traces are arranged for electrical contacting the semiconductor chip 1. For electrical contacting of the semiconductor chip 1, the semiconductor chip 1 is attached, for example, by means of an adhesive layer, such as an adhesive or a solder layer, to one of the conductor tracks of the substrate 2. A second conductor track, electrically insulated from this conductor track, is arranged on the substrate 2, and an upper contact area of ​​the semiconductor chip 1 is electrically connected to this second conductor track by means of a bond wire 3. Cavity 4a of the housing 4 has inclined side surfaces that serve to reflect the radiation emitted by the semiconductor chip 1. The semiconductor chip 1 has an active layer for radiation generation. The semiconductor chip 1 is encapsulated with a potting material 5, which is placed in the cavity 4a of the housing 4. A conventional potting material used to encapsulate the semiconductor chip 1 is, for example, silicone or epoxy. Silicone is characterized by particularly good light stability and is therefore insensitive to degradation by, for example, UV radiation. However, silicone is disadvantageously gas-permeable, so that pollutants or sulfur-containing compounds from the environment of the semiconductor device can diffuse through the silicone and thus penetrate to the substrate and the conductive traces arranged on it. This can adversely affect corrosion of the conductive traces of the substrate. Harmful gases or compounds such as NOx, H2O, or H2S can diffuse through the silicone potting compound to the conductor tracks of the substrate. In silver-containing conductor tracks, this can result in the formation of Ag2S as a corrosion product, causing the tracks to darken. Furthermore, this can make the conductor tracks susceptible to mechanical stress, causing them to become brittle and negatively impacting the lifespan of such components. While epoxy as a potting material is gas-tight, it exhibits degradation effects when exposed to, for example, UV light. In particular, irradiation of an epoxy potting compound leads to yellowing of the material and / or cracking, which negatively reduces the lifespan of such semiconductor devices. To overcome this disadvantage of conventionally used potting materials, according to the invention the semiconductor chip is encased with a potting material comprising a first, a second, and a third potting layer. Such a manufacturing process and such a semiconductor device are illustrated in conjunction with Figures 1A and 1B. Fig. 1A shows a semiconductor device in the manufacturing process. A semiconductor chip 1 is arranged on a substrate 2 in a housing 4, which has a cavity 4a. The substrate forms the bottom surface of the cavity 4a. The substrate 2 has conductive traces on a surface facing the semiconductor chip for electrical contacting the semiconductor chip 1. The semiconductor chip 1 is attached to one of the conductive traces with its underside by means of a solder layer 2a. On its upper side, the semiconductor chip 1 is electrically connected to another conductive trace of the substrate 2 by means of a bonding wire 3. The semiconductor chip 1 has a radiation output side 1b, from which most of the radiation generated in an active layer 1a of the semiconductor chip 1 exits. The side surfaces of the cavity 4a are inclined so that laterally emitted radiation is reflected at these side surfaces towards the output coupling side of the device. The substrate 2 is integrated within the housing 4. Specifically, the substrate 2 is enclosed by the housing material of the housing 4, with a top surface, on which the semiconductor chip is mounted, being at least partially free of housing material. The semiconductor chip 1 is electrically contacted via the substrate or the conductive traces of the substrate. For this purpose, the substrate 2 can be electrically contacted externally, for example, by means of vias through the housing material of the housing 4 (not shown). Alternatively, the substrate 2 and / or the conductor tracks of the substrate 2 can project laterally through the housing 4, thus enabling external electrical contact (not shown). Such contacting techniques for the substrate or the conductor tracks of the substrate are known to those skilled in the art and are therefore not discussed in detail here. The substrate 2 is, for example, a printed circuit board or a so-called leadframe. The conductive traces of the substrate 2 preferably consist of silver or a silver alloy. In the subsequent process step, the semiconductor chip 1 is encapsulated with a potting material. For this purpose, as shown in Fig. 1B, a first potting layer is applied directly into the cavity 4a of the housing 4. Since the semiconductor chip 1 is already mounted on the substrate 2, the first potting layer 5a is applied laterally next to the semiconductor chip directly onto the substrate 2. The first potting layer 5a envelops the semiconductor chip 1 laterally. The first potting layer 5a is preferably thin, so that the semiconductor chip 1 extends vertically beyond the first potting layer 5a for the most part. The first potting layer 5a is preferably an epoxy layer characterized by particularly good gas impermeability. This prevents the diffusion of gases to the surface of the conductor track of the substrate 2. The first potting layer 5a thus forms a gas barrier that prevents the penetration of harmful gases or sulfur-containing compounds to the substrate and the conductor tracks. This advantageously prevents corrosion, for example, silver corrosion in the case of silver-containing conductor tracks. A second potting layer 5b is subsequently applied to the first potting layer 5a. The second potting layer is also thin, so that the semiconductor chip 1 extends vertically beyond most of the second potting layer 5a. Preferably, the combined height of the first potting layer 5a and the second potting layer 5b is less than the height of the semiconductor chip 1, preferably less than half the height of the semiconductor chip 1. Preferably, the active layer 1a is not enclosed by the first and second potting layers 5a and 5b. The second potting layer is, for example, a silicone layer that preferably contains a white pigment. This white pigment advantageously increases the reflectivity of the second potting layer, thereby protecting the underlying epoxy layer from light exposure and thus from light-induced yellowing. In particular, this protects the underlying epoxy layer from degradation. A third potting layer 5c is applied to the second potting layer 5b, completely encasing the semiconductor chip 1 on its upper surface. In particular, the third potting layer 5c completely fills the cavity of the housing, so that a surface 4b of the housing and a surface 51 of the third potting layer 5c form a flat surface. The third potting layer 5c extends completely beyond the semiconductor chip 1 in the vertical direction and is applied directly above the radiation-emitting side of the semiconductor chip 1. The third potting layer 5c is preferably a silicone layer made of a highly transparent, light-stable material. This allows for effective light extraction from the radiation generated in the active layer of the semiconductor chip 1. In particular, the third potting layer 5c is a clear silicone potting layer that covers the semiconductor chip 1 against the environment. The potting material of the embodiment shown in Fig. 1B thus comprises three potting layers 5a, 5b, 5c, arranged vertically one above the other. The potting layers are designed to ensure desired properties in specific areas. This allows for a potting material that is gas-impermeable due to the bottom epoxy layer and enables efficient light extraction due to the silicone layers above it. The middle silicone layer protects the bottom epoxy layer from degradation, resulting in an overall age-resistant, radiation-efficient, and potted component.

Claims

Optoelectronic semiconductor device comprising a substrate (2) and at least one semiconductor chip (1) arranged thereon, wherein: - the semiconductor chip (1) has an active layer (1a) suitable for generating radiation, - conductive traces for electrical contacting the semiconductor chip (1) are arranged on the substrate (2), - the semiconductor chip (1) is encapsulated with a potting material (5), and - the potting material (5) has at least a first potting layer (5a), a second potting layer (5b) and a third potting layer (5c), wherein: - the first potting layer (5a), the second potting layer (5b) and the third potting layer (5c) differ from each other in at least one of the following properties: their material composition, their optical properties, their chemical properties, and - in the second potting layer (5b), which is arranged on the side of the first potting layer (5a) facing away from the substrate (2),The pigments are included, which increase the reflectivity of the second potting layer (5b). Semiconductor device according to claim 1, wherein the potting layers (5a, 5b, 5c) of the potting material (5) are arranged one above the other in a vertical direction. Semiconductor device according to one of the preceding claims, wherein the first potting layer (5a) facing the support substrate (2) is designed as a gas barrier. Semiconductor device according to claim 3, wherein the first potting layer (5a) is an epoxy layer. Semiconductor device according to one of the preceding claims, wherein the pigments are white pigments. Semiconductor device according to one of the preceding claims, wherein the second potting layer (5b) is a silicone layer. Semiconductor device according to one of the preceding claims, wherein the third potting layer (5c), which is arranged on the side of the second potting layer (5b) facing away from the first potting layer (5a), comprises a highly transparent light-stable material. Semiconductor device according to claim 7, wherein the third potting layer (5c) is a silicone layer. Semiconductor component according to one of the preceding claims, comprising a housing (4) with a cavity (4a) in which the semiconductor chip (1) is arranged, wherein the potting material (5) is introduced into the cavity (4a) and surrounds the semiconductor chip (1). A method for manufacturing a semiconductor device comprising the following process steps: - providing a substrate (2) with conductive traces applied thereon, - applying and electrically contacting a semiconductor chip (1) on the substrate (2), - applying a first potting layer (5a) to the substrate (2) which at least partially encloses the semiconductor chip (1), - applying a second potting layer (5b) on the first potting layer (5a) which at least partially encloses the semiconductor chip (1), and - applying a third potting layer (5c) on the second potting layer (5b) which at least partially laterally encloses the semiconductor chip (1), wherein the first potting layer (5a), the second potting layer (5b) and the third potting layer (5c) differ from each other in at least one of the following properties: their material composition, their optical properties, their chemical properties. Method according to claim 10, wherein the semiconductor device has a housing (4) with a cavity (4a), and the semiconductor chip (1) and the potting layers (5a, 5b, 5c) are placed into the cavity (4a).

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