Method for manufacturing an optoelectronic component

Abstract

A method for producing an optoelectronic device, wherein a layer structure with a first semiconductor layer (2) and a second semiconductor layer (3), and with an active zone (16) for generating light, is grown on a growth substrate (1), wherein a mirror layer (4) is applied to the second semiconductor layer (3) facing away from the growth substrate (1), wherein the layer structure is attached to a first side of a support (10) via a connection layer (8), and wherein electrical contacts (32, 33) for the layer structure are provided via a second side of the support (10), and wherein the growth substrate (1) is removed, and wherein the support (10) is a support which is mirrored on one side facing the connection layer (8) and wherein the connection layer (8) is formed from an electrically insulating material.

Description

[0001] The invention relates to a method according to claim 1 and a component according to claim 9.

[0002] The publications DE 10 2009 032 486 A1 and DE 10 2007 022 947 A1 describe optoelectronic components and methods for their manufacture.

[0003] From DE 10 2010 025 320 A1, an optoelectronic component and a method for its fabrication are known. In the described method, an optically active layer is grown on a substrate. Subsequently, the optically active layer is structured from the free side, whereby electrical contacts are introduced. The electrical contacts are in contact with a positively doped layer and a negatively doped layer. After completion of the structuring, the component is mounted on a substrate. The substrate is then removed.

[0004] The object of the invention is to provide an improved method for manufacturing the component and a component with a simple structure.

[0005] The object of the invention is solved by the method according to claim 1 and by the component according to claim 9.

[0006] One advantage of the described method and component is that the carrier is integrated into the component. This eliminates the steps that are usually required for carrier fabrication, such as forming vias, filling vias, bond pads on the front face, etc.

[0007] Furthermore, by integrating the carrier into the optoelectronic component, both the structure and the size of the carrier can be optimally adapted to the component.

[0008] Further advantageous embodiments of the method and the component are specified in the dependent claims.

[0009] An electrically insulating material, particularly an adhesive, is used as the bonding layer. Using an electrically insulating material as the bonding layer offers the advantage that electrically conductive or semiconducting materials can also be used as the substrate. In particular, the use of an adhesive allows for a secure and strong bond between the layer structure and the substrate with a small layer thickness. Furthermore, the use of an adhesive can lead to cost savings.

[0010] In another embodiment, an electrically semiconducting or electrically conductive material, particularly in the form of a film, is used as the substrate. Using an electrically semiconducting or electrically conductive material as a substrate, especially in the form of a film, offers the advantage of simplified processing. Furthermore, thin substrates can be produced that provide sufficient stability for the optoelectronic component. Particularly when using thin substrates, the recess for forming the contacts can be created quickly. This saves process time and therefore costs.

[0011] In another version, the electrical contacts are coated with a mirror layer to improve their reflective properties.

[0012] In a further embodiment, to improve the reflective properties of the component, a bonding material is used on the substrate side that is essentially transparent to the light emitted by the component. Additionally, a substrate is used whose side facing the bonding layer is reflective. This means that light emitted from the active zone towards the substrate is reflected by the reflective side of the substrate. Thus, the luminous flux emitted from the emission side is increased.

[0013] In another embodiment, the first contact is designed such that the side facing the negatively doped semiconductor layer is reflective. This also increases the reflection of the emitted light towards the emitting side.

[0014] In another embodiment, a filler material with inhomogeneities is used, wherein the filler material is, for example, a photosensitive material. This allows for simple processing. Furthermore, the filler material can be quickly and easily removed to create a contact, for example, using a DRIE process.

[0015] For example, the recesses in the bonding layer can be created by laser ablation, with an opening in the substrate acting as an aperture. This also enables fast and simple processing.

[0016] The properties, features and advantages of this invention described above, as well as the manner in which they are achieved, will become clearer and more easily understood in connection with the following description of the exemplary embodiments, which are explained in more detail in conjunction with the drawings, wherein Fig. 1, Fig. 2 to Fig. 3 a first procedural stage, Fig. 4 a second procedural stage, Fig. 5 and Fig. 6 a third procedural stage, Fig. 7 and Fig. 8 a fourth procedural stage, Fig. 9 and Fig. 10 a fifth procedural stage, Fig. 11 a sixth procedural stage, Fig. 12 a view looking at the carrier of a first embodiment according to Fig. 11, Fig. 13 a view with regard to the carrier of a second embodiment according to the sixth procedural step, Fig. 14 a view of a carrier according to a third embodiment, Fig. 15, Fig. 16 to Fig. 17 a fourth process stage, Fig. 18 a thinned wafer, Fig. 19 a schematic representation of an optical component using a thinned wafer as a support, Fig. 20 components with converter and lens, and Fig. 21 a building element with a support structure.

[0017] Fig. Figure 1 shows a first process step in which a negatively doped semiconductor layer 2 is grown onto a growth substrate 1. A positively doped semiconductor layer 3 is then grown onto the negatively doped semiconductor layer 2. An active zone is provided at an interface between the negatively doped semiconductor layer 2 and the positively doped semiconductor layer 3, which is designed to generate light. The negatively doped semiconductor layer 2 is referred to below as the first semiconductor layer 2 and the positively doped semiconductor layer 3 as the second semiconductor layer 3. Alternatively, the first semiconductor layer 2 can be p-doped and the second semiconductor layer n-doped. The first and second semiconductor layers 2, 3 form, for example, a thin-film diode. The first and second semiconductor layers 2, 3 form a layered structure.

[0018] The growth substrate 1 can be, for example, in the form of sapphire or crystalline silicon. It can also be composed of silicon carbide or gallium nitride. The first and second semiconductor layers 2, 3 are grown epitaxially on the growth substrate 1. Depending on the chosen embodiment, an intermediate layer can be applied to the growth substrate 1, which has essentially the same lattice structure as the layer structure to be grown. In this way, the growth of the first semiconductor layer 2 can be improved, so that fewer or no defects are generated in the lattice structure of the first semiconductor layer during growth.

[0019] Then, as in Fig. As shown in Figure 2, a mirror layer 4 is applied to the second semiconductor layer 3. The mirror layer 4 can contain a metal, for example silver and / or titanium, with a high reflection coefficient. Furthermore, an opening 5 is provided in the mirror layer 4, so that after the application of the mirror layer 4, a surface of the positively doped semiconductor layer 3 is exposed in the region of the opening 5, as shown in Figure 2. Fig. 2 is shown. The opening 5 can be provided simultaneously with the application of the mirror layer 4 or subsequently introduced into the mirror layer 4. In a subsequent process step, which is shown in Fig. As shown in Figure 3, an electrically conductive layer 6 is applied to the reflective layer 4. Depending on the chosen embodiment, the conductive layer 6 can also be omitted. The conductive layer 6, like the reflective layer 4, has the opening 5. This opening can be created separately or together with the opening in the reflective layer 4. Therefore, the opening 5 in both layers 4 and 6 can have the same or different recesses.

[0020] The first and second semiconductor layers 2, 3 can be implemented as an epitaxial layer sequence, i.e., as an epitaxially grown layer structure. These semiconductor layers 2, 3 can, for example, be based on InGaAlN. InGaAlN-based layer structures include, in particular, those in which the epitaxially grown layer structure typically comprises a sequence of different individual layers, containing at least one layer made of a material from the III-V compound semiconductor material system InxAlyGa1-x-yN with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. The layer structures, which have at least one active layer or region based on InGaAlN, can, for example, preferably emit electromagnetic radiation in the ultraviolet to green wavelength range.

[0021] Alternatively or additionally, semiconductor layers 2, 3, or the semiconductor chip itself, can also be based on InGaAlP. This means that the layer structure can comprise different individual layers, at least one of which is a material from the III-V compound semiconductor material system InxAlyGa1-x-yP with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1. The layer structure, which has at least one active layer or region based on InGaAlP, can, for example, preferably emit electromagnetic radiation with one or more spectral components in a green to red wavelength range.

[0022] Alternatively or additionally, the semiconductor layers 2 and 3 can also comprise other III-V compound semiconductor material systems, for example, an AlGaAs-based material, or II-VI compound semiconductor material systems. In particular, an active layer comprising an AlGaAs-based material can be suitable for emitting electromagnetic radiation with one or more spectral components in a red to infrared wavelength range.

[0023] A II-VI compound semiconductor material system can comprise at least one element from group 2, such as Be, Mg, Ca, Sr, and one element from group 6, such as O, S, Se. In particular, a II-VI compound semiconductor material system comprises a binary, ternary, or quaternary compound containing at least one element from group 2 and at least one element from group 6. Such a binary, ternary, or quaternary compound can also include, for example, one or more dopants and additional components. Examples of II-VI compound semiconductor materials include ZnSe, ZnTe, ZnO, ZnMgO, ZnS, CdS, ZnCdS, and MgBeO.

[0024] The growth substrate 1 can comprise a semiconductor material, for example, a compound semiconductor material system as described above. In particular, the growth substrate 1 can comprise or be made of sapphire, GaAs, GaP, GaN, InP, SiC, Si and / or Ge.

[0025] The semiconductor layers 2 and 3 can, for example, have a conventional pn junction, a double heterostructure, a single quantum well (SQW) structure, or a multiple quantum well (MQW) structure as their active region. Within the scope of this application, the term "quantum well" encompasses, in particular, any structure in which charge carriers can undergo quantization of their energy states through confinement. Specifically, the term "quantum well" does not specify the dimensionality of the quantization. It therefore includes, among other things, quantum wells, quantum wires, and quantum dots, and any combination thereof.The semiconductor layers 2, 3 can comprise, in addition to the active region, further functional layers and functional regions, such as p- or n-doped charge carrier transport layers (i.e., electron or hole transport layers), undoped or p- or n-doped confinement, cladding, or waveguide layers, barrier layers, planarization layers, buffer layers, protective layers, contact layers, and / or electrodes, as well as combinations thereof. Such structures relating to the active region or the further functional layers and regions are known to those skilled in the art, particularly with regard to their structure, function, and composition, and are therefore not described in more detail here.

[0026] In a subsequent procedural step, which in Fig. As shown in Figure 4, a trench 7 is formed in the first and second semiconductor layers 2, 3, separating a portion of the layer structure consisting of the first and second semiconductor layers 2, 3 from the remaining portion of the layer structure. The trench 7 extends around a portion of the layer structure 2, 3 and reaches down to the growth substrate 1.

[0027] Depending on the chosen embodiment, the process steps of the Fig. 1, Fig. 2 to Fig. 3 on a larger area of ​​a growth substrate 1, whereby the process steps of the Fig. 2 and Fig. 3. Separate mirror layers 4 and conductive layers 6 corresponding to several optoelectronic components are applied to the large-area first and second semiconductor layers 2, 3. In the process step according to Fig. 4. Areas of the large-area layered structure are divided into individual sub-areas for each building element.

[0028] Fig. 5 shows the arrangement of the Fig. 4, where the arrangement is reversed. The arrangement according to Fig. The first and second semiconductor layers 2, 3, the reflective layer 5, and the conductive layer 4 are attached to the top surface 9 of a substrate 10 via a bonding layer 8. The bonding layer material is also applied to the opening 5. Depending on the chosen embodiment, the opening 5 can be filled with a further filler material 11. The bonding layer 8 connects the first and second semiconductor layers 2, 3, the reflective layer 5, and the conductive layer 4 to the top surface 9 of the substrate 10. In one embodiment, a filler material 11 with inhomogeneities, such as cavities and / or fillers and / or scattering particles, is used. Furthermore, the filler material 11 can, for example, be a photosensitive material. This allows for simplified processing.

[0029] The interconnect layer 8 can be formed from an adhesive material, for example, an electrically non-conductive adhesive. In another embodiment, the interconnect layer 8 can also be formed from an electrically conductive material, for example, metal, which attaches the semiconductor layers 2, 3 to the top surface 9 of the carrier 10 via a soldered connection.

[0030] The following materials are suitable for forming the bonding layer in the form of an adhesive: thermoplastics (e.g. Brewer Science Waferbond), two-component polyurethanes (DELO-PUR 9604), two-component epoxy resins (di- or polyepoxides based on bisphenol A, novolacene, etc., hardeners polyamines, mercaptans), polyimides (adhesives HD 3007 / HD 7010 Dupont / HD Microsystems), acrylates, silicones (dimethyl silicone).

[0031] The gluing process according to Fig. The process is carried out, for example, in a membrane bonder. Depending on the chosen embodiment, layer thicknesses for the bonding layer 8 in the range of less than 10 µm between the top surface of the support 10 and the free top surface of the free mirror layer or the free top surface of the conductive layer 6 can be achieved. The thickness of the bonding layer 8 can, for example, also be less than 1 µm.

[0032] When using a non-electrically conductive compound layer 8, electrically conductive materials such as metals (Mo, W, C, CuW, AlSi, AlSiC) or electrically semiconducting materials such as Si, Ge, GaAs can also be used as the substrate 10. The substrate 10 can also be in the form of a film, with layer thicknesses ranging from 100 µm to as low as 10 µm. If the substrate 10 is made of a metal, it can be provided with an electrically insulating layer, for example, by an ALDCVD or PVD process. The substrate 10 can also be in the form of an electrically insulating layer, particularly in the form of a film, such as a plastic film.

[0033] Furthermore, the opening 5 can be filled with a filler material 11 before the bonding process. Suitable filler material 11 includes, for example, a photosensitive material (ProTEK) or a coating that can be removed again using a DRIE process.

[0034] By providing the carrier 10 in the form of films, in particular in the form of metal films, a roll-to-roll manufacturing process can be carried out in accordance with Fig. 6. Furthermore, the connection between the carrier 10 and the semiconductor layers 2 and 3 can be designed to be planar, very thin, and homogeneous due to the process sequence. An ESD diode can also be integrated directly into the system, e.g., between the contact pads on one underside of the carrier. If the carrier 10 is made of silicon, the ESD diode can also be integrated directly into the silicon. This can be achieved through local implantation, with the connection made via bond pad metallization or the associated rewiring layers.

[0035] When using a solder joint as a bonding layer on a passivated silicon substrate 10, the structuring by the grooves 7 (mesastructuring) is carried out after detachment of the growth substrate 1. The passivation is performed, for example, using an ALD process after etching back the mirror layer 4.

[0036] In a subsequent procedural step, which in Fig. As shown in Figure 7, a first recess 14 is formed from a lower surface 13 of the carrier 10 in the area of ​​the opening 5 of the mirror layer 4. A second recess 15 is also formed in the area of ​​the mirror layer. The first and second recesses 14, 15 are formed using appropriate methods depending on the material of the carrier 10. For example, etching processes can be used when the carrier 10 is made of semiconducting material. When the carrier 10 is made of metal, metal-removing processes such as laser ablation can be used. This process is described in Fig. 7 shown.

[0037] In a subsequent process step, the interconnect layer 8 and, if applicable, the filler material 11 above the first recess 14 are removed, so that the recess 14 borders the negatively doped semiconductor layer 2, which is located above the active zone 16. Furthermore, in the area of ​​the second recess 15, the interconnect layer 8 is removed, so that the second recess 15 extends to the conductive layer 6 or, if there is no conductive layer 6, to the mirror layer 4. This process stage is described in Fig. 8 shown.

[0038] Depending on the type of filler material 11 and the bonding layer 8, a DRIE process can be used, for example, to remove the bonding layer 8 and the filler material 11. Alternatively, the filler material 11 and the bonding layer 8 can be removed, for example, using a laser ablation process. In this case, the first and / or second recess 14, 15 already provided in the carrier 10 serves as an aperture.

[0039] In a subsequent procedural step, which in Fig. As shown in Figure 9, an insulating layer 17 is applied to the underside 13 and the side walls of the first and second recesses 14, 15. Depending on the chosen embodiment, the insulating layer 17 on the side wall of the recess 14 can be in the form of a mirror layer. After the insulating layer 17 has been applied and structured, the first recess 14 still borders directly on the first semiconductor layer 2. Furthermore, the second recess 15 borders the conductive layer 6 or, if there is no conductive layer 6, the mirror layer 4. The insulating layer 17 can be deposited, for example, using an ALD or a TEOS-based CVD process.In a further embodiment, before the electrically conductive material is introduced for making the first contact, an electrically conductive and reflective metal layer is applied to the free area of ​​the negatively doped semiconductor layer 2 and the free area of ​​the insulating layer 17 in the area of ​​the first recess 14.

[0040] In a subsequent process step, the first and second recesses 14, 15 are filled with an electrically conductive material, for example, a metal, using an electroplating process, and then a first or second contact pad 18, 19 is applied to a lower side of the insulating layer 17. Depending on the embodiment of the carrier 10, a planarization step can be performed before or after the application of the contact pads 18, 19, e.g., by means of CMP. This process state is described in Fig. 10 shown.

[0041] Furthermore, when using a support made of a semiconducting material, for example in the form of a silicon wafer, the insulating layer 17 can be formed as a silicon dioxide layer.

[0042] The growth substrate 1 is then removed. This can be done, for example, by laser removal or by CMP ablation. Subsequently, an upper side surface 20 of the first semiconductor layer 2 is roughened. This process is described in Fig. Figure 11 shows the thickness of the first semiconductor layer 2 enlarged. The individual components are also shown separately.

[0043] Fig. Figure 12 shows a first component 21 with a top view of the first and second contact pads 18, 19. The first and second contact pads 18, 19 are electrically separated by a second groove 22. In addition, the illustrated embodiment provides several first and second recesses 14, 15, which are filled with electrically conductive material and represent the first and second electrical contacts 32, 33, respectively. The first electrical contacts for the negatively doped semiconductor layer 2 are arranged in a 4 x 4 configuration. The second electrical contacts for the positively doped semiconductor layer 3 are arranged as four second electrical contacts in series.

[0044] Fig. Figure 13 shows an embodiment of a second component 34, wherein second contact pads 19 are provided in four corner regions. The second contact pads 19 are separated from the first contact pad 18 by a second groove 22. Analogous to the arrangement of the second contact pads 19, the second electrical contacts 33 are also arranged in the corner regions of the square. Analogous to the shape of the first contact pad 18, the first electrical contacts 32 are arranged evenly distributed over the surface of the first contact pad 18.

[0045] Fig. Figure 14 shows an embodiment of a third component 35, wherein only a second contact pad 19 is arranged in a corner region, which is electrically isolated from the first contact pad 18, which is essentially square, by means of a second groove 22. Similarly, only one second electrical contact 33 is provided for contacting the positively doped semiconductor layer 3. Furthermore, first electrical contacts 32 are provided evenly distributed over the area of ​​the first contact pad 18.

[0046] The in the Fig. 12, Fig. 13 to Fig. The embodiments shown in Figure 14 are only examples of possible divisions of the first and second contact pads 18, 19 and the corresponding first and second electrical contacts 32, 33.

[0047] Fig. Figure 15 shows another embodiment, which is essentially in accordance with Fig. The first contact pad 18 is constructed as described above, with an additional insulating layer 23 applied to it, partially adjacent to the second contact pad 19. Furthermore, the second contact pad 18 extends laterally beyond the additional insulating layer 23. The first contact pad 18 is also formed in two layers, with the first layer resting on the insulating layer 17 and the second layer on the first layer and the additional insulating layer 23. The additional insulating layer 23 has a depression in the area of ​​the first recess 14, which is formed by a lack of planarization. Similarly, the first contact pad 18 has an indentation 24 in the area of ​​the second layer. Such an indentation can also occur in the area of ​​the recess 15. Subsequently, the first and second contact pads 18, 19 can be planarized so that their structure is as described above. Fig. 16 will be received.

[0048] Fig. Figure 17 shows a view of the first and second contact pads 18, 19. By providing the additional insulating layer 23, it is possible to make the geometry of the first and second contact pads 18, 19 more flexible and to decouple them from the actual arrangement of the first and second contacts.

[0049] Fig. Figure 18 shows a support 10 in the form of a semiconductor wafer, which has an annular circumferential rim 24 with a thickness increased compared to a central region 36. For example, the wafer is designed as a silicon wafer. This support shape is achieved by thinning an inner region of the wafer while leaving a circumferential rim region with a greater thickness. This enhances the wafer's mechanical stability. The support according to Fig. 18 is manufactured, for example, using a Taiko process from the company Disco. The thickness of the silicon wafer in the center area 36 is, for example, 10 µm.

[0050] The in Fig. The beam shown in section 18 is designated as beam 10 according to Fig. 6 is used. Subsequently, appropriate structuring measures are carried out, whereby Fig. 19 the procedural status according to Fig. 8 represents. Analogous to the one in Fig. In the arrangement shown in 19, a variety of components can be placed on the support according to Fig. 19 will be prosecuted.

[0051] Fig. 20 shows a process state in which two components according to Fig. 16 components are arranged on a support 10, with a circumferential separating structure 25 in the form of a frame, for example using a photoresist, being applied between the components 21. In addition, a converter layer 26 and a lens 27 were applied to the negatively doped semiconductor layer 2 within the frame.

[0052] The frame-shaped separation structure 25 is produced, for example, using a photoresist process. The frame structure can be made, for example, from a plastic such as benzocyclobutene. The converter layer 26 comprises, for example, silicone in which a luminescent conversion material, e.g., YAG:Ce or other materials, is embedded.

[0053] In Fig. Figure 20 schematically shows an ESD diode 28 incorporated into the carrier 10 by means of appropriate doping. The ESD diode 28 can also be formed on a lower surface of the carrier 10, e.g., between the contact pads 18, 19.

[0054] The in Fig. The component shown in 20 can then be applied to a further support structure 29 with vias 30 and further contacts 31, as shown in a schematic cross-section in Fig.21 is shown. The further contacts 31 are arranged on a bottom side of the support structure 29 and the component 21 on the top side of the support structure 29.

[0055] The other contacts are arranged on the underside of the support structure 29 and are connected via the vias 30 to corresponding contact pads 18, 19 of the component. Reference symbol list 1 Growth substrate 2 negatively doped semiconductor layers 3 positively doped semiconductor layers 4 Mirror layer 5 Opening 6 conductive layer 7 trenches 8. Compound layer 9 Top 10 carriers 11 Filling material 13 Underside 14 1. Exclusion 15 2. Exclusion 16 active zones 17 Insulation layer 18 1. Contact pad 19 2. Contact pad 20 Top 21 1. Component 22 2nd trench 23 additional insulation layers 24 Rand 25 Separation structure 26 Converter layer 27 lens 28 ESD Diode 29 Support structure 30 Via 31 more contacts 32 1. electrical contact 33 2. electrical contact 34 2. Component 35 3. Component 36 Middle area

Claims

A method for producing an optoelectronic device, wherein a layer structure with a first semiconductor layer (2) and a second semiconductor layer (3), and with an active zone (16) for generating light, is grown on a growth substrate (1), wherein a mirror layer (4) is applied to the second semiconductor layer (3) facing away from the growth substrate (1), wherein the layer structure is attached to a first side of a support (10) via a connection layer (8), and wherein electrical contacts (32, 33) for the layer structure are provided via a second side of the support (10), and wherein the growth substrate (1) is removed, and wherein the support (10) is a support which is mirrored on one side facing the connection layer (8) and wherein the connection layer (8) is formed from an electrically insulating material. Method according to claim 1, wherein the bonding layer is formed from an adhesive material. Method according to one of the preceding claims, wherein the carrier (10) is an electrically semiconducting or an electrically conductive material, in particular in the form of a film. A method according to any one of claims 1 to 3, wherein a recess (14) is provided in the interconnect layer (8), in the carrier (10) and in the second semiconductor layer (3), wherein the recess borders the first semiconductor layer (2), wherein a side surface of the recess (14) is covered with an insulating layer (17), wherein a first electrical contact (32) for contacting the first semiconductor layer (2) is provided in the recess (14), wherein a second recess (15) is provided in the carrier (10), wherein the second recess (15) borders the mirror layer (4) or an electrically conductive layer (6) covering the mirror layer (4), wherein a side surface of the second recess (15) is covered with a further insulating layer (17), and wherein a second electrical contact (33) for contacting the second semiconductor layer (3) is provided in the second recess (15). Method according to any one of claims 1 to 4, a. wherein a further reflective layer is applied to the side surface of the first and / or the second recess before the insertion of the first (32) and / or the second contact (33), b. or wherein a connecting material is used which is substantially transparent to the light emitted by the active zone (16), or c. wherein the first contact (32) is designed such that the first contact is reflective on a side facing the first semiconductor layer (2). A method according to one of the preceding claims, wherein a third insulating layer (17) is applied to the carrier (10), wherein an electrically conductive first contact surface (18) is applied to the third insulating layer (17) which is in contact with the first contact (32), and wherein an electrically conductive second contact surface (18) is applied to the third insulating layer (17) which is in contact with the second contact (33), wherein the first and the second contact surfaces (17, 18) are electrically insulated from each other, wherein a fourth insulating layer (23) is applied to the first contact surface (18), wherein the second contact surface (19) is applied at least partially to the fourth insulating layer (23). Method according to one of the preceding claims, wherein the growth substrate (1) is removed from a surface of the first semiconductor layer (2), wherein the exposed surface of the released first semiconductor layer is roughened. Method according to one of the preceding claims, wherein a wafer, in particular a thinned wafer with a thicker edge region, is used as the support (10). Optoelectronic component (21, 34, 35), which is manufactured in particular according to one of claims 1 to 8, comprising a carrier (10) with a layer structure comprising a second semiconductor layer (3) and a first semiconductor layer (2) with an active zone for generating light and a mirror layer (4), wherein the layer structure (2, 3) is connected to a first side of the carrier (10) via a connecting layer (8), and wherein electrical contacts (32, 33) for contacting the layer structure (2, 3) are provided in the carrier (10), wherein the contacts are led from the first side to an opposite second side of the carrier (10), and wherein the connecting layer (8) is formed from an electrically insulating material. Component according to claim 9, wherein the support (10) is formed from an electrically semiconducting or electrically conductive material, in particular from metal. Component according to claim 9 or 10, wherein the support (10) is formed in the form of a foil made of metal or a semiconductor material. Component according to one of claims 9 to 11, wherein the mirror layer (4), the interconnect layer (8), the second semiconductor layer (3) and the support (10) have a recess (14), wherein the recess (14) borders the first semiconductor layer (2), wherein the second semiconductor layer (3) is arranged between the first semiconductor layer (2) and the support (10), wherein a side surface of the recess (14) is covered with an insulating layer (17), wherein a first electrical contact (32) is arranged in the recess (14), wherein a further recess (15) is provided in the support (10), wherein the further recess (15) borders the mirror layer (4) or an electrically conductive layer (6) covering the mirror layer, wherein a side surface of the further recess (15) is covered with an insulating layer (17), and wherein a second electrical contact (33) is arranged in the further recess (15). Component according to one of claims 9 to 12, wherein an insulating layer (17) is applied to the carrier (10), wherein an electrically conductive first contact surface (18) is applied to the insulating layer (17) which is in contact with the first contact (32), and wherein an electrically conductive second contact surface (19) is applied to the insulating layer (17) which is in contact with the second contact (32), and wherein the first and the second contact surfaces (18, 19) are electrically separated from each other, wherein a further insulating layer (23) is applied to the first contact surface, and wherein the second contact surface (19) is also partially applied to the further insulating layer (23). Component according to one of claims 9 to 13, wherein the connecting layer (8) has a layer thickness of less than 10 µm, in particular less than 1µm, and wherein the support (10) has a layer thickness of less than 100µm, in particular less than 10µm. Component according to one of claims 9 to 14, wherein a connecting material is provided which is substantially transparent to the light emitted by the active zone, and wherein a support is used which is designed to be reflective on one side facing the connecting layer. Component according to one of claims 9 to 15, wherein the carrier (10) extends laterally in every direction beyond the layer structure of first and second semiconductor layers (2, 3) applied to the interconnection layer (8).

Images