Field-effect transistor with a raised drain structure

Abstract

A transistor comprising: a frustoconical projection formed on a substrate; a gate (306) having a gate contact surface (403A, 403B); wherein the frustoconical projection comprises: a source region (904A, 904B) formed in an upper portion of the frustoconical projection; and a drain region (206A, 206B) with a drain contact surface (506A, 506B), wherein a portion of the drain region (206A, 206B) is formed in a lower portion of the frustoconical projection, and wherein the drain contact surface (506A, 506B) is substantially coplanar with the gate contact surface (403A, 403B);wherein the transistor further comprises a dielectric layer (304) arranged between the gate (306) and the source (904A, 904B) and drain regions (206A, 206B), wherein the gate (306) overlaps a portion of the source region (904A, 904B) and a portion of the drain region (206A, 206B), the overlapped portion of the source region (904A, 904B) having a perimeter smaller than the perimeter of the overlapped portion of the drain region (206A, 206B); wherein the drain contact surface (506A, 506B) is an upper surface of a raised platform that has grown epitaxially from a surface of the semiconductor substrate.

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