Protection systems for integrated circuits and methods for training them

Abstract

Device (1) comprising: a first contact surface (101); an internal circuit (3) electrically connected to the first contact surface (101); and a protection system (8) configured to protect the internal circuit (3) from transient electrical events, the protection system (8) comprising: a first primary protection device (41a) electrically connected to the first contact surface (101) and configured to provide a first holding voltage and bidirectional blocking voltage protection; a first secondary protection device (42a) connected to the first contact surface (101) and configured to provide a second holding voltage and bidirectional blocking voltage protection, the first primary protection device (41a) having a current handling capacity greater than the current handling capacity of the first secondary protection device (42a).and wherein the space requirement of the first secondary protection device (42a) is smaller than the space requirement of the first primary protection device (41a) and has a switch-on speed that is faster than a switch-on speed of the first primary protection device (41a), and wherein a magnitude of the first holding voltage is smaller than a magnitude of the second holding voltage, such that when the first primary protection device (41a) has been activated, the activated first primary protection device (41a) clamps a voltage of the first contact surface (101) and reduces a current flow through the first secondary protection device (42a), and wherein the first primary protection device (41a) and the first secondary protection device (42a) each comprise: a first resistor (111) and a first bipolar NPN transistor (104),wherein a first side of the first resistor (111) and an emitter of the first bipolar NPN transistor (104) are electrically connected to the first contact surface (101); a second resistor (112) and a second NPN bipolar transistor (105), wherein a first side of the second resistor (112) and an emitter of the second NPN bipolar transistor (105) are electrically connected to a second contact surface (102); and a bidirectional bipolar transistor (103) with an emitter / collector electrically connected to a base of the first NPN bipolar transistor (104) and a second side of the first resistor (111), with a collector / emitter electrically connected to a base of the second NPN bipolar transistor (105) and a second side of the second resistor (112), and with a base electrically connected to a collector of the first NPN bipolar transistor (104) and to a collector of the second NPN bipolar transistor (105).

Description

GENERAL STATE OF THE TECHNOLOGY

[0001] The embodiments of the invention relate to electronic systems and, more precisely, protection systems for integrated circuits (ICs). Description of related technology

[0002] Certain electronic systems may be exposed to a transient electrical event or a relatively short-duration electrical signal exhibiting rapidly changing voltage and high energy. Transient electrical events can include, for example, electrostatic discharge (ESD) events and / or electromagnetic interference (EMI) events.

[0003] Transient electrical events can damage integrated circuits (ICs) within an electronic system due to overvoltage conditions and / or high power dissipation levels over relatively small IC areas. High power dissipation can increase the IC temperature and lead to numerous problems, such as gate oxide breakdown, junction damage, metal damage, and surface charge buildup. Furthermore, transient electrical events can cause latch-up (in other words, the unintended creation of a low-resistance path), disrupting IC operation and potentially causing permanent damage. Therefore, there is a need to provide ICs with protection against such transient electrical events, such as during IC turn-on and turn-off conditions. SUMMARY

[0004] In one embodiment, a device comprises a first contact surface, an internal circuit electrically connected to the first contact surface, and a protection system configured to protect the internal circuit from transient electrical events. The protection system comprises a first primary protection device electrically connected to the first contact surface and configured to provide a first holding voltage and bidirectional reverse voltage protection. The protection system further comprises a first secondary protection device electrically connected to the first contact surface and configured to provide a second holding voltage and bidirectional reverse voltage protection.The first primary protection device has a current-handling capacity greater than that of the first secondary protection device, and the first secondary protection device has a smaller current-handling capacity than the first primary protection device and a faster turn-on speed than that of the first primary protection device. The magnitude of the first holding voltage is smaller than that of the second holding voltage, so that when the first primary protection device is activated, it blocks the voltage across the first contact surface and reduces current flow through the first secondary protection device.

[0005] In another embodiment, a device comprises a contact surface, an internal circuit electrically connected to the contact surface, and a protection system configured to protect the internal circuit from transient electrical events. The protection system includes a means for providing primary bidirectional blocking voltage protection, electrically connected to the contact surface and configured to exhibit a first holding voltage. The protection system further comprises a means for providing secondary bidirectional blocking voltage protection, electrically connected to the contact surface and configured to exhibit a second holding voltage.The primary protective device has a current-handling capacity greater than that of the secondary protective device, and the secondary protective device has a switching-on speed faster than that of the primary protective device. The magnitude of the first holding voltage is lower than the magnitude of the second holding voltage, so that when the primary bidirectional blocking protection device is activated, the activated primary protection device blocks a voltage across the contact area to reduce current flow through the secondary protective device.

[0006] In another embodiment, a device comprises a substrate, a contact surface, a primary protection device electrically connected to the contact surface and configured to provide a first holding voltage, and a secondary protection device electrically connected to the contact surface and configured to provide a second holding voltage. The primary protection device comprises a first bidirectional bipolar transistor located in the substrate, and the secondary protection device comprises a second bidirectional bipolar transistor located in the substrate. The primary protection device has a current-handling capacitance greater than that of the secondary protection device, and the secondary protection device has a turn-on speed faster than that of the primary protection device.The magnitude of the first holding voltage is lower than the magnitude of the second holding voltage, so that when the primary protection device is activated, the activated primary protection device blocks a voltage across the contact surface to reduce current flow through the secondary protection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] They show:

[0008] Fig. 1A a schematic block diagram of an integrated circuit (IC).

[0009] Fig. 1B A schematic block diagram of an electronic system comprising an engine control unit (ECU), a printed circuit board, a system-level protection block, and the ICs. Fig. 1A includes.

[0010] Fig. 2 a schematic block diagram of an embodiment of an IC.

[0011] Fig. 3A a graphical representation showing a relationship between current and voltage for an example of primary, secondary and tertiary protective devices from Fig. 2 shows.

[0012] Fig. 3B a graphical representation of an example of voltage to time for the primary, secondary and tertiary protective devices from Fig. 3A.

[0013] Fig. 4A to Fig. 4C circuit diagrams of various architectures of an internal circuit of an IC interface.

[0014] Fig. 5 a circuit diagram that depicts two implementations of a part of an internal circuit of an IC.

[0015] Fig. 6 a circuit diagram illustrating a protection circuit according to one embodiment.

[0016] Fig. 7A a schematic perspective view of a protective device, which includes the protective circuit from Fig. 6 depicts one embodiment.

[0017] Fig. 7B an annotated cross-sectional view of the protective device made of Fig. 7A, along lines 7B-7B.

[0018] Fig. 8A a schematic perspective view of a protective device, which includes the protective circuit from Fig. 6 implements according to another embodiment.

[0019] Fig. 8B a schematic perspective view of a protective device, which includes the protective circuit from Fig. 6 according to yet another embodiment.

[0020] Fig. 9A a schematic top-down arrangement plan of a protective device according to one embodiment.

[0021] Fig. 9B an enlarged partial top view of an implementation of the protective device Fig. 9A.

[0022] Fig. 10A a schematic top-down arrangement plan of a protective device according to another embodiment.

[0023] Fig. 10B an enlarged partial top view of an implementation of the protective device Fig. 10A. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0024] The following detailed description of certain embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be implemented in a variety of ways, as defined and covered by the claims. In this description, reference is made to the drawings, in which the same reference numerals indicate identical or similarly functioning elements.

[0025] Terms such as above, below, over, and so forth, as used here, refer to a device oriented as shown in the figures and should be interpreted accordingly. It is also understood that, since regions within a semiconductor device (such as a transistor) are defined by doping different parts of a semiconductor material with different impurities or different concentrations of impurities, there may not be separate spatial boundaries between different regions in the finished device, but rather the regions may merge into one another. Some boundaries, as shown in the accompanying figures, are of this nature and are depicted as separate structures only for the reader's convenience. In the embodiments described below, p-doped regions may comprise a p-doped semiconductor material, such as boron, as the dopant.Furthermore, n-doped regions can contain an n-doped semiconductor material, such as phosphorus, as a dopant. A person skilled in the art will understand various concentrations of dopants in the regions described below.

[0026] Certain electronic systems are configured to protect circuits or components within them from transient electrical events. Furthermore, to ensure the reliability of an electronic system, manufacturers may test it under defined stress conditions, which can be described by standards established by various organizations, such as the Joint Electronic Device Engineering Council (JEDEC), the International Electrotechnical Commission (IEC), the Automotive Engineering Council (AEC), and the International Organization for Standardization (ISO). These standards can cover many different transient electrical events, as previously discussed, including electrostatic discharge (ESD) events and / or electromagnetic interference (EMI) events.

[0027] The reliability of electronic circuits is improved by providing protective devices for the IC's contact pads. These protective devices can be integrated on a chip or at the system level and can maintain the voltage level at the contact pads within a predefined safe range by transitioning from a high-resistance to a low-resistance state when the transient signal voltage reaches a trigger voltage. Subsequently, the protective device can parallel-circuit at least a portion of the current associated with the transient signal before the transient signal voltage reaches a positive or negative dropout voltage, which can lead to one of the most common causes of IC damage. As described below with reference to Fig. As described in detail in section 3A, a protective device can remain in the low-impedance state after activation as long as the voltage level of the transient signal is above a positive holding voltage or below a negative holding voltage.

[0028] An integrated circuit (IC) may include one or more contact pads that are exposed to an operating voltage ranging from negative to positive. In certain applications, it is desirable to have a protective device that can shield the internal circuit from both negative and positive transient signals with voltage magnitudes outside the circuit's normal operating conditions. For example, it may be desirable for the protective device to shield the internal circuit from transient signals that exceed the IC's high-power and low-power voltage levels (e.g., ground) by a certain amount.The use of a protective device to provide protection against both positive and negative transient electrical events can allow a reduction in the layout area compared to a design that uses separate structures to protect against positive and negative transient signals, thereby enabling a more scalable design solution. Overview of electronic systems with protective devices

[0029] Fig. 1A is a schematic block diagram of an integrated circuit (IC) 1 The IC 1 is shown as they are connected to a first capacitor 2a and a second capacitor 2b electrically connected, and includes an internal circuit 3 , a voltage regulator 4 , a first or energy-deep contact surface 5 , a second or signal contact surface 6, a third or high-energy contact surface 7 , a protective block or a protective system 8 , a first low-stress contact surface 18 and a second low-stress contact surface 19 .

[0030] The internal circuit 3 can receive energy and / or signals via the contact surfaces 5 until 7 communicate. During implementation, the energy-deep contact area is crucial. 5 configured to receive an initial power supply voltage V1, the signal contact surface 6 is configured to provide a signal voltage V OUT to receive and / or generate, and the high-energy contact surface 7 is configured to receive a second power supply voltage V2. Although a configuration of the contact surfaces 5 until 7 As described, the IC 1be suitable to include more or fewer contact surfaces and / or a different arrangement of the contact surfaces.

[0031] The internal circuit 3 can also be used on the first and second low-stress contact surfaces 18 , 19 be electrically connected directly or via one or more components. The first and second low-stress contact surfaces 18 , 19 They can be universal contact surfaces that can be exposed to an electrical environment that is less harsh than the electrical environment to which the contact surfaces are exposed. 5 until 7 are exposed. For example, the first and second low-stress contact surfaces can be 18 , 19 receive transient electrical events that are of a lower order of magnitude in relation to transient electrical events that occur at the contact surfaces 5 until 7be received, exhibit. Although Fig. 1A represents a configuration which includes the first and second low-stress contact surfaces 18 , 19 In some implementations, the first and second low-stress contact surfaces may be included. 18 , 19 be omitted.

[0032] One or more of the contact surfaces 5 until 7 the IC 1 can(s) a transient electrical event 14 They may be exposed to signals that go beyond those associated with normal IC operation and can cause IC damage and / or latch-up. For example, the transient electrical event 14For example, it could be an ESD event at the IC level, associated with the handling of the IC by a user or machine, such as an ESD event defined by the AEC-Q100 specifications. The transient electrical event 14 It can generate overvoltage or undervoltage conditions and can dissipate high energy levels that can disrupt the operation of the internal circuitry. 3 This can cause disruption and potentially permanent damage. As used here, the term "undervoltage ratio" refers to an overvoltage ratio of a negative magnitude.

[0033] To protect the IC 1 To help protect against transient electrical events, the protection system was developed. 8 added. The protection system 8 can be used to improve the reliability of the IC 1 to ensure by controlling the voltage level at the contact surfaces 5 until 7 the IC 1is held within a specific voltage range, which can vary from contact surface to contact surface. The protection system 8 It can be configured to divert a current associated with a transient electrical event received at one IC contact surface to other nodes or contact surfaces of the IC, thereby providing protection against transient electrical events. In certain implementations, the protection system 8 not only to the contact surfaces 5 until 7 the IC 1 , but also to one or more internal nodes of the IC 1 and / or to the first and second low-stress pins 18 , 19 electrically connected. For example, the protection system 8 be electrically connected to an internal power supply, which is regulated by the voltage regulator 4is generated to protect circuits that use the voltage regulator 4 be electrically operated.

[0034] In certain implementations, the first and second capacitors can 2a , 2b between certain contact surfaces to help protect the contact surfaces from transient electrical events. For example, in the implementation shown, the first capacitor 2a between the signal contact surface 6 and the energy-deep contact surface 5 electrically connected, and the second capacitor 2b was between the high-energy contact surface 7 and the energy-deep contact surface 5 electrically connected. Although the first and second capacitors 2a , 2b outside the IC 1The first and second capacitors may be included to help provide protection against transient electrical events. 2a , 2b In certain implementations, components may be omitted, and / or a different arrangement of external components may be provided.

[0035] The IC 1 It can be used, for example, in protocol systems of local area networks (LIN) and local area controller networks (CAN), transmission line systems, industrial control systems, energy management systems, sensor systems of microelectromechanical systems (MEMS), transducer systems, or various other systems. The IC 1 can be used in electronic systems where the contact surfaces of the IC 1 are exposed to user contact through a low-resistance connection. In one embodiment, the IC 1An integrated circuit (IC) for processing a pressure sensor signal for a motor vehicle.

[0036] Fig. 1B is a schematic block diagram of an electronic system 20 , that the IC 1 out of Fig. 1A includes. The electronic system 20 includes a printed circuit board or card 11 and an engine control unit (ECU) 12 The circuit board 11 The IC includes 1 , a first pen 15 , a second pen 16 and a third pen 17 In certain implementations, the printed circuit board includes 11 furthermore, a protective block 13 at the system level.

[0037] The IC 1 can be connected to the ECU 12 be electrically connected so that energy is available for the IC 1 can be provided and / or signals between the IC 1 and the ECU 12They can be communicated. For example, the first to third contact surfaces can be used. 5 until 7 the IC 1 each to the first to third pens 15 until 17 the circuit board 11 be electrically connected to the ECU 12 They can be electrically connected, for example using wires or cables. In certain implementations, the first pin 15 the circuit board 11 an energy-low pen, the second pen 16 the circuit board 11 is a signal pen and the third pen 17 the circuit board 11 This is a high-energy pin. However, other configurations are possible, including configurations that use more or fewer pins.

[0038] In the electronic system 10 transient electrical events can occur which affect the IC 1This can occur, for example, at the system level, due to the inductive coupling of a cable harness used to connect the printed circuit board. 11 and the ECU 12 to connect electrically, in order to generate a transient electrical event 14 lead.

[0039] Conventional electronic systems may include a system-level protection block on a printed circuit board to protect an integrated circuit from transient electrical events at the system level. In contrast, in certain implementations described here, the protection system 8 Configured to provide protection against transient electrical events at both the IC and system levels, which helps to reduce the size of the protection block. 13 to reduce or eliminate it at the system level. For example, the protection system 8 be configured to use the IC 1not only to protect against transient electrical events at the device level, such as those defined by the AEC-Q100 N standards, but also against transient electrical events at the system level, such as those defined by the IEC-61000-4-2 standards. Thus, unlike a conventional electronic system that uses separate protection systems for IC and system level protection, in certain embodiments the protection system 8 the IC 1 Configured to provide full system-level protection or at least part of the system-level protection, to reduce the size of the protection block 13 to reduce it at the system level or off the circuit board 11 to eliminate.

[0040] By reducing the size of the protection block at the system level 13 or by eliminating it, the costs of the electronic system are reduced.20 Furthermore, configuring the protection system 8 the IC 1 , to provide protection at both the IC level and the system level, the robustness of the IC 1 increase, thereby expanding the range of applications where the IC 1 can be used, and / or the roughness of the electrical environment in which the IC 1 It can work, it can be increased.

[0041] Fig. 2 is a schematic block diagram of an embodiment of an IC 30 The IC 30 is shown as they are using the first capacitor 2a and the second capacitor 2b is connected, and includes the voltage regulator 4 , the first or low-energy contact surface 5 , the second or signal contact surface 6 , the third or high-energy contact surface 7 , a first primary protective device 41a , a second primary protective device 41b, a first secondary protective device 42a , a second secondary protective device 42b , a first tertiary protective device 43a , a second tertiary protective device 43b , a first internal circuit 45 , a second internal circuit 46 , an initial resistance 47 and a second resistor 48 In the configuration shown, the primary protective devices are functioning. 41a until 41b , the secondary protective devices 42a until 42b and the tertiary protective devices 43a until 43b as a protection system of the IC 30 .

[0042] The IC 30 includes the first and second internal circuits 45 , 46 , which can be used to communicate data via an interface. For example, the first and second internal circuits can 45 , 46be configured to provide a signal voltage V OUT at the signal contact surface 6 to generate and / or sample. In the configuration shown, the first internal circuit is... 45 to the signal pen 6 over the first resistance 47 electrically connected, and the second internal circuit 46 is attached to the signal pen 6 via the second resistance 48 electrically connected. Although the IC 30 depicts a configuration in which the two internal circuits are connected to the signal pin 6 Depending on the implementation, more or fewer internal circuits are provided.

[0043] The IC 30 can be achieved using the energy-deep contact surface 5 and the high-energy contact surface 7 electrically operated. For example, the energy-deep contact surface can be 5be configured to receive an initial supply voltage V1, and the energy-high contact surface 7 It can be configured to receive a second supply voltage V2. In the configuration shown, the IC includes 30 the voltage regulator 4 , which can be used to regulate voltage V REG to generate from the second supply voltage V2, which is located at the high-energy contact surface 7 is received. The regulated voltage V REG can access the first and second internal circuits 45 , 46 to be provided to supply a voltage suitable for the electrical operation of transistors and other circuits of the first and second internal circuits 45 , 46 is suitable. In certain implementations, the controller can 4However, they can be omitted and / or configured to generate additional regulated voltage feeds. In one embodiment, the controller 4 a low-dropout (LDO) regulator.

[0044] The IC shown 30 includes a multi-stage protection system that includes the primary protective devices 41a until 41b , the secondary protective devices 42a until 42b and the tertiary protective devices 43a until 43b includes. As described in detail below, the primary protective devices can 41a until 41b , the secondary protective devices 42a until 42b and the tertiary protective devices 43a until 43b Each be configured to have different current handling capabilities to help the IC 30to protect against transient electrical events at both the IC and system levels. For example, the primary protection devices can 41a until 41b These can be relatively large devices configured to have a current handling capacity suitable for providing system-level protection against transient electrical events, such as ESD events as defined by IEC 61000-4-2 and / or EMI events as defined by ISO 7633-3. Furthermore, the secondary protective devices can 42a until 42b Devices that are smaller than the primary protective devices 41a until 41bare, and can be configured to have relatively small current handling capacities suitable for withstanding transient electrical events at the IC level, such as those defined by the AEC-Q100 standard. In certain implementations, the tertiary protection devices can 43a until 43b It may also be included to provide additional protection against transient electrical events at the IC level for sensitive IC circuits. 30 to provide. The tertiary protective devices 43a until 43b They may have a smaller current handling capacity but a faster switching-on speed relative to the primary protection devices. 41a until 41b and the secondary protective devices 42a until 42b exhibit. In other configurations, the tertiary protective devices may 43a until 43bhowever, they may be omitted in favor of using a two-stage protection system comprising one or more primary protective devices and one or more secondary protective devices.

[0045] In one embodiment, the primary protective devices 41a until 41b a current handling capacity that is at least 3 times greater than the current handling capacity of the secondary protective devices 42a until 42b It is. However, other implementations are possible.

[0046] As explained below with reference to Fig. 3A to Fig. As described in detail in section 3B, the secondary protective devices can be used. 42a until 42b be configured to exhibit holding voltages greater than those of the primary protective devices 41a until 41b are, and the tertiary protective devices 43a until 43bcan be configured to have holding voltages greater than those of the primary protection devices 41a until 41b and the secondary protective devices 42a until 42b are. Such a configuration of the protection system can prevent the IC from 30 to enable rapid response to transient electrical events and prevent secondary and / or tertiary protective devices from conducting currents exceeding their current handling capacities.

[0047] For example, the tertiary protective devices 43a until 43b have a smaller current handling capacity than the primary protective devices 41a until 41b and the secondary protective devices 42a until 42bHowever, they can also have a faster switching speed. Therefore, if a transient signal is received at a contact surface, one or more of the tertiary protective devices may be activated. 43a until 43b relatively quickly they enter a low-resistance state, which helps to reduce the initial voltage overshoot at the contact surface. This prevents the tertiary protection devices from 43a until 43b The secondary protective devices can be damaged by sustained high current conditions. 42a until 42b be configured to exhibit holding voltages lower than those of the tertiary protection devices 43a until 43b are. As soon as the secondary protective devices are therefore in place... 42a until 42bIf sufficient time has been allowed for activation, the contact surface voltage can be reduced to a voltage level below the holding voltages of the tertiary protection devices. 43a until 43b are set or blocked, thereby preventing the flow of current through the tertiary protective devices. 43a until 43b reduced or stopped to prevent the tertiary safeguards from 43a until 43b be damaged. Similarly, to prevent the secondary protective devices from being damaged, one can 42a until 42b primary protective devices may be damaged due to sustained high current conditions. 41a until 41b Configure them so that they have holding voltages lower than those of the secondary protection devices. 42a until 42b are, so that the primary protective devices 41a until 41b, once activated, block the contact surface voltage to a level sufficient to prevent current flow through the secondary protection devices. 42a until 42b to reduce or interrupt.

[0048] In the configuration shown, the first primary protective device 41a between the signal contact surface 6 and the energy-deep contact surface 5 electrically connected, and the second primary protection device 41b is between the high-energy contact surface 7 and the energy-deep contact surface 5 electrically connected. Furthermore, the first secondary protective device is 42a between the high-energy contact surface 7 and the signal contact surface 6 electrically connected, and the second secondary protective device 42b is between the high-energy contact surface 7 and the regulated voltage V REGelectrically connected. Furthermore, the first tertiary protective device 43a between an output of the second internal circuit 46 and the energy-deep contact surface 5 electrically connected, and the second tertiary protection device 43b is between the regulated voltage V REG and the output of the second internal circuit 46 electrically connected. The arrangement of the primary protective devices. 41a until 41b , the secondary protective devices 42a until 42b and the tertiary protective devices 43a until 43b This represents one possible arrangement of protective devices. However, in certain implementations, more or fewer primary protective devices may be used. 41a until 41b , secondary protective devices 42a until 42b and / or tertiary protective devices 43a until 43bwill be provided. Furthermore, in some implementations, one or more of the primary protective devices are required. 41a until 41b , the secondary protective devices 42a until 42b and the tertiary protective devices 43a until 43b in a different arrangement between the contact surfaces and / or nodes of the IC 30 tied together.

[0049] For example, the IC can 30 This may include a different arrangement of protective devices to meet specific performance requirements. For example, the IEC 61000-4-2 standard defines system-level ESD events with positive and negative polarity, which occur with respect to a low-energy contact area of ​​a system. Thus, to protect the IC 30 To configure it to comply with IEC-61000-4-2, the first primary protective device can be used. 41a between the signal contact surface 6 and the energy-deep contact surface 5be provided, and the second primary protective device 41b can be between the energy-high contact surface 7 and the energy-deep contact surface 5 must be provided. However, a primary protective device is not required between the high-energy contact surface. 7 and the signal contact surface 6 This must be included to meet the system-level ESD tests defined by IEC 61000-4-2. Thus, in certain implementations, an arrangement of protective devices can be based, at least partially, on a desired set of performance specifications with which the IC 30 It should be compliant.

[0050] In the configuration shown, the tertiary protective devices were 43a , 43b at the output of the second internal circuit 46 provided, but were at the output of the first internal circuit 45Omitted. In certain implementations, tertiary protection devices may be included to protect circuits that are particularly sensitive to voltage overshoot or other transient stress conditions. However, the present teachings are applicable to two-stage protection systems that protect an internal circuit using only primary and secondary protection devices. Furthermore, the number of protection stages can be extended to four or more for certain internal circuit configurations.

[0051] The first and second resistors 47 , 48 can also contribute to protecting the first and second internal circuits, respectively. 45 , 46 to provide. For example, the first and second resistors can 47 , 48to help prevent currents associated with a transient electrical event from entering or exiting the first and second internal circuits respectively. 45 , 46 flow. The first and second resistances 47 , 48 However, they can also attenuate signals from the first and second internal circuits. 45 , 46 generated and / or received, and it may therefore be desirable to have a value for the first and second resistors in certain configurations. 47 , 48 to restrict or eliminate them.

[0052] In some implementations, the first resistance 47 one resistor is chosen to be in the range of approximately 0.5 Ω and approximately 1 kΩ, for example at approximately 500 Ω, and the second resistor 48It has a resistance that is selected to be in the range of approximately 0.5 Ω to approximately 20 Ω, for example, approximately 10 Ω. However, a person skilled in the art will readily identify other suitable resistance values, such as resistance values ​​associated with requirements for signal processing integrity and / or minimal noise.

[0053] In certain implementations, the first and second capacitors can 2a , 2b It may be contained between certain contact surfaces to help protect the contact surfaces from transient electrical events. For example, in the implementation shown, the first capacitor 2a between the signal contact surface 6 and the energy-deep contact surface 5 electrically connected, and the second capacitor 2b was between the high-energy contact surface 7 and the energy-deep contact surface 5electrically connected. Although the first and second capacitors 2a , 2b outside the IC 1 The first and second capacitors may be included to help provide transient electrical protection. 2a , 2b They may be omitted in certain implementations. In some implementations, the first capacitor 2a a capacitance is selected to be in the range of approximately 0 pF and approximately 200 nF, for example approximately 20 nF, and the second capacitor 2b It has a capacitance that is selected to be in the range of approximately 100 pF to approximately 200 nF, for example, approximately 100 nF. However, a person skilled in the art will readily determine other suitable capacitance values.

[0054] Although a protection system has been depicted in connection with an interface IC, the protection systems can be used in a wide variety of ICs and other electronics.

[0055] Fig. 3A is a graphical representation 50 , which establishes a relationship between current and voltage for an example of primary, secondary and tertiary protective devices from Fig. Figure 2 shows the graphical representation. 50 includes a first, almost static curve 51 from current to voltage for a primary protection device, a second nearly static curve 52 from current to voltage for a secondary protection device and a third, nearly static curve 53 from current to voltage for a tertiary protection device, such as can be achieved via transmission line pulse (TLP) measurements.

[0056] The primary, secondary, and tertiary protection devices can be configured to maintain the voltage level at a contact surface within a predefined safe range by paralleling a large portion of the current associated with a transient signal before the voltage of the transient signal becomes either a positive failure voltage +V F or a negative dropout voltage –V F This prevents the current from reaching levels that would otherwise damage the IC. Furthermore, the primary, secondary, and tertiary protection devices can limit the current to a relatively small amount at the normal operating voltage +V. op conducting, thereby reducing or minimizing the static power loss resulting from the leakage current, thus improving the energy efficiency of the IC.

[0057] As shown in the graphic representation 50As shown, the primary, secondary and tertiary protective devices were configured to each exhibit different, nearly static holding and tripping voltages.

[0058] For example, the primary protection device was configured to transition from a high-impedance state to a low-impedance state when the voltage of the transient signal exceeded a first positive trip voltage +V TR1 Once reached, the primary protection device can remain in the low-impedance state as long as the transient signal voltage level is above a first positive holding voltage +V. H1To provide protection against both negative and positive transient signals, and thus to provide bidirectional reverse voltage protection, the primary protection device was also configured to transition from the high-impedance state to the low-impedance state when the voltage of the transient signal exceeds a first negative trip voltage –V TR1 achieved, and to remain in the low-impedance state as long as the voltage magnitude of the negative transient signal is greater than the voltage magnitude of a first negative holding voltage –V H1 is.

[0059] In addition, the secondary protection device was configured to provide a second positive trip voltage +V TR2 , a second positive holding voltage +V H2 , a second negative trigger voltage –V TR2 and a second negative holding voltage –V H2to exhibit. Furthermore, the tertiary protection device was configured to provide a third positive trip voltage +V TR3 , a third positive holding voltage +V H3 , a third negative trigger voltage –V TR3 and a third negative holding voltage –V H3 to demonstrate.

[0060] By configuring the protective devices to each have a tripping voltage and a holding voltage, the protective device can exhibit better performance and greater stability against unintentional activation.

[0061] In the configuration shown, the secondary protection device was configured to have positive holding and trip voltages that are greater than the positive holding and trip voltages of the primary protection device. For example, the second positive trip voltage was +V TR2 and the second positive holding voltage +V H2Each configured to be greater than the first positive trip voltage +V TR1 and the first positive holding voltage +V H1 Furthermore, the tertiary protection device was configured to have positive holding and tripping voltages that are greater than the positive holding and tripping voltages of both the primary and secondary protection devices.

[0062] Providing primary, secondary, and tertiary protection devices can improve the protection offered by an integrated circuit (IC) compared to a method using only a primary protection device in a protection system, even if the primary protection device has a current-handling capacity large enough to safely sustain the maximum transient signal current. In particular, using a multi-stage protection system can help reduce the voltage overshoot associated with the turn-on time of the primary protection device. For example, the primary protection device can be configured to have a larger current-handling capacity than the secondary and tertiary protection devices.However, since the primary protective device may be sized to be relatively large in order to reliably handle the large protective current, it may have a switching speed that is slower than that of the secondary and tertiary protective devices. Likewise, the secondary protective device may be sized to have a current-handling capacity greater than that of the tertiary protective device, but it may also have a slower switching speed.

[0063] Since a slow turn-on speed can lead to an initial voltage overshoot that can damage an IC, the multi-stage protection methods described here can exhibit reduced voltage overshoot by providing protection devices that turn on relatively quickly to reduce peak voltage ratios. Furthermore, the smaller and faster devices with lower current-handling capacity can be configured to have a higher hold voltage than the slower devices with higher current-handling capacity.Configuring the protection system in this way allows the larger devices, once activated, to block the contact surface voltage to a level sufficient to reduce or interrupt the current through the smaller devices, thus preventing the smaller protective devices from being damaged by sustained high current.

[0064] In certain implementations, such as the one in Fig. In the configuration shown in 3A, the trip voltage of a slower device with a larger current-handling capacity is selected to be lower than the trip and hold voltages of faster devices with high current-handling capacity. For example, the trip voltage of a primary protection device may be selected to be lower than the hold voltage of a secondary protection device and lower than the trip voltage of a secondary protection device. Similarly, the trip voltage of a secondary protection device may be selected to be lower than the hold voltage of a tertiary protection device and lower than the trip voltage of a tertiary protection device.Configuring the devices in this way can help ensure that the primary and secondary protective devices are activated during a transient electrical event. However, other implementations are possible, such as configurations where the tripping voltage of a primary protective device is higher than the tripping voltage of the secondary and / or tertiary protective devices.

[0065] In one embodiment, the primary protection device has the largest size, slowest activation speed, and lowest holding voltage among the primary, secondary, and tertiary protection devices. The holding voltage of the primary protection device can be configured to be lower than the holding voltages of the secondary and tertiary protection devices, enabling the primary protection device to also protect the secondary and tertiary protection devices during activation under very high-voltage stress conditions. The primary protection device can be optimized to withstand system-level ESD and EMI stress conditions that may occur between pins connected to a high-voltage interface.The secondary protection device can be smaller and faster than the primary protection device and can provide additional discharge paths to offer protection against device-level stresses caused by manufacturing and handling, such as those of a human body model (HBM) and / or a charge device model (CDM) that may occur on any pin of the IC. The tertiary protection devices can have the fastest turn-on speed and highest holding voltage of the protection devices and can be used to parallel overvoltage protection before the primary protection devices have been activated, thus protecting the primary devices from overstress beyond safe operating conditions.

[0066] In Fig. In 3A, voltage is expressed on a horizontal axis and current is expressed on a vertical axis. In the illustrated embodiment, the protective device has symmetrical IV characteristics. In other implementations, the protective devices described here may have asymmetrical IV characteristics. For example, protective devices may have different tripping voltages, holding voltages, and / or failure voltages with different IV curves in the positive and negative regions of the graphical representation.

[0067] Fig. 3B is a graphical representation 60 an example of voltage-to-time for the primary, secondary, and tertiary protective devices Fig. 3A. The graphical representation 60 includes a first curve 61 from voltage to time for a primary protection device, a second curve 62from voltage to time for a secondary protection device and a third curve 63 from voltage to time for a tertiary protection device. The first to third curves 61 until 63 can map a transient voltage against time when a transient electrical event, starting at time t0 and ending at time t1, is received at a contact surface, each protected by a primary protective device, a secondary protective device, and a tertiary protective device.

[0068] As in the first to third turns 61 until 63 out of Fig. As shown in Figure 3B, the primary protective device can exhibit a voltage overshoot greater than that of the secondary and tertiary protective devices, and the secondary protective device can exhibit a voltage overshoot greater than that of the tertiary protective device. For example, a first voltage overshoot V OS1 the primary protection device greater than a second voltage overshoot V OS5 the secondary protective device as well as a third voltage overshoot V OS3 the tertiary protection device. In addition, the second voltage overshoot V can OS2 the secondary protection device greater than the third voltage overshoot V OS3The voltage overshoot can be caused by many different factors, such as a switching speed associated with the activation of the protective devices, which may take longer for protective devices designed to have a relatively large current handling capacity.

[0069] Although the third voltage overshoot V OS3Since the tertiary protection device can be of the smallest size, it can be damaged if it conducts a large current during a transient electrical event. To prevent damage to the tertiary protection device from sustained high-current conditions, the secondary and primary protection devices can each be configured to have a holding voltage lower than that of the tertiary protection device. Thus, once the secondary and primary protection devices have had sufficient time to activate, the transient voltage can be blocked to a level below the holding voltage of the tertiary protection device, thereby reducing or interrupting the current through the tertiary protection device and preventing damage.To similarly prevent damage to the secondary protection device due to sustained high current conditions, the primary protection device can be configured to have a holding voltage lower than the holding voltage of the secondary protection device, so that once activated, the primary protection device blocks the contact surface voltage to a level sufficient to reduce or interrupt the current through the secondary protection device.

[0070] Fig. 4A to Fig. 4C are circuit diagrams of various architectures of an internal circuit of an IC interface.

[0071] Fig. 4A is a circuit diagram of an example of an internal circuit. 70 an IC. The internal circuitry 70 includes an n-doped metal oxide semiconductor (NDMOS) transistor 71with double diffusion or extended drain, a p-doped metal oxide semiconductor (PDMOS) transistor 72 with double diffusion or extended drain, a first diode-connected PNP bipolar transistor 73 , a second diode-connected PNP bipolar transistor 74 , a first control circuit 75 , a second control circuit 76 , a first MOS protection circuit 77 , a second MOS protection circuit 78 and first to fourth resistors 81 until 84 The internal circuit 70 is depicted as they are at an energy-deep contact surface 5 , a signal contact surface 6 and a high-energy contact surface 7 is electrically connected to an IC. The internal circuit 70 It may be suitable, for example, as the first and / or second internal circuit 45 , 46 out of Fig. 2 to serve. The internal circuit70 It can, for example, be used as a driver circuit for a LIN interface.

[0072] The NDMOS transistor 71 includes a body and a source that connects to the energy-deep contact surface. 5 are electrically connected. The NDMOS transistor 71 further includes a drain connected to a base of the first diode-connected PNP bipolar transistor 73 electrically connected, and a gate that is connected to the first control circuit 75 It is electrically connected. The PDMOS transistor 72 comprises a body and a source that connect to a base of the second diode-connected PNP bipolar transistor 74 are electrically connected. The PDMOS transistor 72 further includes a drain that connects to a first end of the second resistor. 82 electrically connected, and a gate that is connected to the second control circuit 76electrically connected. As they are used here, and as the person skilled in the art will understand, MOS transistors can have gates made of non-metal materials, such as polysilicon, and can include dielectric regions that are not simply silicon oxide but other dielectrics, such as high-k dielectrics.

[0073] The first diode-connected PNP bipolar transistor 73 It also includes a collector that is connected to the energy-deep contact surface. 5 is electrically connected, and an emitter connected to a first end of the first resistor. 81 is electrically connected. The second diode-connected PNP bipolar transistor 74 It also includes a collector that is connected to the energy-deep contact surface. 5 electrically connected, and an emitter that is connected to the high-energy contact surface. 7is electrically connected. The first resistor 81 furthermore includes a second end that connects to a second end of the second resistance 82 , a first end to the third resistance 83 , a first end to the fourth resistance 84 and to the signal contact surface 6 electrically connected. The first MOS protection circuit 77 is between a second end of the third resistance 83 and the energy-deep contact surface 5 electrically connected. The second MOS protection circuit 78 is between a second end of the fourth resistance 84 and the high-energy contact surface 7 electrically connected.

[0074] The internal circuit 70 can be used to measure the voltage level of the signal contact surface 6 to control. For example, NDMOS and PDMOS transistors include 71 , 72Gates, each connected to the first and second control circuits 75 , 76 are electrically connected. In certain implementations, the gate of the NDMOS transistor is 71 controlled to a voltage level corresponding to a desired consumer current of the internal circuit 70 corresponds to, and the gate of the PDMOS transistor 72 is controlled to a voltage level that corresponds to a desired source current of the PDMOS transistor. 72 corresponds to a voltage level of the signal contact surface 6 to control.

[0075] The first and second diode-connected PNP bipolar transistors 73 , 74 can help to control the operating voltage range of the signal contact surface 6 to expand. For example, the signaling conditions at the signal contact surface can be improved. 6include positive and negative voltage signaling levels, and the first and second diode-connected PNP bipolar transistors. 73 , 74 can be used to prevent the bodies of NDMOS and PDMOS transistors from 71 , 72 are pre-tensioned in the direction of transmission when the signal contact surface 6 below the voltage level of the energy-deep contact surface 5 falls or exceeds the voltage level of the high-energy contact surface. 7 increases. In certain implementations, such as those using a silicon-on-insulator (SOI) or other suitable isolation process, the first and second diode-connected PNP bipolar transistors can 73 , 74 omitted in favor of using high-voltage blocking diodes. Although Fig. 4A a specific sequence of NDMOS and PDMOS transistors 71 , 72and the first and second diode-connected PNP bipolar transistors 73 , 74 While other configurations are possible, if certain processes are used, such as SOI processes, the order of the PDMOS transistors can be changed. 72 and the second diode-connected PNP bipolar transistor 74 It could be the other way around.

[0076] The first and second resistors 81 , 82 can help prevent current from flowing through the NDMOS and PDMOS transistors during a transient electrical event. 71 , 72 flows. In some implementations, the first resistance is evident. 81 one resistor is chosen to be in the range of approximately 0 Ω and approximately 5 Ω, for example at approximately 0.5 Ω, and the second resistor 82It has a resistance that is selected to be in the range of approximately 0 Ω to approximately 5 Ω, for example, approximately 0.5 Ω. However, a person skilled in the art will readily identify other suitable resistance values, such as resistance values ​​associated with requirements for signal processing integrity and / or minimal noise. Furthermore, in certain implementations, one or both of the first and second resistances can be selected. 81 , 82 omit.

[0077] When a transient electrical event occurs at the signal contact surface 6 The voltage of the signal contact surface can be received. 6 increase until the trip voltages of the protective devices connected to the signal contact surface rise. 6 are connected, are reached (see Fig. 2) However, in certain implementations, there may be an overshoot of the voltage at the signal contact surface. 6before the protection devices are activated. In certain implementations, the first and second MOS protection circuits can be used. 77 , 78 to be provided for the NDMOS and PDMOS transistors respectively. 71 , 72 to provide additional protection. However, in other implementations, one or both of the first and second MOS protection circuits can be used. 77 , 78 omit.

[0078] In certain implementations, the third resistance can 83 with the first MOS protection circuit 77 be connected in series, and the fourth resistor 84 can be used with the second MOS protection circuit 78 They must be connected in series to reduce the impedance of electrical interference paths between the high-energy contact surface. 7 and the energy-deep contact surface 5 through the first and second MOS protection circuits 77 , 78to increase. In one embodiment, the third resistor has 83 a resistance in the range of approximately 0 Ω to approximately 5 Ω, for example approximately 1 Ω, and the fourth resistance 84 exhibits a resistance in the range of approximately 0 Ω to approximately 5 Ω, for example, approximately 1 Ω. However, a person skilled in this field will readily identify other suitable resistance values. Furthermore, in certain implementations, one or both of the third and fourth resistances can be used. 83 , 84 omit.

[0079] Fig. 4B is a circuit diagram of another example of an internal circuit. 85 an IC. The internal circuitry 85 includes NDMOS and PDMOS transistors 71 , 72 , the first and second diode-connected PNP bipolar transistors 73 , 74 , the first and second control circuits 75 , 76, the first and second MOS protection circuits 77 , 78 and the first to fourth resistors 81 until 84 The internal circuit 85 is depicted as they connect to an energy-deep contact surface 5 , a first signal contact surface 6a , a second signal contact surface 6b and a high-energy contact surface 7 is electrically connected to an IC. The internal circuit 85 may be suitable, for example, as the first and / or second internal circuit 45 , 46 out of Fig. 2 to serve by providing an additional signal contact area in the IC 30 out of Fig. 2 includes the internal circuit. 85 It can, for example, be used as a driver circuit for a CAN interface.

[0080] The internal circuit 85 out of Fig. 4B can be used similarly to the internal circuit. 70 out of Fig. It should be 4A. In contrast to the internal circuit. 70 out of Fig. 4A, where the NDMOS and PDMOS transistors 71 , 72 were configured to use the signal pen 6 The internal circuit forms the control mechanism. 85 out of Fig. 4B uses a differential configuration in which the NDMOS and PDMOS transistors 71 , 72 were configured to use the first and second signal pins respectively 6a , 6b to control it. For example, the NDMOS transistor was used. 71 configured to receive the first signal pen 6a through the first resistance 81 and the first diode-connected PNP bipolar transistor 73 to control, and the PDMOS transistor 72 was configured to use the second signal pen 6b through the second resistance 82 to control. Additional details of the internal circuitry. 85may be similar to those previously mentioned in relation to Fig. 4A were described.

[0081] Fig. 4C is a circuit diagram of another example of an internal circuit. 90 an IC. The internal circuitry 90 includes a first PDMOS transistor 91 , a second PDMOS transistor 92 , a Zener diode 93 , a switching control circuit 94 and a low-voltage driver 95 The internal circuit 90 is shown as they connect to a signal contact surface 6 is electrically connected to an IC. The internal circuit 90 may be suitable, for example, as the first and / or second internal circuit 45 , 46 out of Fig. 2 to serve. The internal circuit 90 It can, for example, be used as a driver circuit for an interface.

[0082] The first PDMOS transistor 91includes a drain that connects to the signal contact surface 6 electrically connected. The first PDMOS transistor 91 further includes a body and a source connected to a body and a source of the second PDMOS transistor 92 and a cathode of the Zener diode 93 are electrically connected. The first PDMOS transistor 91 It also includes a gate that connects to a gate of the second PDMOS transistor. 92 , to an anode of the Zener diode 93 and to the switching control circuit 94 is electrically connected. The second PDMOS transistor 92 It also includes a drain connected to the low-voltage driver. 95 electrically connected, which uses the regulated voltage supply V REG electrically powered.

[0083] The internal circuit 90 can be used to measure the voltage level of the signal contact surface 6to control. For example, the first and second PDMOS transistors comprise 91 , 92 Gates connected to the switching control circuit 94 , which can be used to determine the resistance between the low-voltage driver 95 and the signal pen 6 to change by changing the channel impedance of the first and second PDMOS transistors 91 , 92 controls, are electrically connected.

[0084] The Zener diode 93 can contribute to damage to the first and second PDMOS transistors 91 , 92 to prevent this. For example, if a transient electrical event occurs at the signal contact surface. 6 The received signal can be determined by the size of the voltage across the signal contact area. 6 increase until the tripping voltages of the protective devices used to protect the contact surface are reached (see Fig. 2) The Zener diode 93can provide bidirectional breakdown protection during a transient electrical event to help reduce the magnitude of the gate-drain and / or gate-source voltages of the first and second PDMOS transistors. 91 , 92 to prevent reaching levels that are associated with transistor damage.

[0085] Fig. Figure 5 is a circuit diagram illustrating two implementations of a portion of an internal circuit. As described below, the diagram shows that serial components of an internal circuit can be implemented as an equivalent parallel combination of lumped components with intermediate finger pre-connection in series. Configuring the components in this way can provide improved robustness when designed in conjunction with the protection architecture.

[0086] As the first circuit implementation 98 out of Fig. As shown in section 5, an internal circuit can use a PDMOS transistor. 72 include, which is connected to a diode-connected PNP bipolar transistor 74 and a resistance 82 is electrically connected in series. For example, a drain of the PDMOS transistor 72 to the first resistance 82 and a source be electrically connected, and the main part of the PDMOS transistor 72 can be connected to a base of the diode-connected PNP bipolar transistor 74 be electrically connected. The diode-connected PNP bipolar transistor 74 It can further comprise a collector electrically connected to a first voltage supply V1 and an emitter, which may be connected, for example, to a high-energy contact pad. The diode-connected PNP bipolar transistor 74 can function as a locking crossing.

[0087] In certain implementations, an internal circuit comprising a series combination of one or more transistors and a resistor can be implemented using multiple subcircuits or power branches within a single circuit arrangement. Such configuration of the internal circuit arrangement can serve as an additional safeguard to protect the transistors from damage by providing a higher resistance when considering each power branch in relation to a configuration using a single power branch while meeting or exceeding the design requirement for low net resistance.For example, in an implementation that uses four power branches to implement the serial combination of a transistor and a 5 Ω resistor, each of the four transistor power branches can be protected from transient electrical events using a 20 Ω resistor, while providing an equivalent resistance for signals generated by the transistors in the normal operation of the internal circuit.

[0088] A second circuit implementation 99 out of Fig. Figure 5 illustrates an example of an internal circuit configuration that uses multiple power branches. For example, the second circuit implementation includes 99 the first to third PDMOS transistor power branches 72 until 72c , the first to third diode-connected PNP bipolar transistor power branches 74a until 74c and the first to third resistance segments 82a until 82cThe emitters of the first to third diode-connected PNP bipolar transistor power branches 74a until 74c They were electrically connected to each other. In addition, the gates of the first to third PDMOS transistor power branches were connected. 72a until 72c electrically interconnected. Furthermore, the sources and bodies of the first to third PDMOS transistor power branches were connected. 72a until 72c electrically connected to the bases of the first to third diode-connected PNP-bipolar transistor power branches 74a until 74c connected. The first to third diode-connected PNP bipolar transistor power branches 74a until 74c They also include collectors that are electrically connected to the first voltage supply V1. The first to third PDMOS transistor power branches 72a until 72c They also include drains, each connected to the first ends of the first to third resistance segments.82a until 82c are electrically connected. The second ends of the first to third resistance segments 82a until 82c were electrically connected to each other.

[0089] Although the second circuit implementation 99 out of Fig. 5 represents an implementation that uses three power branches, the second circuit implementation can 99 can be adapted to include more or fewer power branches. Furthermore, other circuits using multiple power branches can be added to the one in Fig. The circuit shown in section 5 can be formed. For example, in certain implementations, the serial combination of the NDMOS transistor can be used. 71 , of the first diode-connected PNP bipolar transistor 73 and the first resistance 89 out of Fig. 4A to Fig. 4B can be implemented using multiple power branches as part of an optimization through the joint design of a protection architecture core circuit. Overview of specific designs of protective devices

[0090] Fig. 6 is a circuit diagram showing a protection circuit 100 depicted according to one embodiment. The illustrated protection circuit 100 is between a first contact surface 101 and a second contact surface 102 electrically connected and can be used, for example, to provide bidirectional reverse voltage protection. The protection circuit 100 includes a bidirectional bipolar transistor 103 , first and second NPN bipolar transistors 104 , 105 , first and second PNP bipolar transistors 106 , 107 and first to sixth resistors 111 until 116As described in detail below, the protection circuit can 100 can be implemented in various configurations to serve as one or more of the primary, secondary, and tertiary protective devices. 41a until 41b , 42a until 42b , 43a until 43c out of Fig. 2 to function.

[0091] The protection circuit 100 can be between the first and second contact surfaces 101 , 102 They must be electrically coupled so that a current shunt path can be established between the contact pads when an overvoltage or undervoltage condition exists. For example, the first contact pad can be a high-energy contact pad or a signal contact pad of an IC, such as the high-energy contact pad. 7 or the signal contact surface 6 out of Fig. 2, and the second contact surface can be an energy-deep contact surface, such as the energy-deep contact surface 5 out of Fig. 2. In certain implementations, the second contact surface 102 a grounding contact surface. The protective circuit 100 can create a low-resistance path between the first contact surface during a transient electrical event 101 and the second contact surface 102 provide.

[0092] The first NPN bipolar transistor 104 includes an emitter connected to a first end of the first resistor. 111 , to a first end of the third resistance 113 and to the first contact surface 101 electrically connected. The first NPN bipolar transistor 104 further includes a base that connects to an emitter / collector E / C of the bidirectional bipolar transistor. 103 and to a second end of the first resistance 111is electrically connected. The second NPN bipolar transistor 105 includes an emitter connected to the first end of the second resistor. 112 , to a first end of the fourth resistance 114 and to the second contact surface 102 is electrically connected. The second NPN bipolar transistor 105 further includes a base that is connected to a collector / emitter C / E of the bidirectional bipolar transistor 103 and to a second end of the second resistance 112 is electrically connected.

[0093] The bidirectional bipolar transistor 103 further includes a base that connects to a collector of the first NPN bipolar transistor 104 , to a collector of the second NPN bipolar transistor 105 , to a base of the first PNP bipolar transistor 106 and to a base of the second PNP bipolar transistor 107is electrically connected. In certain implementations, the base of the bidirectional bipolar transistor is 103 formed from an n-well electrically connected to an ungrounded n-doped insulating layer. The first PNP bipolar transistor. 106 further includes an emitter connected to a second end of the third resistor 113 is electrically connected, and a collector connected to a first end of the fifth resistor. 115 is electrically connected. The second PNP bipolar transistor 107 further includes an emitter connected to a second end of the fourth resistor 114 is electrically connected, and a collector connected to a first end of the sixth resistor. 116 is electrically connected. The sixth resistor 116 It also includes a second end that connects to a second end of the fifth resistance. 115and is electrically connected to the first supply voltage V1, which can be, for example, a grounding node. In certain implementations, the second ends of the fifth and sixth resistors 115 , 116 electrically connected to a p-doped guard ring.

[0094] The bidirectional bipolar transistor 103 can function bidirectionally, and the operation of the emitter / collector E / C and the collector / emitter C / E as emitter and collector can depend on the voltage ratios of the first and second contact surfaces. 101 , 102 depend. For example, if there is a voltage difference between the first contact surface 101 and the second contact surface 102 greater than approximately a positive trigger voltage (see, for example, the voltages +V T1 , +V T2 , and +V T3 out of Fig. 3A) of the protection circuit 100The emitter / collector E / C of the bidirectional bipolar transistor serves this purpose. 103 as emitter, and the collector / emitter C / E of the bidirectional bipolar transistor serves as collector. If, on the other hand, there is a voltage difference between the first contact surface... 101 and the second contact surface 102 less than approximately a negative trigger voltage (see, for example, the voltages -V T1 , –V T2 , and –V T3 out of Fig. 3A) of the protection circuit 100 The emitter / collector E / C of the bidirectional bipolar transistor serves this purpose. 103 as collector, and the collector / emitter C / E of the bidirectional bipolar transistor 103 serves as an emitter.

[0095] In certain implementations, the bidirectional bipolar transistor can 103 be a PNP bipolar transistor configured to handle the response and current discharge of the protection circuit 100to control during an overvoltage or undervoltage condition. For example, the first and second NPN bipolar transistors can 104 , 105 be configured to have limited injection efficiency at their emitter-base junctions, thus making it suitable for bidirectional bipolar transistors 103 to essentially control the response behavior.

[0096] The first to sixth resistors 111 until 116 For example, they can be formed using the specific resistance of doped regions to achieve the desired resistances. In one embodiment, the first to sixth resistances are 111 until 116For example, this can be implemented using the specific resistance of n-doped or p-doped wells to achieve a switching speed and stability desired for a particular application. For example, the resistance of the first and second resistors can be 111 , 112 selected to achieve a desired increase in the emitter-base junctions of the first and second NPN bipolar transistors respectively 104 , 105 to pre-tension in the direction of passage.

[0097] During implementation, the protective device 100 suitable to be used as one or both of the primary protective devices 41a until 41b , one or both of the secondary protective devices 42a until 42b and / or one or both of the tertiary protective devices 43a until 43b out of Fig. 2 to serve.

[0098] Fig. 7A is a schematic perspective view of a protective device 120 , which is the protection circuit 100 out of Fig. 6 according to one embodiment. The protective device 120 includes a substrate 121 , first to fourth p-tubs 122a until 122d , first to fourth p-doped active surfaces 123a until 123d , first to third n-tubs 124a until 124c , first to fourth n-doped active surfaces 125a until 125d , first and second deep p-tubs 126a , 126b , first to third shallow n-tubs 127a until 127c , oxide areas 128 and an n-doped insulating layer 129 The protective device 120 depicts an example of a protective device that can be used as the tertiary protective devices 43a , 43b out of Fig. 2 is suitable.

[0099] Although the protective device 120While one embodiment of the tertiary protection device is depicted, other configurations can be used. For example, in certain implementations, the tertiary protection device can be implemented using continuous structures of high-voltage avalanche blocking diodes, which may be suitable for implementing low-current leading-capacitance blocking components without occupying a relatively large area.

[0100] As in Fig. As shown in 7A, the substrate includes 121 the first to third n-tubs 124a until 124c and the first to fourth p-tubs 122a until 122d , which are formed therein. The second and third p-tubs 122b , 122c are on opposite sides of the second n-tub 124b arranged. The first n-tub 124a is on one side of the second p-tub 122b opposite the second n-tub 124b arranged. The third n-tub124c is on one side of the third p-tub 122c opposite the second n-tub 124b arranged. The n-doped insulating layer 129 is below the second n-tub 124b , the second and third p-tubs 122b , 122c and below part of the first and third n-tubs 124a , 124c arranged. The first p-tub 122a is next to the first n-tub on one side of the first n-tub 124a opposite the second p-tub 122b formed. The fourth p-tub 122d is next to the third n-tub 124c on one side of the third n-tub opposite the third p-tub 122c formed. In the configuration shown, the first and fourth p-tubs are 122a , 122d each from the first and third n-tubs 124a , 124c spaced apart in such a way that the first p-tub 122anot to the first n-tub 124a bumps, and the fourth p-tub 122d not to the third n-tub 124c This encounters a problem. However, other implementations are possible.

[0101] The first, second and third shallow n-tubs 127a until 127c are each in the first, second and third n-tubs 124a until 124c formed. The first deep p-tub 126a is along a boundary between the second p-tub 122b and the n-doped insulating layer 129 formed, and the second deep p-tub 126b is along a boundary between the third p-tub 122c and the n-doped insulating layer 129 educated.

[0102] In the configuration shown, the protective device 120 in the substrate 121formed, which can be a p-doped substrate. In another embodiment, the substrate can comprise a p-doped epitaxial layer formed on a silicon (Si) substrate. Although this in Fig. 7A is not shown, the substrate 121 also include other devices or structures formed therein.

[0103] The first to fourth p-doped active surfaces 123a until 123d are in the first to fourth p-tubs 122a until 122d arranged. The first and fourth n-doped active surfaces 125a , 125d are located in the first and third shallow n-tubs, respectively 127a , 127c the first and third n-tubs 124a , 124c arranged. The second n-doped active area 125b is in the second p-tub 122barranged and positioned such that they are located between part of the second p-doped active area 123b and the second n-tub 124b The third n-doped active area is located. 125c is in the third p-tub 122c arranged and positioned such that they are located between a part of the third p-doped active area 123c and the second n-tub 124b is located.

[0104] In the configuration shown, the second n-doped active surface comprises 125b a multitude of island areas 125b1 , which are arranged along the X-direction, and the third n-doped active surface 125c encompasses a variety of island areas 125c1 , which are arranged along the X-direction. Furthermore, the second p-doped active surface comprises 123b an elongated area 123b1 , which extends in the X direction, and a multitude of protruding areas 123b2, which in the Y direction to the second n-tub 124b extend. As in Fig. As shown in 7A, each of the above areas extends 123b2 between two of the island areas 125b1 Similarly, the third p-doped active area comprises 123c an elongated area 123c1 , which extends in the X direction, and a multitude of protruding areas 123c2 , which extend in the Y direction towards the second n-tub 124b extend. Each of the above areas 123c2 extends between two of the island areas 125c1 As described in more detail below, such configuration of the second and third p-doped active surfaces is possible 123b , 123c and the second and third n-doped active areas 125b , 125c to contribute to the holding and / or tripping voltages of the protective device 120to increase, thereby helping to protect the device 120 for operation as the tertiary protective devices 43a , 43b out of Fig. 2 to make suitable. Although they are depicted and described with reference to X directions, Y directions and Z directions, it is understood that the directions can be interchanged and that they can vary based on the view.

[0105] In one embodiment, the width W1 of the island areas is 125b1 in the X direction in the range of approximately 0.4 μm to approximately 1.5 μm, for example at approximately 1 μm. However, other implementations are possible. For example, the width W1 can be increased to enhance the effect of the NPN bipolar transistors and lower the holding voltage, which helps to control the holding voltage for various configurations of the primary, secondary, and tertiary protection devices.

[0106] The first and third n-tubs 124a , 124c and the n-doped insulating layer 129 can help with the second and third p-tubs 122b , 122c from the substrate 121 to electrically insulate the p-doped substrate 121 and the second and third p-tubs 122b , 122c can function at different electrical potentials. As used here and as understood by those skilled in the art, the term “n-doped insulating layer” refers to any suitable n-doped insulating layer, including, for example, those used in silicon-on-insulator (SOI) technologies, buried n-layer technologies, or deep n-well technologies. In certain implementations described here, the first to third n-wells are until 124c and the n-doped insulating layer 129configured to be electrically ungrounded. Although the protective device 120 is shown as they are the first and third n-tubs 124a , 124c and the n-doped insulating layer 129 includes the protective device 120 In certain applications, isolation from a substrate can be achieved in a different way. For example, isolation can be achieved using silicon-on-insulator (SOI) processes by employing dielectric structures. SOI processes can be used in various applications, including those with high electrical robustness requirements.

[0107] The first and fourth p-tubs 122a , 122d and the first and fourth p-doped active surfaces 123a , 123d can be a protective structure of the protective device 120 form. For example, the first and fourth p-tubs can122a , 122d In a ring-shaped configuration, they form part of a protective ring that protects the protective device 120 surrounds when they are from above the substrate 121 The protective ring can be used to prevent the formation of unintended interference paths between the protective device and the protective device. 120 and surrounding semiconductor components when they are integrated on the chip.

[0108] The protective device shown 120 includes the oxide areas 128 The formation of insulating areas can be caused by the etching of trenches in the substrate. 121 This includes filling the trenches with a dielectric, such as silicon dioxide (SiO2), and removing the excess dielectric using any suitable method, such as chemical-mechanical planarization. In certain reactions, the oxide regions can 128These may be areas with shallow trenches (STI) or areas with local oxidation of silicon (LOCOS) located between active surfaces.

[0109] In one embodiment, the first to fourth p-tubs can be 122a until 122d and the first to third n-tubs 124a until 124c exhibit a similar depth to each other, such as a depth between approximately 3 μm and approximately 5.5 μm in relation to a surface area 130 of the substrate 121 In some implementations, the first to fourth p-doped active surfaces can 123a until 123d and the first to fourth n-doped active areas 125a until 125d exhibit a depth that is approximately 15 to 25 times less than the depth of the trough in which the active area is formed. In certain transformations, the first to third shallow n-troughs exhibit 127a until 127ca depth that is approximately 1.2 times to approximately 2.5 times less than the depth of the first to third n-tubs until 124c is. The oxide areas 128 can have any suitable depth, such as a depth approximately 5 times to approximately 15 times less than the depth of the first to fourth p-tubs 122a until 122d is. In certain reactions, the oxide regions can 128 relatively deeper than the first to fourth p-doped active surfaces 123a until 123d and the first to fourth n-doped active areas 125a until 125d be.

[0110] The protective device 120 It can undergo backend processing to form contacts and metallization. Those skilled in the art will understand that these details have been omitted from this figure for the sake of clarity.

[0111] Fig. 7B is a cross-sectional view of the protective device120 out of Fig. 7A, seen along lines 7B-7B. The protective device 120 The substrate includes 121 , the first to fourth p-tubs 122a until 122d , the first to fourth p-doped active surfaces 123a until 123d , the first to third n-tubs 124a until 124c , the first to fourth n-doped active areas 125a until 125d , the first and second deep p-tubs 126a , 126b , the first to third shallow n-tubs 127a until 127c , the oxide areas 128 and the n-doped insulating layer 129 , which, as above, with reference to Fig. 7A can be designed as described.

[0112] The cross-section of the protective device 120It was annotated to show examples of circuit devices formed from the illustrated structure, such as the bidirectional bipolar transistor. 103 , the first and second NPN bipolar transistors 104 , 105 , the first and second PNP bipolar transistors 106 , 107 and the first to sixth resistors 111 until 116 Furthermore, the cross-section was annotated to identify the first and second contact surfaces. 101 , 102 as well as the electrical connections in the protective device 120 and with the first and second contact surfaces 101 , 102 to show. For example, the first contact surface 101 to the second p-doped active area 123b and to the second n-doped active area 125b electrically connected, and the second contact surface 102 is attached to the third p-doped active area123c and to the third n-doped active area 125c electrically connected. Furthermore, the first n-doped active area is 125a to the fourth n-doped active area 125d electrically connected, and the first and fourth p-doped active surfaces 123a , 123d are electrically connected to the first supply voltage V1. The electrical connections shown can be made, for example, using contacts and metallization during backend processing.

[0113] The bidirectional bipolar transistor 103 can from the second n-tub 124b and the second and third p-tubs 122b , 122c can be formed. For example, the bidirectional bipolar transistor 103 an emitter / collector E / C that comes from the second p-well 122b a basis is formed from the second n-tub 124bis formed, and a collector / emitter C / E, which is formed from the third p-well. 122c is formed, exhibit. The first and second NPN bipolar transistors 104 , 105 can be derived from the second and third n-doped active surfaces 125b , 125c , from the second and third p-tubs 122b , 122c and from the n-doped insulating layer 129 They can be formed and can be perpendicular NPN bipolar interference devices. For example, the first NPN bipolar transistor can be 104 an emitter consisting of the second n-doped active area 125b a basis is formed, consisting of the second p-tub 122b is formed, and a collector consisting of the n-doped insulating layer 129 is formed, exhibit. In addition, the second NPN bipolar transistor can 105 an emitter consisting of the third n-doped active area 125ca basis is formed from the third p-tub 122c is formed, and a collector consisting of the n-doped insulating layer 129 is formed, exhibit. The first and second PNP bipolar transistors 106 , 107 can be from the first to fourth p-tubs 122a until 122d and the first and third n-tubs 124a , 124c They can be formed and can be lateral PNP-bipolar interference devices. For example, the first PNP-bipolar transistor can be 106 an emitter that comes from the second p-well 122b a basis is formed, consisting of the first n-tub 124a is formed, and a collector that comes from the first p-tub 122a is formed, exhibit. In addition, the second PNP bipolar transistor can 107 an emitter that comes from the third p-well 122c is formed, a basis consisting of the third n-tub 124cis formed, and a collector that comes from the fourth p-tub 122d is formed, exhibit.

[0114] The first and third resistances 111 , 113 can be derived from the resistance of the second p-tub 122b be formed, and the second and fourth resistors 112 , 114 can be derived from the resistance of the third p-tub 122c can be formed. Furthermore, the fifth resistance can be... 115 from the resistance between the collector of the first PNP bipolar transistor 106 and the first p-doped active area 123a be formed, and the sixth resistance 116 can be derived from the resistance between the collector of the second PNP bipolar transistor 107 and the fourth p-doped active area 123d be formed.

[0115] The expert in this field will understand that the in Fig. 7B shown cross-section of the in Fig. 6 shown protection circuit 100 can comply. Although the protective device 120 out of Fig. 7A and Fig. 7B an implementation of the protection circuit 100 out of Fig. As depicted in 6, other implementations are possible.

[0116] As in Fig. As shown in 7B, the first and fourth n-doped active surfaces can be 125a , 125d , the first to third n-tubs 124a until 124c and the n-doped insulating layer 129 be configured to be electrically ungrounded, which can help extend a range of voltages over which the first and second contact surfaces 101 , 102 can work.

[0117] The second and third p-doped active surfaces 123b , 123c can be used to control the trip voltage of the protective device 120contribute. For example, the second and third p-doped active surfaces can 123b , 123c a higher doping concentration than the second and third p-wells, respectively 122b , 122c exhibit, and can therefore be used to control the emitter coupling of the bidirectional bipolar transistor 103 and / or the base resistance of the first and second NPN bipolar transistors 104 , 105 to control. In addition, the second and third p-doped active surfaces can 123b , 123c In certain implementations, the holding voltage of the protective device also applies. 120 affecting the system, for example by changing the gain of the bipolar transistor.

[0118] With reference to Fig. 7A and Fig. 7B can be the second and third p-doped active surfaces 123b , 123cserving as hole injection centers and recombination centers for electrons, located within the second and third p-wells respectively 122b , 122c be injected. By accessing the second p-doped active surface 123b configured so that they include the preceding parts 123b2 includes areas located between the islands 125b1 the second n-doped active area 125b extend, and by extending the third p-doped active surface 123c configured so that they include the preceding parts 123c2 includes areas located between the islands 125c1 the third n-doped active area 125c Extending the operation of the second and third p-doped active areas is possible. 123b , 123c as hole injection centers and electron recombination centers.

[0119] By increasing the injection of holes and the recombination of electrons, the operation of the bidirectional bipolar transistor can be improved. 103 to be improved, and the operation of the first and second NPN bipolar transistors 104a , 104b can be reduced, which can help to lower the holding and tripping voltages of the protective device. 120 to raise to a level suitable for use as the tertiary protective device 43a , 43b out of Fig. 2 is suitable. In addition, the formation of the second and third n-doped active surfaces can 125b , 125c each from the island areas 125b1 , 125c1 , reduce the resistance in the emitters and the size of the emitter area of ​​the first and second NPN bipolar transistors 104a , 104b reduce, which can further contribute to reducing the holding and / or tripping voltages of the protective device 120to control. Furthermore, the inclusion of the deep p-tub areas can 126a , 126b further operation of the first and second NPN bipolar transistors 104a , 104b prevent the holding and / or tripping voltages of the protective device from being reached. 120 will be increased further.

[0120] Once again with reference to Fig. 7B was the protective device 120 annotated to show various dimensions of the previously described tubs, areas, and layers. Fig. 7B is the protective device 120Asymmetrical. Accordingly, although the dimensions are described below with reference to the left half of the device, the right half of the device may have the same dimensions. The person skilled in the art will understand that the present teachings are also applicable to asymmetrical devices. For example, asymmetrical structures can be provided by arranging the troughs, active areas, and / or other structures of the device in an asymmetrical configuration.

[0121] A first spacing d1 between the second p-doped active surface 123b and the second n-doped active area 125b The spacing d1 can be selected to be relatively short, such as the minimum spacing allowed by the process technology. Selecting a relatively short spacing d1 can improve the operation of the second p-doped active surface. 123bas a recombination center for electrons that are in the second p-well 122b The material is injected. In certain applications, the first spacing d1 can be selected to lie in the range from approximately 0 μm (closest) to approximately 1.5 μm, for example, at approximately 1 μm. However, other dimensions can readily be determined by a person skilled in the art.

[0122] A second spacing d2 between an edge of the first n-doped active surface 125a and an edge of the second p-tub 122b can be selected to be large enough to avoid the first PNP bipolar transistor 106 between the first n-tub 124a and the second p-tub 122b during a transient electrical event. Likewise, a third spacing d3 can be established between an edge of the second p-doped active surface. 123b and an edge of the first n-tub be selected to be large enough to avoid the first PNP bipolar transistor 106 between the first n-tub 124a and the second p-tub 122b during a transient electrical event. In certain implementations, the second spacing d2 can be selected to lie in the range of approximately 1.5 μm to approximately 3 μm, for example at approximately 2.75 μm, and the third spacing d3 can be selected to lie in the range of approximately 1.5 μm to approximately 3 μm, for example at approximately 2.5 μm. However, other dimensions can readily be determined by a person skilled in the art.

[0123] A fourth spacing d4 was used to determine a distance between an edge of the first n-doped active surface 125a and an edge of the first n-tub 124a opposite the first p-tub 122ato be designated. The fourth spacing d4 can be dimensioned to contribute to the resistance of the fifth resistor. 115 to control, and to help achieve penetration onto the substrate 121 to prevent this during a transient electrical event. In certain implementations, the fourth spacing d4 can be selected to lie in the range of approximately 1.5 μm to approximately 3 μm, for example, at approximately 2.5 μm. However, other dimensions can readily be determined by a person skilled in the art.

[0124] A fifth spacing d5 was used to determine a distance between an edge of the first p-doped active surface. 123a and an edge of the first p-tub 122a opposite the first n-tub 124a to be designated. The fifth spacing d5 can be dimensioned to contribute to reducing the resistance of the fifth resistor. 115to control, and to help achieve penetration onto the substrate 121 to prevent damage during a transient electrical event. In certain implementations, the fifth spacing d5 can be selected to lie in the range of approximately 1.5 μm to approximately 3 μm, for example, at approximately 2.5 μm. However, other dimensions can readily be determined by a person skilled in the art.

[0125] A sixth spacing d6 was used to create a distance between the first p-tub 122a and the first n-tub 124a to be designated. The sixth spacing d6 can be increased to increase the breakdown voltage of the protective device. 120 on the substrate 121 to increase, which can help prevent the device from 120 is damaged or current enters the substrate 121The sixth spacing d6 is injected when the device is subjected to relatively high signaling conditions. In certain implementations, the sixth spacing d6 can be selected to lie in the range of approximately 0 μm to approximately 2 μm, for example, at approximately 1 μm. However, other dimensions can readily be determined by a person skilled in the art.

[0126] A seventh spacing d7 was used to determine a distance between an edge of the first n-tub. 124a and an edge of the n-doped insulating layer 129 to be designated. In certain implementations, the seventh spacing d7 can be selected to lie in the range from approximately 0 μm (aligned) to approximately 2.5 μm, for example at approximately 2.25 μm. However, other dimensions can readily be determined by a person skilled in the art.

[0127] An eighth spacing d8, which determines the width of the second n-tub 104bThis can be represented based on a desired holding voltage characteristic of the bidirectional bipolar transistor. 103 The eighth spacing d8 can be selected for certain implementations to fall within the range of approximately 8 μm to approximately 40 μm, for example, at approximately 25 μm. However, other dimensions can easily be determined by a person skilled in the art.

[0128] A ninth spacing d9 was used to determine a distance between an edge of the second p-tub 122b and an edge of the second shallow n-tub 127b to describe, which is based on a desired holding voltage characteristic of the bidirectional bipolar transistor 103The ninth spacing d9 is selected for certain implementations to lie in the range from approximately 0 μm (closest) to approximately 2 μm, for example at approximately 0.8 μm. However, other dimensions can easily be determined by a person skilled in the art.

[0129] In one embodiment, the protective device 120 The protective device has a tripping voltage of approximately ±30–60 V and a holding voltage in the range of ±20–55 V. 120 may be suitable for certain implementations of tertiary protective devices 43a , 43b out of Fig. 2 to function.

[0130] The n- and p-doped wells used to form the protective devices can function as blocking junctions, providing effective resistances that can help achieve a desired holding voltage. In certain implementations, the n-wells can exhibit peak doping concentrations in the range of approximately 10 16 Donors / cm 3 up to about 10 18 Donors / cm 3 , for example approximately 7 × 10 17 Donors / cm 3 and exhibit a transition depth in the range of approximately 3 μm to approximately 5.5 μm, for example 3.4 μm. Furthermore, the p-wells can achieve a peak doping concentration in the range of approximately 10 in certain reactions. 16 Donors / cm 3 up to about 10 18 Donors / cm 3 , for example approximately 9 × 10 17 Donors / cm 3and exhibit a transition depth in the range of approximately 3 μm to approximately 5.5 μm, for example, approximately 3.5 μm. However, a person skilled in this field will readily observe different doping levels and transition depths.

[0131] Fig. 8A is a schematic perspective view of a protective device 140 , which is the protection circuit 100 out of Fig. 6 according to another embodiment. The protective device 140 The substrate includes 121 , first to fourth p-tubs 122a until 122d , first to fourth p-doped active surfaces 123a until 123d , first to third n-tubs 124a until 124c , first to fourth n-doped active surfaces 125a until 125d , the second shallow n-tub 127b , first to fourth shallow p-tubs 145a until 145d , the oxide areas 128 and the n-doped insulating layer 129The protective device 140 can be used as secondary protective devices 42a , 42b out of Fig. 2 to function. As further explained below with reference to Fig. 8B is discussed, the protective device 140 Furthermore, in certain implementations, they may be configured to act as the primary protective devices. 41a , 41b out of Fig. 2 to function.

[0132] The protective device 140 out of Fig. 8A can be used similarly to the protective device 120 out of Fig. 7A to Fig. It should be 7B. In contrast to the protective device. 120 out of Fig. 7A to Fig. 7B, which are the first and third shallow n-tubs 127a , 127c and the first and second deep p-tubs 126a , 126b The protective device includes 140 out of Fig. 8A, however, does not include these structures. Instead, these structures were omitted to create the first shallow p-tub. 145a below the second p-doped active area 123b , the second shallow p-tub 145b below the second n-doped active area 123c , the third shallow p-tub 145c below the third n-doped active area 125c and the fourth shallow p-tub 145d below the third p-doped active area 123c to include. By configuring the protective device in this way 140 out of Fig. 8A can be used to determine the amplification of the perpendicular NPN bipolar transistor structures (see, for example, the first and second NPN bipolar transistors). 104 , 105 out of Fig. 7B) reduce and the holding voltage of the protective device 140 in relation to the protective device 120 out of Fig. 7A and Fig. 7B further increase. For example, the first to fourth shallow p-tubs 145a until 145d to contribute to the holding voltage of the protective device 140 to increase the current gain of the first and second NPN bipolar transistors 104 , 105 in the protective device 140 is reduced.

[0133] Although Fig. 8A represents a configuration in which the first and third flat n-tubs 127a , 127c The protective device may be omitted. 120 In certain implementations, they may be adapted to accommodate the first and third shallow n-tubs. 127a , 127c out of Fig. 7A and Fig. 7B to include. For example, the first and third shallow n-tubs can be 127a , 127c in reactions where a higher doping concentration is desired in the isolation structure, which is contained in the first and third n-wells 124a, 124c is formed. Increasing the doping concentration in the insulating structure can help reduce substrate injection when the protective device is in use. 120 is activated.

[0134] In one embodiment, the width W2 of the island areas 125b1 in the range of approximately 1 μm to approximately 2.5 μm, for example at approximately 1.5 μm. However, other implementations are possible. For example, the width W2 can be increased in certain implementations to enhance the effect of the NPN bipolar transistors and reduce the holding voltage.

[0135] Fig. 8B is a schematic perspective view of a protective device 150 , which is the protection circuit 100 out of Fig. 6 according to another embodiment. The protective device 150 The substrate includes 121 , first to sixth p-tubs 122a until 122f, first to sixth p-doped active surfaces 123a until 123f , first to fifth n-tubs 124a until 124e , first to sixth n-doped active areas 125a until 125f , the second shallow n-tub 127b , first to fourth shallow p-tubs 145a until 145d , the oxide areas 128 and the n-doped insulating layer 129 The protective device 150 depicts an example of a protective device intended for use as the primary protective device. 41a until 41b out of Fig. 2 is suitable.

[0136] The protective device 150 out of Fig. 8B can be used similarly to the protective device 140 be those previously referring to Fig. 8A was described, except that the second and third p-doped active surfaces 123b , 123c and the second and third n-doped active areas 125b , 125cwere arranged in a different configuration. For example, instead of the second and third p-doped active surfaces 123b , 123c made of elongated parts 123b1 , 123c1 and the preceding parts 123b2 , 123c2 to form and the second and third n-doped active surfaces 125b , 125c from island parts 125b1 , 125c1 to form, were used in the protective device 150 out of Fig. 8B the second and third p-doped active surfaces 123b , 123c and the second and third n-doped active areas 125b , 125c each is formed from channels that extend parallel to each other in the X-direction. This configuration of the second and third p-doped active surfaces 123b , 123c and the second and third n-doped active areas 125b , 125ccan be used to determine the trip and holding voltages of the protective device 150 out of Fig. 8B in relation to the protective device 140 out of Fig. to reduce 8A, which helps to ensure that the protective device 150 It exhibits protective characteristics suitable for functioning as a primary protective device. In certain implementations, the protective device 150 configured to have a holding voltage suitable for operation as a primary protective device by adjusting the width d8 from Fig. 7B is controlled to a value suitable for achieving the desired holding voltage.

[0137] Furthermore, in contrast to the protective device, it includes 140 out of Fig. 8A the protective device 150 out of Fig. 8B also the fifth and sixth p-tubs 122e , 122f , the fifth and sixth p-doped active areas 123e ,123f , the fourth and fifth n-tubs 124d , 124e and the fifth and sixth n-doped active areas 125e , 125f As in Fig. Figure 8B shows the fourth n-tub. 124d on one side of the first p-tub 122a opposite the first n-tub 124a arranged, and the fifth n-tub 124e is on one side of the fourth p-tub 122d opposite the third n-tub 124c arranged. In addition, the fifth p-tub is 122e on one side of the fourth n-tub 124d opposite the first p-tub 122a arranged, and the sixth p-tub 122f is on one side of the fifth n-tub 124e opposite the fourth p-tub 122d arranged. Furthermore, the fifth and sixth p-doped active surfaces are 123e , 123f each in the fifth and sixth p-tubs 122e , 122farranged, and the fifth and sixth n-doped active surfaces 125e , 125f are located in the fourth and fifth n-tubs, respectively 124d , 124e arranged. In the configuration shown, the n-doped insulating layer is 129 below the first to third n-tubs 124a until 124c , below the second and third p-tubs 122b , 122c and below part of the fourth and fifth n-tubs 124d , 124e arranged. In addition, the fifth and sixth p-tubs are 122e , 122f each of the fourth and fifth n-tubs 124d , 124e spaced apart, so that the fifth p-tub 122e not to the fourth n-tub 124d bumps into, and so that the sixth p-tub 122f not to the fifth n-tub 124e It initiates. However, other implementations are possible.

[0138] The fourth and fifth n-tubs 124d , 124eand the fifth and sixth n-doped active areas 125e , 125f can function as the first insulating structure to protect the protective device 150 opposite the substrate 121 to isolate, and the fifth and sixth p-tubs 122e , 122f and the fifth and sixth p-doped active areas 123e , 123f can function as a second insulating structure to protect the protective device 150 opposite the substrate 121 to isolate. For example, in a ring-shaped configuration, the fourth and fifth n-tubs can be isolated. 124d , 124e and the fifth and sixth n-doped active areas 125e , 125f function as the first insulating ring, and the fifth and sixth p-tubs 122e , 122f and the fifth and sixth p-doped active areas 123e , 123f can function as a second insulating ring. Since the protective device 150Since it can function as a primary protective device configured to handle a relatively high current, the inclusion of one or more insulating rings can help reduce the amount of charge entering the substrate. 121 is injected, which helps to prevent a latch-up.

[0139] Although the protective device 150 out of Fig. Figure 8B shows how they form the fourth and fifth n-tubs 124d , 124e , the fifth and sixth n-doped active areas 125e , 125f , the fifth and sixth p-tubs 122e , 122f and the fifth and sixth p-doped active areas 123e , 123f includes, and the protective device 140 out of Fig. 8A is shown without including these structures; the protective device 140 out of Fig. 8A may need to be adapted in certain implementations to include these structures. For example, the protective device 140 out of Fig. 8A These structures are designed to help reduce the amount of charge that enters the substrate during a transient electrical event. 141 is injected.

[0140] Fig. 9A is a schematic top view of a protective device 160 according to one embodiment. The protective device 160 depicts an example of a protective device intended for use as the primary protective device. 41a , 41b out of Fig. 2 is suitable. The protective device 160 However, it can also be configured to function as other protective devices, such as secondary protective devices. The protective device 160 includes first to fourth contact surfaces 161a until 161d , first to sixth p-tubs162a until 162f , first and second n-tubs 164a , 164b and the n-doped insulating layer 169 Although only certain structures of the protective device 160 in Fig. 9A shown, the protective device 160 Other structures include, such as contacts and metallization, oxide regions, active surfaces, shallow wells and / or deep wells. The person skilled in the art will understand that these details are omitted for clarity in Fig. 9A are omitted.

[0141] As in Fig. As shown in 9A, the second to fifth p-tubs were 162b until 162e as non-adjacent islands in the first n-tub 164a arranged. The first contact surface 161a was about the second p-tub 162b formed, the second contact surface 161b was about the third p-tub 162c formed, the third contact surface 161c was about the fourth p-tub162d formed and the fourth contact surface 161d was via the fifth p-tub 162e formed. In addition, the second p-tub was 162a configured as the first ring, forming the first n-tub 164a surrounds and abuts them. Furthermore, the second n-tub was 164b configured as a second ring, which forms the first p-tub 162a surrounds and abuts them. In addition, the sixth p-tub was 162f configured as a third ring, which forms the first p-tub 162a surrounds it, but does not touch it. The n-doped insulating layer 169 was below the first n-tub 164a , the first to fifth p-tubs 162a until 162e and below part of the second n-tub 164b arranged. Although Fig. While 9A represents a specific configuration of a protective device, other implementations are possible, such as ring-shaped and circular circuit arrangements, to adapt the device configuration to the requirements for an arrangement at the chip level, metallization and packaging.

[0142] The protective device 160 can be configured to provide protection by attaching the protective device to the first to fourth contact surfaces 161a until 161d connects. For example, in an implementation, the first and third contact surfaces are 161a , 161c Energy-deep contact surfaces, and the second and fourth contact surfaces 161b , 161d These are high-energy contact surfaces, and the protective device 160 is used to provide protection against overvoltage and undervoltage conditions received between the high-energy and low-energy contact surfaces. Although Fig. 9A represents an implementation in which the protective device 160 Configured to protect four contact surfaces, the protective device can 160 It can be configured to protect more or fewer contact surfaces. In certain implementations, the first and third contact surfaces are protected. 161a , 161c connected to a common energy-deep contact surface, and the second and fourth contact surfaces 161b , 161d are connected to a common high-energy contact surface.

[0143] The protective device 160 out of Fig. 9A is an example of a ring-shaped implementation of the protective device. 150 out of Fig. 8B off. For example, the first n-tub can 164a out of Fig. 9A the first to third n-tubs 124a until 124c out of Fig. 8B correspond, and the second n-tub 164b out of Fig. 9A can handle the fourth and fifth n-tubs 124d, 124e out of Fig. 8B corresponds. In addition, the first p-tub can 162a out of Fig. 9A the first and fourth p-tubs 122a , 122d out of Fig. 8B correspond to the second and fourth p-tubs 162b , 162d out of Fig. 9A can be used in the second p-tub 122b out of Fig. 8B correspond to the third and fifth p-tubs 162c , 162e out of Fig. 9A can access the third p-tub 122c out of Fig. 8B correspond, and the sixth p-tub 162f out of Fig. 9A can access the fifth and sixth p-tubs 122e , 122f out of Fig. 8B. Furthermore, the n-doped insulating layer can 169 out of Fig. 9A of the n-doped insulating layer 129 out of Fig. 8B corresponds.

[0144] As previously described, the correspondence between the structures of the protective device must be ensured. 160 out of Fig. 9A and the protective device 150 out of Fig. 8B is not a one-to-one match. For example, the second n-tub may not 164b out of Fig. 9A be a ring that forms the first p-tub 162a surrounds, and can therefore be considered both the fourth and the fifth n-tub 122d , 122e out of Fig. 8B function. Configuring one or more trays as rings can help improve the current handling capacity of the device and / or reduce the device's footprint. Furthermore, certain structures of the protective device can 160 out of Fig. 9A are implemented as substructures that are electrically connected to each other to form a corresponding structure in the protective device. 150 out of Fig. 8B to form. For example, the second and fourth p-tubs can be used. 162b , 162d out of Fig. 9A are electrically connected to each other to form a second p-tub.122b out of Fig. 8B to function. Implementing certain basins using substructures connected electrically in parallel can help control the size and / or electrical characteristics of a protective device. The person skilled in the art will understand that numerous configurations are possible, and that Fig. 9A represents one of many possible implementations.

[0145] In one embodiment, the space requirement of the protective device 160 a width WDx1, which is in the range of approximately 200 μm to approximately 300 μm, for example at approximately 250 μm, and the protective device 160The finger has a length WDy1 in the range of approximately 180 μm to approximately 300 μm, for example, approximately 230 μm. Furthermore, the finger width Wfx1 is in the range of approximately 120 μm to approximately 250 μm, for example, approximately 150 μm, and the finger length Lfy1 is in the range of approximately 2 μm to approximately 8 μm, for example, approximately 5 μm. However, a person skilled in the art will readily determine other dimensions.

[0146] Fig. 9B is an enlarged partial top view of an implementation of the protective device. 160 out of Fig. 9A. The top view shows part of the protective device. 160 in the case 9B out of Fig. 9A. The illustrated part of the protective device comprises the first n-tub. 164a and the second and third p-tubs 162b , 162c out of Fig. 9A. In addition, the part of the protective device was annotated to identify the second p-doped active area. 123band the second n-doped active area 125b in the second p-tub 162b and the third p-doped active surfaces 123c and the third n-doped active area 125c in the third p-tub 162c to show additional details of the second and third p-doped active surfaces. 123b , 123c and the second and third n-doped active areas 125b , 125c can, as before, with reference to Fig. 8B will be described.

[0147] Although Fig. 9B an implementation of part of the protective device 160 out of Fig. 9A shows that the protective device can 160 be arranged differently. For example, in one embodiment, the part of the protective device 160 in the case 9B out of Fig. 9A similar to the part of the protective device that is in Fig. 10B is shown, which is described in more detail below.

[0148] Fig. 10A is a schematic top-down view of a protective device. 180 according to another embodiment. The protective device 180 depicts an example of a protective device that can be used as the secondary protective devices. 42a , 42b out of Fig. 2 is suitable. The protective device 180 However, it can also be configured to function as other protective devices, such as tertiary protective devices. The protective device 180 includes the first to fourth contact surfaces 161a until 161d , the first to fifth p-tubs 162a until 162e , the first n-tub 164a and the n-doped insulating layer 169 Although only certain structures of the protective device 180 in Fig. 10A are shown, the protective device 180Other structures include, such as contacts and metallization, oxide areas, active surfaces, shallow wells and / or deep wells.

[0149] The protective device 180 out of Fig. 10A is similar to the protective device 160 out of Fig. 9A, except that the protective device 180 out of Fig. 10A not the second n-tub 164b and the sixth p-tub 162f It includes. Furthermore, in the configuration shown, the n-doped insulating layer is also included. 129 below the second to fifth p-tubs 162b – 162e and below part of the first n-tub 164a arranged.

[0150] The protective device 180 out of Fig. 10A provides an example of an implementation of the protective device. 140 out of Fig. 8A off. For example, the first n-tub can 164a out of Fig. 10A the first to third n-tubs 124a until 124cout of Fig. 8A corresponds to the first p-tub 162a out of Fig. 10A can handle the first and fourth p-tubs 122a , 122d out of Fig. 8A correspond to the second and fourth p-tubs 162b , 162d out of Fig. 10A can be used in the second p-tub 122b out of Fig. 8A correspond to the third and fifth p-tubs 162c , 162e out of Fig. 10A can be used in the third p-tub 122c out of Fig. 8A correspond, and the n-doped insulating layer 169 out of Fig. 10A can be applied to the n-doped insulating layer 129 out of Fig. 8A corresponds.

[0151] In one embodiment, where the protective device 180 It is configured to function as a secondary protective device, the space requirement of the protective device 180a width WDx2, which is in the range of approximately 180 μm to approximately 250 μm, for example at approximately 200 μm, and the protective device 160 The finger has a length WDy2 in the range of approximately 130 μm to approximately 200 μm, for example, approximately 160 μm. In certain reactions, the finger width Wfx2 is in the range of approximately 120 μm to approximately 250 μm, for example, approximately 150 μm, and the finger length Lfy2 is in the range of approximately 1.2 μm to approximately 4 μm, for example, approximately 1.8 μm. However, a person skilled in the art will readily determine other dimensions.

[0152] In another embodiment, where the protective device 180 It is configured to function as a tertiary protective device, the space requirement of the protective device 180 a width WDx2, which is in the range of approximately 60 μm to approximately 140 μm, for example at approximately 90 μm, and the protective device160 The finger has a length WDy2 in the range of approximately 110 μm to approximately 160 μm, for example, approximately 120 μm. Furthermore, the finger width Wfx2 is in the range of approximately 50 μm to approximately 100 μm, for example, approximately 75 μm, and the finger length Lfy2 is in the range of approximately 1.1 μm to approximately 2 μm, for example, approximately 1.2 μm. However, a person skilled in the art will readily determine other dimensions.

[0153] Fig. 10B is an enlarged partial top view of an implementation of the protective device 180 out of Fig. 10A. The top view shows part of the protective device. 180 in the case 10B out of Fig. 10A. The illustrated part of the protective device comprises the first n-tub. 164a and the second and third p-tubs 162b , 162c out of Fig. 10A. In addition, the part of the protective device was annotated to identify the second p-doped active area. 123b and the second n-doped active area 125b in the second p-tub 162b and the third p-doped active area 123c and the third n-doped active area 125c in the third p-tub 162c to show additional details of the second and third p-doped active surfaces. 123b , 123c and the second and third n-doped active areas 125b , 125c can, as before, with reference to Fig. 8A will be described.

[0154] Although Fig. 10B an implementation of part of the protective device 180 out of Fig. 10A indicates the protective device 180 be arranged differently. For example, in one embodiment, the part of the protective device 180 in the case 10B out of Fig. 10A similar to the part of the in Fig. Protective device shown in 9B.

[0155] In the embodiments described above, the protective devices can comprise layers, regions, and / or basins containing n-doped or p-doped dopants. In other embodiments, the doping characteristics of all layers, regions, and basins of the protective devices can be the opposite of those described and shown in the embodiments above, and the same principles and advantages can still apply to the other embodiments. For example, a supplementary version of the protective devices made of Fig. 7A to Fig. 9C can be formed using an n-doped substrate or using a p-doped substrate on which an n-doped epitaxial layer is formed. In such embodiments, the n-doped insulating layer 129The p-doped insulating layer is replaced, and the n-wells and p-wells of the protective device can each be replaced by p-wells and n-wells, respectively. Furthermore, the n-doped active areas and the p-doped active areas can each be replaced by p-doped active areas and n-doped active areas, respectively. Applications

[0156] Devices employing the methods described above can be implemented in various high-performance electronic devices and interface applications operating under harsh electrical conditions. Examples of such electronic devices include, but are not limited to, consumer electronics, consumer electronics components, electronic test equipment, and highly rugged industrial and automotive applications. Examples of electronic devices may also include optical network circuitry or other communication network circuits.Electronic consumer products can include, without limitation, a motor vehicle, a vehicle engine handling controller, a transmission controller, a seatbelt controller, an anti-lock braking system controller, a camcorder, a camera, a digital camera, a portable memory chip, a washing machine, a dryer, a washer-dryer, a copier, a fax machine, a scanner, a multifunction peripheral device, etc. Furthermore, the electronic device can include unfinished products, including those for industrial, medical, and automotive applications.

[0157] The foregoing description and the claims may refer to elements or features as being “connected” or “coupled” to one another. As used herein, and unless expressly stated otherwise, a “connected” means that an element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically. Likewise, and unless expressly stated otherwise, a “coupled” means that an element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically. Thus, although the various diagrams shown in the figures represent exemplary arrangements of elements and components, an actual embodiment may include additional intervening elements, devices, features, or components (provided that the functionality of the depicted circuits is not adversely affected).

[0158] Although the present invention has been described in terms of certain embodiments, other embodiments that are apparent to a person skilled in the art, including embodiments that do not provide all the features and advantages set forth herein, also fall within the scope of the present invention. Furthermore, the various embodiments described above can be combined to provide further embodiments. In addition, certain features shown in connection with one embodiment can also be integrated into other embodiments. Accordingly, the scope of the present invention is defined only with reference to the accompanying claims. QUOTES INCLUDED IN THE DESCRIPTION

[0159] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited non-patent literature

[0160] AEC-Q100

[0032] AEC-Q100 N

[0039] Standards IEC-61000-4-2

[0039] Standards IEC-61000-4-2

[0044] Standards ISO-7633-3

[0044] AEC-Q100

[0044] Standards IEC-61000-4-2

[0049]

Claims

[1] Device ( 1 ) comprehensive: a first contact surface; an internal circuit ( 3 ) which is electrically connected to the first contact surface; and a protection system configured to protect the internal circuitry from transient electrical events, wherein the protection system includes the following: a first primary protection device that is electrically connected to the first contact surface and configured to have a first holding voltage and provide bidirectional blocking voltage protection; A first secondary protection device electrically connected to the first contact surface and configured to have a second holding voltage and provide bidirectional blocking voltage protection, wherein the first primary protection device has a current handling capacity greater than the current handling capacity of the first secondary protection device, and wherein the first secondary protection device is smaller than the first primary protection device and has a turn-on speed faster than the turn-on speed of the first primary protection device, and wherein the magnitude of the first holding voltage is less than the magnitude of the second holding voltage, such that when the first primary protection device is activated, the activated first primary protection device blocks a voltage across the first contact surface and reduces current flow through the first secondary protection device. [2] Device according to claim 1, wherein the internal circuit comprises a high-voltage, double-diffusion, metal-oxide-semiconductor (DMOS) transistor in series with a resistor and a reverse junction, wherein the resistor and the reverse junction comprise a plurality of segments, and the DMOS transistor comprises a plurality of fingers, wherein each of the plurality of segments is independently electrically connected in series with a corresponding of the plurality of fingers to provide an independent finger pre-connection. [3] Device according to claim 1, wherein the protection system further comprises: a first tertiary protection device that is electrically connected to the first contact surface and configured to have a third holding voltage and provide bidirectional blocking voltage protection, wherein the current handling capacity of the first secondary protection device is greater than the current handling capacity of the first tertiary protection device, and wherein the first tertiary protection device has a switching-on speed that is faster than the switching-on speed of the first primary protection device, and wherein the magnitude of the first holding voltage is less than the magnitude of the third holding voltage, such that when the first primary protection device has been activated, the activated first primary protection device blocks the voltage of the first contact surface to reduce current flow through the tertiary protection device. [4] Device according to claim 3, wherein the primary protection device is optimized to provide robustness against system-level electrostatic discharge (ESD) and system-level electromagnetic interference (EMI) by providing a discharge path from the first contact surface to an energy-deep contact surface. [5] Device according to claim 1, wherein the first contact surface is a signal contact surface, and wherein the device further comprises an energy-low contact surface and an energy-high contact surface, wherein the first primary protective device is electrically connected between the signal contact surface and the energy-low contact surface, and the first secondary protective device is electrically connected between the signal contact surface and the energy-high contact surface. [6] Device according to claim 5, further comprising a second primary protective device which is electrically connected between the high-energy contact surface and the low-energy contact surface. [7] Device according to claim 6, further comprising a first capacitor electrically connected between the signal contact surface and the energy-low contact surface, and a second capacitor electrically connected between the energy-high contact surface and the energy-low contact surface. [8] Device according to claim 5, further comprising a resistor which is electrically connected between an output of the internal circuit and the first contact surface, wherein the resistor has a resistance which is selected to be in the range of approximately 0.5 Ω to approximately 1 kΩ. [9] Device according to claim 5, further comprising a voltage regulator and a second secondary protection circuit, wherein the voltage regulator is configured to generate a regulated voltage supply for the internal circuit, and wherein the second secondary protection circuit is electrically connected between the energy-high contact surface and the regulated voltage supply. [10] Device according to claim 1, wherein the first primary protection device comprises a first bidirectional bipolar transistor, and the first secondary protection device comprises a second bidirectional bipolar transistor, wherein the first bidirectional bipolar transistor is configured to control the first holding voltage, and the second bidirectional bipolar transistor is configured to control the second holding voltage, and wherein the first and second bidirectional bipolar transistors are each configured to provide dual-polarity reverse voltage protection. [11] Device according to claim 1, wherein the first primary protection device and the first secondary protection device are configured to provide asymmetric bidirectional blocking voltage protection. [12] Device ( 1 ), comprehensive: a contact surface; an internal circuit ( 3), which is electrically connected to the contact surface; and a protection system configured to protect the internal circuitry from transient electrical events, wherein the protection system includes the following: a means of providing primary bidirectional blocking voltage protection, which is electrically connected to the contact surface and configured to exhibit an initial holding voltage; A means for providing secondary bidirectional blocking voltage protection, electrically connected to the contact surface and configured to have a second holding voltage, wherein the primary protection means has a current handling capacity greater than the current handling capacity of the secondary protection means, and wherein the secondary protection means has a switching-on rate faster than the switching-on rate of the primary protection means, and wherein the magnitude of the first holding voltage is less than the magnitude of the second holding voltage, such that when the primary bidirectional blocking voltage protection means has been activated, the activated primary protection means blocks a voltage across the contact surface to reduce current flow through the secondary protection means. [13] Device ( 1 ) comprehensive: a substrate; a contact surface; a primary protection device electrically connected to the contact surface and configured to exhibit a first holding voltage, the primary protection device comprising a first bidirectional bipolar transistor located in the substrate; and a secondary protection device electrically connected to the contact surface and configured to have a second holding voltage, wherein the secondary protection device comprises a second bidirectional bipolar transistor arranged in the substrate, wherein the primary protection device has a current handling capacity greater than the current handling capacity of the secondary protection device, and wherein the secondary protection device has a switching-on speed faster than the switching-on speed of the primary protection device, and wherein the magnitude of the first holding voltage is less than the magnitude of the second holding voltage, such that when the primary protection device has been activated, the activated primary protection device blocks a voltage across the contact area to reduce current flow through the secondary protection device. [14] Device according to claim 13, further comprising: a first central trough arranged in the substrate, wherein the first central trough has a doping of a first type; a first trough arranged in the substrate next to the first central trough, the first trough having a doping of a second type opposite to the first type; and a second well arranged in the substrate next to the first central well and on the opposite side of the first central well relative to the first well, wherein the second well has a second-type doping, wherein the first central well, the first well and the second well are configured to function as a first bidirectional bipolar transistor. [15] Device according to claim 14, further comprising a flat trough of the second type formed in the first central trough. [16] Device according to claim 14, further comprising a first annular ring of the second type and an insulating layer of the second type, wherein the first annular ring surrounds the first central trough, the first trough and the second trough, and wherein the insulating layer is arranged below the first central trough, the first trough, the second trough and at least a part of the first annular ring, and wherein the first annular ring and the insulating layer are not electrically grounded. [17] Device according to claim 16, further comprising a second annular ring of the first type and a third annular ring of the second type, wherein the second annular ring is configured to surround the first annular ring, and wherein the third annular ring is configured to surround the second annular ring, and wherein the insulating layer is configured to extend below at least a part of the second annular ring. [18] Device according to claim 14, further comprising: a first active region and a second active region arranged in the first trough, the second active region having a part located further away from the first central trough than at least a part of the first active region, the first active region having a doping of the first kind, and the second active region having a doping of the second kind; and a third active area and a fourth active area arranged in the second trough, wherein the fourth active area has a part that is further away from the first central trough than at least a part of the third active area, wherein the third active area has a doping of the first kind, and wherein the fourth active area has a doping of the second kind. [19] Device according to claim 18, wherein the first, second, third and fourth active areas comprise a plurality of channels which are generally oriented in one direction. [20] Device according to claim 18, further comprising flat trough areas of the first type below the first, second, third and fourth active areas. [21] Device according to claim 14, wherein the first type is p-doped and the second type is n-doped. [22] Device according to claim 14, further comprising: a second central trough arranged in the substrate, wherein the second central trough has a doping of the first type; a third trough arranged in the substrate next to the second central trough, the third trough having a doping of the second type; and a second well arranged in the substrate next to the second central well and on the opposite side of the second central well relative to the third well, wherein the fourth well has a doping of the second kind, wherein the second central well, the third well and the fourth well are configured to function as the second bidirectional bipolar transistor. [23] Device according to claim 22, further comprising: a first active region and a second active region arranged in the third well, the second active region having a part located further away from the second central well than at least a part of the first active region, the first active region having a doping of the first kind, and the second active region having a doping of the second kind; and a third active area and a fourth active area arranged in the fourth trough, wherein the fourth active area has a part that is further away from the second central trough than at least a part of the third active area, wherein the third active area has a doping of the first kind, and wherein the fourth active area has a doping of the second kind. [24] Device according to claim 23, wherein the first active area comprises a plurality of first separate areas which are generally oriented in one direction, wherein the part of the second active area forms a first elongated part extending in the direction such that the plurality of first separate areas is inserted between the first elongated part and the second central trough when viewed from above, wherein the third active area comprises a multitude of second separate areas, which are generally oriented in the direction, wherein the part of the fourth active area forms a second elongated part which extends in such a direction that the plurality of second separate areas is inserted between the second elongated part and the second central trough when viewed from above.

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