Device for a mixed-signal interface circuit arrangement and associated methods

Abstract

Integrated circuit, IC (10), comprising: several pads (120, 125) designed for sending or receiving signals; and several mixed-signal interface blocks (100), wherein each mixed-signal interface block (100) in the multiple mixed-signal interface blocks (100) is coupled to a corresponding pad (120, 125) in the multiple pads (120, 125); wherein each mixed-signal interface block in the multiple mixed-signal interface blocks is designed to be configurable to provide a selected functionality independently of other mixed-signal interface blocks (100) in the multiple mixed-signal interface blocks (100);wherein at least one mixed-signal interface block (100) in the multiple mixed-signal interface blocks (100) is designed to provide analog-to-digital conversion functionality for converting an analog signal received at the corresponding pad (120, 125) into digital data for supplying the digital data to a digital core (110) of the IC (10).

Description

Cross-reference to related registrations

[0001] The present application claims priority and incorporates, for all purposes by reference in its entirety, the preliminary US patent application No. 61 / 666,837 filed on June 30, 2012, entitled “APPARATUS FOR MIXED SIGNAL INTERFACE CIRCUITRY AND ASSOCIATED METHODS”, attorney file number SILA344P1. Technical field

[0002] The disclosed concepts relate generally to an electronic circuit arrangement and in particular to a device for an interface circuit arrangement or blocks in integrated mixed-signal circuits (IC – Integrated Circuits) and associated methods. General state of the art

[0003] Modern integrated circuits (ICs) have helped to integrate electronic circuit designs, reducing size and cost. Consequently, modern ICs can form complex circuit designs and systems. For example, almost all the functionality of a system can be implemented using only one or a handful of ICs.

[0004] The result is a growing trend to manufacture circuit designs and systems with increasing reliability, flexibility, and functionality. Such circuit designs and systems can receive and process both analog and digital signals, and can output both analog and digital signals. Consequently, such circuit designs and systems can contain both analog and digital circuits that are interconnected. Brief description of the invention

[0005] An integrated circuit (IC) according to one embodiment contains several pads designed for sending or receiving signals. The IC further contains several mixed-signal interface blocks, each mixed-signal interface block being coupled to a corresponding pad within the multiple mixed-signal interface blocks. Each mixed-signal interface block within the multiple mixed-signal interface blocks is designed to be configurable to provide selected functionality independently of other mixed-signal interface blocks within the multiple mixed-signal interface blocks.

[0006] According to another embodiment, a mixed-signal IC comprises multiple pads designed for sending or receiving signals and multiple mixed-signal interface blocks. Each mixed-signal interface block within the multiple mixed-signal interface blocks is coupled to and permanently associated with a corresponding pad within the multiple pads. Each mixed-signal interface block within the multiple mixed-signal interface blocks is designed to be configurable to provide at least one selected function from a set of functions to couple the corresponding pad within the multiple pads to a core circuit arrangement of the mixed-signal IC.

[0007] According to yet another embodiment, a method for processing signals using a mixer-signal IC includes communicating signals to a circuit arrangement outside the mixer-signal IC using multiple pads of the mixer-signal IC and supplying the communicated signals to multiple mixer-signal interface blocks, wherein each mixer-signal interface block in the multiple mixer-signal interface blocks is coupled to a corresponding pad in the multiple pads. The method further includes processing the communicated signals using the multiple mixer-signal interface blocks, wherein the processing by each mixer-signal interface block in the multiple mixer-signal interface blocks can be performed independently of the processing by other mixer-signal interface blocks in the multiple mixer-signal interface blocks. Brief description of the drawings

[0008] The accompanying drawings illustrate only exemplary embodiments and should therefore not be considered as limiting the scope of protection. The person skilled in the art understands that the disclosed concepts lend themselves to other, equally effective embodiments. In the drawings, numerical designations used in more than one drawing denote the same, similar, or equivalent functionality, the same, similar, or equivalent components, or blocks.

[0009] Fig. Figure 1 shows a block diagram of an IC containing several mixed signal interface blocks (MSIBs) according to an exemplary embodiment.

[0010] Fig. Figure 2 shows a block diagram of an exemplary embodiment that includes a general embodiment of an MSIB.

[0011] Fig. Figure 3 shows an MSIB configured to provide digital output functionality according to an exemplary implementation.

[0012] Fig. Figure 4 shows an MSIB configured to provide digital input functionality according to an exemplary implementation.

[0013] The Fig. 5– Fig. Figure 6 shows an MSIB configured to provide voltage-to-digital-to-analog conversion (DAW) functionality according to an exemplary embodiment.

[0014] Fig. Figure 7 shows an MSIB configured to provide power DAW functionality according to an exemplary implementation.

[0015] Fig. Figure 8 shows an MSIB configured to provide analog-to-digital conversion functionality for a data register (Successive Approximation Register – SAR) according to an exemplary implementation.

[0016] Fig. Figure 9 shows an MSIB configured to provide ratiometric SAR-ADW functionality according to an exemplary implementation.

[0017] Fig. Figure 10 shows an MSIB configured to provide Delta-Sigma-ADW functionality according to an example implementation.

[0018] Fig. Figure 11 shows an MSIB configured to provide differential comparator functionality according to an exemplary embodiment.

[0019] Fig. Figure 12 shows an MSIB configured to provide the functionality of a comparator with a programmable threshold according to an exemplary embodiment.

[0020] Fig. Figure 13 shows a delta-sigma modulator for an MSIB according to an exemplary embodiment.

[0021] The Fig. 14– Fig. Figure 16 shows block diagrams of exemplary embodiments, which include general embodiments of MSIBs. Detailed description

[0022] The disclosed concepts generally relate to the provision of an interface circuit arrangement in ICs. In particular, the disclosed concepts provide devices and methods for mixed-signal interfaces in ICs.

[0023] In illustrative embodiments, the mixed-signal interfaces can be implemented as mixed-signal interface blocks (MSIBs) or circuit arrangements. In some embodiments, one or more MSIBs can be associated with, coupled to, configured to, or designed to operate with a corresponding pad of the IC. In some embodiments, several MSIBs can be permanently assigned to corresponding pads of the IC (that is, each such MSIB is coupled to, configured to, or designed to operate with a corresponding pad).

[0024] MSIBs offer a multitude of advantages. Their use enables flexible interface circuitry for communication or coupling within the IC and / or with external circuitry. Furthermore, MSIBs allow for system-on-a-chip (SoC) designs without requiring the designer to consider analog interfaces or engage in resource allocation (e.g., by including a relatively large number of MSIBs with a one-to-one correspondence between the number of MSIBs and the corresponding pads on the IC).

[0025] From a chip assembly perspective, the use of MSIBs simplifies chip assembly because analog interfaces are typically local, while higher-level interfaces are digital and therefore suitable for automation. (The reference voltage, which usually remains an analog global signal, and the power grid are two exceptions.)

[0026] From a product portfolio perspective, the availability of MSIBs, which can be configured in a variety of modes, allows a single product to cover a wide range of applications. The functions included in MSIBs (ADW, DAW, comparator, in various modes, plus digital input and output functionality) can be assigned arbitrarily.

[0027] Furthermore, an application that makes relatively heavy or extensive use of ADWs and sensor interfaces (temperature, pressure, etc.) can be served by the same IC containing MSIBs as one that makes relatively heavy or extensive use of DAWs, such as biasing an optical module. This same IC using MSIBs could be configured to detect and generate digital signals with unusual or atypical logic thresholds in comparator mode. Some applications incorporate a mixture of all the above functions, which is unique to each system or specifies them. Without limitation, examples include biasing sensors with a DAW, reading sensors with an ADW, controlling an analog input with a potentiometer, monitoring temperature for safety purposes, acquiring impedance values ​​on a line using DAWs and ADWs, and so on.

[0028] Such systems are sometimes controlled by software and / or firmware. If hardware resources are limited and shared, the scheduling of various tasks, such as the one described above, may need to be considered and could impose constraints. For example, a worst-case scenario may need to be determined, and relatively complex software may need to be written and maintained to meet the bandwidth specifications for each measurement while still ensuring that relatively high-priority measurements are performed and analyzed quickly enough (for example, safety-related tasks). If the system's complexity increases, the architecture, operations, and specifications would need to be re-analyzed and likely redesigned.

[0029] The relative abundance of independent, concurrently operating, and dedicated resources for IC pads provided by MSIBs simplifies this task. Each measurement can be scheduled independently and / or simultaneously, without regard to other measurements taking place on the chip at the same time (e.g., other measurements performed by MSIBs for other IC pads). A non-time-critical signal, such as battery monitoring, does not need to find an unused time slot between higher-priority events, and time-critical events (e.g., overcurrent protection) would not be delayed due to the scheduling of a less critical measurement.

[0030] Consequently, all desired data is made available in memory at the expected time, and a controller, host, or other circuit can take actions based on the available data. A more complex system that handles more tasks does not need to consider when and how each individual measurement is taken. Existing routines can be easily integrated at the top level. The impact of having a relatively abundant supply of configurable MSIB resources at each pin on the simplicity of software development would be an additional benefit.

[0031] Fig. Figure 1 shows a block diagram of an IC 10 , which includes several MSIBs 100 according to one embodiment. The MSIBs are connected to a core circuit arrangement. 105 The IC is coupled and they communicate with it.

[0032] The core circuit arrangement 105 of the IC 10can a digital core 110 represent the MSIBs 100 can be used with pads (not shown), and in some embodiments with MSIBs 100 (may be included) of the IC 10 As noted above, some MSIBs may be hard-coupled to corresponding pads of the IC (i.e., each such MSIB is coupled to, configured to, or designed to work with a corresponding pad). In such arrangements, the hard-coupled MSIBs can be configured, used, reused, etc., independently of and / or simultaneously with other pads (whether hard-coupled or not).

[0033] In some embodiments, the corresponding MSIBs can be used. 100 coupled pads are a subset of all pads of the IC 10 In other words, in such embodiments, some pads may have corresponding, permanently assigned MSIBs. 100on, while some pads may not have this feature.

[0034] In some embodiments, the pads of the IC can 10 They may be coupled to pins of the IC package. In some embodiments, the pads may be coupled to another circuit arrangement via bond wires, as might be the case for multi-chip modules (MCMs).

[0035] In exemplary implementations, the digital core 105 of the IC 10A digital computer contains a variety of digital circuits or blocks, as the average person understands. Examples include one or more controllers, microcontrollers, processors, field-programmable gate arrays (FPGAs), programmable controllers, and the like. Other examples include memory (e.g., random-access memory, read-only memory, flash memory (or generally non-volatile memory)), a one-time programmable (OTP) circuit arrangement, and the like.

[0036] For further examples of a circuit arrangement in the core (digital core or other core circuit arrangement) of the IC 10These include counters, timers, controllers, clock and timing circuit arrangements (including distribution circuit arrangements), arithmetic circuit arrangements (e.g., adders, subtractors, multipliers, dividers), general and programmable logic circuit arrangements, gates, registers, flip-flops, multiplexers (MUXs), demultiplexers (DeMUXs), and the like. The examples given above serve only as illustrative embodiments. As the person skilled in the art can understand, many embodiments are possible that include one or more of the above circuit arrangements, types of circuit arrangements, and / or other circuit arrangements.

[0037] The MSIBs 100 provide a flexible mechanism for coupling between the core circuit arrangement 105 (and / or the digital core) 110 ) of the IC 10 and the pads and / or pins of the IC 10coupled circuit arrangement. In exemplary embodiments, some MSIBs may be used. 100 Provide analog interfaces (in Fig. 1 (designated with “A”), to provide analog input and / or output functionality. The analog interfaces can accommodate a variety of physical signaling methods, such as voltage or current levels, etc., as a person skilled in the art understands.

[0038] In some embodiments, some MSIBs may 100 provide digital interfaces (in Fig. 1 (designated with “D”), to provide digital input and / or output functionality, for example, digital interfaces that use common, standard, or conventional signal levels, protocols, etc. Examples include transistor-transistor logic (TTL), CMOS (complementary metal oxide semiconductor) logic, and the like. As the average person skilled in the art understands, a variety of other digital signaling methods and protocols are possible in exemplary implementations.

[0039] In some embodiments, some MSIBs may 100 provide digital interfaces (in Fig. 1 (designated with “D”), to provide digital input and / or output functionality, for example, digital interfaces that use unusual, proprietary, or uncommon signal levels, protocols, etc. For example, such MSIBs 100Consider a logic signaling method where a binary 0 corresponds to 2 volts and a binary 1 to 3 volts, in order to reduce the signal swing and thus increase the operating speed. As the average person understands, a variety of other digital signaling methods and protocols are possible in exemplary implementations.

[0040] In some embodiments, some MSIBs may 100 GPIO interfaces (General Purpose Input Output) (e.g. the “digital interface” 115 in Fig. 1) provide. In some embodiments, the GPIOs can provide analog interface capability. In some embodiments, the GPIOs can provide analog interface capability, whereas in other embodiments, the GPIOs can provide both analog and digital interface capability. In exemplary embodiments, the GPIOs can have fixed, programmable, or configurable functionality, as desired and as understood by the average person skilled in the art.

[0041] Fig. Figure 2 shows a block diagram of an exemplary embodiment, which is a general embodiment of an MSIB. 100 It contains. In the embodiment shown, the MSIB couples to two pads. 120 and 125 (labeled “pad1” and “pad2”) of the IC. The MSIB 100 can provide analog and / or digital two-pin capability. The in Fig. The embodiment shown in Figure 2 can provide current and voltage mode DAWs, a fast low-resolution SAR ADW and a slow high-resolution Delta-Sigma ADW, a variety of comparator modes, ratiometric conversion for ADWs and DAWs, and full GPIO functionality.

[0042] An analog signal at pad2 125 will be connected to the RMUX 130 (a reference multiplex unit) is applied, along with a reference voltage Vref* and a supply voltage Vdd. The output signal of the RMUX 130 is used as a reference voltage at a V-DAW 135 (Voltage-to-Digital-to-Analog Converter). In response to the reference voltage and the control signals from a data register state machine (SAR FSM) and a DAW register, the V-DAW delivers 135 an output voltage at a first MUX 140 , which sends an input signal to the comparator 145 delivers. The first MUX 140 also receives the signal at pad2125 as another input signal.

[0043] The DAW register 150 controls the output of the V-DAW circuit 135 according to the equation Vout = Vref·D / 2 N , where N represents the length of the digital DAW data word. During DAW operation, data can be fed into the DAW register via the MSIB's data input line. 150 to be written.

[0044] In response to unseen control signals, which may be derived, for example, from the configuration register that receives MSIB configuration data in response to a clock signal “clk”, the first MUX provides 140 one of its input signals to the comparator 145 The output signal of the comparator 145 controls a second MUX 155 to, which provides the output data of the MSIB.

[0045] A second input of the comparator 145 receives an output signal from a third MUX 160 The third MUX160 It receives its input signals from several blocks, including the Schmitt trigger circuit. 165 , the (referred to as “integrator + I-source”) integrator / current source 170 -circuit, a follow-stop circuit 175 and the signal at pad1 120 In response to unseen control signals, which may be derived from the configuration register, for example, the third MUX provides 160 one of its input signals to the comparator 145 .

[0046] The Schmitt trigger 165 In exemplary embodiments, it can have programmable hysteresis levels. The integrator / power source 170 can be used together with other circuit arrangements of the MSIB 100 It can be used as a component for a delta-sigma converter. The follow-hold circuit 175 can be used to implement a SAR circuit.

[0047] Instead of receiving input signals, pad1 can 120 be configured to provide output signals. In particular, pad1 can 120 the output signal of a voltage buffer 180 , a transconductor 185 or a digital output driver 190 supply. The voltage buffer 180 Provides buffering of the output voltage of the V-DAW circuit 135 The transconductor 185 can the output voltage of the V-DAW circuit 135 convert it into an electric current.

[0048] The digital output driver 190 can provide buffer or control functionality and can be accessed from the configuration register 195 or from the input data of the MSIB 100 Information received at pad2 125 deliver. The digital output driver 190 It may feature a programmable slew rate, drive strength, open drain, or standard CMOS capabilities.

[0049] The configuration register 195 receives configuration information or data for the MSIB 100 The configuration information or data can be obtained from a desired source, such as the core circuit layout. 105 of the IC 10 be received. The configuration register 195 The configuration information or data can be used to configure one or more blocks or circuits in the MSIB 100 Configure, program, or adapt as desired, depending on the implementation for a given specification or situation. Thus, the configuration register can be used. 195 In exemplary implementations, an activation, deactivation, parameter setting (e.g., hysteresis, slew rate, etc.) for one or more blocks or circuits of the MSIB. 100 provide.

[0050] As the average professional understands, the structure and functionality described above are exemplary, and many other configurations, structures, and functions can be implemented. For example, some of the blocks or circuits of the MSIB can be 100 In some embodiments, they may have programmable functionality and / or parameters (see above for examples). As another example, all or almost all blocks (e.g., with the exception of the MUXs) in the MSIB may have programmable functionality and / or parameters (see above for examples). 100 exhibit programmable functionality and / or parameters.

[0051] As noted above, the support in Fig. 2 MSIBs shown 100 a variety of functions or operating modes. Some of the circuit layout blocks in the MSIB 100These blocks may not be used for a particular function or operating mode. Such blocks may be shown in some of the accompanying drawings with outlines and connections in a lighter gray (or dashed or other notation). The follow-stop block is shown as an example. 175 , the comparator 145 etc. not for implementing the below regarding the in Fig. The functionality described in the circuit shown in section 3 is used.

[0052] Fig. 3 shows an MSIB 100 , which is configured to provide digital output functionality according to an exemplary implementation. In this mode, pad1 provides 120 as a digital output signal from the digital output driver 190 received signal. The digital output driver 190 buffers, processes, or conditions as the data input of the MSIB 100received signal and delivers the resulting signal to pad1 120 .

[0053] In some embodiments, the MSIB 100 Use digital CMOS circuits (e.g., standard CMOS circuits) to implement a fast CMOS output with strong drive, as desired. In some embodiments, the MSIB can 100 Options for disabling the CMOS output pull-up (e.g., to provide open drain functionality), programming the drive strength, controlling the slew rate, etc., as desired and as the average professional understands.

[0054] Fig. 4 shows an MSIB 100 , which is configured to provide digital input functionality according to an exemplary implementation. In this mode, pad1 receives 120 an input signal and delivers the signal to the Schmitt trigger. 165 The Schmitt trigger 165The input signal is processed and the resulting signal is delivered as the data output signal of the MSIB. 100 via the second MUX 155 .

[0055] Thus, pad1 can 120 In this mode, it should be configured similarly to a standard or typical digital input pad. The Schmitt trigger 165 implements input buffering with optional hysteresis, which is controlled via the configuration register. 195 can be programmed. The functionality of the MSIB 100 In this mode, it can be configured or programmed for CMOS, TTL, or other input levels as desired.

[0056] Fig. 5 shows an MSIB 100 , which is configured to provide voltage DAW functionality according to an exemplary embodiment. In this mode, the data to be converted to the analog domain can be, for example, by a digital circuit in the core circuit arrangement. 105(or 110 ) of the IC 10 to the data input of the MSIB 100 will be delivered.

[0057] The V-DAW circuit 135 generates an analog voltage level according to the received digital code or signal and the V-DAW circuit. 135 supplied reference voltage. The digital code or digital signal is received via the MSIB data input. 100 to the DAW register 150 delivered. The DAW register 150 provides a register function and delivers the digital code or digital signal to the V-DAW circuit. 135 .

[0058] The V-DAW circuit 135 delivers the analog voltage resulting from the digital-to-analog conversion to the voltage buffer. 180 The voltage buffer 180 buffers the analog voltage and delivers the resulting signal to pad1 120, which in turn delivers the buffered signal to another circuit arrangement not shown. The voltage buffer 180 can have programmable parameters (e.g., control stability) and can be connected to the MSIB 100 the ability to control pad1 120 in the presence of relatively large capacitive loads or relatively small resistive loads (or both).

[0059] The one connected to the V-DAW circuit 135 The supplied reference voltage can be a bandgap voltage generated on the chip, the supply voltage of the MSIB 100 or one on pad2 125 The supplied external reference will be the RMUX. 130 provides one of those voltages as the reference voltage for the V-DAW circuit. 135 . Fig. Figure 6 shows the situation in which one is connected to pad2 125 supplied voltage as that supplied to the V-DAW circuit 135 The supplied reference voltage is used.

[0060] Fig. 7 shows an MSIB100 , which is configured to provide power DAW functionality according to an exemplary implementation. The MSIB 100 In this mode, it works similarly to the voltage DAW functionality described above. The output voltage of the V-DAW circuit 135 However, it is connected to the transconductor circuit 185 delivered.

[0061] The transconductor circuit 185 converts the signal through the V-DAW circuit. 135 The supplied analog voltage is converted into an analog current. The resulting analog current is then applied to pad1. 120 and thus ultimately to each one on pad1 120 A coupled circuit is supplied. Analogous to the voltage DAW mode, the reference signal for the V-DAW circuit can be used. 135 , as described in detail above, via the RMUX 130 be elected.

[0062] Fig. 8 shows an MSIB 100, which is configured to provide SAR-ADW functionality according to an exemplary implementation. In this mode, a device is connected to pad1 125 received analog signal to the follow-hold circuit 175 delivered. The follow-hold circuit 175 samples the input signal.

[0063] The outcome of the follow-hold circuit 175 is connected to an input of the comparator 145 coupled. The output signal of the comparator 145 is applied to the Successive Approximation FSM 200 delivered. A successive approximation technique is used to generate digital data for the final control of the V-DAW circuit. 135 To provide, as the average professional understands. In short, for each bit position from a high value to a low value, the bit at that position is set, then the output of the comparator is checked. 145 The bit is reset if the comparator145 sends back a signal indicating a level that is "too high". This process is repeated for each bit position. During the ADW operation of the MSIB 100 The SAR-FSM controls the DAW register 150 according to this process.

[0064] The outcome of the successive approximation FSM 200 feeds the input of the DAW register 150 The output of the DAW register 150 is connected to the input of the V-DAW circuit 135 delivered. The output of the V-DAW circuit 135 controls the second input of the comparator 145 Thus, the comparator is used. 145 A feedback circuit is formed around it.

[0065] The outcome of the comparator 145 It delivers digital data resulting from the analog-to-digital conversion. This digital data can be accessed via the data output signals / lines of the MSIB. 100 to desired destinations such as the core circuit arrangement 105(or 110 ) will be delivered.

[0066] Although Fig. 8 the V-DAW circuit 135 While it shows that it receives the supply voltage Vdd as a reference voltage, other configurations are possible in exemplary embodiments. For example, as described above, external or internal voltages can be used as the reference voltage for the V-DAW circuit. 135 be used.

[0067] Fig. 9 shows an MSIB 100 , which is configured to provide ratiometric SAR-ADW functionality according to an exemplary implementation. In this operating mode, a connection to pad2 can be used. 125 The external reference voltage provided enables the ratiometric SAR-ADW functionality to be implemented. In this mode, the analog-to-digital conversion occurs as described above, except that a voltage is applied to pad2. 125 received analog signal as the reference voltage to the V-DAW circuit 135 will be delivered.

[0068] Consequently, the output digital data represents the voltage ratio at pad1 120 to pad2 135 The existing voltage is represented. The ratiometric ADW provides additional functionality for the MSIB. 100 Examples include measuring impedance, potentiometer position, resistance dividers, etc., as the average professional understands.

[0069] Fig. 10 shows an MSIB 100 , which is configured to provide delta-sigma ADW functionality according to an exemplary implementation. In this mode, a high-precision slow analog-to-digital conversion can be implemented.

[0070] The output signal of the integrator / current source circuit 170 controls one input of the comparator 145 The reference voltage Vref* controls another input of the comparator. 145 The outcome of the comparator 145provides a feedback signal to the integrator / current source circuit 170 .

[0071] The analog voltage to be converted into the digital domain is measured at pad1 125 received. The integrator / power source circuit 170 integrates the difference between the input voltage as it is converted into a current to be integrated, and one provided by the output signal of the comparator. 145 controlled feedback current source.

[0072] As noted above, the MSIB contains 100 In exemplary embodiments, a transconductor circuit and a voltage buffer are used. In some embodiments, the transconductor circuit or the voltage buffer can be used to provide the functionality of the integrator (instead of using a separate integrator).

[0073] Fig. 11 shows an MSIB 100, which is configured to provide differential comparator functionality according to an exemplary embodiment. In this mode, pad1 120 and pad2 125 Signals applied to or received from the respective inputs of the comparator 145 delivered. Consequently, the comparator can 145 act as a difference comparator. (As the average expert understands, grounding pad1 provides 120 or from pad2 125 (Of course, a single-ended comparator function instead of a difference comparator function.)

[0074] Fig. 12 shows an MSIB 100 , which is configured to provide the functionality of a comparator with a programmable threshold, according to an exemplary implementation. In this operating mode, a connection to pad1 is established. 120 applied voltage to an input of the comparator 145 coupled. The output of the V-DAW circuit 135is connected to a second input of the comparator 145 coupled. The output voltage of the V-DAW circuit 135 provides the threshold voltage for the comparator 145 .

[0075] The comparator 145 compares the voltages applied to its inputs and provides a resulting output voltage via the data outputs of the MSIB 100 For example, if the input voltage at pad1 120 the output voltage of the V-DAW circuit 135 If the voltage exceeds the threshold voltage, the comparator can 145 Provide a binary logical 1 as output data.

[0076] The one connected to the V-DAW circuit 135 The applied reference voltage programs the threshold of the comparator. 145As mentioned, a choice of reference voltages can be used. For example, in some embodiments, the supply voltage or an external voltage (applied to pad2) can be used instead of Vref* to program the comparator threshold voltage.

[0077] In some embodiments, the comparator can 145 Hysteresis can be added. One way to implement hysteresis is by adjusting the V-DAW reference level according to the previous comparator decision. 145For example, if the preceding decision was a binary logic 1, the threshold of the V-DAW circuit can be lowered so that a noticeable change in input voltage is required to return the comparator output to a binary logic 0. This operation can be useful in a variety of situations, as the average professional understands. Examples include implementing a digital interface with unusual or arbitrary signaling levels or protocols.

[0078] In some embodiments, a window comparator can be implemented as desired. A window comparator can be implemented by a subsequent test against two different levels (corresponding to the window thresholds) and the decision as to whether the input signal lies inside or outside the window.

[0079] Fig. Figure 13 shows a delta-sigma modulator for an MSIB 100according to one exemplary embodiment. The modulator can be used in MSIBs. 100 can be used to provide the functionality of a delta-sigma modulator.

[0080] In the illustrated embodiment, the delta-sigma modulator is implemented by integrating currents through a capacitor. The input voltage is converted into a current using a transconductor circuit. The reference voltage is also converted into a current using a transconductor circuit to generate a signal Iref.

[0081] The voltage across the capacitor is monitored by a comparator. The comparator's output signal controls the feedback in the circuit. Specifically, signals D and Db are generated from the comparator's output signal. These signals control switches that couple the current Iref to the capacitor and an input of the comparator. The comparator's output signal can be supplied to various circuit configurations, such as the core circuitry of the integrated circuit.

[0082] In some implementations, the full functionality of the MSIB described above is not available. 100 It may not be required or specified. In exemplary implementations, the functionality of the MSIBs may be limited. 100to adapt to a given situation, a desired implementation, or a given set of specifications. The following description provides details of some implementation examples with functionality that differs from that in the MSIB. 100 in Fig. 2 provided reduced or different from it.

[0083] Fig. Figure 14 shows a block diagram of an exemplary embodiment, which is a general embodiment of an MSIB. 100 with a contrast to the in Fig. 2 MSIBs shown 100 contains reduced functionality. In particular, the one in Fig. 14 MSIB shown provides analog or digital GPIO functionality for a pad (as “pad1”) 120 (designated). Various blocks and circuits are similar to the corresponding blocks and circuits in Fig. 2, described in detail above.

[0084] The exemplary embodiment in Fig. Version 14 supports various operating modes such as current and voltage mode DAWs, a relatively fast and relatively low-resolution SAR ADW, a relatively slow and relatively high-resolution SAR ADW, a comparator with a programmable threshold, and full GPIO functionality. The implementation in Fig. 14 does not support differential or ratiometric functions (because they use two input signals, consequently two pads).

[0085] Fig. Figure 15 shows a block diagram of an exemplary embodiment, which is a general embodiment of an MSIB. 100 with a compared to the one in Fig. 2 MSIBs shown 100 It contains reduced functionality compared to the MSIB. 100 from Fig. 2 is supplied by the MSIB 100 in Fig. 15 a simpler analog / digital GPIO functionality.

[0086] In particular, the mixed-signal interface blocks 100 from Fig. 15 removed the current DAW and delta-sigma ADW modes to save semiconductor area (and thus costs). The MSIB 100 from Fig. 15 delivers full digital functionality as well as full comparison functionality, an ADW mode and a DAW mode.

[0087] Fig. Figure 16 shows a block diagram of an exemplary embodiment, which is a general embodiment of an MSIB. 100 with a compared to the one in Fig. 2 MSIBs shown 100 It contains reduced functionality. In particular, the MSIB provides 100 in Fig. 16 an analog GPIO functionality.

[0088] The MSIB 100 in Fig. The MSIB lacks differential and ratiometric modes, special digital circuits, and current DAW and delta-sigma ADW modes (to reduce area and thus costs). However, it retains comparator, DAW, and ADW functionality. 100It can receive and control digital signals in response to analog signals.

[0089] In exemplary implementations, some or all of the MSIBs may be used. 100 around a pad circuit arrangement (e.g., a protection circuit arrangement against electrostatic discharge (ESD), etc.). In other embodiments, MSIBs can 100 The MSIBs are implemented separately from the pad circuit arrangement and coupled to the respective pads or pad circuit arrangements via suitable coupling mechanisms, as the average person skilled in the art understands. As mentioned above, in some embodiments multiple MSIBs are possible. 100 a corresponding plurality of pads of the IC 10 be permanently assigned.

[0090] As described above, the MSIBs deliver 100According to exemplary embodiments, MSIBs provide a flexible mechanism for providing coupling and signal processing functions in mixed-signal circuits and systems. By giving designers the ability to include and implement desired functions, MSIBs offer 100 a way to weigh a desired functionality against semiconductor chip size, power consumption, manufacturing complexity, testing complexity, costs, etc.

[0091] Referring to the figures, the average person will notice that the various blocks shown may primarily represent the conceptual functions and signal flow. The actual circuit implementation may or may not include separately identifiable hardware for the different functional blocks and may or may not use the specific circuit arrangement shown. For example, the functionality of different blocks can be combined into a single circuit block as desired. Furthermore, the functionality of a single block can be implemented in multiple circuit blocks, if desired. The choice of circuit implementation depends on various factors, such as specific design and performance specifications for a given implementation.Other modifications and alternative embodiments, in addition to those described here, will be apparent to the person skilled in the art. Accordingly, this description teaches the person skilled in the art how to implement the disclosed concepts and is to be interpreted as illustrative only.

[0092] The forms and embodiments shown and described should be considered illustrative embodiments. A person skilled in the art can make various modifications regarding the shape, size, and arrangement of parts without deviating from the scope of protection of the disclosed concepts in this document. For example, a person skilled in the art can substitute equivalent elements for those shown and described herein. Furthermore, a person skilled in the art can use certain features of the disclosed concepts independently of other features without deviating from the scope of protection of the disclosed concepts.

Claims

[1] Integrated circuit (IC) comprising the following: several pads designed for sending or receiving signals; and multiple mixed-signal interface blocks, each mixed-signal interface block in the multiple mixed-signal interface blocks being coupled to a corresponding pad in the multiple pads; wherein each mixed signal interface block in the multiple mixed signal interface blocks is designed to be configurable to provide a chosen functionality independently of other mixed signal interface blocks in the multiple mixed signal interface blocks. [2] IC according to claim 1, wherein at least one mixed-signal interface block in the multiple mixed-signal interface blocks is designed to provide digital input functionality. [3] IC according to claim 1 or 2, wherein at least one mixed-signal interface block in the multiple mixed-signal interface blocks is designed to provide a digital output functionality. [4] IC according to one of the preceding claims, wherein at least one mixed-signal interface block in the multiple mixed-signal interface blocks is designed to provide a general-purpose input / output (GPIO) functionality. [5] IC according to one of the preceding claims, wherein at least one mixed-signal interface block in the multiple mixed-signal interface blocks is designed to provide digital-to-analog conversion functionality. [6] IC according to one of the preceding claims, wherein at least one mixed-signal interface block in the multiple mixed-signal interface blocks is designed to provide analog-to-digital conversion functionality. [7] IC according to one of the preceding claims, wherein each mixed-signal interface block in the multiple mixed-signal interface blocks is coupled to a core circuit arrangement of the IC. [8] IC according to any of the preceding claims, wherein the multiple pads comprise a subset of pads of the IC. [9] Integrated mixed-signal circuit (IC) comprising the following: several pads designed for sending or receiving signals; and multiple mixing signal interface blocks, each mixing signal interface block in the multiple mixing signal interface blocks being coupled to a corresponding pad in the multiple pads and being permanently assigned to the corresponding pad in the multiple pads; wherein each mixed-signal interface block in the multiple mixed-signal interface blocks is designed to be configurable to provide at least one selected function from a set of functions for coupling the corresponding pad in the multiple pads to a core circuit arrangement of the mixed-signal IC. [10] Mix-signal IC according to claim 9, wherein each mix-signal interface block in the multiple mix-signal interface blocks is permanently assigned to the corresponding pad in the multiple pads to which the mix-signal interface block provides the at least one selected function. [11] Mixed-signal IC according to claim 9 or 10, wherein the set of functions includes digital input and digital output functionality. [12] Mixed-signal IC according to any one of claims 9 to 11, wherein the set of functions comprises an analog input and analog output functionality. [13] Mixed-signal IC according to any one of claims 9 to 12, wherein the set of functions includes an analog-to-digital conversion (ADW) functionality. [14] Mixed signal IC according to any one of claims 9 to 13, wherein the set of functions further comprises a digital-to-analog conversion (DAW) functionality. [15] Mixed-signal IC according to any one of claims 9 to 14, wherein the multiple pads comprise a subset of pads of the IC. [16] Method for processing signals using an integrated mixed-signal circuit (IC), the method comprising: Communicating signals with a circuit arrangement outside the mixer-signal IC using multiple pads of the mixer-signal IC; Supplying the communicated signals to multiple mixed-signal interface blocks, each mixed-signal interface block being coupled to a corresponding pad of the multiple pads within the multiple mixed-signal interface blocks; and Processing the communicated signals using the multiple mixed-signal interface blocks, wherein the processing by each mixed-signal interface block in the multiple mixed-signal interface blocks can be performed independently of the processing by other mixed-signal interface blocks in the multiple mixed-signal interface blocks. [17] Method according to claim 16, wherein the processing of the communicated signals using the multiple mixed-signal interface blocks further comprises performing an analog-to-digital conversion in some of the mixed-signal interface blocks. [18] Method according to claim 16 or 17, wherein the processing of the communicated signals using the multiple mixed-signal interface blocks further comprises performing a digital-to-analog conversion in some of the mixed-signal interface blocks. [19] Method according to any one of claims 16 to 18, further comprising configuring the processing by each mixed-signal interface block in the multiple mixed-signal interface blocks. [20] Method according to any one of claims 16 to 19, wherein each mixing signal interface block in the multiple mixing signal interface blocks is permanently assigned to a corresponding pad of multiple pads.

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