Charge flow frequency converter with fault indicator

Abstract

Converter device (2, 34) for converting a charge flow (4) into a frequency signal (23), comprising at least one integrator (5, 5a, 5b) and at least one comparator (16, 16a, 16b, 39a, 39b, 39c), wherein the at least one integrator (5, 5a, 5b) and the at least one comparator (16, 16a, 16b, 39a, 39b, 39c) are connected in series and the at least one comparator (16, 16a, 16b, 39a, 39b, 39c) outputs a signal (21) when an integrated charge flow is exceeded relative to a threshold voltage (19, 36, 37, 38), characterized by at least one frequency exceedance signal output device (29).

Description

[0001] The invention relates to a converter device for converting a charge flow into a frequency signal, which has at least one integrator and at least one comparator, wherein at least one integrator and at least one comparator are connected in series and the comparator outputs a signal when an integrated charge flow is exceeded relative to a threshold value.

[0002] Charge-flux-frequency converters are used when measuring a typically low-level electric charge flux. Such charge fluxes occur, for example, in particle accelerators (such as electron, proton, or ion accelerators, especially heavy-ion accelerators) or in particle detectors (for example, for dosimetry, measurement setups, and the like). The currents to be measured here are typically in the range of a few tens of fA to several hundred microamps. It is easy to see that at such low currents, "classical measurement methods," which rely, for example, on the voltage drop across a resistor or on the magnetic field generated by the current (such as moving-coil instruments), do not provide sufficient accuracy or even fail completely.

[0003] In some areas, however, precise measurement of a (particle) current (especially electron or ion currents with comparatively low current intensity) is required with high accuracy. This applies particularly to some research applications, but especially to the field of medical technology. Since particle accelerators are now used very successfully in medical technology (both electron and ion accelerators), there is a need for highly precise measuring instruments and methods that should nevertheless be as cost-effective as possible.

[0004] One way to measure such small electrical currents with high accuracy is to use charge-flux-frequency converters. In these converters, the charge flow is integrated into an integrator over a certain period of time. Once a certain charge has accumulated in the integrator, an output signal is generated, and the integrator is simultaneously reset to zero ("emptied") to be ready for a new measurement cycle. Since the frequency of the output signals corresponds to the incoming charge flow, the frequency of the output signal can be used as a measure of the charge flow.

[0005] Such charge-flow-frequency converters have been known for some time. One problem with these is that no charge flow can be measured during the integrator's "reset phase." This results in a certain measurement inaccuracy. In some fields of application (such as medical technology or some research accelerators), the associated measurement inaccuracy is unacceptable; in other fields, it is at least undesirable. Therefore, German patent application DE 198 41 308 A1 proposed the use of two parallel measurement branches, each with its own integrator. The two integrators are interconnected in such a way that the incoming charge flow is initially directed into the first branch.As soon as the first integrator branch reaches its threshold, it outputs a signal, switches the signal to be measured to the input of the other integrator branch, and then resets itself. Meanwhile, the second integrator branch fills up, and as soon as its threshold is reached, it outputs a signal, the circuit switches back to the first integrator branch, and the second integrator branch is reset. Since the other integrator branch takes over the measurement of the charge flow during the "dead time" of the first integrator branch being reset, the described undesirable dead time losses and thus measurement inaccuracies do not occur.

[0006] A problem with known charge-flow-frequency converters lies in their behavior under unexpectedly high charge flows. Often, these converters even display a "zero signal" at excessively high charge flows (meaning the frequency of the output signals drops to zero). This can lead to incorrect conclusions based on the measured value, potentially resulting in an overdose. This is particularly critical in medical applications.

[0007] Accordingly, there is a need for a charge-flow-frequency converter that outputs an error signal indicating the occurrence of a fault condition when the maximum charge flow that the converter can process is exceeded. Furthermore, the output of such a fault condition signal should be implemented in a particularly simple circuit design.

[0008] The object of the invention is therefore to propose a converter device for converting a charge flow into a frequency signal which is improved compared to converter devices for converting a charge flow into a frequency signal as known in the prior art.

[0009] The invention solves this problem.

[0010] It is proposed to equip a converter device for converting a charge flow into a frequency signal, comprising at least one integrator and at least one comparator, in which at least one integrator and at least one comparator are connected in series, and the comparator outputs a signal when an integrated charge flow is exceeded relative to a threshold value, with at least one frequency-over-signal output device. Typically, the currents to be measured, for example in particle accelerators or particle detectors, are in the range of a few tens of fA to several hundred microamperes, particularly between 100 fA and 130 µA. The converter device can be constructed from discrete components or as an integrated circuit (especially in an ASIC (application-specific integrated circuit)).It is also possible, of course, to achieve "partial integration" into an integrated circuit, meaning that while some discrete components remain, a preferably larger proportion of the components are integrated into the circuit. In principle, the greatest possible integration into an integrated circuit is advantageous. On the one hand, this can save costs, reduce the required installation space, generally allow the converter device to be supplied with less electrical energy, and, on the other hand, largely avoid charge losses (especially of the current being measured). The integrator is typically designed such that (parts of) the charge flow are directed into a capacitor. Preferably, the size of the capacitor can be changed to adapt the converter device to different currents.Switching between different capacitances can be done via hardware (for example, by switching external capacitances on or off), but also by changing the circuit configuration (using different input pins) or by appropriately programming an integrated circuit. Typical capacitance values ​​are in the range of 2.5 pF to 25 pF, so that with typical charge currents in the range of 100 fA to 130 µA, a charge resolution (the amount of charge required to output a pulse) and pulse frequency can be achieved that is advantageous for further processing. However, other capacities are also conceivable, such as in particular 1 pF, 2 pF, 3 pF, 4 pF, 5 pF, 6 pF, 7 pF, 8 pF, 9 pF or 10 pF as a lower limit and / or 10 pF, 20 pF, 30 pF, 40 pF, 50 pF, 60 pF, 70 pF, 80 pF, 90 pF or 100 pF as an upper limit.A particular advantage of the aforementioned capacitances is that they can be implemented relatively easily in an integrated component, which can offer corresponding benefits. The proposed capacitance values ​​are especially advantageous for integrated circuits because a beneficial compromise can be achieved. On the one hand, the capacitances are large enough that parasitic capacitances can generally be largely neglected during manufacturing; on the other hand, the capacitances are small enough to be manufactured economically on a semiconductor chip.It is advantageous if (in the case of "switchable" capacitance) a "capacitance dynamic" with a ratio of 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, 1:15, 1:20, 1:25, 1:30, 1:40, 1:50, or 1:100 is provided (where the aforementioned values ​​can represent both a lower and an upper limit of the interval). A "decadal division" (i.e., especially 1:10 or 1:100) is particularly advantageous because it is especially easy for humans to understand. This makes it possible to achieve a favorable compromise between simple construction on the one hand and maximum adaptability to different current intensities on the other. Typically, the integrator outputs a signal corresponding to the already accumulated charge. With a constant current, for example, a voltage output signal increases linearly over time.As soon as the output signal exceeds a certain value (threshold), an action is performed (preferably utilizing the comparator, which in particular compares the integrator's output value with the current threshold). This action can take various forms. Specifically, it is possible to output a pulsed signal (frequency signal as the output signal), reset the integrator ("charge clearing"), or adjust the threshold. Adjusting the threshold, in particular, allows for the generation of a comparatively high-frequency signal and, furthermore, increases measurement accuracy, especially by eliminating dead times.It is also possible to increase the threshold and only issue an output signal after multiple threshold increases (whereby an output signal is possible with each threshold adjustment or, for example, only when the threshold is reset). The threshold voltage can be provided by an external signal or an internally generated signal. The proposed frequency-overshoot signal output device can output a signal, in particular, when the incoming charge flow is so high that the converter device no longer has sufficient time to reset. This typically results in the output signal dropping to a "zero signal" (i.e., no more pulses, each indicating the input of a certain amount of charge to the integrator, are output).Accordingly, the measurement error increases in a manner that is usually unacceptable. Such a faulty signal is generally unacceptable, especially for medical applications. (The proposed behavior is particularly advantageous when two or more integrator branches are present, which will be discussed in more detail below; in this case, an excessive charge flow necessitates switching the integrator branch more frequently than the reset time of an integrator allows.) The output signal of the frequency overshoot signal device can, for example, be used as a type of error signal (in particular, a so-called "flag signal"), enabling, for instance, an emergency shutdown of the system for which the converter device is used, as its safe operation can no longer be guaranteed.Following such an emergency shutdown, it is possible, for example, to readjust the part of the system that generates the measurement signal (e.g., to adjust a particle beam to a lower particle fluence). Alternatively, the fault signal can be used to switch the transducer device to a lower sensitivity, either manually or automatically. This can be achieved, for example, by adding one or more capacitors to the transducer device. The output signal of the frequency overshoot signaling device can be used as a trigger signal for such a switchover.At the same time, it is possible that the frequency overshoot output signal is still used as an emergency shutdown signal, whereby in the event of a switch (especially an automatic switch) of the input sensitivity of the converter device, preferably no "permanent" emergency shutdown of the system occurs, but only a "temporary emergency shutdown" (i.e. a brief interruption of the particle beam application or the like).

[0011] It is proposed to design the converter device such that the frequency overshoot signal output device includes at least one fault indication comparator and / or a signal inversion device, the signal inversion device preferably being designed as an exclusive-OR logic gate. Initial tests have shown that the proposed design is particularly suitable for generating a fault signal in a simple yet effective manner, which can, for example, be used to implement an emergency shutdown.

[0012] It is further proposed to implement the converter device such that the fault indication comparator includes a comparator component, wherein preferably the inverting input of the comparator component is connected to a charge-flow reference signal and / or the non-inverting input of the comparator component is connected to an output signal of the integrator. The proposed circuit proves particularly advantageous for the function of the fault indication comparator, especially in combination. Comparator components have proven effective for measuring small currents or voltages and / or for comparing comparatively low voltages with reference voltages (for example, threshold voltages) (by appropriate input circuitry and, if necessary, appropriate feedback). In particular, comparator components can be implemented with particularly high impedance, so that the resulting leakage currents are particularly low.Such behavior is particularly advantageous for the application proposed here (measuring small charge flows). The comparator component can, in particular, measure the voltage (and compare it with a reference voltage or a threshold voltage, especially the charge flow reference voltage) that results from accumulation ("integration") in a capacitor. It is further preferred to use comparator components with MOSFET inputs, as these have particularly high impedance and are therefore particularly low-loss.

[0013] Preferably, the converter device is designed such that it has at least two integrators or integrator branches connected in parallel, which are alternately supplied with the charge flow. With such a design, it is particularly possible to prevent the dead time that occurs during the reset of an integrator (which is generally unavoidable due to the nature of the device; for example, due to the discharge of the capacitors) from leading to a deterioration of the measurement accuracy due to "loss of charge carriers to be measured." According to the proposed improvement, the charge flow during this dead time can be measured by the other integrator. This allows the measurement accuracy to be significantly increased in a simple manner.It is also quite possible, particularly over short time intervals, for both integrators to be supplied with a charge flow "simultaneously" (with each integrator receiving essentially half the charge flow in the case of two integrators) to make switching phases particularly advantageous and thereby, for example, further increase the measurement accuracy. However, it is equally possible to use only a single integrator or a single integrator branch. Such a converter setup is usually particularly simple and therefore particularly cost-effective. The loss of "measured charge flow" can be at least partially compensated for by, for example, "numerically balancing" the dead time with a correction factor. However, this is not a true measurement, but merely a kind of "simulation" in which charge carrier peaks, or...Short-term dropouts are not detected. It is conceivable that only one of the two integrator branches is equipped with the proposed frequency-overshoot signal output device. This reduces circuit complexity while still achieving good temporal resolution regarding the occurrence of a fault. However, it is preferred that two integrator branches (or a plurality of, preferably substantially all, particularly preferably all integrator branches) are equipped with a frequency-overshoot signal output device. In such a case, a particularly high level of reliability can be achieved, so that a fault (if it occurs) is detected particularly reliably and, in particular, very quickly. This prevents unwanted orImpermissible overdoses should be reduced to a particularly low level (which is generally essentially negligible).

[0014] Furthermore, it is proposed to design the converter device such that it includes at least one charge flow direction selection device, allowing the device to be selectively set to either a positive or a negative charge flow. This enables particularly versatile applicability of the proposed converter device. In particular, one and the same converter device can be used for different applications. This means that only a single converter device needs to be produced, regardless of whether positive or negative charge flows are to be measured. Due to the rapid changeover capability of the converter device, it is also possible to use it when alternating positive and negative charge flows need to be measured. The charge flow direction selection device can be implemented in various ways.For example, a fully automatic conversion is conceivable. However, it is also possible that the converter device, depending on the current polarity, must be supplied with current via a different input connection (whereby a switching device, which can be either external or internal, may be provided). In particular, it is also possible that switching to different current directions is achieved by programming the converter device, and any necessary switching is provided by internally provided switching elements.

[0015] Another possible configuration of the converter device arises when the charge flow direction selection device supplies the integrator and / or the comparator, preferably alternately, with one of two charge flow reference voltages. The charge flow reference voltages can differ in their magnitude and / or sign. Generally, it is advantageous for the charge flow reference voltages to differ primarily in their sign. This allows for approximately identical measurement behavior of the converter device for both positive and negative charge flows. Furthermore, it is fundamentally possible for the charge flow reference voltages to be provided by external components.However, it is also possible that the charge flow reference voltages are provided by the converter device itself, in particular by a part of the converter device that is designed in the form of an integrated circuit.

[0016] It is particularly advantageous if the charge flow direction selection device of the converter assembly includes at least one changeover switch. This allows the same charge flow reference voltages to be used for both the integrator and the comparator. These voltages are supplied to the integrator or the comparator as appropriate by means of the changeover switch. This advantageously reduces the number of reference voltages required, thus lowering the overall construction costs. The changeover switch can be operated either by mechanical contacts or by electronic switches.A "changeover switch device" is understood to mean, in particular, a device in which, in a first switching state, a first voltage is applied to the integrator and a second voltage to the comparator, while in a second switching state, a second voltage is applied to the integrator and a first voltage to the comparator.

[0017] Furthermore, it is proposed to design the converter device such that a preferably conditional signal inversion device is connected downstream of the comparator, which preferably acts inverting depending on the position of the charge flow direction selection device. The signal inversion device can, in particular, be designed as an exclusive-OR logic gate. It has been shown that with a conventional design of the converter device, especially when an output signal of an integrator is fed to a comparator and compared there with a charge flow reference voltage and / or a threshold voltage, the signal output logic of the converter device is (initially) different depending on whether a positive or a negative charge flow is measured. If a signal inversion device is switched on or off depending on the polarity of the measured charge flow,When the power supply is switched off, the output logic of the converter device can remain the same despite the different polarity of the charge flow. This is particularly advantageous for further processing of the signal output by the converter device. In particular, the converter device can then be used very easily as a "drop-in" solution.

[0018] It is further preferred that the integrator in the converter device includes an operational amplifier, and in particular that the charge-flow input signal is connected to the inverting input of the operational amplifier and / or the charge-flow reference voltage is connected to the non-inverting input of the operational amplifier. It is advantageous to place the integration capacitor in the negative feedback loop between the output and the inverting input of the operational amplifier. Operational amplifiers are differential amplifiers that exhibit very high gain and high input impedance. The proposed circuit configuration has proven particularly effective because the operational amplifier can serve to decouple the input from the integration signal. The input can be kept constant at the voltage specified via the non-inverting input.Accordingly, it makes sense to connect the non-inverting input to the charge-flow reference voltage. What has already been said about comparators and comparator components (high-impedance inputs, circuit options, characteristics, etc.) also applies largely by analogy to operational amplifiers. Therefore, the use of operational amplifiers proves advantageous in this context. In particular, the proposed circuit (especially when implemented in combination) has proven beneficial for generating the desired frequency output signal.

[0019] It is further proposed that the converter device be designed such that the comparator includes a comparator component and, in particular, that the output signal of the integrator is connected to the non-inverting input of the comparator component and / or a threshold voltage is connected to the inverting input of the comparator component. The threshold voltage can, in particular, be a threshold voltage generated by a digital-to-analog converter. The advantages of comparators or comparator components already described in connection with the integrator also apply analogously to the comparator(s) presented here. Accordingly, comparator components are also advantageous here. The proposed circuit (especially in combination) is particularly suitable for realizing the functionality of the converter device in a simple and effective manner.

[0020] It is further proposed that the output signal of the comparator and / or the output signal of the signal inversion device in the converter device be fed to a pulse shaping device. In this way, a defined pulse can be emitted each time a unit of charge flow has been delivered. The pulse shaping device can be used to feed a signal back into the converter device (for example, to switch the active integrator branch) or to reset an integrator.It is also possible that such a generated pulse signal serves to increase a threshold voltage at the comparator, so that before a reset of the integrator and / or a change of the integrator branch, the integrator in question "counts up several times" and in this way switching operations (and possibly also dead times) can be reduced, even if comparatively large charge flows have to be measured by the converter device.

[0021] According to a preferred embodiment, it is proposed to equip the converter device with a digital counter and / or a digital-to-analog converter, which can supply different reference voltages to the comparator, particularly depending on an output value of the comparator, preferably depending on a count value of the counter. In this way, the number of reset cycles for the integrators of the converter device can be reduced. This can, in particular, help to reduce dead times and measurement errors in the components of the converter device. Depending on the embodiment, a high frequency can still be output with comparatively low charge fluxes, so that a comparatively high sensitivity of the converter device can be achieved. In a design based on this proposal, the threshold voltage supplied to the comparator generally follows a kind of step-like sawtooth curve.At each upward step, a frequency pulse can be output (not only to the digital-to-analog converter or the digital counter, but also, in particular, to an output terminal of the converter device). A digital counter can be understood to be either a positive or negative counter. Preferably, it is a counter that, depending on an input signal or programming, can be used as both an upward and a downward counter. It is possible that the counter has a reset function (applying a reset signal).Additionally or alternatively, the counting device can also be equipped with an "overflow" function, such that after a certain number of counting steps have been completed, the counting device automatically returns to the beginning (for example, after 4 steps, after 8 steps, after 16 steps, after 32 steps, or the like).

[0022] Furthermore, it is proposed that the converter device be equipped with a digital-to-analog converter voltage signal input. Here, for example, programming can be used to specify after how many increasing steps the threshold voltage supplied to the comparator returns to zero. For instance, it can be specified that the threshold voltage returns to zero after four, eight, or sixteen increasing steps (with a switch to the other integrator branch, if available). Such (pre-programming) allows the converter device to be advantageously configured for different expected or measured input charge fluxes, thus enabling particularly versatile application.

[0023] It is further proposed to provide the converter device with a reset signal output device that resets one integrator and preferably activates another. With such a reset signal, the converter device can be specifically and controllably "internally controlled." In particular, the reset signal output device can be fed to input switches that direct the input charge flow to different integrator branches. Furthermore, the reset signal output device can effect the "reset" of an integrator and, optionally, also reset a digital-to-analog converter (which, in particular, provides a threshold signal for a comparator) or a digital counter to zero.

[0024] Furthermore, it is proposed that the converter device include at least one self-adjusting charge flow direction selection device. With such a particularly preferred design of the converter device, pre-programming of the converter device to determine whether a positive or negative charge flow is to be measured is usually unnecessary. With such a design, the converter device is particularly reliable and highly versatile (although it is of course possible to pre-program the converter device with a kind of "expected value"). In particular, in the case of multiple branches, one branch can communicate such an "expected value" to a subsequent branch in the "integration sequence".

[0025] The invention will now be explained in more detail using advantageous embodiments and with reference to the accompanying drawing. The drawing shows:

[0026] Fig. 1: A first embodiment of a converter core in a schematic block diagram;

[0027] Fig. 2: a second embodiment of a converter core in a schematic block diagram;

[0028] Fig. 3: an embodiment of a converter with two integrator branches and alternating branch control.

[0029] In Fig. 1 is a first conceivable embodiment of a converter core 2 shown, for example, for a charge flow-frequency converter 1 (Converter device for converting a charge flow into a frequency signal) with two parallel, alternately operated integrator branches 3a , 3b can be used. Even if such an operation involves two alternately operated integrator branches. 3a , 3bWhile the ability to largely eliminate measurement errors due to dead times is particularly advantageous, other uses of the converter core are nevertheless possible. 2 conceivable. The charge flow to be measured. 4 The actual integrator is connected via an input terminal (In). 5 supplied. The integrator 5 consists essentially of an operational amplifier 6 and a capacity 7a , 7b Furthermore, there is a reset switch. 8 intended to increase capacities 7a , 7b can be unloaded so that the integrator 5 is available for another measurement cycle. In the illustrated embodiment, the capacity is 7 in two partial capacities 7a , 7b divided, with one of the two partial capacities 7b via a switch 10can be activated as needed. For example, the first capacity (always used) is... 7a a capacitance of 2.5 pF. A capacitor connected in parallel to this is one controlled by the switch. 10 switchable second capacity 7b a capacitance of 22.5 pF is provided, so that the total capacity 7 the integrator 5 The capacitance can be adjusted between 2.5 pF and 25 pF. This switching action allows for different charge flows. 4 They can be measured with different resolutions (amount of charge required to generate an output pulse), with higher total capacitance being a factor to consider. 7 Naturally, the sensitivity of the integrator also varies. 5 reduced. In the exemplary embodiment shown here, the sensitivity of the converter core is 2 (which, in addition to the capacity, is also determined by the voltage swing of the integrator) 5 and the number of counting steps of the up and down counter 27is determined) at low capacity (only first capacity 7a switched on) 250 fC, whereas with larger capacity (second capacity) 7b (switched on) is 2.5 pC. From this and from the speed of the setup 2 In contrast, this essentially results in the maximum measuring current. 4 In the example shown, the maximum measuring current is... 4 13 µA or 130 µA. The minimum measuring current is determined by leakage currents, which are unavoidable in practical implementation. In the present setup, they are on the order of 100 fA. In the illustrated embodiment, the capacitance 7b through prior programming of the converter core 2 preset. In particular, the converter core shown here is 2 (together with other components) in the form of an integrated circuit (ASIC).

[0030] Furthermore, the integrator5 an input switch 9 to see with which the integrator 5 with the charge flow 4 can be connected to or disconnected from it. Such an input switch 9 is particularly necessary if the converter core 2 in a charge flow-frequency converter 1 with two integrator branches 3a , 3b is used. By alternately switching the input switch. 9 Then the other integrator branch can 3a , 3b can be used when the “represented” converter core 2 by closing the reset switch 8 is reset, resulting in a dead time during which, due to the nature of the process, no measurement can be taken.

[0031] The charge flow 4 will be, how to Fig. 1 can be seen from the inverting input 11 of the operational amplifier 6fed into the non-inverting input. 12 of the operational amplifier 6 in the integrator 5 In contrast, a first reference voltage is used. 13a (V max ) or a second reference voltage 13b (V min ) supplied (“charge flux reference signal”). The selection of the reference voltage 13 This is achieved through a polarity signal. 14 , which, for example, involves prior programming of the converter core 2 indicates whether positive or negative charge flows 4 to be measured (whereby the corresponding selection can also be made by other inputs, such as in particular by using certain circuit-related measures). Are negative charge flows 4 To measure, the lower (usually negative) second reference voltage is used. 13b (V min ) selected so that the output voltage 15 (V Ramp ) of the integrator 5It can increase from small voltages (to positive values). With positive charge flows 4 In contrast, the first (typically positive) reference voltage 13a (V max ) selected so that the output voltage 15 the integrator 5 It can decrease from a high value.

[0032] The output voltage 15 the integrator 5 Firstly, the non-inverting input 17 a comparator 16 (K1) fed in. At the inverting input 18 of the comparator 16 In contrast, there is a threshold voltage 19 (V Thres ) which are connected to a digital-to-analog converter 20 is generated. When measuring negative charge flows. 4 The threshold voltage 19 of the comparator 18 first above the output voltage 15 the integrator 5 Once sufficient charge is available in the capacities 7The integrated output voltage exceeds the output voltage. 15 the integrator 5 finally the threshold voltage 19 and the output voltage 21 The comparator switches to a high value (high level).

[0033] Conversely, if positive charge flows 4 The measured output voltage is 15 the integrator 5 initially at a high value and especially above the threshold voltage 19 After sufficient integration of charge into the capacity 7 The output voltage 15 at a certain point in time the threshold voltage 19 The output voltage falls below a certain threshold. Accordingly, the output voltage changes. 21 of the comparator 18 at this point from a high level to a low level.

[0034] Since one can measure regardless of the polarity of the charge flow to be measured 4If one wants to have a consistently identical output signal, the output signal must be 21 of the comparator 16 The output voltage can be selectively inverted. For this purpose, the output voltage is... 21 of the comparator 16 an exclusive-OR logic block 22 (XOR gate) where the other input carries the polarity signal 14 is connected.

[0035] The output signal thus cleaned up 23 On the one hand, it is output to further electronic components for processing (output). 24 ; “Out”). Furthermore, the cleaned output signal is 23 a pulse shaper 25 supplied, which generates a short pulse of fixed length. The pulses shaped in this way 26 are applied to the clock input of an up and down counter 27 Given. When measuring negative charge flows 4 must the up and down counter 27They function as upward counters when measuring positive charge flows 4 In contrast, it acts as a downward counter. For this reason, the up and down counter is called a counter. 27 also with the polarity signal 14 supplied. The output signal of the up and down counter. 27 It will eventually be converted to a digital-to-analog converter. 20 supplied, which exceeds the threshold voltage 19 generated, whereby the threshold voltage 19 especially can be increased over several stages before a reset of the integrator 5 is required. The bandwidth of the digital-to-analog converter 20 issued threshold voltages 19 is determined by two voltage levels 28 (V high , V low ) (“digital-to-analog converter range signal”) specified.

[0036] Further details on various aspects of the converter core 2 or the charge flow-frequency converter 1can be seen in particular in the German patent application DE 198 41 308 A1, the disclosure content of which is to be considered as being fully incorporated into the disclosure content of this application.

[0037] In the case of real components, such as the integrators used here 5 , comparators 16 , counters 27 and digital-to-analog converters 20 Are there time delay effects that cause the threshold voltage to 19 only after a certain delay τ del (del for delay) is adjusted. This τ del determines the maximum output frequency of the converter core 2 (or the charge flow-frequency converter) 1 The following relationship applies: f max = 1 / τ del , which also determines the maximum measurable charge flow 4 I n,max is determined. Is the charge flow 4 (In) higher than the maximum permissible value I n,max, would be during the time τ del , which the converter core 2 for adjusting the threshold voltage 19 The next adjustment of the threshold voltage is already needed. 19 required. This results in the output voltage 15 the integrator 5 permanently above the threshold voltage 19 remains (since the output voltage 15 rises faster than the threshold voltage 19 (can follow), whereby the threshold voltage is usually also 19 "freezes" and no longer outputs the voltage 15 the integrator 5 The following is the output voltage. 15 It therefore continues to rise until the operational amplifier 6 the integrator 5 goes into saturation.

[0038] To detect this error condition, another comparator, an error detection comparator, is used. 29 , provided for. The non-inverting input is used in this case. 30of the error detection comparator 29 with the output voltage 15 the integrator 5 connected, whereas the inverting input 31 of the error detection comparator 29 with one of the two reference voltages 13a , 13b is connected (depending on the polarity signal) 14 ). In the case of measuring negative charge flows 4 The output voltage 15 the integrator 5 with the first reference voltage 13a , in the case of measuring positive charge flows 4 in contrast, with the second reference voltage 13b , compared (i.e., "inverse" to the wiring of the non-inverting input) 12 of the operational amplifier 6 in the integrator 5 ). If the output voltage 15 the integrator 5 about the maximum possible voltage values ​​of the digital-to-analog converter 20 (determined by the voltage levels)28 ) goes beyond this, which has the consequence that the error detection comparator 29 its initial level 32 This changes the situation and thus indicates an error state. The same applies to the comparator. 16 (the output signal) 21 (provided) depends on the polarity of the charge flow (and thus depends on the polarity signal). 14 A selective signal inversion is required. This is also achieved using an exclusive-OR logic element. 22 The ultimately generated error signal 33 can be supplied to other electronic components.

[0039] In Fig. 2 is, also in the form of a schematic diagram, a further developed converter core. 34 The converter core is shown. 34 It is used for operation in combination with a second (not shown) converter core and thus, for example, for a charge flow-frequency converter. 1 , as he in Fig. 3 is outlined.

[0040] The converter core 34 is able to decide independently whether a positive or a negative charge flow is desired. 4 This is achieved using a modified digital-to-analog converter. 35 , which, in addition to the average reference voltage 37 (the actual threshold voltage), generates two further reference voltages (lower reference voltage) 36 or upper reference voltage 38 ), which preferably have a similar voltage difference from the mean reference voltage 37 are offset. The lower reference voltage (V) has proven to be a useful design criterion. Thresl ) 36 with V Thresl = i × V LSB (where V LSB to select the current voltage interval. 37 (V Thresm ) then results from V Thresm = V Thresl +1 / 2 V LSBand the upper reference voltage 38 , V Thresh results from the relationship V Thresh = V Threshl + V LSB .

[0041] These three reference voltages 36 , 37 , 38 become suitable for a set of three comparators 39a , 39b , 39c supplied. The average reference voltage 37 (V Thresm ) is used to decide whether the output voltage 15 the integrator 5 in the upper or lower range of the current voltage interval V LSB is located. If it is located in the upper range, it can be expected that the upper reference voltage 38 is exceeded, meaning that the mean reference voltage 37 (the actual threshold voltage) must be shifted upwards by one interval step. Accordingly, the signal to the digital-to-analog converter 35 upstream, up and down counters27 through the output of the comparator 39b Configured to count up. The pulse shapers 25 , the OR logic block 41 and the inverter 40 They serve to generate the counting clock. 26 (Signal processing).

[0042] Is the output voltage located 15 the integrator 5 in contrast, in the lower range of the current voltage interval V LSB On the contrary, it is to be expected that the lower reference voltage 36 The threshold is undershot. In this case, the mean equivalent voltage must be exceeded. 37 (Threshold voltage) is shifted downwards by one interval step. The up and down counter 27 It will therefore be configured to count down.

[0043] The first comparator K1 monitors this. 39a and the third comparator K3 39c , whether the current voltage interval is moving upwards (first comparator) 39a) or downwards (third comparator) 39c ) is exited. If this is the case, the pulse shaper will be used. 25 (possibly after prior inversion) 40 A pulse of fixed length is generated. The pulse is controlled via an OR logic gate. 41 to the clock input of the up and down counter 27 given.

[0044] As soon as the up and down counter 27 "overflows" (either upwards or downwards; the converter core) 34 (It then needs to be reset), the charge flow measurement is taken over by the second converter core. A switching signal is used for this purpose. 42 . At the same time, the converter 34 detected “counting direction” in the form of a polarity signal 14 transmitted to the other converter core so that it can be pre-initialized. Accordingly, the other converter is configured according to the concept already described in relation to the one in Fig. 1 converter core shown 2as described, pre-initialized.

[0045] In Fig. Figure 3 is a schematic representation of how a charge flow-frequency converter works. 1 with two integrator branches 3a (for example, converter cores) 1 , 34 according to the design of Fig. 1 or of Fig. 2; other construction methods are also conceivable). The following are presented for clarification: the information relating to the above. Fig. 1 converter cores shown 2 The reference numbers used are not to be understood as restrictive.

[0046] As soon as through the relevant integrator branch 3a , 3b (in this case consisting of integrator) 5 and comparator 16 ) a (cleaned) output signal 23 This is done via an OR logic block. 41 both a tap 43 as well as a D-flip-flop 44supplied. Due to the signal in question. 23 changes the D flip-flop 44 Its state, that is, the signals at outputs Q and / Q, are inverted. This changes the previously open input switch. 9 closed and the previously closed entrance switch 9 opened. In parallel, the "fully loaded" integrator is opened. 5 by closing a reset switch 8 reset to zero. Preferably, the reset of the integrator in question occurs immediately and over a certain period of time (correspondingly, a certain period of time elapses until the reset signal is received at the reset switch). 8 is then reversed; a typical value for this is 50 ns). Delay elements are used to generate this time delay. 45 .

[0047] Details on the "alternating parallel operation" of the integrator branches 3a , 3bFor example, the information on the charge flow frequency converter can be found in the aforementioned German patent application DE 198 41 308 A1.

[0048] Further advantages, properties, and developments of the proposed invention can be found in the German patent application, which was filed on the same day with the German Patent and Trade Mark Office under the applicant's file number P 434-a-DE and entitled "Charge-flux-frequency converter with different charge-flux direction". The disclosure content of the application documents therein is fully incorporated into the disclosure of the present application by cross-reference. Reference symbol list 1 Charge flow-frequency converter 2 converter cores 3 Integrator branch 4 Charge flow 5 Integrator 6 operational amplifiers 7 Capacity 8 reset switches 9 input switches 10 switch 11 Inverting Input 12 Non-inverting input 13 Reference voltage 14 Polarity signal 15 Output voltage 16 Comparator 17 Non-inverting input 18 Inverting Input 19 Threshold voltage 20 digital-to-analog converters 21 Output voltage 22 exclusive-or logic module 23 Corrected output voltage 24 Exit 25 Pulse shapers 26 Puls 27 Up and Down Counters 28 voltage levels 29 Error Detection Comparator 30 Non-inverting input 31 Inverting Input 32 Output voltage 33 Error signal 34 converter core 35 Digital-to-Analog Converters 36 Lower reference voltage 37 Average reference voltage 38 Upper reference voltage 39 Comparator 40 inverters 41 OR logic block 42 Switching signal 43 Tap 44 D-Flip-Flop 45 Delay element QUOTES INCLUDED IN THE DESCRIPTION

[0049] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0050] DE 19841308 A1 [0005, 0036, 0047]

Claims

[1] Converter device ( 1 , 2 , 34 ) to convert a charge flow ( 4 ) into a frequency signal ( 23 , 43 ), having at least one integrator ( 5 ) and at least one comparator ( 16 , 39 ), where at least one integrator ( 5 ) and at least one comparator ( 16 , 39 ) are connected in series and the comparator ( 16 , 39 ) when an integrated charge flow is exceeded relative to a threshold value ( 19 , 36 , 37 , 38 ) a signal ( 23 , 43 ) emits, characterized by at least one frequency-overshooting signal output device ( 29 , 33 ). [2] Converter device ( 1 , 2 , 34 ) according to claim 1, characterized by that the frequency exceedance signal output device ( 29 , 33) at least one error indication comparator ( 29 ) and / or a signal inversion device ( 22 ) has the signal inversion device ( 22 ) preferably as an exclusive-OR logic block ( 22 ) is trained. [3] Converter device ( 1 , 2 , 34 ) according to claim 1 or 2, characterized by that the fault indication comparator ( 29 ) a comparator component ( 29 ) has, preferably the inverting input ( 31 ) of the comparator component ( 29 ) with a charge flow reference signal ( 13a , 13b ) and / or the non-inverting input ( 17 ) of the comparator component ( 29 ) with an output signal ( 15 ) of the integrator ( 5 ) is connected. [4] Converter device ( 1 , 2 , 34) according to one of the preceding claims, characterized by at least two integrators connected in parallel to each other ( 5a , 5b ) or integrator branches ( 3a , 3b ), which alternate with the charge flow ( 4 ) will be charged. [5] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, characterized by at least one charge flow direction selection device ( 14 ), with which the converter device ( 1 , 2 , 34 ) optionally onto a positive or a negative charge flow ( 4 ) can be set. [6] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, characterized by that the charge flow direction selection device ( 14 ) the integrator and / or the comparator ( 16 , 39) preferably alternately with one of two charge flow reference voltages ( 13a , 13b ) supplied. [7] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, characterized by that the charge flow direction selection device ( 14 ) has at least one changeover switch device. [8] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, characterized by that the comparator ( 16 ) a preferably conditional signal inversion device ( 22 ), in particular an exclusive-OR logic block ( 22 ), downstream, which is preferably dependent on the position of the charge flow direction selection device ( 14 ) has an inverting effect. [9] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, characterized by that the integrator (5 ) an operational amplifier ( 6 ) exhibits and in particular the charge flow input signal ( 4 ) with the inverting input ( 11 ) of the operational amplifier ( 6 ) and / or the charge flow reference voltage ( 13a , 13b ) with the non-inverting input ( 12 ) of the operational amplifier ( 6 ) is connected. [10] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, characterized by that the comparator ( 16 , 39 ) a comparator component ( 16 , 39 ) exhibits and in particular the output signal ( 15 ) of the integrator ( 5 ) with the non-inverting input ( 17 ) of the comparator component ( 16 ) and / or a threshold voltage ( 19 , 36 , 37 , 38 ) with the inverting input ( 18 ) of the comparator component (16 , 39 ) is connected. [11] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, characterized by that the output signal ( 21 ) of the comparator ( 16 , 39 ) and / or the signal inversion device ( 22 , 40 ) a pulse shaping device ( 25 ) is supplied. [12] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, in particular according to claim 11, characterized by a digital counting device ( 27 ) and / or a digital-to-analog converter ( 20 , 35 ), which corresponds to the comparator ( 16 , 39 ) different threshold voltages ( 19 , 36 , 37 , 38 ) can be supplied, especially depending on an initial value ( 23 ) of the comparator ( 16 , 39), preferably depending on a count value of the counting device ( 27 ). [13] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, in particular according to claim 12, characterized by a digital-to-analog converter amplitude signal input means ( 28 ). [14] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, in particular according to one of claims 4 to 13, characterized by a reset signal output means ( 45a , 45b ), which includes an integrator ( 5 ) postponed and prefers another integrator ( 5 ) activated. [15] Converter device ( 1 , 2 , 34 ) according to one of the preceding claims, characterized by at least one self-adjusting charge flow direction selection device ( 14 ).

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