Enclosed semiconductor device with tensile stress and method for manufacturing an enclosed semiconductor device with tensile stress

Abstract

Composite device (100, 150) comprising the following: a support (130) which has a first thickness; a bonding layer (120) arranged on the support (130); and a chip (110) arranged on the interconnect layer (120), wherein the chip (110) has a second thickness, where the second thickness is greater than the first thickness, wherein an upper surface of the chip (110) is subject to tensile stress and wherein a lower surface of the chip (100) is subject to compressive stress, where the tensile stress is equal to or greater than 100 MPa, and wherein the connecting layer (120) has a diffusion-brazed layer with a thickness equal to or less than 3 µm.

Description

[0001] The present invention relates generally to packaged semiconductor devices and in particular to packaged planar semiconductor chips.

[0002] Consumer market demand for semiconductor devices with increased performance, more diverse functionality, and improved reliability has driven technological innovation in all relevant technical fields. This also applies to the areas of packaging and assembly, which constitute the final stage of single- or multi-chip manufacturing. Packaging provides the necessary wiring between a chip and a chip carrier, as well as a protective housing for the assembly that shields it from chemical or mechanical damage.

[0003] The occurrence of defects in encapsulated components caused by thermomechanically induced mechanical stress is a critical problem that affects the service life of electronic devices. Peeling or cracking at device interfaces or solder joint defects are typical problems for these devices.

[0004] DE 10 2011 053 362 A1 describes a vertical power semiconductor chip with an epitaxial layer and a bulk semiconductor layer. A first contact point is arranged on a first primary surface of the power semiconductor chip, and a second contact point is arranged on a second primary surface of the power semiconductor chip opposite the first primary surface. The device further comprises an electrically conductive support attached to the second contact point. US 2004 / 0 089 926 A1 describes an ultrathin semiconductor device. The ultrathin semiconductor device comprises a conductor frame, a chip, and encapsulation material. Furthermore, the ultrathin semiconductor device comprises a chip pad with a recess, the chip being arranged in this recess.US 2005 / 0 179 109 A1 describes a semiconductor device in which mechanical stresses arise due to thermal mismatch effects between a chip and a substrate.

[0005] The invention is set out in the appended claims. In accordance with one embodiment of the invention, a composite device comprises a carrier having a first thickness, a bonding layer arranged on the carrier, and a chip arranged on the bonding layer, wherein the chip has a second thickness, the second thickness being greater than the first thickness, wherein an upper surface of the chip is subject to tensile stress, and wherein a lower surface of the chip is subject to compressive stress.

[0006] In one embodiment, the second thickness can be equal to or greater than 50 µm, and the first thickness can be equal to or less than 50 µm. In another embodiment, the second thickness can be equal to or greater than 100 µm, and the first thickness can be equal to or less than 100 µm. In yet another embodiment, the interconnect layer can have a third thickness, wherein the third thickness is between 1 µm and 3 µm. In yet another embodiment, the interconnect layer can be a diffusion solder layer. In yet another embodiment, an upper surface of the chip can be subjected to tensile stress, and a lower surface of the chip can be subjected to compressive stress. In yet another embodiment, the tensile stress can be equal to or greater than 100 MPa.

[0007] In accordance with one embodiment of the invention, a composite device comprises a carrier, a bonding layer arranged on the carrier, and a planar chip having an upper surface and a lower surface, wherein the planar chip is arranged with its lower surface on the bonding layer, wherein the upper surface of the planar chip is subject to tensile stress and wherein the lower surface of the planar chip is subject to compressive stress.

[0008] In one embodiment, the tensile stress can be equal to or greater than 100 MPa. In yet another embodiment, the composite device can further exhibit compressive stress at the lower surface of the chip. In yet another embodiment, the composite device can further comprise: wiring connecting chip contact patches to carrier contact patches; and an encapsulation encapsulating the carrier, the interconnect layer, and the planar chip. In yet another embodiment, the interconnect layer can have a thickness equal to or less than 20 µm.

[0009] In accordance with one embodiment of the invention, a composite device comprises a carrier, a bonding layer arranged on the carrier, and a chip having an upper surface and a lower surface, wherein the chip is arranged with its lower surface on the bonding layer, wherein the chip further comprises a first source / drain contact at the upper surface and a second source / drain contact at the upper surface, wherein the chip has a tensile stress between the first source / drain contact and the second source / drain contact, and wherein the lower surface of the chip has a compressive stress.

[0010] In one embodiment, the tensile stress can be equal to or greater than 100 MPa. In another embodiment, the chip can include a power semiconductor device. In yet another embodiment, the interconnect layer can be an organic or inorganic adhesive layer with a thickness of 20 µm or less. In yet another embodiment, the interconnect layer can be a diffusion-soldered layer with a thickness of 3 µm or less.

[0011] In accordance with an embodiment of the invention, a method for manufacturing a semiconductor device comprises arranging a semiconductor substrate having a lower main surface on a conductor frame and thereby creating a tensile stress at an upper main surface of the semiconductor substrate and a compressive stress at a lower main surface of the semiconductor substrate, wherein the conductor frame has a greater thickness than the semiconductor substrate.

[0012] In one embodiment, the method further comprises thinning the semiconductor substrate before arranging it on the conductor frame. In yet another embodiment, arranging the semiconductor substrate on the conductor frame comprises diffusion soldering of the semiconductor substrate onto the conductor frame.

[0013] For a more comprehensive understanding of the present invention and its advantages, reference is now made to the following descriptions in conjunction with the accompanying drawings, in which: Fig. 1 represents a cross-sectional view of a chip / carrier arrangement, wherein Fig. 1a shows the arrangement of the chip carrier attachment at the beginning of contacting, while Fig. 1b shows the connected arrangement after cooling; Fig. 2 shows a cross-sectional view of an embodiment of a packaged planar semiconductor device having a tensile stress on the upper surface of the semiconductor device; Fig. 3 shows a graphical representation of experimental data, illustrating different voltage levels for different combinations of silicon / copper conductor frame thicknesses on the lower surface of the silicon chip; Fig. 4 shows a graphical representation of experimental data, illustrating different voltage levels for different combinations of silicon / copper conductor frame thickness at the top surface of the silicon chip; and Fig. Figure 5 shows an embodiment of a method for manufacturing a packaged planar semiconductor device which has a tensile stress in the uppermost region of its semiconductor substrate.

[0014] The manufacture and use of the currently preferred embodiments are discussed in detail below. However, it should be noted that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of manufacturing and using the invention and do not limit the scope of protection of the invention.

[0015] The present invention is described with regard to embodiments in a specific context, i.e., with regard to packaged planar semiconductor devices. However, the invention can also be applied to other packaged semiconductor devices or packaged components.

[0016] The housing of a semiconductor component generally involves attaching a component (e.g., a single chip or chip) to a component carrier, thereby forming a mechanical and / or electrical component-carrier contact.

[0017] The contacting of a single chip to a carrier is carried out at elevated temperatures, generally in the range of 200 °C to 400 °C. Fig. Figure 1 illustrates in a simplified way the initial and final phases of a chip carrier assembly. Fig. Figure 1a shows a composite semiconductor device 100 at the moment of the first physical contact between a single semiconductor chip 110, a connection layer 120, and a single-layer carrier 130. At this stage, at the beginning of the contacting process, the arrangement 100 has not yet developed any mechanical stress emanating from the connection between the single chip 110 and the carrier 130. In contrast, Figure 1a shows Fig. 1b the assembled state 150 after completion of the contacting process. In between, the assembled semiconductor device 100 was heated to an elevated temperature and subsequently cooled to room temperature.

[0018] During the cooling phase, all elements of the 100 / 150 assembly are subjected to contraction forces based on the coefficients of thermal expansion (CTE) of the materials involved. Since the CTEs of the materials involved generally differ—attempts to adjust the CTEs, if made, can only partially reduce the CTE mismatch—the cooled 150 assembly exhibits internal mechanical stress resulting from the connection between the single chip 110 and the support 130. This leads to mechanical distortions in the 150 assembly, resulting in a slight upward or downward bending of the layers of the 150 assembly. Fig. Figure 1b shows an exaggerated downward bend. This type of fault can be observed, for example, when metal beams 130 are used, which exhibit relatively high CTEs.

[0019] Each individual element of the composite packaged component 150 can influence the other elements in the packaged component 150. In particular, thick layers can have a greater influence on stress-induced faulting than thin layers. For example, the closer the thick layers are positioned to each other and the greater the differences in CTE between them, the greater the faulting may be.

[0020] The observed stress can be either tensile or compressive. According to the adopted nomenclature, tensile stress is indicated by positive values ​​and compressive stress by negative values. The mechanical stress observed within a specific region of the packaged component 150 can be non-uniform and orientation-dependent. The mechanical stress within a topmost region of the semiconductor chip 110 can differ in magnitude and / or sign from that of the bottommost region of the chip 110. Similarly, the support regions 132, 134 around the perimeter of the support 130 can exhibit relatively lower surface distortion and lower values ​​of mechanical stress than the central support region 136.

[0021] The mechanical stress generated within the architecture of an electronic component can lead to reliability problems. This is well known. However, the use of mechanical stress to improve the electrical performance of semiconductor devices in encapsulation configurations is not known.

[0022] Embodiments of the present invention utilize a compressive and / or tensile stress based on a component-support interface in such a way as to improve the electrical performance of the component. Various embodiments provide a tensile stress for an upper main surface of a planar device (where the active devices are located) and a compressive stress for a lower main surface of the planar device. In some embodiments, the tensile stress has values ​​exceeding 100 MPa.

[0023] In some embodiments, the device performance is improved by the presence of a tensile stress in a direction parallel to the current flow. Furthermore, a compressive stress in a direction parallel to the current flow is to be avoided in some embodiments, as it degrades the device performance. In various embodiments, the tensile stress generates an increase in electron mobility, leading to device performance advantages in terms of speed and power consumption. It is assumed that a reduction in the effective electron mass and a reduction in electron scattering are the mechanisms that lead to the observed increase in electron mobility.

[0024] Fig. Figure 2 illustrates a cross-sectional view of an embodiment of a packaged semiconductor device 200. The packaged semiconductor device 200 comprises a semiconductor chip 210, which is connected via a bonding layer 250 to the central section 262 of a chip carrier 260. The semiconductor chip 210 comprises a semiconductor substrate 220. An upper first main surface 222 of the substrate 220 is covered by a top layer 230. A backside metallization layer (BSM layer) 240 is arranged beneath the second main surface 224 of the semiconductor substrate 220, with the second main surface 224 facing the carrier 260. Furthermore, the enclosed component 200 has wiring elements 270, 272, 274, which run from defined areas (or component contacts) of the termination layer 230 to circumferential sections 264, 266, 268 of the carrier 260.Furthermore, the semiconductor chip 210, the wiring 270, 272, 274 and the chip carrier 260 are fully or partially enclosed by an encapsulation material 280.

[0025] In various embodiments, the semiconductor substrate 220 can comprise a single-element semiconductor material such as silicon or germanium. Alternatively, the semiconductor substrate 220 can comprise a composite semiconductor material such as SiC, SiGe, InP, InAs, GaAs, GaN, or GaP. The semiconductor substrate 220 can comprise only a single semiconductor substrate material or, alternatively, a combination of a semiconductor epitaxial layer arranged over a semiconductor substrate material. The thickness of an epitaxial or semiconductor substrate layer can be, for example, equal to or greater than 20 µm, 50 µm, or 100 µm. The total thickness of the semiconductor substrate 220 cannot be less than 1000 µm. In some embodiments, the semiconductor substrate 220 can comprise a silicon-on-insulator (SOI) substrate.

[0026] Several of the semiconductor materials mentioned above exhibit CTE values ​​in the range of 2.3 ppm / K to 7 ppm / K. The CTEs of Si and GaN cannot exceed 2.3 ppm / K and 3.2 ppm / K, respectively. Semiconductor materials with relatively high CTEs include Ge (5.8 to 5.9 ppm / K) and GaAs (5.7 to 6.9 ppm / K).

[0027] The semiconductor chip 210 can include a planar power device, such as a planar power MOSFET (planar power metal-oxide-semiconductor field-effect transistor), having a source, a drain, and a gate region, all oriented toward the first main surface 222. Alternatively, the semiconductor chip 210 can include another type of semiconductor device, such as a passive device, a MEMS, or an optoelectronic device. The semiconductor chip 210 can be a single device or an integrated circuit.

[0028] In one embodiment, the semiconductor chip 210 has a backside metallization layer (BSM layer) 240 located beneath the second main surface 224 of the semiconductor substrate 220. The BSM layer 240 can be a single layer or multiple layers comprising metal or metal alloy materials. For example, the BSM layer 240 can be a three-layer stack of Al / Ti / NiV, a two-layer stack comprising Al / Ti or Al / TiW, or it can be a more complex composition (e.g., Al / Ti / Cu / Sn / Ag or Al / TiW / Cu / Sn / Ag). The overall thickness of a BSM stack 240 can be in the range of 0.5 µm to 5 µm. Alternatively, the BSM layer 240 has a thickness between 0.1 µm and 10 µm. The BSM layer (the BSM stack) 240 is configured to enable effective heat transfer from the semiconductor chip 210 to the carrier 260.

[0029] The carrier 260 has a central section 262 on which the chip 210 is mounted, and peripheral regions (e.g., 264, 266, 268). The carrier 260 can be a metal conductor frame made of materials with a CTE ≥ 15 ppm / K, such as copper (CTE 16.6 to 17.6 ppm / K), brass (CTE ~ 20 ppm / K), or aluminum (CTE 23 to 24 ppm / K). The thickness of the conductor frame 260 can be in the range of 50 µm to 1000 µm or, alternatively, between 100 µm and 500 µm.

[0030] In some embodiments, rigid materials with significantly higher CTEs than the semiconductor substrate 220 can be used as the support material 260. As explained below, materials with low CTEs, such as most ceramics or CuMo with CTEs in the range of 4 ppm / K to 8 ppm / K, may be less suitable for some embodiments of the invention. On the other hand, zirconium dioxide ceramics with CTEs around 10.5 ppm / K may be suitable as support materials, even though their CTE values ​​are approximately 30% lower than those of conventional metal conductor frame materials.

[0031] The interconnect layer 250 enables contact between the chip 210 and the carrier 260. In one embodiment, the interconnect layer 250 can comprise a solder material such as AuSn, AgSn, CuSn, or SnSb, which facilitates contact with the metal conductor frame 260. In some embodiments, the solder layer can exhibit high rigidity and be as thin as possible to minimize its effectiveness as a stress-buffer layer that mitigates the mechanical stress emanating from the single-chip / carrier connection. In one embodiment, the thickness of the solder material can be less than 20 µm. The thickness of the solder layer 250 can be no greater than 1 µm to 3 µm. A solder thickness between 50 µm and 100 µm, as is commonly used for conventional applications, may be unsuitable for various embodiments of the invention.

[0032] In alternative embodiments, the bonding layer 250 can be a conductive or non-conductive, organic or inorganic adhesive layer. Organic adhesive layers can comprise epoxy, epoxy / urethane, polyester, or polyimide resins mixed with a crosslinking component. Electrically conductive adhesive layers can also comprise nanoparticles (up to 85 vol%) of metals / alloys such as Ag-, Cu-, Au-, Ag-coated Ni, or Au-plated Ni. Electrically conductive adhesive layers can offer better thermal conductivity than non-conductive ones and thus provide more effective heat dissipation from the semiconductor device to the support 260. The thickness of the deposited adhesive layers can be low, e.g., less than 50 µm. Alternatively, the thickness can be in the range of 5 µm to 20 µm.

[0033] The termination layer 230, arranged over the first main surface 222 of the semiconductor substrate 220, can have electrically conductive contact patches (not shown) to which wiring elements (e.g., 270, 272, 274) are attached. The contact patches can have one or more layers of highly conductive metals (e.g., Cu, Al, Ni), metal alloys, solder, conductive adhesive, or combinations thereof. Furthermore, the termination layer 230 can have insulating sections (not shown) that electrically isolate the contact patches from one another. These insulating elements of the termination layer 230 can, for example, comprise silicon oxide or silicon nitride. The contact patches can be conductively connected to active device elements. The contact patches can, for example, be arranged over the source, drain, and gate regions of a planar power MOSFET.

[0034] The wiring elements 270, 272, 274 can establish conductive paths between the contact patches in the termination layer 230 and circumferential sections 264, 266, 268 of the conductor frame (so-called outer patches). Such wiring can be wire contacts with diameters ranging from 16 µm to 500 µm. The wire contacts can be made of, for example, Au, Cu, Ag, or Al. Alternatively, instead of wire contacts, prefabricated (punched) metal parts with a predefined configuration (so-called terminals) can be used. In general, the wiring between a top region of the chip 210 and the carrier 260 can be used for other possible component architectures that are described in Fig. 2 not shown, can also be formed by other means, e.g. using through-contact holes that are made vertically through the chip 210 and are connected to the carrier 260 by means of solder ball connections.

[0035] Furthermore, the enclosed electrical component 200 comprises an encapsulation material 280 that fully or partially encloses the chip 210, the carrier 260, and the wiring elements 270, 272, 274. The encapsulation material 280 can comprise epoxy, polyacrylate, polyurethane, polysulfone, polyimide, or polyetherimide compounds, or other polymer compounds. If encapsulation materials with elastic modulus values ​​E of approximately 13,000 MPa are used, the contribution of the encapsulation body 280 to the mechanical forces acting on the critical device areas is expected to remain small. Alternatively, the encapsulation material 280 can be a laminate instead of a molding compound.

[0036] In various embodiments, the region 225 near the upper surface of the semiconductor substrate 220 exhibits a tensile stress parallel to the first main surface 222. The tensile stress region 225 is configured to provide a current flow between approximately 0.1 A and 100 A. The region 225 can be located between the first source / drain region of the semiconductor device 210 and the second source / drain region of the semiconductor device. In some embodiments, the tensile stress values ​​are equal to or greater than 100 MPa. In other embodiments, tensile stress values ​​greater than 1 GPa are avoided to minimize stress-induced defects in the packaged device 200, such as peeling or cracking.

[0037] The tensile stress within the uppermost region 225 of the semiconductor substrate 220 is primarily generated by mechanical forces at the connection between the single chip 210 and the support 260. In some embodiments, the semiconductor substrate 220 and the support 260 have the strongest influence on the tensile stress region, while other sources, such as the interface between the single chip and the encapsulation material 210 / 280, the BSM layer 240, or the interconnect layer 250, play a lesser role.

[0038] In various embodiments, the most influential parameter affecting the tensile stress in the device area 225 is the difference in the CTEs of the semiconductor substrate 220 and the support 260. In some embodiments, the performance of the device 210 increases if the thickness of the semiconductor substrate 220, D sub , greater than the thickness of the support 260, D carr , is. For example, D should sub be as large as possible and should be Dcarr be as thin as possible. In some embodiments, compressive stress is avoided in region 225 or on the upper surface 222.

[0039] In some embodiments, the compound layer 250 is as small as possible to avoid buffering effects. In particular, a thick compound layer 250 can mitigate the CTE difference between the semiconductor substrate 220 and the support.

[0040] In some embodiments, the tensile stress on the surface of the semiconductor device 210 for planar devices improves electron mobility. In particular, the resistivity is significantly reduced compared to conventional devices.

[0041] In some embodiments, a larger difference between the CTE of the substrate 220 and the CTE of the support 260 in the connection area generates a higher mechanical stress. In various embodiments, the CTE of the support is at least twice as high as the CTE of the semiconductor device.

[0042] The Fig. 3 and Fig. Figure 4 shows the resulting voltage values ​​for different thicknesses of the silicon substrate 220 and the conductor frame 260 on the underside of the chip ( Fig. 3) and on the top of the chip ( Fig. 4) These two figures show experimental data relating to a set of silicon single-chip / copper conductor frame assemblies with different silicon and conductor frame thicknesses. The silicon thickness was varied between 10 µm and 725 µm, and the copper conductor frame thickness was varied between 50 µm and 1000 µm. The measured voltage values ​​refer to the assembled semiconductor device 200 after cooling from a contact temperature of 300 °C.

[0043] With reference to Fig. 3. Compressive stresses on the underside of the chip were determined across the entire investigated ranges of silicon and copper conductor frame thickness. For a copper thickness range of 250 µm to 1000 µm, the compressive force decreased with increasing silicon thickness (i.e., a shift to less negative values). Except for the case of 50 µm Cu, where the trend continued to the upper end of the investigated silicon thickness range (725 µm), this trend flattened out for silicon thicknesses exceeding 200 µm.

[0044] Fig. Figure 4 shows the stress values ​​in the uppermost region of the chip, which contains the silicon area relevant for improving electron mobility / device performance. For a copper conductor frame thickness range of 250 µm to 1000 µm, an increase in silicon chip thickness was accompanied by a gradual shift from compressive to tensile stress. For a conductor frame thickness of 50 µm, the highest tensile stress values ​​were determined for silicon thicknesses of 60 µm and 100 µm, with the tensile stress worsening if the silicon thickness was increased beyond 100 µm.

[0045] In one embodiment, the ratio of the thickness of the semiconductor substrate 220, D varies. sub , to the thickness of the carrier 260, D carr , between 1 and 2 (e.g. 1 ≤ D sub / D carr ≤ 1.33; 1.33 ≤ D sub / D carr ≤ 1.66 or 1.66 ≤ D sub / D carr≤ 2). In contrast, the semiconductor substrate thickness of conventionally manufactured devices is in many cases significantly thinner than the thickness of the substrate used. Often, the total chip thickness of a conventional device is about half the thickness of its substrate.

[0046] Fig. Figure 5 shows a flow chart of an embodiment for the manufacture of a capped planar semiconductor device which has a tensile stress in the uppermost region of its semiconductor substrate.

[0047] In a first step 510, several planar semiconductor devices are fabricated in / on a semiconductor substrate. Step 510 represents a sequence of processing steps dedicated to the formation of active device elements and wiring along a top main surface of the semiconductor substrate. In step 515, a termination or passivation layer is formed on the top main surface of the semiconductor substrate. The termination layer isolates the contact patches on the first main surface of the semiconductor device from each other.

[0048] In step 520, the semiconductor substrate is optionally thinned. Typically, the wafer arrives at a standard thickness and must be thinned to the specified optimal thickness. Wafer thinning can be achieved, for example, by grinding or lapping. Grinding tools can utilize a grinding wheel. Lapping tools use a liquid fluid (referred to as an "abrasive powder emulsion") containing abrasive particles acting between two surfaces. Chemical-mechanical polishing (CMP) is another process option for wafer thinning, employing a combination of mechanical grinding and chemical attack.

[0049] In the next step, a backside metallization layer (BSM layer) can optionally be formed on the back side of the semiconductor substrate (e.g., on the back side of the wafer). The wafer can be temporarily bonded to a support wafer with its top main surface. A backside metallization layer (BSM layer) is then deposited on the back side of the substrate. The BSM layer can consist of one or more layers of metal or metal alloys. Possible material options have already been mentioned above. The BSM layer(s) can be deposited, for example, by ion beam sputtering, reactive sputtering, electroplating, or chemical vapor deposition (CVD). Higher sputtering temperatures may result in higher tensile strength in the topmost region of the chip.

[0050] In step 530, the semiconductor wafer containing the devices is cut or separated into individual chips. The semiconductor wafer can be cut, for example, by a saw or a laser.

[0051] In step 535, a substrate is prepared for mounting at least one of the isolated chips by depositing a compound layer material in defined areas on the substrate's upper surface. In one embodiment, a high-rigidity diffusion solder material is applied. AuSn, AgSn, CuSn, or AgIn can be used as solder materials. The solder layer can be formed in a full-surface deposit over the entire substrate by applying electroplating, vapor deposition, or evaporative sputtering techniques. Subsequently, the solder can be removed from areas that are to be solder-free by a combination of conventional lithography and etching steps or by laser ablation using high-energy Nd:YAG or excimer lasers. Alternatively, the solder layer can be removed by applying techniques such as edge shielding, spray / spray application, or stencil printing (e.g.,selectively deposited (due to the application of a solder paste).

[0052] In another embodiment, a layer of metallic printing ink can be selectively applied to the substrate. Metallic printing inks contain particles that include metal / alloy materials such as Ag, Cu, or Ag-coated Cu or Ni. The metallic printing ink particles can be a few tens of nanometers in size.

[0053] In another embodiment, a conductive or non-conductive adhesive paste can be applied as a bonding layer to defined locations on the substrate using a paste dispensing system. The adhesive paste contains a solvent. After paste deposition, the solvent is removed by a drying process in an oven or by passing warm air over it. The adhesive paste is then cured for a few minutes at temperatures of approximately 100 °C to 250 °C. Alternatively, an adhesive material can be applied in the form of pre-cut sections of an adhesive film (so-called preforms). The thickness of such preforms can range from 5 µm to 10 µm. If a preform material contains a UV-sensitive component, the preform can be UV-cured for approximately 1 s to 20 s, the curing time depending on the thickness of the preform.Alternatively, thermal curing can be carried out at temperatures in the range of approximately 130 °C to approximately 160 °C, with curing times ranging from approximately 20 s to approximately 60 s.

[0054] In step 540, at least one semiconductor chip is attached to the substrate, with the inactive back side(s) of the chip facing the substrate. Using conventional pick-up and placement equipment, a first chip is picked up and positioned over a defined section of the preheated substrate. Subsequently, the precisely aligned chip is contacted to the substrate at an elevated temperature. In some embodiments, the picking, placement, and contacting of the chip to the substrate can be repeated.

[0055] The contact temperature depends on the nature of the bonding material. If the selected mounting layer is a diffusion-type solder, thermocompression contacting can be used to bond the chip to the substrate. Contacting temperatures for diffusion-type solder are generally in the range of approximately 300 °C to 400 °C. To achieve higher mechanical stress in the single-chip / substrate connection, contacting can preferably be performed at temperatures between approximately 350 °C and 400 °C. Example processing conditions for contacting with a 75% Au / 25% Sn solder are: 1200 nm, 360 °C, 350 ms, contact force 3.3 N / mm². 2 , Contacting soft delay of 150 ms in a contacting tunnel with a forming gas atmosphere (85% N2 + 15% H2).

[0056] In another embodiment, the chip and the substrate with an intermediate layer of metallic ink can be sintered together at temperatures between approximately 200 °C and approximately 250 °C, while a pressure in the range of approximately 1 MPa to approximately 5 MPa is applied for at least 1 to 2 minutes. In a further embodiment, the chip / substrate contacting can involve contacting an electrically conductive or non-conductive layer of an adhesive layer or adhesive paste. For such materials, the contacting temperature can be in the range between approximately 180 °C and approximately 250 °C.

[0057] In step 545, the wiring elements are attached. The ends of the wire contacts or external terminals are connected to corresponding contact patches at the termination layer of the semiconductor layer and the substrate. If the substrate is a metal conductor frame, the wiring elements are connected to circumferential outer patches of the conductor frame. For signal wiring, gold wire contacts with diameters ranging from approximately 16 µm to approximately 40 µm are frequently used. For wiring in the load path of an electrical system, significantly thicker aluminum wires with diameters ranging from approximately 100 µm to approximately 500 µm are generally used. The contacted wire ends can be either spherical or wedge-shaped. Spherical wire ends can be formed using a hydrogen flame or by applying a capacitive discharge technique.Ball contacting can be carried out in a shielding gas atmosphere of Ar with 10% H2, while wedge contacting uses N2 + 10% H2.

[0058] Three different wire contacting techniques are available: ultrasonic, thermocompression, and thermosonic contacting. Ultrasonic contacting is only applicable to wedge contact formation. The other two techniques can be used for either ball or wedge contacting. Ultrasonic contacting utilizes ultrasonic energy in the range of approximately 20 kHz to 60 kHz, applying a contact load of 0.5 g to 2.5 g per wire contact during contact times of around 20 ms at room temperature. Ultrasonic wedge contacting is the preferred contacting method for aluminum wires. Thermocompression contacting is performed at temperatures in the range of approximately 300 °C to 500 °C, applying a contact load of 15 g to 25 g per wire contact.Thermosonic contacting uses a combination of heat, ultrasonic energy (in the range of 60–120 kHz), and pressure. Thermosonic contacting can be performed using less heat and less pressure than thermocompression contacting. Temperatures in the range of 125 °C to 150 °C and contact loads between 0.5 g and 2.5 g per wire contact are sufficient for this contacting technique.

[0059] In step 550, the attached component(s), wiring, and support are fully or partially encapsulated. The encapsulation material can be a molding compound, a laminate, or a potting compound coating. Various encapsulation techniques can be used with a dielectric material, such as die casting, heat pressing, injection molding, powder or liquid casting, dispensing, or layering.

[0060] In mass production, several electrical components are attached to a carrier. In one embodiment, an encapsulated arrangement comprising a carrier and several semiconductor components is cut by a saw or a laser, thereby separating it into individually encapsulated semiconductor components. This is shown in step 555.

Claims

[1] Composite device (100, 150) comprising the following: a support (130) which has a first thickness; a bonding layer (120) arranged on the support (130); and a chip (110) arranged on the interconnect layer (120), wherein the chip (110) has a second thickness, where the second thickness is greater than the first thickness, wherein an upper surface of the chip (110) is subject to tensile stress and wherein a lower surface of the chip (100) is subject to compressive stress, where the tensile stress is equal to or greater than 100 MPa, and wherein the connecting layer (120) has a diffusion-brazed layer with a thickness equal to or less than 3 µm. [2] Composite device (100, 150) according to claim 1, wherein the second thickness is equal to or greater than 50 µm and the first thickness is equal to or less than 50 µm. [3] Composite device (100, 150) comprising the following: a carrier (130); a bonding layer (120) arranged on the support (130); and a planar chip (110) having an upper surface and a lower surface, wherein the planar chip (110) is arranged with its lower surface on the interconnect layer (120), wherein the upper surface of the planar chip (110) is subject to tensile stress and wherein the lower surface of the planar chip (110) is subject to compressive stress, where the tensile stress is equal to or greater than 100 MPa, and wherein the connecting layer (120) has a diffusion-brazed layer with a thickness equal to or less than 3 µm. [4] Composite device (100, 150) according to claim 3, further comprising: Wiring connections linking chip contact patches to carrier contact patches; and an encapsulation that encapsulates the carrier (130), the interconnect layer (120) and the planar chip (110). [5] Composite device (100, 150) comprising the following: a carrier (130); a bonding layer (120) arranged on the support (130); and a chip (110) having an upper surface and a lower surface, wherein the chip (110) is arranged with its lower surface on the interconnect layer (120), wherein the chip (110) further comprises a first source / drain contact at the upper surface and a second source / drain contact at the upper surface, wherein the chip (110) has a tensile stress between the first source / drain contact and the second source / drain contact and wherein the lower surface of the chip (110) has a compressive stress, where the tensile stress is equal to or greater than 100 MPa, and wherein the connecting layer (120) has a diffusion-brazed layer with a thickness equal to or less than 3 µm. [6] Composite device (100, 150) according to claim 5, wherein the chip (110) comprises a power semiconductor device (100, 150). [7] Method for manufacturing a semiconductor device (100, 150) wherein the method comprises: Arranging a semiconductor substrate (110) with a lower main surface (112) on a conductor frame (130) and thereby creating a tensile stress at an upper main surface of the semiconductor substrate and a compressive stress at a lower main surface of the semiconductor substrate, wherein the conductor frame has a smaller thickness than the semiconductor substrate, where the tensile stress is equal to or greater than 100 MPa, and wherein the arrangement of the semiconductor substrate (110) on the conductor frame (130) comprises diffusion soldering of the semiconductor substrate onto the conductor frame, wherein the diffusion-soldered junction layer (120) has a thickness equal to or less than 3 µm. [8] Method according to claim 7, further comprising thinning the semiconductor substrate (110) prior to arranging the semiconductor substrate (110) on the conductor frame (130).

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