Semiconductor stack, matrix with a semiconductor stack, method for performing a logic operation and using the semiconductor stack

Abstract

Semiconductor stack (1) for performing at least one logical operation, comprising: adjacent layers (2, 2') arranged in a stacked configuration, each layer (2, 2') comprising at least one phase-change memory cell in which a phase-change material (3), on one of whose opposite faces (4') a first electrical heating terminal (T2, T9) is provided and on whose other opposite faces (4'') at least two further electrical heating terminals (T5, T6) are provided, is operable between the first electrical heating terminal (T2, T9) and each of the two further electrical heating terminals (T5, T6) in one of at least two reversibly convertible phases, an amorphous phase (3') and a crystalline phase (3''), wherein the adjacent layers (2, 2') share the at least two further electrical heating terminals (T5, T6), wherein the semiconductor stack is configured for this purpose,that it stores information by means of an electrical resistance (R2, R8, R3, R9) of the phase (3", 3') of the phase-change material (3) between the at least one first electrical heating terminal (T2, T9) and each of the two further electrical heating terminals (T5, T6) in the adjacent layers (2, 2'), and the logical operation is executable on the basis of the information (R2, R8, R3, R9) stored in the adjacent layers (2, 2').

Description

Field of invention

[0001] The present invention relates to a semiconductor stack for performing a logical operation, with which information relating to or used in the logical operation can be stored. Background of the invention

[0002] It is known to use several individual electronic units, such as electronic transistors, connected together in an electrical circuit to perform logical operations. To perform a given logical operation, a specific group of electronic units is used in a predefined electrical circuit. To enable the performance of various logical operations, each electrical circuit, predefined and / or assigned to perform a given logical operation, can be embedded in an integrated circuit and / or a semiconductor device via its specific group of electronic units.

[0003] A problem associated with performing logic operations using an integrated circuit and / or semiconductor unit as described above may be the limited flexibility and / or adaptability, since a given logic operation can only be performed by an electrical circuit which has a given group of electronic units predefined for performing this task, and is not interchangeable with and / or between other electrical circuits configured to perform, or capable of performing, logic operations.Another problem can be that, since a special amount of space must be reserved for the integration of the electrical circuits, each of which is predefined to perform a given logical operation, the density of an integrated circuit / unit may be relatively reduced when using such electrical circuits to perform logical operations.

[0004] In known logic units and / or applications, logic functionality is based on volatile information, such as a charge. In this context, the information representing the logical inputs is retrieved from memory, a given logical operation is performed on the logical inputs, and the result of the logical operation, the logical output, is stored externally. Resources required for performing the steps of retrieving the logical inputs and storing the logical output, as well as space / memory for storing such information, are necessary with respect to the information used in or related to the logical operation, namely the logical inputs and the logical output.

[0005] US Patent 7,186,998 B2 discloses a multi-terminal logic unit comprising a phase-change material exhibiting crystalline and amorphous states in electrical communication with three or more electrical terminals. The phase-change material can undergo reversible transformations between amorphous and crystalline states in response to applied electrical energy, with the amorphous and crystalline states exhibiting measurably different electrical resistances. Electrical energy in the form of current or voltage pulses applied to a terminal pair influences the structural state and the measured electrical resistance between the terminals. In the units disclosed in this document, independent input signals are provided at different terminal pairs, and the output is measured as resistance between yet another terminal pair.The logic functionality is achieved through relationships between the applied input signals and the measured output resistance, where the relationship is determined by the effect of the input signals on the structural state and electrical resistance of the phase-change material. Logical values ​​can be associated with the crystalline and amorphous states of the phase-change material or the measured resistance between them.

[0006] The terminal pair must be connected. Publication US 7,186,998 B2 also discloses a method for operating a phase-change memory cell to achieve a given logic functionality. The disclosed phase-change memory cell has three terminals, allowing the corresponding input signals applied to two different terminal pairs to be used to generate crystalline or amorphous states in the phase-change material, which have corresponding, distinguishable resistances that can be used to represent required inputs of a given logic function. An output resistance, measured between a third terminal pair, corresponds to the output of the logic function.

[0007] Document US 2006 / 0071244A1 relates to a method for operating a switching device which has an active material centrally arranged between at least three electrodes, each consisting of conductive material, which can be brought into a more or less conductive state by appropriate switching operations, wherein the active material is an ion-doped chalcogenide, and wherein the method comprises the steps of: applying a voltage between a first and a second electrode such that a conductive channel is created between the first and the second electrode by metal deposition, and applying a voltage between a third electrode and the second electrode such that a further conductive channel is created between the third and the second electrode by metal deposition, so that the first electrode and the third electrode are connected via the conductive channel,and are conductively connected to the other electrically conductive channel.

[0008] Document US 7,729,158 B2 relates to a resistance-change memory device comprising: a semiconductor substrate; cell arrays stacked over the substrate, each containing memory cells, bit lines, and word lines; a read / write circuit formed on the semiconductor substrate; first and second vertical wiring arranged to connect the bit lines to the read / write circuit; and third vertical wiring connecting the word lines to the read / write circuit.The memory cell contains a variable resistance element for storing a resistance value as information, which has a recording layer consisting of a composite compound containing at least two types of cationic elements, wherein at least one type of cationic element is a transition element with a “d” orbit in which electrons are incompletely filled, with the shortest distance between adjacent cationic elements being 0.32 nm or less.

[0009] Document US 2011 / 0 096 594 A1 discloses techniques for reading a phase-change memory that mitigate resistance drift. One method comprises applying a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell that result from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals as a function of the configuration of an amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In an embodiment of the invention disclosed in this document, the method further comprises mapping the plurality of electrical output signals onto a measurement zone of a plurality of measurement zones.The measurement zones correspond to the storage states of the memory cell.

[0010] Document US 2004 / 0051094A1 relates to a non-volatile semiconductor memory device comprising: a plurality of memory cells arranged in rows and columns, each having a physical state set in accordance with stored data to store data in a non-volatile manner; and a plurality of dummy cells arranged in alignment with the memory cells in at least one of a row direction and a column direction, each having a layout identical to a layout of the memory cell.

[0011] Document US 4,646,266 A relates to a solid-state semiconductor device having at least two terminals and a plurality of layers of semiconductor material to provide a plurality of interacting semiconductor functions, wherein the device is programmable in a first state in which the electrical impedance between the two terminals is relatively high in both directions, a second state in which the electrical impedance between the two terminals is relatively high in one direction and relatively low in the opposite direction, a third state in which the electrical impedance between the two terminals is relatively high in the opposite direction and relatively low in one direction, and a fourth state in which the electrical impedance between the two terminals is relatively low in both directions.

[0012] The task is to improve corresponding semiconductor devices.

[0013] The problem is solved by the semiconductor stack according to claim 1, the matrix according to claim 11, the method according to claim 14 and the use according to claim 15.

[0014] Further details are set out in the dependent patent claims. Brief description of the invention

[0015] According to one embodiment of a first feature of the present invention, a semiconductor stack according to claim 1 is provided for performing at least one logical operation. Such a semiconductor stack can, for example, comprise the following: adjacent layers arranged in a stacked configuration, each layer comprising at least one phase-change memory cell in which a phase-change material is provided between an electrical heating terminal and at least two further electrical heating terminals, wherein the phase-change material is provided between the electrical heating terminal and each of the two further electrical heating terminals, and wherein the phase-change material between the electrical heating terminal and each of the two further electrical heating terminals is to operate in one of at least two reversibly convertible phases, an amorphous phase and a crystalline phase.wherein the semiconductor stack, when in use, is configurable to store information by means of an electrical resistance of the phase of the phase-change material between each electrical heater terminal and each of the two other electrical heater terminals in each layer, and the logical operation is performed based on the information stored in the adjacent layers. Some advantages that may be associated with embodiments of the present invention, compared to previously proposed units and / or techniques using transistors, include: an alternative to performing logical operations with transistors is provided; improved performance and / or efficiency, since connections between the adjacent layers are not necessary.the phase-change memory cells of these and / or the electrical connections belonging to the phase-change memory cells can be made possible without wire connections; and relatively simple realization and fabrication compared to previously proposed units and / or techniques in which an electrical circuit is used in which several transistors are wired together to perform a given logic operation. Also, since the adjacent layers are provided in a stacked configuration, this can enhance the advantage of increased unit density in a scenario where an embodiment of the present invention is integrated into or used in conjunction with a unit / electrical circuit for performing logic operations. It should be noted with regard to an embodiment of the present invention that information corresponding to a given logic input,stored by means of an electrical resistance belonging to the amorphous or crystalline phase of the phase-change material provided between each electrical heating terminal and each of the two other electrical heating terminals in each layer. Since the amorphous and crystalline phases of the phase-change material are non-volatile, a separate step for loading logical inputs on which a logical operation is to be performed, and / or memory space / storage for the logical inputs and / or the logical output with respect to a given manifestation of the logical operation being performed, may not be provided in one embodiment of the present invention.

[0016] Preferably, the logical operation performed corresponds to a read operation in which the information stored in the adjacent layers between a group of read ports is read. Compared with previously proposed units and / or techniques, this feature can offer the advantage of simple execution of a logical operation because a logical operation is performed directly via a read operation carried out between a group of read ports that are a component in an embodiment of the present invention.

[0017] Desirably, logical inputs 1 and 0 are represented by the electrical resistances of the amorphous and crystalline phases, respectively, of the phase-change material provided between the electrical heating terminal and each of the two other electrical heating terminals in the phase-change memory cell of each of the adjacent layers. This feature can enhance the performance advantage of an embodiment of the present invention, since the logical inputs 1 and 0 can be effectively distinguished from one another based on the electrical resistances of the amorphous and crystalline phases of the phase-change material, which typically differ by several orders of magnitude.For the present implementation of an embodiment of the present invention, the logical operation performed preferably comprises a given logical OR operation, which corresponds to a form of the read operation that involves reading the information stored in the adjacent layers along at least one path between the group of read terminals. Furthermore, in the present implementation of an embodiment of the present invention, the logical operation performed desirablely comprises a logical AND operation, wherein each of the logical inputs of the logical AND operation is generated in a different form of the read operation that involves reading the information stored in the adjacent layers along a given path between the group of read terminals.

[0018] Preferably, a selected group of read ports is used for the read operation. In one embodiment of the present invention, various logical operations can be performed depending on the selection made for the group of read ports to be used for the read operation.This feature extends the advantage of increasing the density of electrical / logic circuits into which an embodiment of the present invention can be integrated, compared with previously proposed units and / or techniques, particularly using transistors, where typically a single logic operation can be performed by a dedicated electrical circuit having several connected transistors; therefore, several such dedicated electrical circuits may be required to perform the logic operations that are possible with an embodiment of the present invention by selecting different groups of read terminals.

[0019] Desirably, in one embodiment of the present invention, the logical operation performed is carried out simultaneously with a write operation performed with respect to write ports provided on a write path of the adjacent layers, wherein, according to the logical operation, a given format of the information stored on at least one memory path with respect to the adjacent layers is modified. This feature is associated with a write operation performed in one embodiment of the present invention; it provides an alternative path on which, in one embodiment of the present invention, a logical operation with respect to the adjacent layers can be performed.It can enhance the adaptability and efficiency of an embodiment of the present invention because a given format of information stored in the adjacent layers can be modified by the logical operation performed simultaneously with the write operation. Such modification of the information is enabled without a two-step approach, wherein: a logical operation is performed to locate where the information in the adjacent layers is to be modified, and a corresponding write operation is performed to enable a desired modification of the information stored at that location. With respect to the embodiment of the present invention described herein, preferably at least one write terminal is configurable to receive a crystallizing voltage pulse relative to another write terminal.In this context, the write terminals can be the electrical heating terminals and the other electrical heating terminals that span the adjacent layers or are part of one of the adjacent layers. By configuring at least one of the write terminals to receive a crystallizing pulse with respect to another write terminal, a logical operation is simultaneously performed, whereby, for a given format of information stored on at least one memory path with respect to the adjacent layers, the phase of the phase-change material provided between at least one of the electrical heating terminals and another electrical heating terminal of the phase-change memory cell in one of the adjacent layers can be changed from the amorphous phase to the crystalline phase.This feature can enhance the advantage of simplicity with which a modification of the stored information is enabled in one embodiment of the present invention. Furthermore, in the embodiment described here, information is desirablely stored as modified by the logical operation being performed and stored at the location where it is modified. In one embodiment of the present invention, the logical operation, performed concurrently with the write operation, modifies the information stored in the adjacent layers for a given format used for information storage. The modified information corresponds to the logical output of the logical operation being performed and is stored at the location where the modification of the information by the logical operation has been effected.This feature eliminates the need to provide additional resources in the form of space / memory for storing the logical output of the logical operation being performed. Furthermore, in one embodiment of the present invention, logic and memory functionalities are combined.

[0020] Preferably, the two additional electrical heating connections for the corresponding phase-change storage cells of the adjacent layers are provided jointly. This feature can extend the advantages of simple manufacturing and / or implementation, including space savings, since no separate manufacturing steps / structures / features need to be introduced to provide each phase-change storage cell with its own pair of the two additional electrical heating connections in one embodiment of the present invention.

[0021] Desirably, for the reconfiguration of logical operations, the information stored between at least one electrical heating terminal and one of the two other electrical heating terminals in the phase-change memory cell in one of the adjacent layers is modified. In one embodiment of the present invention, the logical operations performed depend on how the information is stored in the adjacent layers and are thus different for different formats used for such information storage. By modifying the information stored in at least one of the adjacent layers, for example, in the electrical heating terminal and one of the two other electrical heating terminals of that terminal, a different format for information storage in the adjacent layers is enabled.Thus, the logical operations that can be performed with respect to an embodiment of the present invention are reconfigurable. This feature extends the advantage of simplified execution of various logical operations and increased adaptability for an embodiment of the present invention.

[0022] According to a further embodiment of the present invention, a matrix according to claim 11 is provided which has several semiconductor stacks, wherein each semiconductor stack corresponds to embodiments of the first embodiment of the present invention, wherein the several semiconductor stacks are provided stacked in electrical contact with each other and relative to each other.Some advantages that may be associated with such an embodiment of the present invention include: each semiconductor stack can be used to store different information; each semiconductor stack can be configured to perform different logical operations based on the information stored in each stack and the group of read terminals selected to perform the read operation in that stack; and a timing feature can be introduced by having each stack perform its intended read operation at a given time relative to when the other stacks in the matrix perform their associated logical operations. Due to the stack arrangement of the multiple semiconductor stacks, increased unit density and easier incorporation into / integration with other units and / or techniques may be possible.

[0023] Desirably, the multiple semiconductor stacks are arranged stacked on top of each other, adjacent to each other, or in a combination of both. Preferably, the multiple semiconductor stacks are stacked three-dimensionally relative to each other. These features can enable the incorporation / integration of an embodiment of the present invention into units / electrical circuits in a desired manner with regard to unit density and space constraints.

[0024] According to one embodiment of a method manifestation of the present invention, a method according to claim 14 is provided for performing a logical operation with a semiconductor stack. Such a stack can, for example, comprise the following: adjacent layers arranged in a stacked configuration, each layer comprising at least one phase-change memory cell in which a phase-change material is provided between an electrical heating terminal and at least two further electrical heating terminals, wherein the phase-change material between the electrical heating terminal and each of the two further electrical heating terminals is to operate in one of at least two reversibly convertible phases, an amorphous phase and a crystalline phase, wherein a method carried out using the exemplary semiconductor stack,for example, it includes the following steps: storing information by means of an electrical resistance of the phase of the phase-change material between each electrical heating terminal and each of the two other electrical heating terminals in each layer, and performing the logical operation based on the information stored in the adjacent layers.

[0025] A corresponding use is also provided, and thus, according to one embodiment of a use of the present invention, a use according to claim 15 of a semiconductor stack for performing at least one logical operation is provided. Such a semiconductor stack can, for example, have the following: adjacent layers arranged in a stacked configuration, each layer having at least one phase-change memory cell in which a phase-change material is provided between an electrical heating terminal and at least two further electrical heating terminals, wherein the phase-change material between the electrical heating terminal and each of the two further electrical heating terminals is to operate in one of at least two reversibly convertible phases, an amorphous phase and a crystalline phase, wherein the exemplary semiconductor stack,When in use, it is configurable to store information by means of an electrical resistance of the phase of the phase-change material between each electrical heating terminal and each of the two other electrical heating terminals in each layer, and the logical operation is performed on the basis of the information stored in the adjacent layers.

[0026] According to one embodiment, the logical operation performed corresponds to a read operation in which the information stored in the adjacent layers between a group of read terminals is read.

[0027] According to one embodiment, a semiconductor stack is used for the read operation, wherein a selected group of read terminals is used.

[0028] Features of one embodiment can be applied to another embodiment, and vice versa. Each disclosed embodiment can be combined with one or more of the other illustrated and / or described embodiments. This is also possible for one or more features of the embodiments. Brief description of the drawings

[0029] Reference is now made, by way of example, to the accompanying drawings, in which: Fig. 1 shows an embodiment of the present invention and Fig. 2 shows another embodiment of the present invention. Detailed description of the preferred embodiments of the present invention

[0030] Within the description, the same reference numbers or symbols have been used to identify the same parts or similar items.

[0031] As in Fig. As shown in Figure 1, in one embodiment of the present invention, a semiconductor stack 1 is provided for performing at least one logical operation. The semiconductor stack 1 has adjacent layers 2, 2' arranged in a stacked configuration, each layer 2, 2' having at least one phase-change memory cell. For each of the phase-change memory cells in the adjacent layers 2, 2', a phase-change material 3 is provided between an electrical heating terminal T2, T9 and at least two further electrical heating terminals T5, T6. As already mentioned above, the phase-change material 3 is to be operated in one of at least two reversibly convertible phases, an amorphous phase 3' and a crystalline phase 3".In the amorphous phase 3', the phase-change material 3 exhibits a noticeably higher electrical resistance than in its crystalline phase 3"; the difference in electrical resistance between the corresponding phases is typically two to three orders of magnitude, and up to five orders of magnitude. For example, a suitably chosen germanium-antimony-tellurium alloy can be used for the phase-change material 3.

[0032] For the corresponding phase-change storage cells of the adjacent layers 2, 2', the electrical heating connection T2, T9 is provided on a first surface 4' of the phase-change material 3, and the two further electrical heating connections T5, T6 are provided on a second surface 4" which is arranged opposite the first surface 4' of the phase-change material 3. The two further electrical heating connections T5, T6 are provided jointly for / used jointly by the corresponding phase-change storage cells of the adjacent layers 2, 2'.

[0033] The electrical heating terminals T2, T9 are electrically connected to each of the two further electrical heating terminals T5, T6. The electrical heating terminals T9, T2 and the further electrical heating terminals T5, T6 can, for example, be made of titanium nitride or tungsten, and they can be electrically insulated from each other by means of an insulator 5, which is selected to be a material that preferably has both electrical and thermal insulating properties, such as silicon nitride or silicon oxide.

[0034] In use, one embodiment of the present invention is configurable such that in each of the adjacent layers 2, 2', information about the phase 3", 3' of the phase-change material 3 is stored by means of an electrical resistance R2, R8, R3, R9 between the electrical heating terminal T2, T9 and each of the two further electrical heating terminals T5, T6. A desired phase 3", 3' of the phase-change material 3 between any of the electrical heating terminals T2, T9 and any of the two further electrical heating terminals T5, T6 can be enabled by applying a given phase-changing signal, for example, a voltage pulse, between the aforementioned electrical terminals. The logical operation that is performed is based on the information R2, R8, R3, R9 stored in the adjacent layers 2, 2', as already described above.

[0035] In a first variation of an embodiment of the present invention, the logical operation performed corresponds to a read operation in which the information R2, R8, R3, R9, stored in the adjacent layers 2, 2' between a group of read terminals T2-T9 and T5-T6, is read. The information stored in the adjacent layers 2, 2' is used to represent the logical inputs with respect to the logical operation performed via the read operation. Thus, the logical inputs 1 and 0 can be represented by the electrical resistances R2, R8, R3, R9 of the amorphous phase 3' and the crystalline phase 3" of the phase-change material 3, respectively, which is provided between the electrical heating terminal T2, T9 and each of the two further electrical heating terminals T5, T6 in the phase-change memory cell of each of the adjacent layers 2, 2'.

[0036] The group of read terminals T2-T9; T5-T6 can have a pair of electrical terminals in the semiconductor stack 1, with a combination of these being chosen to be different from each combination of the electrical terminals T2-T5, T5-T9, T2-T6, T6-T9 between which the information R2, R8, R3, R9 is stored in the corresponding phase-change memory cells of the adjacent layers 2, 2'. The read operation and the corresponding logical operation performed depend on a chosen selection of the read terminals T2-T9; T5-T6. In this respect, a read signal can be propagated such that each path T2-T5-T9, T2-T6-T9; T5-T9-T6, T5-T2-T6 between the selected group of read terminals T2-T9; T5-T6 is accessed simultaneously.Each such path T2-T5-T9, T2-T6-T9; T5-T9-T6, T5-T2-T6 has a route between the group of read terminals T2-T9; T5-T6 in which information R2, R8, R3, R9 is stored in the adjacent layers 2, 2'. The electrical resistances R2, R8, R3, R9 on a path T2-T5-T9, T2-T6-T9; T5-T9-T6, T5-T2-T6 between the group of read terminals T2-T9; T5-T6 are connected in series. With respect to multiple paths between the group of read terminals T2-T9; T5-T6, the electrical resistances R2, R8; R8, R9 on one of the multiple paths T2-T5-T9, T5-T9-T6 are connected in parallel with the electrical resistances R3, R9; R2, R3 are connected via another of the several paths T2-T6-T9, T5-T2-T6 between the selected group of read ports T2-T9; T5-T6.

[0037] In the first variation of an embodiment of the present invention, as described above, the logical operation can comprise a given logical OR operation, which corresponds to a form of the read operation in which the information stored in the adjacent layers 2, 2' is read along at least one path T2-T5-T9, T2-T6-T9; T5-T9-T6, T5-T2-T6 between the group of read terminals T2-T9; T5-T6. Furthermore, and in respect of another form of the read operation, the logical operation performed can comprise a logical AND operation, wherein each of the logical inputs of this operation is generated by reading the information stored in the adjacent layers 2, 2' along a given path between T2-T5-T9, T2-T6-T9; T5-T9-T6, T5-T2-T6 between the group of read terminals T2-T9; T5-T6.

[0038] In order to gain an understanding of the first variation of an embodiment of the present invention, and with reference to Fig. Logical inputs 1 and 0 are represented by the electrical resistances of the amorphous phase R3, R9, 3' and the crystalline phase R2, R8, 3'', by means of which information is stored in the adjacent layers 2, 2'. A given logical OR operation is performed on the logical inputs 1, 0, which correspond to the series-connected electrical resistances along a path between the group of read terminals, in which information between the adjacent layers 2, 2' is stored.The logical AND operation is performed for the electrical resistors on one path between the group of read terminals, which are connected in parallel to the electrical resistors on another path between the group of read terminals, wherein each of the logical inputs for the logical AND operation is generated in a corresponding logical OR operation, which is performed for each of the paths between the group of read terminals, as already described above. Thus, with reference to . Fig. 1. A read operation between the group of read ports T2 and T9 corresponds to the logical operation: (R2 OR R8) AND (R3 OR R9), which yields a logical output of 0, and a read operation between the group of read ports T5 and T6 corresponds to the logical operation: (R2 OR R3) AND (R8 OR R9), which yields a logical output of 1. Thus, different logical operations can be performed on the same information stored between adjacent layers 2 and 2' using different groups of read ports.

[0039] In a second variation of an embodiment of the present invention, a write operation is performed using the write terminals T5-T9, which are provided on a write path T2-T5-T9 of the adjacent layers 2, 2'. Simultaneously with the write operation, a logical operation is performed according to which the information stored in a given format on a given memory path T2-T6-T9 in the adjacent layers 2, 2' is modified. As described above with reference to Fig. As already explained in general terms, information can be stored on the given memory path T2-T6-T9 with the electrical resistances R3, R9, which can correspond to the amorphous 3' and crystalline 3" phases of the phase-change material 3, provided between the corresponding combination of electrical heating terminals T2, T9 and another electrical heating terminal T6 on the given memory path T2-T6-T9. In the present example, the logical values ​​1, 0 are used accordingly to represent the amorphous phase 3' and the crystalline phase 3" respectively. The information R3, R9, which is stored on the given memory path T2-T6-T9, can have the logical inputs 1, 0 of a logical AND operation, which is performed concurrently with the write operation.During the write operation, a crystallizing voltage pulse V1 can be applied to write terminals T2 and T5 relative to another write terminal T9 on the write path T2-T5-T9, while terminal T6 remains suspended on the given memory path T2-T6-T9. The logical AND operation, performed concurrently with the write operation, modifies the information R3 and R9 stored on the given memory path T2-T6-T9. The modified information has the logical output 1 and 0 of the logical AND operation; it is stored at the location on the given memory path T2-T6-T9 where the modification occurred.

[0040] For the crystallizing voltage pulse V1, applied during the write operation as mentioned above, and for the information stored on the given memory path T2-T6-T9 by corresponding electrical resistors R3, R9, which represent logical input combinations 1, 1 or 0, 0, the information stored on the given memory path T2-T6-T9 is not modified as a result of the logical AND operation performed simultaneously with the write operation. Instead, only where the corresponding electrical resistors R3, R9 represent the logical input combination 0, 1 or 1, 0, does the execution of the write operation, as described above, cause a modification of this electrical resistance R3, R9 on the given memory path, which corresponds to changing the amorphous phase 3', logical value 1, into the crystalline phase 3", logical value 0.The modified information R3, R9, 3" corresponds in this case to the logical output 0 of the logical AND operation. The modified information is stored again at the point where the modification of the information was effected by the logical AND operation, i.e., by means of the modified electrical resistance R3, R9 between the corresponding combination of electrical heating terminal T2, T9 and the further electrical heating terminal T6 on the memory path T2-T6-T9, which spans the adjacent layers 2, 2'.

[0041] The second variation of an embodiment of the present invention is of course not limited to the example given above, and indeed a modification of the information stored on any desired memory path in one or both of the adjacent layers 2, 2' by performing a write operation with respect to a suitably chosen write path / suitably chosen write terminals is also within the scope of the present invention.

[0042] According to another embodiment of the present invention, as in Fig. As shown in Figure 2, a matrix 100 is provided which has several semiconductor stacks 1, 10 that are stacked in electrical contact with each other and relative to each other. Each of the semiconductor stacks 1, 10 in the matrix 100 has features and advantages which correspond to an embodiment of the present invention as described in Figure 2. Fig. 1 is described. Thus, the semiconductor stack has 10 adjacent layers 2, 2', each layer 2, 2' having a phase-change memory cell. Each phase-change memory cell has a phase-change material 3 provided between an electrical heating terminal T10, T3 and two further electrical heating terminals T6, T7, the electrical heating terminals T10, T3 being in electrical communication with each of the two further electrical heating terminals T6, T7. As in the example of the Fig. As can be seen in Figure 2, the information stored by means of the electrical resistors R4 and R10 corresponds to a logical input of 0, and the electrical resistors R5 and R11 correspond to a logical input of 1.

[0043] In the example that is in Fig. As shown in Figure 2, all semiconductor stacks 110 are arranged adjacent to one another; they share the additional electrical heating connection T6 between them. Although not shown, in a variation of an embodiment of the present invention, the multiple semiconductor stacks 1, 10 can be arranged stacked on top of one another. For example, and with reference to the structural features of the semiconductor stacks 1, 10, as shown in Figure 2, the semiconductor stacks 1, 10 can be arranged in a manner that allows for the arrangement of the semiconductor stacks 1, 10 ... Fig.As shown in Figure 2, the semiconductor stack 10, which is provided on the semiconductor stack 1, uses a common electrical heating connection between them. In this example, this connection can be electrical heating connection T9 of the semiconductor stack 1 or T3 of the semiconductor stack 10. In a further variation of an embodiment of the present invention, the stack arrangements described above can be combined to obtain a two-dimensionally stacked matrix 100, which has at least one semiconductor stack 1 with corresponding semiconductor stacks 10 provided on or adjacent to it. In this respect, and by way of example, at least two structural features, namely one of the electrical heating connections T9, T3 and one of the two further electrical heating connections T6, are used jointly by the stacks 1 and 10 in this arrangement.In yet another variation of an embodiment of the present invention, the multiple semiconductor stacks 1, 10 can be stacked three-dimensionally relative to each other.

[0044] In one embodiment of the present invention, the logical operations performed depend on the information R2, R8, R3, R9 stored in the adjacent layers 2, 2'. To enable reconfiguration of the logical operation, the information stored between at least one electrical heating terminal T2, T9 and one of the two further electrical heating terminals T5, T6 in the phase-change memory cell in one of the adjacent layers 2, 2' is modified.

[0045] One embodiment of the present invention is not limited to the read operation initiated from a given read port. Also included within the scope of the present invention is when a logical input 1 is represented by the electrical resistance of the crystalline phase of the phase-change material between a given group of write ports, and when a logical input 0 is represented by the electrical resistance of the amorphous phase of the phase-change material between a given group of write ports.

Claims

[1] Semiconductor stack (1) for performing at least one logical operation, comprising: adjacent layers (2, 2') arranged in a stacked configuration, each layer (2, 2') comprising at least one phase-change memory cell in which a phase-change material (3), on one of whose opposite faces (4') a first electrical heating terminal (T2, T9) is provided and on whose other opposite faces (4'') at least two further electrical heating terminals (T5, T6) are provided, is operable between the first electrical heating terminal (T2, T9) and each of the two further electrical heating terminals (T5, T6) in one of at least two reversibly convertible phases, an amorphous phase (3') and a crystalline phase (3''), wherein the adjacent layers (2, 2') share the at least two further electrical heating terminals (T5, T6), wherein the semiconductor stack is configured for this purpose,that it stores information by means of an electrical resistance (R2, R8, R3, R9) of the phase (3", 3') of the phase-change material (3) between the at least one first electrical heating terminal (T2, T9) and each of the two further electrical heating terminals (T5, T6) in the adjacent layers (2, 2'), and the logical operation is executable on the basis of the information (R2, R8, R3, R9) stored in the adjacent layers (2, 2'). [2] Semiconductor stack (1) according to claim 1, wherein the logical operation that can be performed is a read operation in which the information (R2, R8, R3, R9) is read which is stored in the adjacent layers (2, 2') between a group of read terminals (T2-T9; T5-T6). [3] Semiconductor stack (1) according to claim 2, wherein logic inputs 1 and 0 are represented by the electrical resistances (R2, R8, R3, R9) of the amorphous phase (3') and the crystalline phase (3") of the phase change material (3) provided between the electrical heating terminal (T2, T9) and each of the two further electrical heating terminals (T5, T6) in the phase change memory cell of each of the adjacent layers (2, 2'). [4] Semiconductor stack (1) according to claim 2 or 3, wherein the logical operation that can be performed comprises a given logical OR operation corresponding to a manifestation of the read operation comprising reading the information stored in the adjacent layers (2, 2') along at least one path (T2-T5-T9, T2-T6-T9; T5-T9-T6, T5-T2-T6) between the group of read terminals (T2-T9; T5-T6). [5] Semiconductor stack (1) according to claim 2, 3 or 4, wherein the logical operation that can be performed comprises a logical AND operation, wherein each of the logical inputs of the logical AND operation is generated in a different manifestation of the read operation, which comprises reading the information stored in the adjacent layers (2, 2') along a given path (T2-T5-T9, T2-T6-T9; T5-T9-T6, T5-T2-T6) between the group of read terminals (T2-T9; T5-T6). [6] Semiconductor stack (1) according to claim 1, wherein the logical operation that can be performed is carried out simultaneously with a write operation that is performed with respect to write terminals (T5-T9) provided on a write path of the adjacent layers (2, 2'), wherein a given format of the information stored on at least one memory path (T2-T6-T9) with respect to the adjacent layers (2, 2') is modified according to the logical operation. [7] Semiconductor stack (1) according to claim 6, wherein at least one write terminal (T5) is configurable to receive a crystallizing voltage pulse (V1) relative to another write terminal (T9). [8] Semiconductor stack (1) according to claim 6 or 7, which is configurable to store information as such and at the location where it is located, modified by the logical operation performed. [9] Semiconductor stack (1) according to one of the preceding claims, wherein the two further electrical heating terminals (T5, T6) are provided jointly for the corresponding phase-change memory cells of the adjacent layers (2, 2'). [10] Semiconductor stack (1) according to one of the preceding claims, wherein for the reconfiguration of logic operations the information stored between at least one electrical heating terminal (T2, T9) and one of the two further electrical heating terminals (T5, T6) in the phase-change memory cell in one of the adjacent layers (2, 2') is changeable. [11] Matrix (100) comprising several semiconductor stacks, wherein each semiconductor stack (1, 10) is configured as in any one of claims 1 to 10, wherein the several semiconductor stacks (1, 10) are provided stacked in electrical contact with each other and relative to each other. [12] Matrix (100) according to claim 11, wherein the multiple semiconductor stacks (1, 10) are provided as stacked on top of each other, adjacent to each other or in a combination thereof. [13] Matrix (100) according to claim 11 or 12, wherein the multiple semiconductor stacks (1, 10) are stacked three-dimensionally relative to each other. [14] Method for performing a logic operation with a semiconductor stack (1) having adjacent layers (2, 2') arranged in a stacked configuration, wherein each layer (2, 2') has at least one phase-change memory cell in which a phase-change material (3), on one of whose opposite faces (4') a first electrical heating terminal (T2, T9) is provided and on whose other opposite faces (4'') at least two further electrical heating terminals (T5, T6) are provided, is operable between the first electrical heating terminal (T2, T9) and each of the two further electrical heating terminals (T5, T6) in one of at least two reversibly convertible phases, an amorphous phase (3') and a crystalline phase (3''), wherein the adjacent layers (2, 2') share the at least two further electrical heating terminals (T5, T6),wherein the method comprises the following steps: storing information by means of an electrical resistance (R2, R8, R3, R9) of the phase (3", 3') of the phase-change material (3) between the at least one first electrical heating terminal (T2, T9) and each of the two further electrical heating terminals (T5, T6) in the adjacent layers (2, 2') and performing the logical operation on the basis of the information stored in the adjacent layers (2, 2'). [15] Use of a semiconductor stack (1) for performing at least one logic operation, wherein the semiconductor stack (1) comprises: adjacent layers (2, 2') arranged in a stacked configuration, each layer (2, 2') comprising at least one phase-change memory cell in which a phase-change material (3), on one of whose opposite faces (4') an electrical heating terminal (T2, T9) is provided and on whose other of the opposite faces (4'') at least two further electrical heating terminals (T5, T6) are provided, is to be operated between the first electrical heating terminal (T2, T9) and each of the two further electrical heating terminals (T5, T6) in one of at least two reversibly convertible phases, an amorphous phase (3') and a crystalline phase (3''), wherein the adjacent layers (2, 2') have the at least two further electrical heating terminals (T5, T6) connected to each other.T6), wherein the semiconductor stack is configured to store information by means of an electrical resistance (R2, R8, R3, R9) of the phase (3", 3') of the phase-change material (3) between each electrical heating terminal (T2, T9) and each of the two other electrical heating terminals (T5, T6) in each layer (2, 2'), and the logical operation is executable on the basis of the information stored in the adjacent layers (2, 2').

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