Processor, method, and processing system for instructions and logic for providing enhanced paging capabilities for secure enclave page caches

Abstract

A processor includes: a first hardware thread and a second hardware thread; a cache for storing secure data in a cache line for a common page address assigned to a respective secure enclave comprising a set of information and processing capabilities protected as a group and accessible to said first and second hardware threads; a decode stage to decode a first instruction for execution by said processor, the first instruction specifying said common page address as an operand, and to decode a second instruction for execution by said processor, the second instruction specifying said secure enclave as an operand, and to decode a third instruction for execution by said processor, the third instruction specifying said common page address as an operand; one or more execution units that respond to the decoded first instruction to: mark an entry corresponding to a cache mapping for the shared page address to block the creation of a new translation for either said first or second hardware threads to access secure data corresponding to the shared page address; wherein the one or more execution units respond to the decoded second instruction to: to record hardware threads that are currently accessing secure data in the cache corresponding to the Secure Enclave, wherein an inter-processor interrupt (IPI) is sent to hardware threads that are currently accessing secure data in the cache corresponding to the Secure Enclave, wherein a recorded number of hardware threads is decremented in response to the hardware threads leaving the Secure Enclave; and wherein the one or more execution units respond to the decoded third instruction to: to flush and write back secure data in the cache according to the shared page address when the recorded number of hardware threads currently executing in the Secure Enclave reaches zero.

Description

FIELD OF THE DISCLOSUREThe present disclosure relates to the field of processing logic, microprocessors, and associated instruction set architecture that, when executed by the processor or other processing logic, performs logical, mathematical, or other functional operations. The disclosure relates more particularly to instructions and logic for providing enhanced paging capabilities for secure enclave page caches.BACKGROUND OF THE DISCLOSUREApplications and high performance networks to support new usage models and services such as voice, video, transactions, and private data present new challenges in the field of security. The need to protect stored or transmitted data for confidentiality and integrity reasons is important, however, the support of high speed encryption and storage required for secure access to protected code and / or data results in higher complexity and ultimately higher cost.One method of creating and managing a secured, protected, or isolated partition or environment is creating an enclave. An enclave is a set of information and processing capabilities that are protected as a group. The information and processing capabilities may include networks, hosts, or applications.A commonly used processing method to access data and / or instructions is via caches that support virtual memories, e.g., by using a translation lookaside buffer (TLB) that quickly executes translations in hardware according to the assignments of linear addresses to physical memory addresses found in the page tables. Entries in the TLB may be associated with one or more particular processor cores, hardware threads, or logical processors. This may protect the data that may be accessed in a cache from access by unauthorized processor cores, hardware threads, or logical processors.Management of permissions, physical storage, and / or change of assignments in page tables is usually adopted by an operating system (OS), but when the storage contents are protected, e.g., as in an enclave, the OS may not be authorized or trusted to access the actual protected contents, i.e., the enclave has private storage. Ensuring the security and / or integrity of private memory contents and managing the technical constraints of limited physical memory without being able to trust an OS therefore presents a number of very special challenges with regard to security and performance.To date, security solutions addressing these challenges and potential solutions to such performance limiting problems, as well as design, validation, and other complications have not been adequately studied.US 2012 / 0159184 A1 discloses a technique for enabling secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed. However, this can lead to a prolonged blockage of the processor core or hardware thread.Bovie, Rick: IBM Research Report. In: IBM. NY (USA): SecureBlue++: CPU Support for Secure Execution. 23.05.2012 (RC25287 (WAT120-070)), pp. 1-9, discloses a secure processor architecture that enables verifierable, secure applications. The architecture protects the confidentiality and integrity of information in an application, so that other software cannot access this information.The invention disclosed here is based on the object of protecting data in an enclave from access by third parties during its write-back. This object is achieved by the subject matter of the independent claims.BRIEF DESCRIPTION OF THE DRAWINGSThe present invention is illustrated by way of example in the figures of the accompanying drawings and is in no way restrictive. FIG. 1A is a block diagram of one embodiment of a system executing instructions to provide enhanced paging capabilities for secure enclave page caches. FIG. 1B is a block diagram of another embodiment of a system executing instructions to provide enhanced paging capabilities for secure enclave page caches. FIG. 1C is a block diagram of another embodiment of a system executing instructions to provide enhanced paging capabilities for secure enclave page caches. FIG. 2 is a block diagram of one embodiment of a processor executing instructions to provide enhanced paging capabilities for secure enclave page caches. FIG. 3A illustrates packed data types, according to an embodiment. FIG. 3B illustrates packed data types, according to an embodiment. FIG. 3C illustrates packed data types, according to an embodiment. FIG. 3D illustrates instruction encoding, providing improved paging capabilities for secure enclave page caches, according to one embodiment. FIG. 3E illustrates instruction encoding providing improved paging capabilities for secure enclave page caches, according to another embodiment. FIG. 3F illustrates instruction encoding providing improved paging capabilities for secure enclave page caches, according to another embodiment. FIG. 3G illustrates instruction encoding providing improved paging capabilities for secure enclave page caches, according to another embodiment. FIG. 3H illustrates instruction encoding, thereby providing improved paging capabilities for secure enclave page caches, according to another embodiment. FIG. 4A illustrates elements of an embodiment processor microarchitecture executing instructions that provide enhanced paging capabilities for secure enclave page caches. FIG. 4B illustrates elements of another embodiment of a processor microarchitecture executing instructions that provide enhanced paging capabilities for secure enclave page caches. FIG. 5 is a block diagram of one embodiment of a processor executing instructions to provide enhanced paging capabilities for secure enclave page caches. FIG. 6 is a block diagram of one embodiment of a computer system executing instructions to provide enhanced paging capabilities for secure enclave page caches. FIG. 7 is a block diagram of another embodiment of a computer system executing instructions to provide enhanced paging capabilities for secure enclave page caches. Figure 8 is a block diagram of another embodiment of a computer system executing instructions to provide enhanced paging capabilities for secure enclave page caches. FIG. 9 is a block diagram of one embodiment of a system-on-a-chip (system-on-a-chip) system executing instructions to provide enhanced paging capabilities for secure enclave page caches. Figure 10 is a block diagram of one embodiment of a processor executing instructions to provide enhanced paging capabilities for secure enclave page caches. Figure 11 is a block diagram of one embodiment of an IP core development system that provides enhanced paging capabilities for secure enclave page caches. FIG. 12 illustrates an embodiment of an architectural emulation system that provides enhanced paging capabilities for secure enclave page caches. FIG. 13 illustrates an embodiment of a system for translating instructions that provide enhanced paging capabilities for secure enclave page caches. FIG. 14 illustrates an embodiment of a processing system for using instructions to provide enhanced paging capabilities for secure enclave page caches. FIG. 15 illustrates an embodiment of an apparatus in a processor for using instructions to provide enhanced paging capabilities for secure enclave page caches. FIG. 16 illustrates a flow diagram of an embodiment of a process for providing enhanced paging capabilities for secure enclave page caches. FIG. 17 illustrates a flow diagram of an alternative embodiment of a process for providing enhanced paging capabilities for secure enclave page caches. FIG. 18A illustrates a flow diagram of another embodiment of a process for providing enhanced paging capabilities for secure enclave page caches. FIG. 18B illustrates a flow diagram of another embodiment of a process for providing enhanced paging capabilities for secure enclave page caches.DETAILED DESCRIPTIONThe following description discloses instructions and processing logic to provide improved paging capabilities for secure enclave page caches within or in connection with a processor, computer system, or other processing device.In a particular cache or part of a cache that contains exclusively private or protected data, e.g. associated with an enclave, access to that private or protected data, if unencrypted, may be restricted to only authorized processor cores, hardware threads, or logical processors. Such a private enclave memory may be referred to as an enclave page cache (EPC).As with other physical memories, the EPC may be used to support a larger private or protected address space by including or removing data and / or code into the page table as needed. The change of assignments of pages is usually taken over by an OS, but in an enclave the OS does not necessarily have access to the contents of the private enclave memory.Entries in the TLB are associated with one or more special processor cores, hardware threads, or logical processors that may not be allowed to change a page as it is read out to memory or persistent storage. For this reason, changing the assignments of pages for an enclave, e.g., removing a page or loading a new page for the enclave, may require the system to "sleep" the one or more processor cores, hardware threads, or logical processors that access the enclave's resources by bringing them into a temporarily inactive or suppressed state, or otherwise disable execution of application(s) in the enclave while encrypting and rewriting the contents of the EPC memory, load and decrypt new pages from memory, flush and replace the TLB entries, etc. Hardware protection mechanisms may be required, This is to protect the pages in the EPC to ensure the security and / or integrity of private storage content, and to support the management of a restricted physical private storage without being able to trust the OS.An exemplary secure enclave approach is described in pending U.S. Patent Application entitled "Method and Apparatus to Provide Secure Application Execution," (Method and Apparatus for Providing Secure Application Execution), filed Jun. 19, 2012, Serial No. 13 / 527,547.Each time a page is removed from the EPC memory, this may result in a message to all processor cores or logical processors utilizing the EPC memory and / or all processor cores or logical processors being requested to exit the enclave to replace the page contents, the TLB entry, and the TLB entries, respectively, etc. Moreover, ensuring in the hardware that such a requirement is met to protect the privacy of the enclave may involve significant design and validation complications.It is understood that if the paging process, e.g., if the EPC memory contents are encrypted and written back, new pages are loaded from memory and decrypted, the TLB entries are flushed and replaced, etc., may be divided into stages in which the processor cores or logical processors are interrupted only briefly during one or more stage(s), the performance degradation due to the paging process may be reduced.Instructions and logic for providing enhanced paging capabilities for secure enclave page caches are described below. Some embodiments include multiple hardware threads, logical processors or processor cores, a cache for storing secure data for common page addresses associated with a secure enclave and accessible by the hardware threads, logical processors or processor cores. A decode stage decrypts a first instruction (e.g., an EBLOCK instruction, discussed in more detail below), the first instruction that sets the common page address as an operand. One or more execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block the creation of a new TLB translation for one of the aforementioned multiple hardware threads, logical processors, or processor cores to access the shared page. A second instruction (e.g., an ETRACK instruction, also discussed in more detail below) is decrypted for execution, the second instruction sets said secure enclave as an operand, and one or more execution units draw the hardware threads that are currently accessing secure data in the enclave page cache corresponding to the secure enclave. When one of the hardware threads exits the secure enclave, the recorded number of hardware threads is decremented.The OS may then send an inter-processor interrupt (IPI) to a hardware thread, logical processor, or processor core that is currently accessing secure data in the enclave page cache corresponding to the secure enclave. When the hardware threads, logical processors, or processor cores acknowledge the IPI and leave the secure enclave, their TLB entry or entries are flushed and the recorded number of hardware threads is decremented. When the recorded number of hardware threads reaches zero, it is safe for the OS to remove, encrypt, and write back to memory or permanent memory. The OS may use a third instruction (e.g., an EWB instruction, also discussed in more detail below) to complete the removal and write-back. Because enclave protection of the secure data may not trust the OS, it is possible that an embodiment of the third instruction fails if the recorded number of hardware threads has not yet reached zero. In an alternative embodiment, the third instruction may wait to execute until the recorded number of hardware threads has reached zero.It is to be understood that the management of permissions, physical storage, and / or the change in assignments is usually still adopted by an OS, but if the storage contents are protected, such as in an enclave, the OS may not be authorized or trusted to access the actual protected contents, as the enclave has private storage. For this reason, ensuring the security and / or integrity of private memory contents and managing the technical constraints of limited physical memory without being able to trust an OS may be accomplished in a stepwise manner using instructions and processing logic to provide enhanced paging capabilities for secure enclave page caches without requiring hardware support and / or design overhead.In the following description, numerous specific details are set forth such as processing logic, processor types, micro-architecture conditions, events, enablement mechanisms, and the like, in order to provide a more thorough understanding of embodiments of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without such specific details. In addition, some well-known structures, circuits, and the like have not been shown in detail in order not to unnecessarily obscure embodiments of the present invention.Although the embodiments below are described with reference to a processor, other embodiments are applicable to other types of integrated circuits and logic units. Similar techniques and teachings of embodiments of the present invention may be applied to other types of circuits or semiconductor devices that may benefit from higher pipelined data throughput and improved performance. The teachings of embodiments of the present invention are applicable to any processor or machine that performs data manipulations. However, the present invention is not limited to processors or machines that perform 512-bit, 256-bit, 128-bit, 64-bit, 32-bit, or 16-bit data operations, and may be applied to any processor or machine in which data manipulations or data management are performed. Moreover, the following description includes examples and the accompanying drawings show various examples for illustrative purposes. However, these examples are not to be understood in a limiting sense as they are intended to be merely examples of embodiments of the present invention, and not an exhaustive list of all possible implementations of embodiments of the present invention.Although the examples below describe instruction processing and distribution in the context of execution units and logic circuits, other embodiments of the present invention may be realized by way of data and / or instructions stored on a machine readable tangible medium that, when executed by a machine, cause the machine to perform functions consistent with at least one embodiment of the invention. In one embodiment, functions associated with embodiments of the present invention are included in machine executable instructions. The instructions may be used to cause a general purpose or special purpose processor programmed with the instructions to perform the steps of the present invention. Embodiments of the present invention may be provided as a computer program product or software, which may comprise a machine- or computer-readable medium having instructions stored thereon, which may be used to program a computer (or other electronic device) to perform(s) one or more operations according to embodiments of the present invention. Alternatively, steps of embodiments of the present invention could be performed by specific hardware components that include fixed function logic for performing the steps, or by any combination of programmed computer components and fixed function hardware components.Instructions used to program logic to perform embodiments of the invention may be stored in memory in the system (such as DRAM, cache, flash memory, or other memory). Additionally, the instructions may be propagated over a network or using other computer readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a machine-readable form (e.g., a computer), but is not limited to, floppy disks, optical drives, CDs, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memories, or a non-transitory machine-readable memory that is used in the transmission of information over the Internet using electrical, optical, optical, or optical, optical, optical, optical, or optical information storage devices associated with the transmission of information over the Internet, However, acoustic or other forms of propagating signals (e.g., carrier waves, infrared signals, digital signals, etc.) may be used. Accordingly, the computer-readable medium includes any type of non-transitory machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).A design may go through several stages, from being created for simulation to fabrication. Data representing a design may represent the design in a number of ways. First, as is useful in simulations, the hardware may be represented using a hardware description language or another function description language. Additionally, a circuit level model with logic and / or transistor gates may be fabricated at some stages of the design process. In addition, most designs eventually reach a data plane representing the physical arrangement of various devices in the hardware model. When conventional semiconductor manufacturing techniques are used, the data representing the hardware model may be the data that specifies the presence or absence of various features on different mask layers for masks used to fabricate the integrated circuit. In a design representation, the data may be stored in the form of a machine readable medium. A memory or magnetic or optical storage medium, such as a disk, may be the machine readable medium to store information transmitted by an optical or electrical wave modulated or otherwise generated to transmit such information. When an electric carrier wave indicating or carrying the code or design is transmitted to an extent that copying, buffering, or retransmission of the electric signal is performed, a new copy is made. Thus, a communication service provider or a network service provider may at least temporarily store, on a tangible machine readable medium, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present invention.In modern processors, a number of different execution units are used to process and execute a variety of code and instructions. Not all instructions are generated similarly, as some may be fully executed more quickly, while others may require a number of clock cycles for full execution. The faster the throughput of instructions, the better the overall performance of the processor. Therefore, it would be advantageous if as many instructions are executed as quickly as possible. However, there are certain instructions that are more complex and require more execution time and processor resources. For example, there are floating point instructions, load / store operations, data moves, etc.As computer systems have been increasingly used in Internet, text and multimedia applications, additional processor support has also been introduced over time. In one embodiment, an instruction set may be associated with one or more computer architectures including data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I / O).In one embodiment, the instruction set architecture (ISA) may be implemented by one or more micro-architectures including processor logic and circuitry used to implement one or more instruction sets. Accordingly, processors with different micro-architectures may share at least a portion of a common instruction set. For example, Intel® Pentium 4 processors, Intel®-Core™ processors, and processors from Advanced Micro Devices, Inc. of Sunnyvale, CA implement nearly identical versions of the x86 instruction set (with some extensions added to more recent versions), but have different internal designs. Similarly, processors designed by other processor development companies, such as ARM Holdings, Ltd., MIPS, or their licensees or users, may share at least a portion of a common instruction set, but may include different processor designs. For example, the same register architecture of the ISA may be implemented in different ways in different microarchitectures using new or well known techniques including dedicated physical registers, one or more physical registers dynamically allocated using a register renaming mechanism (e.g., using a register alias table (RAT), a reorder buffer (ROB), and a reorder register file). In one embodiment, registers may include one or more registers, register architectures, register files, or other instruction sets, which may or may not be addressable by a software programmer.In one embodiment, an instruction may include one or more instruction formats. In one embodiment, an instruction format may indicate various fields (number of bits, location of bits, etc.) to specify, among other things, the operation to be performed and the operand(s) on which the operation is(s) to be performed. Some instruction formats may be further subdivided, defined by instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields and / or defined to have a given field interpreted differently. In one embodiment, an instruction is expressed using an instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and specifies or indicates the operation and operands on which the operation will occur.Scientific, financial, autovectorized general purpose, RMS (recognition, mining, and synthesis), and visual and multimedia applications (e.g., 2D / 3D graphics, image processing, video compression / decompression, speech recognition algorithms, and audio processing) may require that the same operation be performed on a large number of data words. In one embodiment, single instruction multiple data (SIMD) refers to a type of instruction that causes a processor to perform an operation on multiple data elements. SIMD technology may be used in processors that may logically divide the bits in a register into a number of fixed size or variable size data elements, each of which represents a separate value. For example, in one embodiment, the bits in a 64-bit register may be organized as a source operand that includes four separate 16-bit data elements, each representing a separate 16-bit value. This type of data may be referred to as a "packed" data type or "vector" data type, and operands of this data type are referred to as packed data operands or vector operands. In one embodiment, a packed data word or vector may be a sequence of packed data elements stored in a single register, and a packed data operand or vector operand may be a source or destination operand of a SIMD instruction (or 'packed data instruction' or 'vector instruction'). In one embodiment, a SIMD instruction specifies a single vector operation for performing on two source vector operands to generate a destination vector operand (also referred to as a result vector operand) of the same or different size having the same or different number of data elements and in the same or different data element order.SIMD technology, such as that employed in Intel® CoreTM prozessoren having an instruction set including x86, MMXTM, streaming SIMD extension (SSE), SSE2, SSE3, SSE4.1, and SSE4.2 instructions, ARM prozessoren, such as the ARM-Cortex® family of processors having an instruction set including the vector floating point (VFP) and / or NEON instructions, and MIPS prozessoren, such as the Loongson family of processors, As developed by the Chinese Academy of Sciences Institute of Computing Technology (ICT), significant improvement in performance has enabled (CoreTM and MMXTM are registered trademarks or trademarks of Intel Corporation of Santa Clara, Calif.).In one embodiment, the destination and source registers / data are generic terms to represent the source and destination of the corresponding data or operation. In some embodiments, they may be implemented by registers, memory, or other memory areas having different names or functions than those depicted. For example, in one embodiment, "DEST1" may be a temporary storage register or other storage area, whereas "SRC1" and SRC2" may be first and second source storage registers or other storage area, etc. In other embodiments, two or more of the SRC and DEST storage areas may correspond to different data storage elements within the same storage area (e.g., a SIMD register). In one embodiment, one of the source registers may also act as a destination register, for example, by rewriting the result of an operation performed on the first and second source data back into one of the two source registers that serve as destination registers.FIG. 1A is a block diagram of an example computer system formed with a processor including execution units for executing an instruction, according to an embodiment of the present invention. The system 100 includes a component, such as a processor 102, for employing execution units including logic for executing algorithms for process data in accordance with the present invention, such as in the embodiment described herein. The system 100 is representative of processing systems based on the PENTIUM® III, PENTIUM® 4, Xeon™ Itanium® XScale™ and / or StrongARM™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes, and the like) may also be used. In one embodiment, the pattern system 100 may execute a version of the WINDOWS™ operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used. Thus, the embodiments of the present invention are not limited to any particular combination of hardware circuitry and software.Embodiments are not limited to computer systems. Alternative embodiments of the present invention may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include a microcontroller, a digital signal processor (DSP), system on a chip, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system capable of executing one or more commands in accordance with at least one embodiment.FIG. 1A is a block diagram of a computer system 100 formed with a processor 102 that includes one or more execution units 108 for executing an algorithm to execute at least one instruction, in accordance with an embodiment of the present invention. An embodiment may be described in the context of a single processor desktop or server system, however alternative embodiments may be incorporated into a multiprocessor system. System 100 is an example of a hub architecture of the system. The computer system 100 has a processor 102 for processing data signals. The processor 102 may be a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device such as a digital signal processor. Processor 102 is coupled to a processor bus 110 that may transmit data signals between processor 102 and other components in system 100. The elements of system 100 perform their conventional functions well known to those skilled in the art.In one embodiment, processor 102 includes a level 1 (L1) internal cache 104. Depending on the architecture, processor 102 may include a single internal cache or multiple levels of internal cache. Alternatively, in another embodiment, the cache memory may be external to processor 102. Other embodiments may also include a combination of internal and external caches depending on the particular implementation and need. The register file 106 may store various types of data in various registers including integer registers, floating point (FP) registers), status registers, and instruction pointer registers.Execution unit 108, which includes logic for executing integer and floating point operations, is also resident in processor 102. Processor 102 also includes microcode ROM (ucode ROM) that stores microcode for certain microinstruction. In one embodiment, execution unit 108 includes logic for processing a compressed instruction set 109. By including the compressed instruction set 109 in the instruction set of a general purpose processor 102 along with associated circuitry for executing the instructions, the operations used by many multimedia applications may be performed using compressed data in a general purpose processor 102. Thus, many multimedia applications can be accelerated and executed more efficiently using the full width of a processor's data bus to perform operations on packed data. This can eliminate the need to transfer smaller units of data over the processor's data bus for performing one or more operations on one data element at a time.Alternative embodiments of execution unit 108 may also be used in microcontrollers, embedded processors, graphics devices, DSP, and other types of logic circuitry. System 100 includes a memory 120. The memory 120 may be dynamic random access memory (DRAM), static random access memory (SRAM), flash memory device, or other memory device. The memory 120 may store instructions and / or data represented by data signals executable by the processor 102.A system logic chip 116 is coupled to the processor bus 110 and the memory 120. The system logic chip 116, in the illustrated embodiment, is a memory controller hub (MCH). The processor 102 may communicate with the MCH 116 via a processor bus 110. The MCH 116 provides a high bandwidth storage path 118 to the memory 120 for command and data storage and for storing graphics commands, data, and textures. The MCH 116 routes data signals between the processor 102, the memory 120, and other components in the system 100, and couples (bridge) the data signals between the processor bus 110, the memory 120, and the system input and output (I / O) 122. In some embodiments, system logic chip 116 may provide a graphics port for coupling to a graphics controller 112. The MCH 116 is coupled to memory 120 via a memory interface 118. The graphics card 112 is coupled to the MCH 116 via an accelerated graphics port (AGP) port.System 100 uses a proprietary hub interface bus 122 to couple MCH 116 to I / O controller hub (ICH) 130. The ICH 130 provides direct connections to some input and output devices via a local I / O bus. The local I / O bus is a high speed I / O bus for connecting peripheral devices to the memory 120, chipset, and processor 102. Some examples are the audio controller, firmware hub (flash BIOS) 128, wireless transceiver 126, data storage 124, legacy I / O controller containing user input and keyboard interfaces, a serial expansion port such as a universal serial bus (USB), and a network controller 134. The data storage device 124 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.In another embodiment of a system, an instruction according to an embodiment may be used with a system on a chip. An embodiment of a system-on-a-chip includes a processor and a memory. The memory for such a system is flash memory. Flash memory may be located on the same die as the processor and other system components. In addition, other logic blocks, such as a memory controller or graphics controller, may also be located on a system-on-a-chip.FIG. 1B illustrates a data processing system 140 implementing the principles of an embodiment of the present invention. Those skilled in the art will readily understand that the embodiments described herein may be used with alternative processing systems without departing from the scope of embodiments of the invention.The computer system 140 includes a processing core 159 capable of executing at least one instruction according to an embodiment. In one embodiment, processing core 159 represents a processing unit of any type of architecture including, but not limited to, a CISC, RISC, or VLIW architecture type. The processing core 159 may also be suitable for manufacture in one or more process technologies and, being represented in sufficient detail on a machine readable medium, may be suitable for ease of manufacture.The processing core 159 includes an execution unit 142, a register file(s) set 145, and a decoder 144. Processing core 159 also includes additional circuitry (not shown) that is not necessary for understanding embodiments of the present invention. The execution unit 142 is used to execute instructions received from the processing core 159. In addition to executing typical processor instructions, execution unit 142 may execute instructions in packed instruction set 143 for executing operations on packed data formats. The packed instruction set 143 includes instructions for carrying out embodiments of the invention and other packed instructions. Execution unit 142 is coupled to register file 145 by an internal bus. Register file 145 represents a storage area in processing core 159 for storing information including data. As mentioned above, it should be understood that the storage area used to store the packed data is not critical. Execution unit 142 is coupled to decoder 144. Decoder 144 is used to decode instructions received from processing core 159 into control signals and / or microcode entry points. Execution unit 142 performs the appropriate operations in response to these control signals and / or microcode entry points. In one embodiment, the decoder is used to interpret the opcode of the instruction that will indicate which operation should be performed on the corresponding data indicated within the instruction.The processing core 159 is coupled to the bus 141 for communicating with various other system devices including, but not limited to, synchronous dynamic random access memory (SDRAM) controller 146, static random access memory (SRAM) controller 147, burst flash memory interface 148, personal computer memory card international association (PCMCIA) / compact flash (CF) card controller 149, liquid crystal display (LCD) 150, direct memory access (DMA) controller 151, and alternative bus master interface 152, among others. In one embodiment, data processing system 140 may also include an I / O bridge 154 for communicating with various I / O devices via an I / O bus 153. Such I / O devices may include, but are not limited to, Universal Asynchronous Receiver / Transmitter (UART) 155, Universal Serial Bus (USB) 156, Bluetooth Wireless UART 157, and I / O expansion interface 158, among others.One embodiment of data processing system 140 provides mobile, network and / or wireless communication and a processing core 159 capable of performing SIMD operations including a text string comparison operation. The processing core 159 may be programmed with various audio, video, image processing and communication algorithms including discrete transformations such as a Walsh-Hadamard transformation, a fast Fourier transformation (FFT), a discrete cosine transformation (DCT), and their respective inverse transformations; compression / decompression techniques such as color space transformation, video encoded motion prediction (video encode motion estimation), or video decoded motion compensation (video decode motion compensation); and modulation / demodulation (MODEM) functions such as pulse code modulation (PCM).FIG. 1C illustrates another alternative embodiment of a data processing system capable of executing instructions to provide enhanced paging capabilities for secure enclave page caches. According to an alternative embodiment, data processing system 160 may include a main processor 166, a SIMD coprocessor 161, a cache memory 167, and an input / output system 168. The input / output system 168 may optionally be coupled to a wireless interface 169. The SIMD coprocessor 161 is capable of executing operations including instructions, according to one embodiment. The processing core 170 may also be suitable for manufacture in one or more process technologies and, as represented in sufficient detail on a machine-readable medium, may be suitable for facilitating manufacture of all or a portion of the data processing system 160 including the processing core 170.In one embodiment, SIMD coprocessor 161 includes execution unit 162 and register file(s) set 164. One embodiment of main processor 166 includes decoder 165 for detecting instructions of instruction set 163 including instructions according to one embodiment for execution by execution unit 162. For alternative embodiments, the SIMD coprocessor 161 also includes at least a portion of the decoder 165B for decoding instructions of the instruction set 163. Processing core 170 also includes additional circuitry (not shown) that is not necessary for understanding embodiments of the present invention.In operation, the main processor 166 executes a flow of data processing instructions that control data processing operations of a general type including interactions with the cache memory 167 and the input / output system 168. Embedded within the flow of data processing instructions are SIMD coprocessor instructions. The decoder 165 of the main processor 166 recognizes these SIMD coprocessor instructions as being of a type that should be executed by an attached SIMD coprocessor 161. Thus, the main processor 166 outputs these SIMD coprocessor instructions (or control signals representing SIMD coprocessor instructions) to coprocessor bus 171, from where they are received from attached SIMD coprocessors. In this case, the SIMD coprocessor 161 will accept and execute received SIMD coprocessor instructions destined for it.Data may be received via wireless interface 169 for processing by the SIMD coprocessor instructions. As an example, voice communication may be received in the form of a digital signal that may be processed by the SIMD coprocessor instructions to regenerate digital audio patterns representative of the voice communications. As another example, compressed audio and / or video may be received in the form of a digital bitstream that may be processed by the SIMD coprocessor instructions to regenerate digital audio patterns and / or motion video frames. In one embodiment of processing core 170, main processor 166 and SIMD coprocessor 161 are integrated into a single processing core 170 that includes execution unit 162, register file(s) set 164, and decoder 165 to recognize instructions of instruction set 163 including instructions, according to one embodiment.FIG. 2 is a block diagram of the microarchitecture for a processor 200 that includes logic circuitry for executing instructions, in accordance with an embodiment of the present invention. In some embodiments, an instruction may be implemented according to one embodiment to handle data elements of the byte, word, doubleword, quadword, etc. sizes, as well as data types such as integer (single and double precision) data types and floating point (single and double precision) data types. In one embodiment, the in-order front end 201 is the portion of the processor 200 that fetches the instructions to be executed and prepares them for further use in the processor pipeline. The front end 201 may include a plurality of units. In one embodiment, the instruction prefetcher 226 fetches instructions from memory and passes them to the instruction decoder 228, which in turn decodes and interprets them. For example, in one embodiment, the decoder decodes an instruction received into one or more operations that are called "microinstructions" or "micro-operations" (they are also referred to as micro-ops or μ-ops) that the machine is capable of executing. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields used by the microarchitecture to perform operations according to one embodiment. In one embodiment, trace cache 230 fetches the decoded microoperations and assembles them into ordered program sequences or traces in microinstruction queue 234 for execution. When trace cache 230 encounters a complex instruction, microcode ROM 232 provides the micro-operations necessary to complete the operation.Some instructions are converted to simple microoperations, while others require multiple microoperations to complete the complete operation. In one embodiment, if more than four microOp are needed to fully execute an instruction, decoder 228 accesses microcode ROM 232 to satisfy the instruction. In one embodiment, an instruction for handling to a small number of microoperations may be decoded at the instruction decoder 228. In another embodiment, an instruction may be stored in microcode ROM 232 if a number of micro-operations are needed to handle the operation. Trace cache 230 references an entry point programmable logic array (PLA) to determine a correct microinstruction counter for reading the microcode sequences to fully execute one or more instructions from microcode ROM 232, according to one embodiment. After microcode ROM 232 completes the queuing of micro-operations for an instruction, front end 201 of the machine resumes fetching micro-operations from trace cache 230.The instructions are prepared for execution in the out-of-order execution system (in the OOO execution engine). The OOOO execution logic includes a number of buffers to smooth and reorder the flow of instructions for performance optimization as they pass through the pipeline and are scheduled for execution. The allocator logic allocates the buffers and resources of the machine that requires each micro-operation to be executed. The register rename logic renames logical registers to entries in a register memory. The allocator also allocates an entry for each micro-operation in one of the two (one for memory operations and one for non-memory operations) microinstruction queues before the instruction schedulers: memory scheduler, fast scheduler 202, slow / general floating point scheduler 204, and simple floating point scheduler 206. The uop schedulers 202, 204, 206 determine the ready-to-execute of a UOP based on the ready-to-execute of their dependent input register operand sources and the availability of the execution resources required by the UOPs to perform their operation. The fast scheduler 202 of one embodiment may schedule every half of the master clock cycle, while other schedulers may schedule only one time per master processor clock cycle. The schedulers switch between the dispatch ports to schedule microoperations for execution.Register files 208, 210 are located between the schedulers 202, 204, 206 and the execution units 212, 214, 216, 218, 220, 222, 224 in the execution block 211. There is a separate register file 208, 210 for integer and floating point operations, respectively. Each register memory 208, 210 of an embodiment also includes a bypass network that redirects or passes completed results that have not yet been written to the register memory to new dependent microoperations. Integer register memory 208 and floating point register memory 210 are also long to transfer data to each other. In one embodiment, integer register memory 208 is divided into two separate register memories, one register memory for the lower order 32 data bits and a second register memory for the higher order 32 data bits. The floating point register memory 210 of one embodiment has 128 bit wide entries because floating point operations normally comprise operands of 64-128 bit width.The execution block 211 includes the execution units 212, 214, 216, 218, 220, 222, 224 in which the instructions are actually executed. This section includes register memories 208, 210 which store the values of integer and floating point data operands to be executed by the microinstructions. The processor 200 of one embodiment includes a number of execution units: address generation unit (AGU) 212, AGU 214, fast ALU 216, fast ALU 218, slow ALU 220, floating point ALU 222, floating point move unit 224. In one embodiment, floating point execution blocks 222, 224 perform floating point, MMX, SIMD, and SSE or other operations. The floating point ALU 222 of one embodiment includes a 64-bit / 64-bit floating point divisor to perform division, square root, and remainder of microoperations. In embodiments of the present invention, instructions including a floating point value may be processed with the floating point hardware. In one embodiment, the ALU operations go to the execution units 216, 218 of the high speed ALU. The fast ALUs 216, 218 of one embodiment may perform hard operations with an effective latency of half a clock cycle. In one embodiment, the most complex integer operations move to the slow ALU 220 because the slow ALU 220 includes integer execution hardware for long latency operations such as multipliers, offsets, flag logic, jump execution. Load / store storage operations are performed by the AGUs 212, 214. In one embodiment, integer ALUs 216, 218, 220 are described in the context of performing integer operations on 64-bit data operands. In alternative embodiments, the ALUs 216, 218, 220 may be implemented to support a plurality of data bits, e.g., 16, 32, 128, 256, etc. Similarly, the floating point units 222, 224 may be implemented to support a series of operands having bits of different widths. In one embodiment, floating point units 222, 224 may operate at 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.In one embodiment, uops schedulers 202, 204, 206 transmit independent operations before a parent load has completed execution. Because microoperations in processor 200 are speculative scheduled and executed, processor 200 includes logic to handle the memory misses. In the event of a miss in the data cache, there may be dependent operations in the flow of the pipeline that have left the scheduler with temporarily incorrect data. A retry mechanism tracks and executes instructions again that use incorrect data. Only the dependent operations need to be repeated and the independent operations can be completed. The schedulers and retry mechanisms of an embodiment of a processor are also designed to intercept instructions that provide enhanced paging capabilities for secure enclave page caches.The term "register" may refer to the memory locations of the on-board processor used as portions of the instructions to identify operands. In other words, they may be registers usable from outside the processor (from a programmer's perspective). However, the registers of one embodiment should not be limited in meaning to any particular type of circuit. Rather, a register of one embodiment is capable of storing and providing data as well as performing the functions described herein. The registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store 32-bit integer data. A register memory of one embodiment also includes eight multimedia SIMD compressed data registers. For discussions below, the registers are understood as data registers configured to contain packed data, such as 64 bit wide MMX™ registers (also referred to as 'mm' registers in some cases) in microprocessors enabled with the MMX technology of Intel Corporation of Santa Clara, California. These MMX registers, available in both integer and floating point forms, can operate on compressed data elements accompanying SIMD and SSE instructions.Likewise, 128 bit wide XMM registers may also be used in conjunction with SSE2, SSE3, SSE4 technology or higher (commonly referred to as "SSEx") to hold such compressed data operands. In one embodiment, when storing compressed data and integer data, the registers need not distinguish between the two types of data. In one embodiment, integer and floating point numbers are included in either the same register memory or different register memories. Also, in one embodiment, floating point and integer data may be stored in different registers or the same registers.In the examples of the following figures, a number of data operands are described. FIG. 3A illustrates various representations of packed data types in multimedia registers, according to an embodiment of the present invention. FIG. 3A illustrates data types for a packed byte 310, a packed word 320, and a packed doubleword (dword) 330 for 128-bit wide operands. The packed byte format 310 of this example is 128 bits long and contains sixteen packed byte data elements. A byte is defined here as 8 bits of data. Information for each byte data element is stored in bit 7 through bit 0 for byte 0, bit 15 through bit 8 for byte 1, bit 23 through bit 16 for byte 2, and finally bit 120 through bit 127 for byte 15. Thus, all available bits in the register are used. This memory arrangement increases the storage efficiency of the processor. Likewise, with sixteen data items being accessed, an operation can now be performed in parallel on sixteen data items.Generally, a data element is an individual piece of data stored in a single register or memory location with other data elements of the same length. In packed data sequences in connection with SSEx technology, the number of data elements stored in an XMM register is 128 bits divided by the length in bits of an individual data element. Similarly, in packed data sequences associated with MMX technology, the number of data elements stored in an MMX register is 64 bits divided by the length in bits of an individual data element. Although the data types illustrated in FIG. 3A are 128 bits long, embodiments of the present invention may also operate with 64 bits wide, 256 bits wide, 512 bits wide, or other size operands. The packed word format 320 of this example is 128 bits long and contains eight packed word data elements. Each packed word contains sixteen bits of information. The packed doubleword format 330 of FIG. 3A is 128 bits long and contains four packed doubleword data elements. Each packed doubleword data element contains thirty-two bits of information. A packed quadword is 128 bits long and contains two packed quadword data elements.Figure 3B illustrates alternative register internal data storage formats. Each packed data may include more than one independent data element. Three packed data formats are illustrated: packed half 341, packed single 342, and packed double 343. One embodiment of packed half 341, packed single 342, and packed double 343 contain fixed point data elements. In an alternative embodiment, one or more of packed half 341, packed single 342, and packed double 343 may contain floating point data elements. An alternative embodiment of packed half 341 is one hundred twenty eight bits long and contains eight 16-bit data elements. One embodiment of packed single 342 is one hundred twenty-eight bits long and includes four 32-bit data elements. One embodiment of packed duplicate 343 is one hundred twenty-eight bits long and contains two 64-bit data elements. It should be appreciated that such packed data formats may be further extended to other register lengths, for example, 96 bits, 160 bits, 192 bits, 224 bits, 256 bits, 512 bits, or more.FIG. 3C illustrates various representations of signed and unsigned packed data types in multimedia registers, in accordance with an embodiment of the present invention. Unsigned packed byte representation 344 illustrates the storage of an unsigned packed byte in a SIMD register. Information for each byte data element is stored in bits seven to bit zero for byte zero, bit fifteen to bit eight for byte one, bit twenty-three to bit sixteen for byte two, etc., and finally, bits one hundred twenty-twenty to one hundred twenty-seven for byte fifteen. Thus, all available bits in the register are used. This memory arrangement can increase the storage efficiency of the processor. Also, with sixteen data items being accessed, an operation can now be performed in parallel on sixteen data items. Signed packed byte representation 345 illustrates the storage of a signed packed byte. Note that the eighth bit of each byte data element is the sign indicator. The unsigned packed word representation 346 illustrates how word seven through word zero are stored in a SIMD register. Signed packed word representation 347 is similar to intra-register unsigned packed word representation 346. Note that the sixteenth bit of each word data element is the sign indicator. The unsigned packed doubleword representation 348 shows how doubleword data elements are stored. Signed packed doubleword representation 349 is similar to the intra-register unsigned packed doubleword representation 348. Note that the necessary sign bit is the thirty-second bit of each doubleword data element.FIG. 3D is a figure of one embodiment of an operation coding format (opcode format) 360 having thirty two or more bits and register / memory operand addressing modes corresponding to a type of opcode format described in the Intel® 64 and IA-32 Intel Architecture Software Developer's Manual Combined Volumes 2A and 2B: Instruction Set Reference A-Z", available from Intel Corporation, Santa Clara, CA in the World Wide Web (www) at intel.com / products / processor / manuals / . In one embodiment, an instruction may be encoded by one or more of fields 361 and 362. Up to two operand locations per instruction may be identified, including up to two source operand identifiers 364 and 365. In one embodiment, destination operand identifier 366 is the same as source operand identifier 364, whereas in other embodiments they are different. In an alternative embodiment, the destination operand identifier 366 is the same as the source operand identifier 365, whereas in other embodiments they are different. In one embodiment, one of the source operands identified by source operand identifiers 364 and 365 is overwritten by the results of the instruction, whereas in other embodiments, identifier 364 corresponds to a source register element and identifier 365 corresponds to a destination register element. In one embodiment, operand identifiers 364 and 365 may be used to identify 32-bit or 64-bit source and destination operands.FIG. 3E is a figure of another alternative operation coding (opcode) format 370 that has forty or more bits. Opcode format 370 corresponds to opcode format 360 and includes an optional prefix byte 378. An instruction may be encoded by one or more fields of 378, 371, and 372, according to one embodiment. Up to two operand locations per instruction may be identified by source operand identifiers 374 and 375 and by prefix byte 378. In one embodiment, prefix byte 378 may be used to identify 32-bit or 64-bit source and destination operands. In one embodiment, the destination operand identifier 376 is the same as the source operand identifier 374, whereas in other embodiments they are different. In an alternative embodiment, the destination operand identifier 376 is the same as the source operand identifier 375, whereas in other embodiments they are different. In one embodiment, an instruction operates on one or more of the operands identified by operand identifiers 374 and 375 and one or more operands identified by operand identifiers 374 and 375 are overwritten by the results of the instruction, whereas in other embodiments, operands identified by identifiers 374 and 375 are written to another data element in another register. Opcode formats 360 and 370 enable register-to-register, memory-to-register, register-by-memory, register-by-register, register-by-immediate, register-to-memory addressing, which are specified in part by MOD fields 363 and 373 and by optional scale index base and displacement bytes.Turning next to FIG. 3F, in some alternative embodiments, 64-bit (or 128-bit or 256-bit or 512-bit or more) single instruction multiple data (SIMD) arithmetic operations may be performed by a coprocessor data processing (CDP) instruction. The operation coding format (opcode format) 380 depicts such a CDP instruction that includes the CDP opcode fields 382 and 389. In the type of CDP instruction, in alternative embodiments, operations may be encoded by one or more of fields 383, 384, 387, and 388. Up to three operand locations per instruction may be identified, including up to two source operand identifiers 385 and 390 and one destination operand identifier 386. An embodiment of the coprocessor may handle 8-, 16-, 32-, and 64-bit values. In one embodiment, an instruction is executed on integer data elements. In some embodiments, an instruction may be conditionally executed using field 381. In some embodiments, the source data sizes may be encoded by field 383. In some embodiments, the detection of zero (Z), negative (N), transmit (C), and overflow (V) may be performed on SIMD fields. For some instructions, the type of saturation may be encoded by field 384.Turning next to FIG. 3G, there is shown another alternative format 397 for encrypting operations (opcode), providing enhanced paging capabilities for secure enclave page caches according to another embodiment, corresponding to a type of opcode format described in the document Intel® advanced vector extensions programming reference," available from Intel Corp., Santa Clara, CA on the Internet (www) at intel.com / products / processor / manuals / .The original x86 instruction set provided for a 1-byte opcode having various address-syllable formats and immediate operands contained in additional bytes whose presence was known by the first "opcode" byte. In addition, there were certain byte values reserved as modifiers to the opcode (called prefixes because they had to be placed before the instruction). When the original palette of 256 opcode bytes (including these particular prefix values) was used up, a single byte was dedicated as an escape for a new set of 256 opcodes. Because vector instructions (e.g., SIMD) were added, a need for additional opcodes was generated and the "two byte" opcode map was also not sufficient even if extended by the use of prefixes. To this end, new instructions have been added in additional maps that use 2 bytes plus an optional prefix as an identifier.Additionally, to facilitate additional registers in 64-bit mode, an additional prefix (referred to as "REX") between the prefixes and the opcode (and escape bytes necessary to determine the opcode) may be used. In one embodiment, the REX 4 may have payload bits to indicate the use of additional registers in 64-bit mode. In other embodiments, it may have less than or more than 4 bits. The general format of at least one instruction set (generally corresponding to format 360 and / or format 370) is generically illustrated by the following:[Prefixes] [REX] Escape [Escape2] Opcode Modrm (etc.)Opcode format 397 corresponds to opcode format 370 and includes optional VEX prefix bytes 391 (beginning with C4-Hex in one embodiment) to replace most commonly used legacy instruction prefix bytes and escape codes. For example, the following illustrates an embodiment in which two fields are used to encode an instruction that may be used when a second escape code is present in the original instruction or when extra bits (e.g., the XB and W fields) must be used in the REX field. In the embodiment illustrated below, legacy escape is represented by a new escape value, and legacy prefixes are fully compressed as part of the "payload" bytes, legacy prefixes are retrieved and available for future expansion, the second escape code is compressed to a "map" field, with available future map or feature space, and new features are added (e.g., increased vector length and an additional source register specifier). An instruction according to an embodiment may be encoded by one or more of fields 391 and 392. Up to four operand locations per instruction may be identified by field 391 in combination with source operand identifiers 374 and 375 and in combination with optional scale index base (SIB) identifier 393, optional displacement identifier 394, and optional immediate byte 395. In one embodiment, the VEX prefix bytes 391 may be used to identify 32-bit or 64-bit source and destination operands and / or 128-bit or 256-bit SIMD register or memory operands. In one embodiment, the functionality provided by opcode format 397 may be redundant with opcode format 370, whereas in other embodiments it is different. Opcode formats 370 and 397 enable register-to-register, memory-to-register, register-by-memory, register-by-register, register-by-immediate, register-to-memory addressing, which are specified in part by MOD field 373 and by optional (SIB) identifier 393, optional displacement identifier 394, and optional immediate byte 395.Referring next to FIG. 3H, a representation of another alternative format 398 for encrypting operations (opcode) to provide enhanced paging capabilities for secure enclave page caches is provided, according to another embodiment. Opcode format 398 corresponds to opcode formats 370 and 397, and includes optional EVEX prefix bytes 396 (beginning with 62 Hex in one embodiment) to replace most other commonly used legacy instruction prefix bytes and escape codes and provide additional functionality. An instruction according to one embodiment may be encoded by one or more of fields 396 and 392. Up to four operand locations per instruction and a mask may be identified by field 396 in combination with source operand identifiers 374 and 375 and in combination with optional scale index base (SIB) identifier 393, optional displacement identifier 394, and optional immediate byte 395. In one embodiment, the EVEX prefix bytes 396 may be used to identify 32-bit or 64-bit source and destination operands and / or 128-bit, 256-bit or 512-bit SIMD register or memory operands. In one embodiment, the functionality provided by opcode format 398 may be redundant with opcode formats 370 or 397, whereas in other embodiments it is different. Opcode format 398 allows register-to-register, memory-to-register, register-by-memory, register-by-register, register-by-immediate, register-to-memory addressing, with masks specified in part by MOD field 373 and by optional (SIB) identifier 393, optional displacement identifier 394, and optional immediate byte 395. The general format of at least one instruction set (generally corresponding to format 360 and / or format 370) is generically illustrated by the following:For one embodiment, an instruction scrambled according to EVEX format 398 may have additional payload bits that may be used to provide enhanced paging capabilities for secure enclave page caches, with other new characteristics, such as a user configurable mask register, or an additional operand, or a selection between 128-bit, 256-bit, or 512-bit vector registers, or more registers to choose from, etc.For example, if a VEX format 397 may be used to provide enhanced paging capabilities for secure enclave page caches with an implicit mask, the EVEX format 398 may be used to provide enhanced paging capabilities for secure enclave page caches with an explicit user configurable mask. Additionally, if the VEX format 397 may be used to provide enhanced paging capabilities for secure enclave page caches on 128-bit or 256-bit vector registers, the EVEX format 398 may be used to provide enhanced paging capabilities for secure enclave page caches on 128-bit, 256-bit, 512-bit, or larger (or smaller) vector registers.Example instructions for providing enhanced paging capabilities to secure enclave page caches are illustrated by the following examples:EENTER / ERESUMEAddr1Enter secure enclave or further access secure enclave memory corresponding to the secure enclave address, Addr1, and count up the number of logical processors or hardware threads currently accessing the secure enclave.EEXIT / AEXAddr1The secure enclave exits and / or flushes one or more translations to access the secure enclave memory corresponding to the secure enclave address, Addr 1, and decrementing the number of logical processors or hardware threads that concurrently access the secure enclave.EBLOCKAddr1Mark entry corresponding to the shared page with page memory address, Addr1, in a secure enclave page map as blocked to prevent the creation of new translations for accessing the shared page.ETRACKAddr1The logical processors or hardware threads currently accessing the secure enclave memory record corresponding to the secure enclave address, Addr1, and decrement the number of logical processors or hardware threads if they leave the secure enclave.EWRITEBACK / EWBAddr1The shared page of page memory address, Addr1, removes, encrypts, and writes back when the number of logical processors or hardware threads that previously accessed the secure enclave has been decremented to zero.EBLOCK&TRACKAddr1Mark an entry corresponding to the shared page with page memory address, Addr1, in a secure enclave page map as blocked to create new translations for accessing the shared page.To prevent page. The logical processors or hardware threads currently accessing the secure enclave record corresponding to the page memory address, Addr1, and decrement the number of logical processors or hardware threads if they leave the secure enclave.LOADAddr1Decode the shared page with page memory address, Addr1, and load it into the secure enclave page cache.It should be appreciated that by using the above enclave instructions to provide enhanced paging capabilities for secure enclave page caches, the paging process (e.g., when the memory contents of the secure enclave page cache are encrypted and written back, new pages are loaded from memory and decrypted, the TLB entries are flushed and replaced, etc.) may be divided into stages in which the processor cores or logical processors are interrupted only briefly during one or more stages. This degradation due to the paging process can be reduced while security of secure enclave data can be guaranteed without undue complexity and design complexity.Some embodiments include multiple hardware threads, logical processors or processor cores, an enclave page cache to store secure data for common page addresses associated with a secure enclave and that is accessible by the hardware threads, logical processors or processor cores. An embodiment of an EBLOCK instruction sets the common page address as an operand. One or more execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block the creation of a new TLB translation for one of the plurality of hardware threads, logical processors, or processor cores to access the shared page. An embodiment of an ETRACK instruction sets the secure enclave as an operand, and one or more execution units draw the hardware threads that are currently accessing the secure data in the enclave page cache corresponding to the secure enclave. For example, in one embodiment, the enclave may have two or more counters, referred to herein as an "epoch counter," to record a number of hardware threads that are currently accessing secure data in the current epoch of the secure enclave, then copying that number to a latest most recent epoch counter, and initializing a new epoch with no hardware thread as the new current epoch. In an alternative embodiment of an EBLOCK&TRACK instruction, the common page address is defined as an operand. One or more execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block the creation of a new TLB translation for one of the plurality of hardware threads, logical processors or processor cores to access the shared page, and record the logical processors or hardware threads currently accessing the secure enclave corresponding to the page memory address, Addr1, and decrementing the number of logical processors or hardware threads as they leave the secure enclave. In one or more embodiments, epoch counters always track hardware threads, logical processors, or processor cores executing in a secure enclave or accessing secure data associated with a secure enclave.The OS may then send an inter-processor interrupt (IPI) to a hardware thread, logical processor, or processor core that is currently accessing secure data in the enclave page cache corresponding to the secure enclave. Any hardware thread, logical processor or processor core that is currently accessing secure data corresponding to the secure enclave would have entered the secure enclave with an EENTER or ERESUME instruction specifying the secure enclave, and at this time an epoch number would have been associated with the hardware thread, logical processor or processor core. When the hardware threads, logical processors, or processor cores acknowledge the IPI and leave the secure enclave, their TLB translation or TLB translations are flushed. Whenever hardware threads from the latest last epoch leave the secure enclave (e.g., with an EEXIT or AEX instruction), the number of hardware threads in the latest last epoch is decremented.When the recorded number of hardware threads reaches zero, it is safe for the OS to remove a page or pages, encrypt the data, and write it back to memory or permanent memory. In one embodiment, the OS may use an EWRITEBACK or EWB command that sets the common page address as an operand to complete the removal, encryption of the secured data, and write back of the page to permanent memory. Because enclave protection of the secure data may not trust the OS, it is possible that an embodiment of an EWRITEBACK or EWB instruction fails when the recorded number of hardware threads from the latest last epoch has not yet reached zero. In other alternative embodiments, an EWRITEBACK or EWB instruction may wait to execute or cause an exception until the recorded number of hardware threads reaches zero. The OS may allocate the free memory to a new page of the secure enclave and load secure data for the new page that responds to an embodiment of the UNLOAD instruction that sets a new common page address as an operand.It is to be understood that the management of permissions, physical storage and / or the change in assignments may still be taken over by an OS, but if the storage contents are protected, such as in a secure enclave, the OS is not authorized or trusted to access the actual protected contents of the enclave's private storage. Ensuring the security and / or integrity of private memory content and managing the physical constraints of limited memory to support a larger, protected, private enclave memory space without being able to trust an OS may be accomplished in a stepwise manner using instructions and processing logic to provide enhanced paging capabilities for secure enclave page caches without requiring hardware support and / or design overhead.FIG. 4A is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue / execution pipeline, in accordance with at least one embodiment of the invention. FIG. 4B is a block diagram illustrating an in-order architecture core and out-of-order issue / execution logic to be included in a processor according to at least one embodiment of the invention. The solid lined boxes in FIG. 4A illustrate the in-order pipeline, while the dashed lined boxes illustrate the register renaming, out-of-order issue / execution pipeline. Similarly, the solid lined boxes in FIG. 4B illustrate in-order architecture logic, while the dashed lined boxes illustrate register renaming logic and out-of-order issue / execution pipeline.In FIG. 4A, a processor pipeline 400 includes a fetch stage 402, a length decode stage 404, a decode stage 406, an allocation stage 408, a renaming stage 410, a scheduling (also known as a dispatch or issue) stage 412, a register read / memory read stage 414, an execute stage 416, a write back / memory write stage 418, an exception handling stage 422, and a commit stage 424.In FIG. 4B, arrows indicate a coupling between two or more units, and the direction of the arrow indicates a direction of data flow between these units. FIG. 4B shows processor core 490 including a front end unit 430 coupled to an execution engine unit 450, and both are coupled to a memory unit 470.The core 490 may be a reduced instruction set computer (RISC) core, a complex instruction set computer (CISC) core, a very long instruction word (VLIW) core, or a combination or alternative core type. As yet another possibility, the core 490 may be a purpose core, such as a network or communication core, compression engine, graphics core, or the like.The front end unit 430 includes a branch prediction unit (branch prediction unit) 432 coupled to an instruction cache unit 434, which is coupled to an instruction translation buffer (TLB) 436, which is coupled to an instruction fetch unit 438, which is coupled to a decode unit 440. The decode unit or decoder may decode instructions and generates as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that represent or otherwise reflect or are derived from a decoded form of the original instructions. The decoder may be implemented using various mechanisms. Examples of suitable mechanisms include (but are not limited to): look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. The instruction cache unit 434 is further coupled to an L2 cache unit 476 in the memory unit 470. The decode unit 440 is coupled to a rename / allocator unit 452 in the execution engine unit 450.Execution engine unit 450 includes rename / allocator unit 452 coupled to reorder unit (retry) 454 and a set of one or more scheduler unit(s) 456. Scheduler unit(s) 456 represents any number of different schedulers, including reservation stations and main command windows, etc. Scheduler unit(s) 456 is coupled to physical register storage unit(s) 458. Each of the physical register file(s) units 458 represents one or more physical register files, various of which store one or more different types of data, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer, i.e., the address of the next instruction to be executed), etc. Physical register file(s) unit(s) 458 is overlapped by reorder unit 454 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using reorder memory and reorder register file or files, using future file or files, history buffer, and reorder register file or files; using register maps and a pool of registers; etc.). Generally, the architectural registers are visible from the outside of the processor or from the perspective of a programmer. The registers are not limited to any known specific circuit type. Various types of registers are suitable as long as they are capable of storing and providing data as described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically register renamed physical registers, combinations of dedicated and dynamically allocated physical registers, etc. Reorder unit 454 and physical register storage unit(s) 458 are coupled to execution cluster(s) 460. The execution cluster(s) 460 includes (-n) a set of one or more execution units 462 and a set of one or more memory access units 464. The execution units 462 may perform various operations (e.g., offsets, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point numbers, compressed integer, compressed floating point numbers, vector integer, vector floating point numbers). Although some embodiments may include a series of execution units assigned to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that perform all functions. Scheduler unit(s) 456, physical register file(s) unit(s) 458, and execution cluster(s) 460 are shown as possibly multiple because certain embodiments generate separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline each having its own scheduler unit, physical register file(s) unit, and / or execution clusters, and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of that pipeline has memory access unit(s) 464). It will also be appreciated that when separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution and the remainder may be in-order.The set of memory access units 464 is coupled to the memory unit 470, which includes a data TLB unit 474 coupled to a data cache unit 474 coupled to an L2 cache unit 476. In one embodiment, memory access unit 464 may include a load unit, a memory address unit, a memory data unit, each of which is coupled to data TLB unit 472 in memory unit 470. The L2 cache unit 476 is coupled to one or more other levels of cache and possibly to main memory.As an example, the example register renaming, out-of-order issue / execution kernel architecture may implement the pipeline 400 as follows: 1) instruction fetch 438 performs fetch and length decode stages 402 and 404; 2) decode unit 440 performs decode stage 406; 3) reorder / allocator unit 452 performs allocation stage 408 and reorder stage 410; 4) scheduler unit(s) 456 performs (-en) scheduling stage 412; 5) physical register file(s) unit(s) 458 and storage unit 470 perform register read / memory read stage 414; execution cluster 460 performs execution stage 416; In other words, FIG. 6 ) the storage unit 470 and physical register file(s) unit(s) 458 perform the write back / memory write stage 418; 7) various units may be involved at the exception handling stage 422; and 8) the reorder unit 454 and physical register file(s) unit(s) 458 perform the commit stage 424.The core 490 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added to new versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA).It will be appreciated that the core may support multithreading (the execution of two or more parallel sets of operations or threads) and may do so in a variety of ways, for example, time-split multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads for which the physical core performs simultaneous multithreading), or a combination thereof (e.g., time-split fetch and decode, or simultaneous multithreading thereafter, e.g., in Intel® Hyperthreading technology).Although register renaming is described in the context of out-of-order execution, it is understood that register renaming may be used in an ordered architecture. While the illustrated embodiment of the processor also includes a separate instruction and data cache units 434 / 474 and a shared L2 cache unit 476, other embodiments may have a single internal cache for instructions and data, such as a level 1 (L1) internal cache or multiple levels of internal cache memory. In some embodiments, the system may include a combination of an internal cache and an external cache external to the core and / or the processor. Alternatively, all caches may be external to the core and / or the processor.FIG. 5 is a block diagram of a single core processor and a multi-core processor 500 with integrated memory controller and graphics according to embodiments of the invention. The solid line boxes in FIG. 5 illustrate a processor 500 having a single core 502A, a system agent 510, a set of one or more bus controller units 516, while the optional addition of the dashed line boxes illustrates an alternative processor 500 having multiple cores 502A-N, a set of one or more integrated memory controller unit(s) 514 in the system agent unit 510, and an integrated graphics logic 508.The memory hierarchy includes one or more levels of cache within the cores, a set of one or more shared cache units 506, and external memory (not shown) coupled to the set of integrated memory controller units 514. The set of shared cache units 506 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other-level caches, a last-level cache (LLC), and / or combinations thereof. Although in one embodiment a ring-based interconnect unit 512 interconnects the integrated graphics logic 508, the set of shared cache units 506, and the system agent unit 510, alternative embodiments may use any number of well-known techniques for interconnecting such units.In some embodiments, one or more of cores 502A-N are capable of multi-threading. System agent 510 includes those components that coordinate and operate cores 502A-N. The system agent unit 510 may include, for example, a power control unit (PCU) and a visual display unit. The PCU may be or include logic and components needed to regulate the power state of the cores 502A-N and the integrated graphics logic 508. The display unit drives one or more externally connected displays.Cores 502A-N may be homogeneous or heterogeneous in architecture and / or instruction set. For example, some of the cores 502A-N may be in-order cores while others are out-of-order cores. As another example, two or more of the cores 502A-N may be capable of executing the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.The processor may be a general purpose processor such as a Core™ i3, i5, i7, 2-Duo and Quad, Xeon™ Itanium™ XScale™ or StrongARM™ processor available from Intel Corporation of Santa Clara, Calif. Alternatively, the processor may be from another company, such as ARM Holdings, Ltd, MIPS, etc. The processor may be a special purpose processor, such as a network or communication processor, a compression engine, a graphics processor, coprocessor, embedded processor, or the like. The processor may be implemented on one or more chips. The processor 500 may be part of or implemented on one or more substrates (-n) using any of a number of process technologies, such as BiCMOS, CMOS, or NMOS.FIGS. 6 through 8 are example systems suitable for incorporating the processor 500, while FIG. 9 is an example system on a chip (SoC) that may include one or more of the cores 502. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants (PDAs), engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set top boxes, microcontrollers, cell phones, portable media players, handsets, and various other electronic devices are also suitable. In general, a vast variety of systems or electronic devices into which a processor and / or execution logic as disclosed herein may be incorporated are generally suitable.Reference is now made to FIG. 6, which shows a block diagram of a system 600 in accordance with an embodiment of the present invention. The system 600 may include one or more processors 610, 615 coupled to the graphics memory controller hub (GMCH) 620. The optional nature of additional processors 615 is indicated by broken lines in Figure 6.Each processor 610, 615 may be a variant of the processor 500. It should be noted, however, that integrated graphics logic and integrated memory controller units are unlikely to be present in the processors 610, 615. FIG. 6 illustrates that the GMCH 620 may be coupled to a memory 640, which may be, for example, dynamic random access memory (DRAM). The DRAM may be connected to a non-volatile cache, at least in one embodiment.The GMCH 620 may be a chipset or a portion of a chipset. The GMCH 620 may communicate with the processor(s) 610, 615 and control the interaction between the processor(s) 610, 615 and the memory 640. The GMCH 620 may also act as an accelerated bus interface between the processor(s) 610, 615 and other elements of the system 600. In at least one embodiment, GMCH 620 communicates with processor(s) 610, 615 via a multi-drop bus, such as a front-side bus (FSB) 695.In addition, the GMCH 620 is coupled to a visual display 645 (such as a flat panel display). The GMCH 620 may include an integrated graphics accelerator. The GMCH 620 is further coupled to an input / output (I / O) controller hub (ICH) 650, which may be used to couple multiple peripheral devices to the system 600. For example, in the embodiment of FIG. 6, an external graphics device 660, which may be a stand-alone graphics device coupled to the ICH 650, is shown along with another peripheral device 670.Alternatively, additional or different processors may also be present in the system 600. For example, an additional processor or processors 615 may include, but are not limited to, an additional processor or processors corresponding to processor 610, an additional processor or processors heterogeneous or asymmetric with processor 610, accelerators (such as graphics accelerators or digital signal processing units (DSP units)), field programmable gate arrays, or any other processor.A variety of differences may exist between the physical resources 610, 615 with respect to a spectrum of performance metrics including architectural, microarchitectural, thermal, energy consumption characteristics, and the like. These differences may manifest themselves effectively as asymmetry and heterogeneity between processors 610, 615. In at least one embodiment, different processors 610, 615 may be located in the same chip package.Reference is now made to FIG. 7, which shows a block diagram of a second system 700 according to an embodiment of the present invention. As shown in FIG. 7, multiprocessor system 700 is a point-to-point interconnect system and includes a first processor 770 and a second processor 780 coupled together via a point-to-point interconnect 750. Each of the processors 770 and 780 may be a variant of the processor 500 as one or more of the processors 610, 615.Although only two processors 770, 780 are shown, it should be understood that the scope of the present invention is not so limited. In other embodiments, one or more additional processors may be present in a given processor.Processors 770 and 780 are shown including integrated memory controller units 772 and 782, respectively. Processor 770 also includes as part of its bus controller units point-to-point (P-P) interfaces 776 and 778; similarly, second processor 780 includes P-P interfaces 786 and 788. Processors 770, 780 may exchange information via a point-to-point interface 750 using P-P interface circuits 778, 778. As shown in FIG. 7, IMC 772 and 782 couple the processors to respective memories, including a memory 732 and a memory 734, which may be portions of main memory locally attached to the respective processors.Processors 770, 780 may each exchange information with a chipset 790 via individual P-P interfaces 752, 754 using point-to-point interface circuits 776, 794, 786, 798. Chipset 790 may also exchange information with high performance graphics circuitry 738 via high performance graphics interface 739.Each processor or outside of the two processors may include a shared cache (not shown), but which is connected to the processors via the P-P link such that one or both of the processors' local cache information may be stored in the shared cache when a processor is placed in a low power mode.Chipset 790 may be coupled to a first bus 716 via an interface 796. In one embodiment, first bus 716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or other 3GIO interconnect bus, although the scope of the present invention is not so limited.As shown in FIG. 7, various I / O devices 714 may be coupled to the first bus 716, along with a bus bridge 718 that couples the first bus 716 to a second bus 720. In one embodiment, second bus 720 may be a Low Pin Count (LPC) bus. Various devices, including, for example, a keyboard and / or mouse 722, communication devices 727, and a storage unit 728, such as a disk drive or other mass storage device, which may contain instructions / code and data 730, may be coupled to second bus 720, in one embodiment. Further, audio input and output 724 may be coupled to second bus 720. It should be appreciated that other architectures are possible. For example, instead of the point-to-point architecture of FIG. 7, a system may implement a multi-drop bus or other such architecture.Reference is now made to FIG. 8, which shows a block diagram of a third system 800 according to an embodiment of the present invention. Like elements in FIGS. 7 and 8 bear like reference numerals, and certain aspects of FIG. 7 are omitted from FIG. 8 to prevent other aspects of FIG. 8 from becoming unclear.FIG. 8 illustrates that the processors 870, 880 include integrated memory and I / O control logic ("CL") 872 and 882, respectively. In at least one embodiment, CL 872, 882 may include integrated memory controller units, such as those described above in connection with FIGS. 5 and 7. In addition, CL 872, 882 may also include I / O control logic. FIG. 8 illustrates that not only are the memories 832, 834 coupled to the CL 872, 882, but also the I / O devices 814 are also coupled to the control logic 872, 882. Legacy I / O devices 815 are coupled to chipset 890.Reference is now made to FIG. 9, which shows a block diagram of a SoC 900 according to an embodiment of the present invention. Like elements in Fig. 5 bear the same reference numerals. Also, dashed lined boxes are optional features on more advanced SoC. In FIG. 9, an interconnect unit or units 902 is coupled to: an application processor 910 that includes a set of one or more cores 502A-N and shared cache unit(s) 506; a system agent unit 510; a bus controller unit 516; an integrated memory controller unit or units 514; a set of one or more media processors 920 that may include integrated graphics logic 508, an image processor 924 for providing still image and / or video camera functionality, an audio processor 926 for providing hardware audio acceleration, and a video processor 928 for providing video encode / decode acceleration; a static random access memory unit (SRAM) 930; a direct memory access (DMA) unit 932; and a display unit 940 for coupling to one or more external displays.FIG. 10 illustrates a processor including a central processing unit (CPU) and a graphics processing unit (GPU) that may execute at least one instruction, according to an embodiment. In one embodiment, an instruction to perform operations according to at least one embodiment could be executed by the CPU. In another embodiment, the command could be executed by the GPU. In yet another embodiment, the instruction may be executed by a combination of operations performed by the GPU and the CPU. For example, in one embodiment, a command may be received and decoded for execution in the GPU, according to one embodiment. However, one or more operations within the decoded instruction may be performed by a CPU and the result returned to the GPU for last re-ordering the instruction. Conversely, in some embodiments, the CPU may act as the primary processor and the GPU as the coprocessor.In some embodiments, instructions that benefit from highly parallel throughput processors may be executed by the GPU, while instructions that benefit from the performance of processors that benefit from strong pipelined architectures may be executed by the CPU. For example, graphics, scientific applications, financial applications, and other parallel workloads may benefit from and be executed accordingly by the performance of the GPU, whereas more sequential applications, such as kernel or application code, may be more suitable for the CPU.In FIG. 10, processor 1000 includes a CPU 1005, GPU 1010, image processor 1015, video processor 1020, USB controller 1025, UART controller 1030, SPI / SDIO controller 1035, visual display device 1040, high definition multimedia interface (HDMI) controller 1045, MIPI controller 1050, flash memory controller 1055, dual data rate (DDR) controller 1060, security engine 1065, and I 2 S / I 2 C (Integrated Inter Chip Sound / Inter Integrated Circuit) interface 1070. Other logic and circuitry including multiple CPUs or GPUs and other peripheral interface controllers may be included in the processor of FIG. 10.One or more aspects of at least one embodiment may be performed by representative data stored on a machine-readable medium representing various logic within the processor, which, when read by a machine, cause the machine to generate the logic for performing the techniques described herein. Such representations, also known as "IP cores", may be stored on a tangible machine-readable medium ("tape") and provided to various customers or manufacturing facilities where they are loaded into the manufacturing machines that make the logic or processor. For example, IP cores, such as the Cortex™ family of processors developed by ARM Holdings Ltd., and Loongson IP cores developed by the Chinese Academy of Sciences Institute of Computing Technology (ICT), may be licensed or sold to various customers or licensees, such as Texas Instruments, Qualcomm, Apple, or Samsung, and implemented in processors manufactured by these customers or licensees.FIG. 11 is a block diagram illustrating the development of IP cores, according to an embodiment. The memory 1130 includes the simulation software 1120 and / or the hardware or software model 1110. In one embodiment, data representing the IP core design may be provided to memory 1130 via memory 1140 (e.g., hard disk), wired connection (e.g., Internet) 1150, or wireless connection 1160. The IP core information generated by the simulation tool and the model may then be transmitted to a fabrication facility where it may be manufactured by third parties to execute at least one command, according to at least one embodiment.In some embodiments, one or more instructions may conform to a first type or architecture (e.g., x86) and may be translated or emulated to a different type or architecture processor (e.g., ARM). An instruction according to an embodiment may therefore be executed in any processor or processor type including ARM, x86, MIPS, a GPU, or other processor type or architecture.FIG. 12 illustrates how a first type instruction is emulated by a different type processor, according to one embodiment. In FIG. 12, program 1205 includes some instructions that may perform the same or substantially the same function as an instruction, according to one embodiment. However, the instructions of program 1205 may be of a type and / or format that is / are incompatible with processor 1215, meaning that the instructions of the type in program 1205 may not be natively executable by processor 1215. However, by emulation logic 1210, the instructions of program 1205 are translated into instructions that are natively capable of execution by processor 1215. In one embodiment, emulation logic is embedded in hardware. In another embodiment, emulation logic is embedded in a tangible machine readable medium containing software for translating instructions of the type in program 1205 into the type that is natively executable by processor 1215. In other embodiments, emulation logic is a combination of fixed function or programmable hardware and a program stored on a tangible machine readable medium. In one embodiment, the processor includes emulation logic, whereas in other embodiments, the emulation logic is external to the processor and provided by third parties. In one embodiment, the processor is capable of loading emulation logic contained in a tangible machine readable medium containing software by executing microcode or firmware contained in or associated with the processor.FIG. 13 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although the instruction converter may alternatively be implemented in software, firmware, hardware, or various combinations thereof. FIG. 13 shows a program in a high level language 1302 that may be compiled using an x86 compiler 1304 to generate x86 binary code 1306 that may be natively executed by a processor having at least one x86 instruction set core 1316. The processor with at least one x86 instruction set core 1316 represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software directed to run on an Intel processor with at least one x86 instruction set core to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler 1304 represents a compiler that is operable to generate x86 binary code 1306 (e.g., object code) that may be executed with or without additional linkage processing in the processor with at least one x86 instruction set core 1316. Similarly, FIG. 13 shows that the program in high-level language 1302 may be compiled using an alternative instruction set compiler 1308 to generate the alternative instruction set binary code 1310 that may be natively executed by a processor without at least one x86 instruction set core 1314 (e.g., a processor with cores executing the MIPS instruction set of MIPS Technologies of Sunnyvale, CA, and / or executing the ARM instruction set of ARM Holdings of Sunnyvale, CA). The instruction converter 1312 is used to convert the x86 binary code 1306 to code that can be natively executed by the processor without an x86 instruction set core 1314. This converted code is likely not the same as the alternative instruction set binary code 1310 because an instruction converter capable of being difficult to manufacture; however, the converted code will complete the general operation and consist of instructions from the alternative instruction set. Thus, the instruction converter 1312 represents software, firmware, hardware, or a combination thereof that, by emulation, simulation, or any other method, enables a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1306.FIG. 14 illustrates an embodiment of a processing system 1401 for using instructions to provide enhanced paging capabilities for a secure enclave page cache, EPC 1460. System 1401 includes system memory 1490 and processor 1402. Processor 1402 includes a first hardware thread or logical processor 1420 and a second hardware thread or logical processor 1430. It should be understood that although for simplicity processor 1402 is illustrated as being comprised of two logical processors, each representing a single hardware thread, the invention is not so limited. For example, it is typical of processors such as processor 1402 or other processors illustrated herein to have multiple logical processor cores that may or may not have some common physical resources (e.g., EPC 1460) and / or circuitry (e.g., SE unit 1470), where each logical processor or processor core has multiple hardware threads capable of executing software threads simultaneously or simultaneously.Processor 1402 also includes a secure enclave (SE) unit 1470 and an enclave page cache, EPC 1460. In some embodiments, EPC 1460 may be part of a cache unit, e.g., one or more level one caches 1440 and 1450, or a level two cache (not shown). In other embodiments, EPC 1460 may be a separate structure or a distributed structure (e.g., cache 1440 and cache 1450) shared by multiple hardware threads, logical processors or processor cores to store secure data for addresses of common pages 1442, 1444, and 1456 associated with a secure enclave and accessible by the hardware threads, logical processors or processor cores.Similarly, SE unit 1470 may comprise a separate structure or distributed structure (e.g., SE units 1427 and 1437) shared by multiple hardware threads, logical processors or processor cores having encryption units, integrity protection units, access restriction units, range registers, enclave page cache allocations, and two or more epoch counter storage locations to store at least a previous and a current epoch. SE unit 1470 also supports enclave instructions to provide enhanced paging capabilities for secure enclave page caches.In this example, the logical processor 1420 includes a decode stage 1422, a read stage 1424, one or more execution units (e.g., execution unit 1426), and a write stage 1428. The logical processor 1420 also includes a TLB 1425 in which translations may be installed to access the EPC 1460. The logical processor 1430 includes a decode stage 1432, a read stage 1434, one or more execution units (e.g., execution unit 1436), and a write stage 1438. The logical processor 1430 also includes a TLB 1435 in which translations may be installed to access the EPC 1460. Embodiments of logical processors 1420 and 1430 may also include other pipeline stages (e.g., as shown in pipeline 400) for executing enclave instructions to provide enhanced paging capabilities to secure enclave page caches, EPC 1460.It should be appreciated that by using enclave instructions to provide enhanced paging capabilities for secure enclave page caches, the paging process (e.g., when the memory contents of the secure enclave page cache are encrypted and written back, new pages are loaded from memory and decrypted, the TLB entries are flushed and replaced, etc.) may be divided into stages in which the processor cores or logical processors (e.g., logical processors 1420 and 1430) are interrupted only briefly during one or more stages. This degradation due to the paging process can be reduced while security of secure enclave data can be guaranteed without undue complexity and design complexity.In one embodiment, an EBLOCK instruction sets the address of a common page (e.g., page 1442) as an operand. One or more execution units (e.g., execution unit 1426) mark an entry corresponding to an enclave page cache mapping for the common page address to block the creation of a new TLB translation (e.g., in TLB 1435) for one of the plurality of hardware threads, logical processors, or processor cores to access the common page. In one embodiment, an ETRACK instruction sets the secure enclave as an operand, and one or more execution units (e.g., execution unit 1426) draw the hardware threads currently accessing the secure data in the enclave page cache, EPC 1460, corresponding to the secure enclave. For example, in one embodiment, the enclave may have two or more epoch counters to record a number of hardware threads that are currently accessing secure data in the current epoch of the secure enclave, copy that number to a latest most recent epoch counter (e.g., in response to the ETRACK instruction), and initialize a new epoch with no hardware threads as the new current epoch.The OS may then send an IPI to hardware threads, logical processors, or processor cores that are currently accessing secure data in the enclave page cache corresponding to the secure enclave. In one embodiment, any hardware thread, logical processor, or processor core (e.g., logical processors 1420 and 1430) that is currently accessing secure data corresponding to the secure enclave would have entered the secure enclave with an EENTER or ERESUME instruction specifying the secure enclave, and at this time an epoch number would have been associated with the hardware thread, logical processor, or processor core. When the hardware threads, logical processors, or processor cores acknowledge the IPI and leave the secure enclave, their TLB translation or TLB translations are flushed (e.g., by TLB 1425 and / or TLB 1435). Whenever hardware threads from the latest last epoch leave the secure enclave (e.g., with an EEXIT or AEX instruction), the number of hardware threads in the latest last epoch is decremented.When the recorded number of hardware threads reaches zero, it is safe for the OS to remove a page or pages (e.g., page 1442), encrypt the data, and write it back to memory (e.g., as encrypted page 1495) or permanent memory. In one embodiment, the OS may use an EWRITEBACK or EWB command that sets the address of the common page (e.g., page 1442) as an operand to complete the removal, encryption of the secured data, and write back of the page to memory or persistent storage. Because enclave protection of the secure data may not trust the OS, it is possible that an embodiment of an EWRITEBACK or EWB instruction fails when the recorded number of hardware threads from the latest last epoch has not yet reached zero. In other alternative embodiments, an EWRITEBACK or EWB instruction may wait to execute or cause an exception until the recorded number of hardware threads reaches zero. In one embodiment, the OS may then use an UNLOAD command to read a new page (e.g., page 1410) from memory or persistent storage, decrypt the data, and store the decrypted page in EPC 1460. This allows the paging process (e.g., when the memory contents of the secure enclave page cache are encrypted and written back, new pages are loaded from memory and decrypted, the TLB entries are flushed and replaced, etc.) to be divided into stages in which the processor cores or logical processors (e.g., logical processors 1420 and 1430) are interrupted only briefly during one or more stages (e.g., by IPI).FIG. 15 illustrates an embodiment of an apparatus in a processor 1501 for using instructions to provide enhanced paging capabilities for secure enclave page caches. The apparatus includes a secure enclave (SE) unit 1502 and an enclave page cache, EPC 1520. In some embodiments, EPC 1520 may be part of a larger cache unit, e.g., a level one cache, L1 1540, or a level two cache (not shown). In other embodiments, EPC 1520 may be a separate structure or a distributed structure shared by multiple hardware threads, logical processors or processor cores to store secure data for the address of a common page 1542 associated with a secure enclave and accessible by the hardware threads, logical processors or processor cores. The SE unit 1502 may include an encryption unit 1510, an integrity protection unit 1512, an access restriction unit 1514, range registers 1516, enclave page cache allocations EPC 1518, and two or more epoch counter storage locations: previous epoch, PE 1517, and current epoch, CE 1519. SE unit 1502 may also include enclave instructions 1503, including: EBLOCK instruction 1531, ETRACK instruction 1532, EWB instruction 1533, ELOAD instruction 1534, EEXIT instruction 1535, EENTER instruction 1536, and other enclave instructions, not shown (e.g., AEX instruction, ERESLTME instruction, etc.).Processor core 1501 also includes a TLB 1525 into which translations may be installed to access EPC 1520. Processor core 1501 also includes a decode stage 1522, a read stage 1524, one or more execution units (e.g., execution unit 1526), and a write stage 1528. Embodiments of processor core 1501 may also include other pipeline stages (e.g., as shown in pipeline 400) for executing enclave instructions 1503 to provide enhanced paging capabilities for secure enclave page caches, EPC 1520.In one embodiment, EBLOCK instruction 1531 sets a common page address 1542 as an operand. One or more execution units (e.g., execution unit 1526) mark an entry corresponding to an enclave page cache mapping in EPCM 1518 for the common page address 1542 to block the creation of a new TLB translation (e.g., in TLB 1525 or another TLB) for hardware threads, logical processors, or processor cores to access the common page. In one embodiment, an ETRACK instruction 1532 sets the secure enclave as an operand, and one or more execution units (e.g., execution unit 1526, or access restriction unit 1514) draw the hardware threads currently accessing the secure data in the enclave page cache EPC 1520 corresponding to the secure enclave. For example, in one embodiment, the enclave may have two or more epoch counters (e.g., in PE 1517 and in CE 1519) to record a number of hardware threads that are currently accessing secure data in the current epoch of the secure enclave (e.g., in CE 1519), copy that number to a latest last epoch counter (e.g., in PE 1517), and initialize a new epoch with no hardware threads than the new, current epoch (e.g., in CE 1519).The OS may then send an IPI to hardware threads, logical processors, or processor cores that are currently accessing secure data in the Secure Enclave page cache EPC 1520. Any hardware thread, logical processor, or processor core that is currently accessing secure data corresponding to the secure enclave would have entered the secure enclave with an EENTER (or ERESUME) instruction 1536 specifying the secure enclave, and at this time an epoch number would have been associated with the hardware thread, logical processor, or processor core. When the hardware threads, logical processors, or processor cores acknowledge the IPI and leave the secure enclave, their TLB translation or TLB translations are flushed (e.g., by TLB 1525). Whenever hardware threads from the latest last epoch (e.g., corresponding to PE 1517) leave the secure enclave with an EEXIT (or AEX) instruction 1535, the recorded number of hardware threads in the latest last epoch counter (e.g., in PE 1517) is decremented.When the recorded number of hardware threads (e.g., in PE 1517) reaches zero, it is safe for the OS to remove a page or pages (e.g., shared page 1542), encrypt the data, and write it back to memory or persistent storage. In one embodiment, the OS may use an EWB (or EWRITEBACK) command 1533, which sets the address of the shared page 1542 as an operand to complete the removal, encryption of the secured data, and write back of the page 1542 to the persistent memory. Because enclave protection of the secure data may not trust the OS, it is possible that an embodiment of an EWB instruction 1533 fails when the recorded number of hardware threads from the latest last epoch (e.g., in PE 1517) has not yet reached zero. In other alternative embodiments, the EWB instruction 1533 may wait to execute or cause an exception until the recorded number of hardware threads (e.g., in PE 1517) reaches zero.It is to be understood that the management of permissions, physical storage and / or the change in assignments may still be taken over by an OS, but if the storage contents are protected, such as in a secure enclave, the OS is not authorized or trusted to access the actual protected contents of the enclave's private storage. Ensuring security and / or integrity of private memory content and managing the technical constraints of constrained physical memory (e.g., EPC 1520 or EPC 1460) to support a larger protected private enclave storage space without being trusted by an OS may be accomplished in a stepwise manner using instructions and processing logic to provide enhanced paging capabilities for secure enclave page caches without requiring hardware support and / or design overhead.FIG. 16 illustrates a flow diagram of an embodiment of a process 1601 to provide enhanced paging capabilities for secure enclave page caches. Process 1601 and other processes disclosed herein are performed by processing blocks, which may include dedicated hardware, software, or firmware opcodes, executed by general purpose or special purpose computers, or a combination of both.In processing block 1610 of process 1601, a secure enclave is created to protect private data and / or commands. In processing block 1620 EPC, the secure enclave pages are allocated. In processing block 1625, it is determined whether or not paging is required. If not, the EPC pages are further mapped to the secure enclave in processing block 1620, where secure data may be stored in EPC lines for common page addresses mapped to the secure enclave and accessible to a plurality of hardware threads executing in the secure enclave. Otherwise, in processing block 1630, one or more EBLOCK instructions are executed, each EBLOCK instruction, in one embodiment, defining a common page address as an operand. At processing block 1640, an ETRACK instruction is executed, where the ETRACK instruction specifies the secure enclave in one embodiment. In processing block 1650, an IPI is sent to each logical processor executing in the secure enclave to leave the secure enclave(s). Acknowledgments of the IPIs are checked in processing block 1660, and it is determined in processing block 1665 whether or not all IPIs have been acknowledged. If not, processing continues in processing block 1660, but if all IPIs have been acknowledged, processing continues in processing block 1670. In processing block 1670, one or more EWB instructions are executed, each EWB instruction, in one embodiment, setting one of the blocked common page addresses as an operand. In processing block 1680, one or more UNLOAD instructions are executed, each UNLOAD instruction, in one embodiment, defining a new common page address as an operand. Processing then begins again at processing block 1625.FIG. 17 illustrates a flow diagram of an alternative embodiment of a process 1701 to provide enhanced paging capabilities for secure enclave page caches. In processing block 1710 of process 1701, a shared page entry (e.g., in response to an EBLOCK instruction that specifies the shared page address as an operand) is marked to block the creation of new transformations in one of the TLBs. In processing block 1720, the hardware threads, logical processors, or processor cores currently accessing the secure data in the secure enclave are recorded (e.g., in response to an ETRACK instruction specifying the secure enclave as an operand). In processing block 1730, the number of threads recorded is decremented as soon as a thread exits the secure enclave (e.g., using an EEXIT or AEX instruction). In processing block 1735, it is determined whether or not the recorded number of threads is now zero. If not, processing continues in processing block 1730, but if the recorded number of threads is now at zero, processing continues in processing block 1740. In processing block 1740, the secure data for the shared page is removed, and in processing block 1750, the secure data for the remote page is encrypted (e.g., in response to an EWRITEBACK or EWB command specifying the shared page as an operand). Next, in processing block 1760, the encrypted secure remote page data is written back to memory or permanent storage. In processing block 1770, a new page of the secure enclave is allocated free space. In processing block 1780, the secure data for the new page is decrypted (e.g., in response to an UNLOAD command that sets a new common page address as an operand).FIG. 18A illustrates a flow diagram of another embodiment of a process 1801 to provide enhanced paging capabilities for secure enclave page caches. In processing block 1810 of process 1801, a plurality of hardware threads are executed (e.g., in a multi-threaded processor). In processing block 1820, secure data is stored in a cache for a common page allocated to the secure enclave accessible by a plurality of threads. In processing block 1830 of process 1802, an EBLOCK instruction is decoded, wherein the EBLOCK instruction, in one embodiment, sets a common page address as an operand. In processing block 1840, a shared page entry is marked to block the creation of new transformations in one of the TLBs. In processing block 1850, the hardware threads, logical processors, or processor cores currently accessing the secure data in the secure enclave are recorded. In processing block 1860 of process 1803, an ETRACK instruction is decoded, wherein the ETRACK instruction, in one embodiment, sets the secure enclave as an operand. In processing block 1870, the number of threads recorded is decremented as soon as a thread exits the secure enclave (e.g., using an EEXIT or AEX instruction). In processing block 1880, it is determined whether or not the recorded number of threads is now zero. If not, processing continues in processing block 1870, but if the recorded number of threads is now at zero, processing continues in processing block 1890. In processing block 1890, secure data for the shared page is read out to memory or persistent storage (e.g., in response to an EWRITEBACK or EWB command specifying the shared page address as an operand).By using enclave instructions to provide enhanced paging capabilities for secure enclave page caches, the paging process (e.g., when the memory contents of the secure enclave page cache are encrypted and written back, new pages are loaded from memory and decrypted, the TLB entries are flushed and replaced, etc.) may be divided into stages in which the processor cores or logical processors are interrupted only briefly during one or more stages. This degradation due to the paging process can be reduced while security of secure enclave data can be guaranteed without undue complexity and design complexity.FIG. 18B illustrates a flow diagram of another embodiment of a process 1804 for providing enhanced paging capabilities for secure enclave page caches. In processing block 1810 of process 1804, a plurality of hardware threads are executed (e.g., in a multi-threaded processor). In processing block 1820, secure data is stored in a cache for a common page allocated to the secure enclave accessible by a plurality of threads. In processing block 1830 of process 1805, an EBLOCK instruction is decoded, wherein the EBLOCK instruction, in one embodiment, sets a common page address as an operand. In processing block 1840, a shared page entry is marked to block the creation of new transformations in one of the TLBs. In processing block 1860 of process 1806, an ETRACK instruction is decoded, wherein the ETRACK instruction, in one embodiment, sets the secure enclave as an operand. In processing block 1850, the hardware threads, logical processors, or processor cores currently accessing the secure data in the secure enclave are recorded. In processing block 1870, the number of threads recorded is decremented as soon as a thread exits the secure enclave (e.g., using an EEXIT or AEX instruction). In processing block 1880, it is determined whether or not the recorded number of threads is now zero. If not, processing continues in processing block 1870, but if the recorded number of threads is now at zero, processing continues in processing block 1890. In processing block 1890, secure data for the shared page is read out to memory or persistent storage (e.g., in response to an EWRITEBACK or EWB command specifying the shared page address as an operand).Thus, management of permissions, physical storage, and / or change of assignments may still be taken over by an OS, but the OS may not be authorized or trusted to access the actual protected contents of the enclave's private storage. Ensuring security and / or integrity of private memory content and managing the physical constraints of limited memory to support larger protected private enclave storage space may be accomplished in a stepwise manner using instructions and processing logic to provide enhanced paging capabilities for secure enclave page caches without requiring hardware support and / or design overhead. It should be understood that processing blocks illustrated as being executed in a particular order may also be executed in a different order, or simultaneously, or in parallel with each other, if possible in some alternative embodiments of process 1804 and other processes disclosed herein.Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executed on programmable systems that include at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system having a processor, such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. Indeed, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing various logic within the processor that, when read by a machine, cause the machine to generate logic for carrying out the techniques described herein. Such representations, also known as "IP cores", may be stored on a tangible, machine-readable medium and provided to various customers or manufacturing facilities where they are loaded into manufacturing machines that make the logic or processor.Such machine-readable storage media may include, but are not limited to, non-transitory, tangible arrangements of articles manufactured by a machine or device, including storage media such as hard disks, any other type of storage disks including floppy disks, optical disks, compact disk read-only memories (CD-ROM), compact disk rewritables (CD-RW), and magneto-optical disks, semiconductor devices such as read-only memories (ROM), random access memories (RAMs) such as dynamic random access memories (DRAM), static random access memories (SRAM), erasable programmable read-only memories (EPROM), flash memories, and the like, Electrically Erasable Read Only Memories (EEPROM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.Accordingly, embodiments of the invention also include non-transitory tangible machine-readable media containing instructions or design data, such as hardware description language (HDL) defining structures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate an instruction into one or more other instructions to be processed by the core (e.g., using binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be internal to the processor, external to the processor or partially internal to the processor and partially external to the processor.

Claims

A processor comprises: a first hardware thread and a second hardware thread; a cache to store secure data in a cache line for a common page address assigned to a corresponding secure enclave comprising a set of information and processing capabilities protected as a group and accessible to said first and second hardware threads; a decode stage to decode a first instruction for execution by said processor, said first instruction defining said common page address as an operand, and decode a second instruction for execution by said processor, said second instruction defining said secure enclave as an operand, and decode a third instruction for execution by said processor, said third instruction defining said common page address as an operand; one or more execution units responsive to said decoded first instruction to: mark an entry corresponding to a cache map for said common page address to disable creation of a new translation for either said first or second hardware threads to access secure data corresponding to said common page address; wherein the one or more execution units respond to the decoded second instruction to: record hardware threads currently accessing secure data in the cache corresponding to the secure enclave, wherein an interprocessor interrupt (IPI) is sent to hardware threads currently accessing secure data in the cache corresponding to the secure enclave, wherein a recorded number of hardware threads is decremented in response to the hardware threads exiting the secure enclave; and wherein the one or more execution units respond to the decoded third instruction to: clear and write back secure data in the cache corresponding to the common page address when the recorded number of hardware threads currently executing in the secure enclave reaches zero.The processor of claim 1, wherein the cache is an enclave page cache.The processor according to claim 1 or 2, wherein the first instruction is an EBLOCK instruction defining said common page address to prevent the creation of a new translation corresponding to the common page address in one of the translation buffers (TLB).The processor of claims 1 to 3, wherein the second instruction is an ETRACK instruction that specifies said secure enclave to record a number of hardware threads currently executing in the secure enclave.The processor of claim 1, wherein the third instruction is an enclave write back instruction (EWB) that specifies said common page address to remove, write back the common page from the cache.A method comprising: executing, in a multi-threaded processor, a first hardware thread and a second hardware thread; storing secure data in a cache line of a cache of the processor for a common page address assigned to a corresponding secure enclave comprising a set of information and processing capabilities that are protected as a group and that are accessible by said first and second hardware threads; decoding a first instruction for execution by said processor, wherein the first instruction sets said common page address as an operand; in response to decoding the first instruction, marking an entry corresponding to a cache mapping for the common page address to disable creation of a new translation for either said first or second hardware threads to access secure data corresponding to the common page address, decoding a second instruction for execution by said processor, the second instruction defining said secure enclave as an operand; in response to decoding the second instruction, recording hardware threads currently accessing secure data in the cache corresponding to the secure enclave, sending an interprocessor interrupt (IPI) to hardware threads currently pulling secure data in the cache corresponding to the secure enclave, decrementing a recorded number of hardware threads in response to the hardware threads exiting the secure enclave; and decoding a third instruction for execution by said processor, the third instruction specifying said common page address as an operand; and in response to decoding the third instruction, flushing and writing back secure data in the cache corresponding to the common page address when the recorded number of hardware threads currently executing in the secure enclave reaches zero.The method of claim 6, wherein the first instruction is an EBLOCK instruction that defines said common page address to prevent creation of a new translation corresponding to the common page address in one of the TLBs.The method of any of claims 6 to 7, wherein a translation corresponding to the common page address in a TLB corresponding to one of the hardware threads is flushed when the respective hardware thread exits the secure enclave.The method of claim 6, wherein in response to said processor decoding the third instruction for execution, the secure data in the cache is encrypted according to the common page address before the secure data is written back to the memory or permanent memory.A processing system comprising: a memory; and a processor according to any one of claims 1 to 5.

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