POWER ARCHITECTURE WITH MULTI-VOLTAGE IDENTIFICATION (VID), DIGITALLY SYNTHETIZABLE LOW-DROPUT CONTROLLER AND DEVICE FOR IMPROVING THE RELIABILITY OF POWER GATES

Abstract

Device comprising: a first processor core (105) on a chip, which includes a first voltage regulator (110) to provide a first power supply (108) for a load on the first processor core (105) on a chip; a second processor core (105) on a chip, which includes a second voltage regulator (110) to provide a second power supply for a load on the second processor core (105) on a chip; and a power control circuit (104) coupled to the first and second processor cores (105) on a chip, wherein the power control circuit (104) applies an external voltage identifier (eVID) (107) to a voltage regulator (110) outside a chip, which provides an input power supply for the first and second voltage regulators (110).wherein the power control circuit (104) generates the eVID (107) at least partially based on power levels of the first and second processor cores (105) on a chip, wherein the power control circuit (104) sets a first VID (iVID) (109) for the first processor core (105) on a chip, wherein the power control circuit (104) sets a second iVID (109) for the second processor core (105) on a chip, wherein the first iVID (109) and the second iVID (109) adjust reference currents associated with the first and second voltage regulators (110), and wherein the first processor core (105), the second processor core (105), and the first and second voltage regulators (110) are located on the same chip.

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