Semiconductor device with a rim area and method for manufacturing a semiconductor device

Abstract

Semiconductor device with a semiconductor part (100), wherein the semiconductor part (100) comprises: a semiconductor layer (120) with a drift zone (121) of a first conductivity type and at least one foreign material region (115) of a second opposite conductivity type, which borders a first surface (101) of the semiconductor part (100) in an element region (610); a compound layer (130) directly adjacent to the semiconductor layer (120) opposite the first surface (101), wherein the mean concentration of foreign matter in the compound layer (130) is at least ten times greater than the mean concentration of foreign matter in the drift zone (121); and an overcompensation region (125) in a boundary region (690) surrounding the element region (610), wherein the overcompensation region (125) is missing in the element region (610), and wherein the overcompensation region (125) and the connecting layer (130) have opposite conductivity types and part of the drift zone (121) is arranged in a direction perpendicular to the first surface (102) between the first surface (101) and the overcompensation region (125).

Description

BACKGROUND

[0001] Power semiconductor devices are used in electrical power circuits as switches for turning loads supplied with high currents on and off. Typically, power semiconductor devices can carry high electric current in a conducting mode and withstand high blocking voltages in a reverse blocking and / or forward blocking mode. Edge termination structures smooth electric field profiles in an edge region surrounding the active element region in blocking mode such that the maximum electric field strength in the edge region at least approaches the maximum electric field strength in the element region. The edge termination structure of a semiconductor device with an n-type drift zone may include field electrodes arranged in trenches and may include p-type regions directly below the trenches adjacent to the trenches. The p-type regions smooth the curvature of equipotential lines in the edge region.

[0002] The document DE 10 2006 025 958 B3 describes a power semiconductor component with a drift zone and a rear-side emitter formed between the drift zone and a rear electrode. The rear-side emitter is formed as a laterally structured layer with lightly doped first subzones and more heavily doped second subzones. Counterdoped islands are formed between the drift zone and the more heavily doped second subzones. The counterdoped islands and the second subzones of the rear-side emitter form pn junctions for self-regulating hole injection, which results in smoother commutation of the power semiconductor component.

[0003] The publication US 2010 / 0 059 818 A1 describes a superjunction semiconductor component whose superjunction structure extends into the edge region of the semiconductor body. In the edge region, a p-doped lateral RESURF structure interconnects the p-doped columns of the superjunction structure and connects the p-doped columns of the edge region to the front electrode via p-doped columns and other p-doped regions in the cell array. The lateral RESURF structure reduces the curvature of the depletion zone in the edge region during off-state operation, thus improving the dielectric strength of the semiconductor component.

[0004] A vertical n-channel field-effect transistor with a drift zone described in DE 10 2006 036 347 B4 has an edge termination structure with a trench extending from the front side into the drift zone of the field-effect transistor. An edge electrode formed in the trench is electrically connected to p-doped regions laterally adjacent to the trench. A floating p-doped region extends deeper into the drift zone from the trench bottom.

[0005] The publication US 2010 / 0 001 344 A1 relates to an n-channel field-effect transistor with floating p-doped regions in the edge area. The floating p-doped regions are formed at a distance from the heavily n-doped semiconductor substrate on the back of the device.

[0006] It is desirable to increase the reliability of semiconductor devices.

[0007] This object is achieved according to the invention by the independent patent claims. Further developments are the subject of the dependent patent claims. SUMMARY

[0008] According to one embodiment, a semiconductor part of a semiconductor device comprises a semiconductor layer with a drift zone of a first conductivity type and at least one impurity or dopant region with a second conductivity type opposite the first conductivity type. The impurity or dopant region adjoins a first surface of the semiconductor part in an element region. A connecting layer directly adjoins the semiconductor layer opposite the first surface. An average impurity or dopant concentration in the connecting layer is at least ten times greater than an average impurity or dopant concentration in the drift zone. An overcompensation region is arranged in an edge region surrounding the element region. The overcompensation region and the connecting layer have opposite conductivity types.In a direction vertical to the first surface, a part of the drift zone is arranged between the first surface and the overcompensation region.

[0009] A further embodiment relates to a power field-effect transistor with a semiconductor part having a semiconductor layer with a drift zone of a first conductivity type. At least one impurity or dopant region with an opposite second conductivity type directly adjoins a first surface of the semiconductor part in an element region. A connecting layer of the first conductivity type directly adjoins the semiconductor layer opposite the first surface. An average impurity or dopant concentration in the connecting layer is at least ten times greater than an average impurity or dopant concentration in the drift zone. An overcompensation region of the second conductivity type is formed in an edge region surrounding the element region. In a direction vertical to the first surface, a part of the drift zone is arranged between the first surface and the overcompensation region.

[0010] A semiconductor part of an insulated-gate power bipolar transistor comprises a semiconductor layer with a drift zone of a first conductivity type and at least one impurity or dopant region with a second conductivity type opposite the first conductivity type. The impurity or dopant region directly adjoins a first surface of the semiconductor part in an element region. A connecting layer of the second conductivity type directly adjoins the semiconductor layer opposite the first surface. An average impurity or dopant concentration in the connecting layer is at least ten times greater than an average impurity or dopant concentration in the drift zone. An overcompensation region of the second conductivity type is formed in an edge region surrounding the element region.In a direction vertical to the first surface, a part of the drift zone is arranged between the first surface and the overcompensation region.

[0011] A further embodiment relates to a method for producing a semiconductor device. A semiconductor layer having a drift zone of a first conductivity type is formed, wherein the semiconductor layer adjoins a connection layer. An average impurity or dopant concentration in the connection layer is at least ten times as high as an average impurity or dopant concentration in the drift zone. An overcompensation zone having a conductivity type opposite to the conductivity type of the connection layer is formed in an edge region surrounding an element region, wherein a part of the drift zone is arranged between the first surface and the overcompensation region in a direction perpendicular to an interface between the connection layer and the semiconductor layer. At least one impurity or dopant concentration is formed in the element region.Dopant region having a conductivity type opposite to the first conductivity type, which adjoins a first surface of the semiconductor layer opposite the connection layer.

[0012] Those skilled in the art will recognize additional features and advantages after reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain principles of the invention. Other embodiments of the invention and intended advantages will be readily appreciated as they become better understood by reference to the following partial description. The elements of the drawings are not necessarily to scale. Like reference characters indicate corresponding similar parts. Fig. 1A illustrates a schematic cross-sectional view of a semiconductor portion of a semiconductor device having an overcompensation zone in an edge region according to an embodiment of the invention. Fig. 1B shows a schematic cross-sectional view of the semiconductor part Fig. 1A along line BB. Fig. 1C illustrates a schematic cross-sectional view of a semiconductor portion of a semiconductor device according to an embodiment in which an overcompensation region is formed with stripe regions extending into an element region. Fig. 1D illustrates a schematic cross-sectional view of a semiconductor portion of a semiconductor device according to an embodiment in which an overcompensation region is formed with two spatially separated islands. Fig. 1E illustrates a schematic cross-sectional view of a semiconductor portion of a semiconductor device according to an embodiment in which an overcompensation region is formed with a plurality of spatially separated islands. Fig. Figure 2A is a diagram showing impurity profiles along line II in an element region of the semiconductor part of Fig. 1A according to an embodiment relating to two epitaxial layers on a highly doped interconnect layer. Fig. Figure 2B is a diagram showing the impurity profiles along the line II-II in an edge region of the semiconductor part of Fig. 1A according to the embodiment of Fig. 2A. Fig. Figure 3A is a schematic diagram showing the impurity profiles along line II in an element region of the semiconductor part of Fig. 1A according to an embodiment relating to co-implantation. Fig. Figure 3B is a schematic diagram showing impurity profiles along the line II-II in an edge region of the semiconductor device of Fig. 1B according to the embodiment of Fig. 3A represents. Fig. 4 illustrates a schematic cross-sectional view of a semiconductor diode with an overcompensation region according to another embodiment. Fig. 5A illustrates a schematic cross-sectional view of an IGBT (insulated gate bipolar transistor) having an overcompensation region according to another embodiment. Fig. 5B illustrates a schematic cross-sectional view of an IGBT with an overcompensation region according to an embodiment in which a high dynamic robustness region is formed. Fig. 6A illustrates a schematic cross-sectional view of an insulated gate field effect transistor (IGFET) according to an embodiment in which a field plate termination structure and an overcompensation region are formed with spatially separated islands. Fig. 6B illustrates a schematic cross-sectional view of an IGFET according to an embodiment in which termination trenches and an overcompensation region are formed with spatially separated islands. Fig. 6C illustrates a schematic cross-sectional view of an IGFET with a super-junction structure according to another embodiment. Fig. 7 illustrates a simplified flow diagram of a method of manufacturing a semiconductor device according to another embodiment. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which is shown, for purposes of illustration, specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment may be used in or in connection with the other embodiments to arrive at yet another embodiment. It is intended that the present invention include such modifications and changes. The examples are described using specific language that should not be construed as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or manufacturing processes are designated by corresponding reference numerals in the various drawings, unless otherwise noted.

[0015] The terms "have," "contain," "comprise," "have," and the like are open-ended terms. These terms indicate the presence of the identified structures, elements, or characteristics, but do not exclude additional elements or characteristics. The indefinite and definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0016] The term “electrically connected” describes a permanent low-resistance connection between electrically connected elements, for example a direct contact between the elements in question or a low-resistance connection via a metal, a metal compound and / or a highly doped semiconductor.

[0017] In the figures, relative dopant concentrations are represented by indicating “-” or “+” next to the doping type “n” and “p”. For example, “n - ” a smaller dopant concentration than the dopant concentration in an “n” doping region, while an “n +"-doping region has a higher dopant concentration than an "n"-doping region. Doping regions with the same relative dopant concentration do not necessarily have the same absolute dopant concentration. For example, two different "n"-doping regions can have the same or different absolute dopant concentrations.

[0018] Fig. 1A and Fig. 1B illustrate a semiconductor portion 100 of a semiconductor device. The semiconductor portion 100 is formed from a single-crystal semiconductor material such as silicon Si, silicon carbide SiC, germanium Ge, a silicon germanium crystal SiGe, gallium nitride GaN, or gallium arsenide GaAs. The semiconductor portion 100 has a first surface 101 and an opposite second surface 102 that are parallel to each other. A distance between the first and second surfaces 101, 102 is at least 5 µm, for example, at least 50 µm. An outer surface 103 inclined to the first and second surfaces 101, 102 connects the first and second surfaces 101, 102. The semiconductor portion 100 may have a rectangular shape with an edge length in the range of a few millimeters.The normal to the first and second surfaces 101, 102 defines a vertical direction and directions perpendicular to the normal direction and parallel to the first and second surfaces 101, 102 are lateral directions.

[0019] As in Fig. As shown in Figure 1A, the semiconductor part 100 has a connecting layer 130 and a semiconductor layer 120 with a drift zone 121 of a first conductivity type. An impurity or dopant distribution in the connecting layer 130 can be approximately uniform. An average impurity concentration in the connecting layer 130 is comparatively high, e.g., at least 5 × 10 18 cm -3 The interconnect layer 130 may extend along the entire second surface 102. The thickness of the interconnect layer 130 may be at least 30% of the thickness of the semiconductor layer 120.

[0020] In the case where the semiconductor device is a semiconductor diode or an IGFET (Insulated Gate Field Effect Transistor), the interconnect layer 130 has the first conductivity type, which is the conductivity type of the drift region 121. In the case where the semiconductor device is an IGBT, the interconnect layer 130 has a second conductivity type opposite to the first conductivity type and opposite to the conductivity type of the drift region 121.

[0021] The semiconductor layer 120 with the drift zone 121 directly forms the first surface 101 and directly adjoins a process surface of the interconnect layer 130, which is parallel to the second surface 103. An average impurity concentration in the drift zone 121 is at least ten times lower than the average impurity concentration in the interconnect layer 130. A comparatively sharp step in the vertical impurity profile characterizes the interface between the interconnect layer 130 and the drift zone 121. Alternatively, a field stop zone 128 and / or a buffer region of the first conductivity type can be implemented between the drift zone 121 and the interconnect layer 130, wherein an average net impurity concentration in a field stop zone 128 is higher than in the drift zone 121 and an average net impurity concentration in a buffer region is less than or equal to the average impurity concentration in the drift zone 121.

[0022] In an element region 610, at least one impurity region 115 of the second conductivity type is formed in the semiconductor layer 120 along the first surface 101 and at a distance from the interconnect layer 130. The impurity region 115 may be an anode region of a semiconductor diode. Other embodiments provide a plurality of impurity regions 115, each including impurity wells of the first conductivity type, wherein the impurity regions 115 act as body regions and the impurity wells act as source regions. The body and source regions represent control blocks of switching devices such as IGFETs or IGBTs. The semiconductor layer 120 may include further impurity regions of both conductivity types, conductive structures, and / or insulating structures.

[0023] For example, the semiconductor layer 120 may have a superjunction structure with sequentially arranged p-doped and n-doped pillars to achieve a compensation effect that improves the reverse voltage blocking capability of the semiconductor layer 120 without increasing the on- or forward resistance.

[0024] Fig. 1B illustrates an approximately rectangular element region 610, which may have sharp or rounded corners. The element region 610 comprises one or more semiconductor elements that define the function of the semiconductor device, for example, a diode, a bipolar transistor, a junction field effect transistor (JFET), an IGFET, for example, a metal oxide semiconductor field effect transistor (MOSFET) in the usual sense, which comprises FETs with metal and non-metal gate electrodes, or an IGBT, where each transistor may comprise a plurality of transistor cells arranged in one or more cell arrays. For example, the element region 610 may comprise the anode region of a semiconductor diode or the source / emitter and body regions of IGFETs or IGBTs, as described above, as well as gate electrodes.In addition, the semiconductor part 100 may comprise further semiconductor elements, such as logic circuits, driver circuits, processor circuits or memory circuits.

[0025] An edge region 690 may surround the element region 610 in the lateral direction into an outermost region of the semiconductor part 100. The edge region 690 directly adjoins the element region 610 and may extend along the outer surface 103. The width of the edge region 690 is at least a few tens of µm or more than 100 µm and depends on the desired device blocking voltage capability. In the edge region 690, the semiconductor part 100 may include edge termination elements that form an electric field gradient such that in the edge region 690, the maximum electric field strength at least approaches a maximum electric field strength in the element region 610.

[0026] In an on-state or forward mode of the semiconductor device, an on-state or forward current flows between the first and second surfaces 101, 102 in the element region 610. A non-negligible portion of the on-state or forward current flows into the edge region 690.

[0027] An overcompensation region 125 of a conductivity type opposite to the conductivity type of the interconnect layer 130 is formed in the edge region 690 of the semiconductor part 100, wherein, along the vertical direction, a portion of the drift zone 121 is arranged between the first surface 101 and the overcompensation region 125. In the illustrated embodiment, which relates to IGFETs and diodes, the interconnect layer 130 has the first conductivity type, and the overcompensation region 125 has the second conductivity type. In the vertical direction, the drift zone 121 separates the overcompensation region 125 from the first surface 101 and other doped regions or electrical structures of an edge termination structure.

[0028] The overcompensation region 125 can comprise exclusively second foreign substances of the second foreign substance type. According to one embodiment, the overcompensation region 125 comprises both first foreign substances of the first foreign substance type and second foreign substances of the second foreign substance type, wherein within at least a part of the overcompensation region 125 a concentration of second foreign substances exceeds the concentration of the first foreign substances, e.g., by approximately three times at least 10%, e.g., by at least 50% or at least three times. The dosage of the second foreign substances can be at least 3 × 10 13 cm -2 , e.g. 3 × 10 14 or 10 15 cm -2 be.

[0029] According to one embodiment, the first conductivity type is n-type and the second conductivity type is p-type. For example, the first impurities or dopants are arsenic, antimony, or phosphorus atoms, and the second impurities or dopants are boron, gallium, aluminum, or indium atoms. According to further embodiments, the first conductivity type is p-type, wherein the first impurities are boron, gallium, aluminum, or indium atoms, and the second impurities are arsenic, antimony, or phosphorus atoms.

[0030] Immediately after the semiconductor device switches from a forward or on-state to a reverse or off-state, mobile charge carriers carrying the forward or on-state current and residing in both the element region 610 and the edge region 690 at the switching time are dissipated in electrodes on the first and second surfaces 101, 102 of the semiconductor part 100. Charge carriers of the second conductivity type, e.g., holes in the case of an n-FET, are dissipated by an electrode electrically connected to the first surface 101 and therefore traverse a depletion region formed at a pn junction between the impurity region 115 and the drift region 121 on a front side. The charge of the mobile charge carriers adds to the charge of the immobile impurity ions and increases the electric field strength such that a dynamic avalanche breakdown can occur at the front side near the pn junction.

[0031] If the current densities resulting from the dynamic avalanche breakdown triggered by charge carriers of the second conductivity type, e.g. holes in the case of an n-FET, are sufficiently high at the front side of the semiconductor part 100, current filaments in which the current density is locally increased can occur where the semiconductor part 100 is inhomogeneous. At the n / n + -Interface on a backside of the semiconductor part 100, an increased density of mobile charge carriers of the first conductivity type, e.g. electrons in the case of an n-FET, can increase the local electric field strength up to the avalanche field strength in a current filament, so that the electric field profile has a negative gradient between the two peaks at the front and backside (Egawa effect) and a dynamic avalanche breakdown, which further increases the local current density, can even occur at the n / n +-Interface between the semiconductor layer 120 and the connection layer 130. The resulting high thermal stress in the affected current filaments can irreversibly damage the semiconductor part 100.

[0032] In conventional semiconductor devices, an outer portion of the element region 610, which directly adjoins the edge region 690, conducts mobile charge carriers from both the edge region 690 and the affected portion of the element region 610 such that the outer portion of the element region 610 has the highest probability of destructive current filaments occurring therein. The outer portion of the element region 610 determines the avalanche resistance of the entire semiconductor device.

[0033] In contrast, the overcompensation region 125 of the embodiment reduces the active emitter area in the edge region 690 and, consequently, the local emitter efficiency. The reduced emitter efficiency, in turn, results in lower current densities in the edge region 690. When switching from the conducting mode to a blocking mode, the outer part of the element region 610 conducts fewer charge carriers than in conventional devices. Furthermore, the additional impurities in the overcompensation region 125 reduce both the charge carrier mobility and the lifetime of minority charge carriers in the edge region 690, further reducing the injection of free charge carriers in this region.

[0034] Furthermore, in the presence of high densities of mobile charge carriers of the first conductivity type, for example, electrons in the case of an n-FET, the overcompensation region 125 injects charge carriers of the second conductivity type, for example, holes in the case of an n-FET, into the semiconductor layer 120, which partially compensate for the charge carriers of the first conductivity type and counteract an increase in the electric field strength. The risk of a destructive dynamic avalanche breakdown due to the Egawa effect is reduced. Undesired dynamic avalanche effects along the edge region 690, which can be destructive to the semiconductor device, can be avoided in such a way that effects that only occur along the perimeter of the element region 610 do not degrade the avalanche strength of the entire device.

[0035] The overcompensation region 125 may extend along all four edges. According to one embodiment, the overcompensation region 125 may be formed in a circumferential part of the edge region 690 that directly adjoins the outer surface 103 of the semiconductor die 500, or in a circumferential part at a certain distance from the outer surface 103. According to another embodiment, the overcompensation region is formed approximately in the entire edge region 690.

[0036] The overcompensation region 125 may extend into the element region 610 to some extent. For example, an overlap between the overcompensation region 125 and the element region 610 may be uniform along one, two, or more edges, e.g., along the entire circumference. According to another embodiment, the overcompensation region 125 comprises stripe regions extending from the edge region 690 into or through the element region 610. According to another embodiment, the overcompensation region 125 is not formed in the element region 610 or comprises stripe regions that align with conductive lines for connecting gate electrodes or field electrodes in the element region 610, such that the efficiency of the element region 610 is not reduced by the overcompensation region 125. An average net impurity concentration in the overcompensation region 125 is at least 1 × 10 17 cm -3, e.g. at least 1 × 10 18 cm -3 .

[0037] The overcompensation region 125 may extend along the interface between the connection layer 130 and the drift zone 121 and may be formed entirely or mainly in the connection layer 130, entirely or mainly in the drift zone 121, or both in the connection layer 130 and the drift zone 121. According to one embodiment, the overcompensation region 125 is formed in a region of the semiconductor layer 120 that is aligned towards the connection layer 130 and at a distance from the connection layer 130, wherein the distance to the connection layer is smaller than that to the first surface 101. The distance to the connection layer 130 may be between 0% and 30% of a vertical extent of the drift zone 121, so that the overcompensation region 125 is sufficiently close to the n / n +-interface. The vertical extension of the overcompensation region 125 can be at least 200 nm, for example, at least 1 µm, so that the overcompensation region 125 can accommodate a sufficiently large number of charge carriers. Parts of the drift zone 121 separate the overcompensation region 125 from other impurity regions and insulator structures of the edge termination structure.

[0038] The overcompensation region 125 is spatially separated from an electrode structure that is adjacent to the second surface and is potential-free.

[0039] As in Fig. 1A, the semiconductor layer 120 may include a field stop zone 128 of the first conductivity type between the drift zone 121 and the interconnect layer 130, wherein the field stop zone 128 has a higher average impurity concentration than the drift zone 121 and a lower average impurity concentration than the interconnect layer 130. For example, an average impurity concentration in the field stop zone 128 exceeds the average impurity concentration in the drift zone 121 by at least five times and is at least five times lower than the average impurity concentration in the interconnect layer 130. In the field stop zone 128, the net impurity or net dopant concentration may be uniform. According to further embodiments, the field stop zone 128 may include two or more uniformly doped and vertically arranged portions with different impurity or dopant concentrations.The impurity concentration in the field stop zone 128 may change, for example, linearly, with increasing distance from the first surface 101. According to further embodiments, a vertical impurity profile of the field stop zone 128 is a Gaussian distribution. Alternatively or in addition to the field stop zone 128, the semiconductor part 100 may have a buffer region with an average net impurity concentration that is less than or equal to the average net dopant concentration in the drift zone 121.

[0040] The overcompensation region 125 may be formed exclusively within the field stop zone 128, in vertically adjacent sections of the field stop zone 128 and the connecting layer 130, or in vertically adjacent sections of the field stop zone 128 and the drift zone 121.

[0041] Similarly, the overcompensation region 125 may be formed exclusively within the buffer region, in vertically adjacent portions of the buffer region and the interconnect layer 130, or in vertically adjacent portions of the buffer region and the drift zone 121.

[0042] According to Fig. 1B, the overcompensation region 125 is a ring surrounding the element region 610, or comprises such a ring, wherein the overcompensation region 125 directly adjoins both the outer surface 103 and the element region 610 and extends over the entire edge region 690. According to other embodiments, the overcompensation region 125 may be arranged at a distance from the outer surface 103 or the element region 610, or from both the outer surface 103 and the element region 610.

[0043] In Fig. 1C, the overcompensation region 125 includes stripe regions 125b that extend from the edge region 690 into the element region 610 and terminate there. The stripe regions 125b may be aligned with connection lines formed on the first surface 101 to connect conductive structures within the element region 610 to each other and / or to contact pads or electrical circuits outside the element region 610. For example, the stripe regions 125b are vertically aligned with gate fingers that connect gate electrodes to the element region 610. Alternatively or additionally, the overcompensation region 125 may include further stripe regions 125c that extend from the edge region 690 into the element region 610 and extend through the entire element region 610. The further stripe regions 125c may be arranged in the vertical projection of conduction lines arranged above the first surface 101.For example, the further stripe regions 125c may be arranged in the vertical projection of field electrode connecting lines.

[0044] The overcompensation area 125 of the Fig. 1D has two spatially separated concentric annular islands 125a spaced apart from the outer surface 103 and the element region 610.

[0045] Fig. 1E illustrates an overcompensation region 125 comprising a plurality of spatially separated islands 125a. The lateral cross-sections of the islands may be circles, ovals, ellipses, or polygons with sharp or rounded corners, e.g., rectangles. The spatially separated islands 125a may be regularly arranged along one, two, or more concentric rings around the element region 610. Alternatively, the overcompensation region 125 may have the reverse shape and include a connected region with oppositely doped "holes," whose lateral cross-sections may be circles, ovals, ellipses, or polygons with sharp or rounded corners, e.g., rectangles. The holes may be regularly arranged along one, two, or more concentric rings around the element region 610.

[0046] A lateral voltage drop across the overcompensation region 125 is a function of its lateral extent. The voltage drop across each individual island 125a is smaller than the voltage drop across a single overcompensation region 125 surrounding the element region 610. With sufficiently small lateral voltage drops, the islands 125a do not inject charge carriers at the comparatively low current densities in the normal operating mode of the semiconductor device.

[0047] Fig. 2A and Fig. 2B refer to foreign matter profiles along lines II and II-II of the Fig. 1A. Fig. 2A illustrates the vertical impurity profiles (impurity concentration gradients) of atoms of a first impurity type (first impurities) in the element region 610. The connection layer 130 may have a uniform initial impurity concentration of more than 10 17 cm -3 , for example approximately 5 × 10 16 cm-3 or even higher. The field stop zone 128 may be an epitaxial layer having a uniform initial impurity concentration that is at least five times lower than that of the interconnect layer 130. According to one embodiment, the initial impurity concentration in the field stop zone may be at most 5 × 10 16 cm -3 A drift zone 121 of the semiconductor layer 120 is formed from an epitaxial layer having a uniform initial impurity concentration that is at least five times smaller than that of the field stop zone 128, for example at least 10 14 cm -3 , is formed. According to the embodiment, the initial impurity concentration in the drift zone 121 is 2 × 10 14 cm -3 and the initial impurity concentration in the field stop zone 128 2 × 10 15 cm -3 .

[0048] In super-junction devices, the impurity concentration in the part of the drift zone 121 that forms part of the super-junction structure can have an average net impurity concentration between 1 × 10 15 and 1 × 10 17 cm -3 Accordingly, the initial impurity concentration in the field stop zone 128 may be higher than 2 × 10 15 cm -3 , for example up to 2 × 10 16 cm -3 , be.

[0049] According to a further embodiment, the initial impurity concentrations of the field stop zone 128 and / or the drift zone 121 are not uniform, but vary along the vertical direction. The impurities in the connection layer 130 are, for example, arsenic atoms, and the impurities in the field stop zone 128 are phosphorus atoms. The impurity profiles 201a indicate the initial impurity profiles along line II of the Fig. 1A for phosphorus and the impurity profiles 201b for arsenic atoms.

[0050] The final impurity profiles 211a, 211b result from the initial impurity profiles 201a, 201b by thermal annealing at a high temperature, for example, at 1150 degrees Celsius for 200 minutes. During thermal annealing, the impurities diffuse from more highly doped regions to less highly doped regions, smoothing the impurity profiles and resulting in, for example, the final impurity profiles 211a and 211b.

[0051] Fig. Figure 2B shows the corresponding foreign matter profiles in the edge region 690. In addition to the foreign matter profiles 201a, 201b, 211a, 211b of the Fig. 2A represents Fig. 2B illustrates an initial impurity profile 202 for second impurities of the second conductivity type resulting from the implantation of boron at the interface between the semiconductor layer 120 and the interconnect layer 130 with an areal density of 2 × 10 14 cm -2and an implantation energy of 80 keV in the edge region 60. The final impurity profile 212 for the second impurities results after thermal annealing. The initial impurity profile 202, i.e., the implantation of boron, is controlled such that after annealing, the implanted boron overcompensates the first impurities in a predetermined overcompensation region 125. The conductivity type of the overcompensation region 125 is opposite to that of the connection layer 130 and the drift zone 121. The resulting reduced emitter efficiency leads to lower current densities in the edge region 690. At high field strengths along the pn junction along the edges of the overcompensation region 125, the overcompensation region 125 injects mobile charge carriers, which reduce the charge of the mobile charge carriers near the n / n +interface and thereby counteract a further increase in the electric field strength and prevent the triggering of an avalanche breakdown at the n / n + -interface. The hatched area in Fig. 2B between the final impurity profiles 212a, 211b and 211a defines the overcompensation area 125.

[0052] The implantation of the second impurities may be performed before the semiconductor layer 120 is grown by epitaxy on the interconnect layer 130. A high-temperature process, e.g., an RTA ("rapid thermal annealing") process or a laser process with or without melting, may be used to heal implantation damage caused by the second impurities prior to epitaxial deposition. An oxidation process may be performed to heal implantation damage occurring at high implantation doses, removing the grown oxide before further portions of the semiconductor layer 120 are grown by epitaxy on the interconnect layer 130. Alternatively, the implantation of the second impurities may be performed after a first portion of the field stop zone 128 has been formed by epitaxy.The implantation damage caused by the implanted foreign substances can be healed and a second part of the field stop zone 128 can then be formed.

[0053] Fig. 3A and Fig. 3B relate to an embodiment in which co-implantation of first and second impurities into the interconnect layer 130 is used, and illustrate impurity profiles along lines II and II-II of Fig. 1B. According to Fig. 3A, the compound layer 130 in the element region 610 has initial impurity profiles 301b of arsenic atoms with a uniform initial impurity concentration of about 5 × 10 18 cm -3 which correspond to a specific electrical resistance of approximately 10 mΩcm. A field stop zone 128 directly adjoins the connection layer 130. The field stop zone 128 has an initial uniform impurity concentration of first impurities of approximately 2 × 10 15cm -3 A drift zone 121 has a uniform initial impurity concentration of phosphorus atoms of 2 × 10 14 cm -3 After thermal annealing at 1150 degrees Celsius for 200 minutes, the final impurity profile 311a for phosphorus and the final impurity profile 311b for arsenic are derived from the initial impurity profiles 301a and 301b.

[0054] Fig. Figure 3B shows the foreign matter profiles in the edge region 690. The initial and final foreign matter profiles 301a, 301b, 311a, 311b correspond to those of Fig. 3A. Furthermore, to form the overcompensation region 125, an initial impurity profile 303 of boron atoms is implanted by means of an implantation of 3 × 10 14 cm -2boron and an implantation energy of 70 keV. An additional implantation of phosphorus atoms can be used to precisely adjust the position, extent, and impurity profile of the overcompensation region 125. For example, the phosphorus atoms are implanted with an implantation dose of 2 × 10 14 cm -2 and an implantation energy of 45 keV at the interface between the interconnect layer 130 and the semiconductor layer 120, as represented by the initial doping profile 302. Due to the similar diffusion properties of phosphorus and boron, after annealing, the position and extent of the hatched area 125x between the final impurity profiles 312, 313, which defines the overcompensation region 125, are precisely defined.

[0055] The additional phosphorus implantation increases the scattering and recombination of charge carriers, resulting in reduced charge carrier mobility and minority carrier lifetime in the edge region 690 and thus reduced injection of free charge carriers in this area. The additionally implanted phosphorus reduces a potential reduction in breakdown voltage and unwanted injection under other operating conditions.

[0056] While the embodiments of the Fig. 3A and Fig. 3B combine a phosphorus / boron co-implantation with an arsenic compound layer, other embodiments may include implantations of both types in conjunction with other compound layer materials to take advantage of reducing charge carrier mobility and minority carrier lifetime.

[0057] The embodiments comprise a local reduction of the injection of free charge carriers into the edge region by a local compensation-like implantation of impurities to reduce the dynamic robustness of the semiconductor device.

[0058] According to further embodiments, the formation of the overcompensation region 125 may be combined with the formation of a field stop zone 128 in the semiconductor layer 120 in both the edge region 690 and the element region 610, without an epitaxial growth process that provides different dopant concentrations. For example, a field stop zone 128 may be formed by increasing a local phosphorus concentration with respect to a local boron concentration, or by providing a significantly higher implantation energy for boron than for phosphorus. The resulting impurity profiles may provide a field stop zone 128 having an average impurity concentration that is large compared to a concentration of a field stop zone 128 formed from an epitaxially grown layer.

[0059] An average net concentration of foreign matter in the field stop zone 128 in the area 10 15 cm -3 up to 10 16 cm-3 or higher can indicate the beginning of the generation of charge carriers at the n / n + -Interface shift to higher current densities.

[0060] Fig. 4 shows a semiconductor diode 500. A semiconductor part 100 has an n + -doped interconnect layer 130 and a semiconductor layer 120. The interconnect layer 130 may be a substrate layer on which the semiconductor layer 120 is grown by epitaxy. According to further embodiments, the interconnect layer 130 is grown by epitaxy on an auxiliary substrate, which is removed after the epitaxy process by a thinning process of the semiconductor part 100. In other embodiments, the drift zone 121 may be a substrate layer, and the interconnect layer 130 is formed by activated implantation from the second surface 102.

[0061] The semiconductor layer 120 has a drift zone 121 with a lower concentration of n-type impurities than the concentration of the connection layer 130. A p + -doped impurity region 115 forms an anode region that extends along a first surface 101 of the semiconductor part 100. The anode region is formed at a distance from an outer surface 103 that is inclined toward the first surface 101. The p + -doped anode region defines an element region 610 which is surrounded by an edge region 690.

[0062] A first electrode structure 310, which is electrically connected to the anode region, may directly adjoin the first surface 101. A second electrode structure 320 may be formed on a second surface 102 of the semiconductor part 100, which is parallel and opposite the first surface 101. The second electrode structure 320 is electrically connected to the connection layer 130.

[0063] Each of the first and second electrode structures 310, 320 may consist of or contain as a main component: aluminum Al, copper Cu, or alloys of aluminum or copper, for example AlSi, AlCu or AlSiCu. According to further embodiments, one or both of the first and second electrode structures 310, 320 may have as main component(s) nickel Ni, titanium Ti, silver Ag, gold Au, platinum Pt and / or palladium Pd. For example, at least one of the first and second electrode structures 310, 320 has two or more sublayers, wherein each sublayer has one or more from the list of Ni, Ti, Ag, Au, Pt and Pd as main component(s), e.g. silicides and / or alloys.

[0064] In the edge region 690, spatially separated islands 125a form an overcompensation region 125 between the connecting layer 130 and the drift zone 121. In the islands 125a, a counter implant locally overcompensates the n-type impurities of the semiconductor part 100. According to the illustrated embodiment, the overcompensation region 125 is formed in parts of both the drift zone 121 and the connecting layer 130. The overcompensation region 125 is arranged at a distance from the second surface 102, is not electrically connected to the second electrode structure 320, and is potential-free.

[0065] In case a high electric field strength occurs locally next to the pn junctions of the islands 125a, the islands 125a reduce the emitter efficiency and inject holes into the surrounding n-doped structure such that the risk of a destructive avalanche breakdown along an outer part of the element region 610 is reduced.

[0066] Other embodiments may include a field stop zone with an average impurity concentration that is smaller than that of the interconnect layer 130 and greater than that of the drift zone 121, wherein at least a portion of the overcompensation region 125 is formed in the field stop zone. According to other embodiments, the overcompensation region 125 is limited to the interconnect layer 130 or the field stop zone.

[0067] In Fig. 5A, an IGBT 500 has a semiconductor part 100 with a p + -doped connection layer 130. A semiconductor layer 120 with an n - -doped drift zone 121 is arranged in direct contact with the connection layer 130. An n-doped field stop zone 128 can be arranged in the semiconductor layer between the connection layer 130 and the n - -doped drift zone 121. In an element region 610, p-doped impurity regions 115, which form body regions, separate n +-doped emitter regions 110, which are formed as impurity wells within the body regions, from the drift zone 121. A voltage applied to gate electrodes 210, which are arranged in trenches extending through the impurity regions 115 into the drift zone 121 and are separated from the impurity regions (body regions) 115 by gate dielectrics 205, controls a current through the impurity regions 115.

[0068] A first electrode structure 310 is formed on the first surface 101 and is electrically connected to the impurity regions 115 and the emitter regions 110. A second electrode structure 320 directly adjoins the connection layer 130 and is electrically connected to the connection layer 130. Regarding the structure and materials of the first and second electrode structures, reference is made to the description of Fig. 4.

[0069] In an edge region 690 extending along an outer surface 103, a field plate termination structure may be formed, comprising a dielectric layer 295 between the semiconductor portion 100 and the first electrode structure 301 and a lightly p-doped junction termination extension region 125 formed in the semiconductor layer 120 along the first surface 101. On the second surface 102 parallel to the first surface 101, the second electrode structure 320 and the connecting layer 130 may extend over the entire cross-sectional area of ​​the semiconductor portion 100.

[0070] An n-type compensation zone 125, which may be formed in one piece or comprise spatially separated islands 125a, is formed in an edge region 690 in a portion of the semiconductor part 100 oriented toward the second surface 102. The islands 125a may be formed entirely or completely in the semiconductor layer 120. In the islands 125a, a counter implantation overcompensates for the p-type impurities in the semiconductor layer 120.

[0071] When switching from a forward conducting state to a forward blocking state, the n-doped islands can inject 125a electrons, which compensate for holes previously injected from the backside in the forward on state.

[0072] According to the embodiment of Fig. 5B, the electrode structure 320 is missing in the edge region 690. The interconnect layer 130 may be missing in the edge region 690 or may have a region of high dynamic robustness 131 that locally reduces the emitter efficiency in the edge region 690. The n-doped islands 125a may extend into the region of high dynamic robustness 131.

[0073] Fig. 6A refers to an n-IGFET with an n-doped interconnect layer 130. The drift zone 121 has a low-doped region 121a directly adjacent to the interconnect layer 130 and a more highly doped portion 121b between the low-doped portion 121a and the first impurity regions 115 forming the body regions. Gate trenches have field electrodes 250 separated from the drift zone 121 by a field dielectric 235 that is thicker than the gate dielectric 205. In the edge region 690, a field plate termination structure includes a dielectric layer 295 separating the first electrode structure 310 from the semiconductor part 100, and a p-doped junction terminal extension region (JTE) 195 formed in the semiconductor layer 120 and extending from the cell region 610 into the edge region 690. The junction terminal extension region 195 is arranged at a distance from the outer surface 103.

[0074] P-doped islands 125a are formed along an interface between the semiconductor layer 120 and the connection layer 130 in the edge region 690. The islands 125a are arranged at a distance from both the second surface 102 and the junction terminal extension region 195. Parts of the drift zone 121 completely seal off the overcompensation region with the islands 125 from other structures formed between the first surface 101 and the islands 125a. The p-doped islands 125a are completely embedded in n-doped regions.

[0075] The drift zone 121 may have a more highly doped region 121b between the gate trenches and a less highly doped region 121a between the more highly doped region 121b and the interconnect layer 130.

[0076] The n-IGFET from Fig. 6B shows an edge termination structure with field electrodes 250 arranged in trenches extending from the first surface 101 through the more highly doped region 121b of the drift zone 121 into the less highly doped region 121a. Thick field electrode dielectrics 235 electrically insulate the field electrodes 250 from the surrounding semiconductor material. Below the trenches with the field electrodes 250, p-type "bubbles" 123 shape the electric field in the edge region 690 such that the curvature (the radius of curvature) of equipotential lines is smoothed in reverse operation. Parts of the drift zone 121 separate the bubbles 123 and the islands 125a. P-doped islands 125a of an overcompensation zone are spatially separated from the bubbles 123 by parts of the drift zone 121.

[0077] Fig. 6C refers to a superjunction device. In the semiconductor layer 120, p-doped pillars 122a and n-doped pillars 122b alternate in a regular manner. The pillars may be stripes. According to other embodiments, the pillars may have a circular, ellipsoidal, oval, or rectangular cross-sectional area with rounded corners, for example, that of a square or approximately a square. When a reverse voltage is applied to the superjunction n-IGFET of the Fig. 6C, the n-type region 120a is completely depleted, so that a comparatively high reverse breakdown voltage can be achieved at comparatively high impurity concentrations in the n-type columns 120b, which in turn results in a comparatively low on-resistance. A buffer region 128b can be arranged between the connection layer 130 and the drift zone 121, wherein the average impurity concentration in the buffer region 128b is lower than in the connection layer 130. The impurity concentration in the n-columns 122b can be at least 1 × 10 15 and a maximum of 1 × 10 17 cm -3 According to other embodiments, a field stop zone may be formed instead of or in addition to the buffer region 128b. The average impurity concentration in the field stop zone may be at least 2 × 10 15 and a maximum of 2 × 10 16 cm -3 be.

[0078] Fig.7 relates to a method for manufacturing a semiconductor device. A semiconductor layer having a drift zone of a first conductivity type is formed on an interconnect layer (702). An overcompensation region of a second conductivity type is formed in an edge region surrounding an element region of the semiconductor device. The overcompensation region may include first impurities of the first conductivity type and second impurities of the second conductivity type opposite to the first conductivity type (704).

[0079] In an element region surrounded by the edge region, at least one impurity region of the second conductivity type is formed, which adjoins a first surface of the semiconductor layer opposite the connection layer (706).

[0080] A mask implantation can be used to implant second impurities into the edge region. The implantation can be activated by thermal annealing or by a laser-induced melting / welding process. According to one embodiment, the second impurities are boron atoms, and the first impurities are phosphorus atoms. According to one embodiment, the implanted boron atoms can be activated simultaneously with the activation of the implanted phosphorus atoms.

[0081] According to the embodiments relating to power MOSFETs or IGBTs, the implantation(s) performed to create the overcompensation region may be performed on a surface of an interconnect layer on which the semiconductor layer is epitaxially grown.

[0082] Forming the overcompensation region may comprise performing a co-implantation using second impurities of the second conductivity type in combination with first impurities of the first conductivity type.

[0083] Although specific embodiments are illustrated and described herein, it will be understood by those skilled in the art that a variety of alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover all adaptations or modifications of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] A semiconductor device comprising a semiconductor part (100), the semiconductor part (100) comprising: a semiconductor layer (120) having a drift zone (121) of a first conductivity type and at least one impurity region (115) of a second opposite conductivity type, which adjoins a first surface (101) of the semiconductor part (100) in an element region (610); a connecting layer (130) which directly adjoins the semiconductor layer (120) opposite the first surface (101), wherein an average impurity concentration in the connecting layer (130) is at least ten times greater than an average impurity concentration in the drift zone (121); and an overcompensation region (125) in an edge region (690) surrounding the element region (610), wherein the overcompensation region (125) is absent in the element region (610), and wherein the overcompensation region (125) and the connecting layer (130) have opposite conductivity types and a part of the drift zone (121) is arranged in a direction vertical to the first surface (102) between the first surface (101) and the overcompensation region (125). [2] The semiconductor device according to claim 1, wherein the interconnection layer (130) has the first conductivity type. [3] The semiconductor device according to any one of the preceding claims, wherein the overcompensation region (125) comprises at least first impurities of the first conductivity type and second impurities of the second conductivity type, wherein a concentration of the second impurities locally exceeds the concentration of the first impurities. [4] The semiconductor device according to claim 3, wherein the concentration of the second impurities exceeds the concentration of the first impurities in parts of the overcompensation region (125) by at least 10%. [5] The semiconductor device according to any one of the preceding claims, wherein the overcompensation region (125) is formed in a portion of the semiconductor layer (120) oriented toward the interconnect layer (130). [6] The semiconductor device according to any one of the preceding claims, wherein the semiconductor device is a diode (500), the impurity region (115) forms an anode region, and the interconnection layer (130) has the first conductivity type. [7] The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is an insulated gate field effect transistor, the impurity region (115) forms a body region and the connection layer has the first conductivity type, and wherein the semiconductor device further comprises an impurity well of the first conductivity type, the impurity well being formed in the body region and adjacent to the first surface. [8] The semiconductor device according to claim 3 or 4, wherein the first impurities comprise phosphorus atoms and the second impurities are boron atoms. [9] The semiconductor device according to any one of the preceding claims, wherein the semiconductor layer (120) has a field stop zone (128) which directly adjoins the connecting layer (130), wherein the field stop zone (128) has the first conductivity type, an average impurity concentration in the field stop zone (128) is greater than an impurity concentration in the drift zone (121), and an average impurity concentration in the connecting layer (130) exceeds the average impurity concentration in the field stop zone (128) by at least five times, and at least a part of the overcompensation region (125) is formed in the field stop zone (128). [10] The semiconductor device according to any one of the preceding claims, wherein the semiconductor device comprises a buffer region directly adjacent to the interconnect layer (130), wherein the buffer region has the first conductivity type, an average net impurity concentration in the buffer region is lower than an impurity concentration in the drift zone (121), and an average net impurity concentration in the interconnect layer (120) is at least five times the average net impurity concentration in the buffer region, and at least part of the overcompensation area (125) is formed in the buffer area. [11] The semiconductor device according to any one of the preceding claims, wherein the overcompensation region (125) directly adjoins the connection layer (130). [12] The semiconductor device according to any one of the preceding claims, wherein a vertical extension of the overcompensation region (125) in a direction perpendicular to the first surface (101) is at least 200 nm. [13] The semiconductor device according to any one of the preceding claims, wherein the overcompensation region (125) is formed at a distance from the first surface (101) and an opposite second surface (102) of the semiconductor part (100). [14] The semiconductor device according to any one of the preceding claims, wherein the overcompensation region (125) comprises a plurality of spatially separated islands (125a). [15] The semiconductor device according to any one of the preceding claims, wherein a thickness of the connecting layer (130) may be at least 30% of the thickness of the semiconductor layer (120). [16] Power field effect transistor with a semiconductor part (100), wherein the semiconductor part (100) comprises: a semiconductor layer (120) with a drift zone (121) of a first conductivity type, regularly alternating p-doped columns (122a) and n-doped columns (122b) and with at least one impurity region (115) of a second opposite conductivity type, which in an element region (610) directly adjoins a first surface (101) of the semiconductor part (100); a connecting layer (130) of the first conductivity type, which directly adjoins the semiconductor layer (120) opposite the first surface (101), wherein an average impurity concentration in the connecting layer (130) is at least ten times greater than an average impurity concentration in the drift zone (121); and an overcompensation region (125) of the second conductivity type in an edge region (690) surrounding the element region (610), wherein the overcompensation region (125) is vertically spaced from the p-doped columns (122a) and from the n-doped columns (122b), and wherein a part of the drift zone (121) is arranged in a direction vertical to the first surface (101) between the first surface (101) and the overcompensation region (125). [17] An insulated gate power bipolar transistor comprising a semiconductor portion (100), the semiconductor portion (100) comprising: a semiconductor layer (120) having a drift zone (121) of a first conductivity type and at least one impurity region (115) of an opposite second conductivity type, which in an element region (610) directly adjoins a first surface (101) of the semiconductor part (100); a connecting layer (130) of the second conductivity type, which directly adjoins the semiconductor layer (120) opposite the first surface (101), wherein an average impurity concentration in the connecting layer (120) is at least ten times greater than an average impurity concentration in the drift zone (121); and an overcompensation region (125) of the first conductivity type in the semiconductor part (100) in an edge region (690) surrounding the element region (610), wherein the overcompensation region (125) is absent in the element region (610), and wherein a part of the drift zone (121) is arranged in a direction vertical to the first surface (101) between the first surface (101) and the overcompensation region (125). [18] The insulated gate power bipolar transistor of claim 17, wherein the overcompensation region (125) is formed at a distance from the first surface (101) and an opposite second surface (102) of the semiconductor part (100). [19] A method of manufacturing a semiconductor device, the method comprising: Forming a semiconductor layer (120) having a drift zone (121) of a first conductivity type, wherein the semiconductor layer (120) adjoins a connecting layer (130) and an average impurity concentration in the connecting layer (130) is at least ten times an average impurity concentration in the drift zone (121); forming an overcompensation region (125) of a conductivity type opposite to the conductivity type of the connection layer selectively in an edge region (690) surrounding an element region (610), wherein a part of the drift zone (121) is arranged between the first surface (101) and the overcompensation region (125) in a direction vertical to the interface between the connection layer (120) and the semiconductor layer (130); and Forming at least one impurity region (115) of a second conductivity type, which is opposite to the first conductivity type, in the element region (610), wherein the at least one impurity region (115) adjoins a first surface (101) of the semiconductor layer (120) opposite the connection layer (130). [20] The method of claim 19, wherein forming the overcompensation region (125) comprises Forming a foreign matter mask that leaves the edge region (690) free and covers the element region (610); and Forming the overcompensation region (125) by a doping process using the impurity mask. [21] The method of claim 19 or 20, further comprising: Forming impurity wells of the first conductivity type in the impurity regions (115) of the second conductivity type in the element region (610). [22] The method of claim 21, further comprising: Forming a first electrode structure (310) on the first surface (101), wherein the first electrode structure (310) is electrically connected to the impurity wells in the element region (610). [23] The method according to one of claims 19 to 22, wherein the formation of the overcompensation region (125) comprises introducing impurities of the conductivity type opposite to the conductivity type of the connection layer (130) through at least one opening of an impurity mask in a impurity portion of a process surface of the connection layer (130) and growing the semiconductor layer (120) onto the connection layer (130) by means of epitaxy, wherein the impurity portion corresponds to the edge region (690). [24] The method according to any one of claims 19 to 23, wherein forming the overcompensation region (125) comprises Growing a first portion of the semiconductor layer (120) on the connection layer (130) by means of epitaxy, Introducing impurities of a conductivity type opposite to the conductivity type of the connection layer (130) through at least one opening of a impurity mask into a impurity section of a process surface of the first section of the semiconductor layer (120), wherein the impurity section corresponds to the edge region (690), and Growing a second portion of the semiconductor layer (120) on the first portion by epitaxy.

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