SEMICONDUCTOR DEVICE, ELECTRONIC ARRANGEMENT AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising: a cell array (610) comprising a gate structure (150), a plurality of field electrode structures (160) arranged in rows, and cell mesas (170) separating adjacent individual field electrode structures of the field electrode structures (160) from one another, each field electrode structure (160) comprising a needle-shaped field electrode (165) and a field dielectric (161) separating the field electrode (165) from a semiconductor body (100), wherein the cell array (610) has a central part (611) with functional transistor cells (TCF) and a transition region (619) with non-functional transistor cells (TCN), wherein the functional transistor cells (TCF) each have at least one of the field electrode structures (160), a source zone (110) of a first conductivity type and a body zone (115) of a second, complementary conductivity type, wherein the non-functional transistor cells (TCN) each have one of the field electrode structures (160), and wherein source zones (110) are missing in cell mesas that separate the field electrode structures (160) of non-functional transistor cells (TCN) from one another, a termination structure (180) surrounding the cell field (610), wherein the termination structure (180) extends from a first surface (101) into the semiconductor body (100) and has a termination electrode (185) and a termination dielectric (181) separating the termination electrode (185) from the semiconductor body (100), wherein the termination and field dielectrics (181, 181) have the same thickness, and a termination mesa (190) which is wider than the cell mesas (170) and separates the termination structure (180) from the transition region (619) of the cell field (610).

Description

BACKGROUND

[0001] Power semiconductor devices based on IGFET (insulated gate field-effect transistor) cells are typically vertical devices with a load current flowing between a first surface on a front side of a semiconductor die and a second surface on a back side. In a blocking mode, stripe-shaped compensation structures extending from the front side into the semiconductor die deplete semiconductor mesas formed between the stripe-shaped compensation structures. The compensation structures allow higher dopant concentrations in the semiconductor mesas without adversely affecting the blocking capabilities. Higher dopant concentrations, in turn, reduce the on-resistance of the device.Typically, termination structures form end portions of the semiconductor mesas at the edge of a cell array including the IGFET cells in such a way that the doping to be depleted at the end portions is approximately equal to the doping depleted in a central part of the cell array.

[0002] The document DE 10 2004 009 602 A1 describes a field-plate trench transistor with a cell array in which parallel, strip-shaped cell array trenches are formed. An edge structure frames the cell array. An edge trench is formed in the edge structure and is spaced apart from the cell array, with the distance between the edge trench and the cell array trench corresponding to the distance between adjacent cell array trenches.

[0003] The document DE 10 2006 007 096 A1 relates to a MOSFET with a compensation structure and edge termination. Source electrodes extend from the front side into the semiconductor body. A thick oxide separates the source electrodes from the semiconductor body. Gate electrodes are embedded in the upper part of the thick oxide. The outermost compensation structure extends into an outer section of the drift zone, which is more lightly doped than an inner section of the drift zone into which the other compensation structures extend.

[0004] In the trench compensation structures of the MOSFETs of US 2012 / 0 153 386 A1 and DE 11 2004 002 608 B4, the field electrodes are arranged below the gate electrodes in inner compensation trenches. The gate electrode is missing in outer compensation trenches. The outer compensation trenches contain a field electrode, which in US 2012 / 0 153 386 A1 is at the potential of the p-doped region directly adjacent to the inner compensation trenches, and in DE 11 2004 002 608 B4 is at the front-side potential. The inner compensation trenches are strip-shaped, and the outer compensation trenches surround the inner compensation trenches in a ring-shaped manner. In the document DE 11 2004 002 608 B4, the distance between the only outer compensation trench and the end face of the inner compensation trenches is half the distance between adjacent inner compensation trenches.The document DE 11 2004 002 608 B4 also describes a double-trench design in which the gate electrode and field electrode are formed in different trenches. The trenches for the field electrodes extend deeper than the trenches for the gate electrodes.

[0005] Document DE 10 2005 052 734 B4 describes the cell array of a vertical MOSFET with strip-shaped trench gate electrodes and needle-shaped field electrodes arranged in field electrode rows. Each trench gate electrode runs parallel to and between two field electrode rows.

[0006] The vertical power semiconductor components of document DE 10 2014 101 164 A1 have overcompensation regions formed in an edge region near the rear of the component that encloses the active region on all sides. When local charge carrier currents occur as a result of an avalanche breakdown, the overcompensation regions inject charge carriers of the opposite type and counteract a further increase in the electric field strength.

[0007] The document US 2008 / 0 038 891 A1 concerns the cell field of a lateral high-voltage MOSFET (HVMOSFET) with silicon / silicon-germanium heterojunction.

[0008] The document US 2012 / 0 061 753 A1 describes the cell array of a MOSFET with two types of trench electrodes. The gate electrode forms a gate grid. Field plate electrodes extend from the front side into the drift zone through the mesh openings of the gate grid. The vertical extent of the field plate electrodes is greater than that of the gate electrode.

[0009] The document US 2011 / 0 136 309 A1 relates to an IGFET (insulated gate field effect transistor). The cell array comprises a grid-like gate / compensation trench or strip-like gate / compensation trenches, with the field electrode being formed below the gate electrode in each case.

[0010] It is desirable to provide semiconductor devices with low ohmic losses and unproblematic avalanche breakdown properties or characteristics. SUMMARY

[0011] The problem is solved by the subject matter of the independent patent claims. The dependent patent claims relate to further embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain principles of the invention. Other embodiments of the invention and intended advantages will be readily appreciated as they become better understood by reference to the following detailed description. Fig. 1A is a schematic top view of a semiconductor device according to an embodiment related to a perimeter termination structure and a termination mesa that is wider than cell mesas. Fig. 1B is a schematic vertical sectional view of a portion of the semiconductor device of Fig. 1A. Fig. 2A is a schematic perspective cross-sectional view of a portion of a semiconductor device according to an embodiment. Fig. 2B shows a charge carrier generation during an avalanche breakdown in the semiconductor device part of Fig. 2A. Fig. 3 is a schematic diagram plotting the breakdown voltage as a function of the termination mesa width to illustrate effects of the embodiments. Fig. 4A is a schematic horizontal cross-sectional view of a portion of a semiconductor device according to an embodiment related to a termination structure with chamfered corners and gate structures in gates. Fig. 4B is a schematic vertical sectional view of the semiconductor device part of Fig. 4A along a line BB. Fig. 4C is a schematic horizontal cross-sectional view of a portion of a semiconductor device according to another embodiment related to a termination structure with chamfered corners and gate structures embedded in field dielectrics. Fig. 4D is a schematic vertical sectional view of the semiconductor device part of Fig. 4C along a line DD. Fig. 5A is a schematic perspective sectional view of a part of a semiconductor device according to an embodiment with chamfered corners for illustrating effects of the embodiments. Fig. 5B shows a charge carrier generation in the semiconductor device part of Fig. 5A during an avalanche breakthrough. Fig. Figure 5C is a schematic diagram illustrating process windows applied to the semiconductor device of the Fig. 5A and Fig. 5B are related. Fig. 6A is a schematic horizontal cross-sectional view of a portion of a semiconductor device according to an embodiment related to octagonal field electrode structures arranged in shifted lines and a termination structure of approximately constant width. Fig. 6B is a schematic horizontal cross-sectional view of a portion of a semiconductor device according to an embodiment related to square field electrode structures arranged in shifted lines and a termination structure with rectangular bulges. Fig. 7 is a simplified circuit diagram of an electronic circuit according to another embodiment. Fig. 8A is a schematic cross-sectional view of a portion of a semiconductor substrate for illustrating a method of manufacturing a semiconductor device according to an embodiment after forming a termination trench and field electrode trenches. Fig. 8B is a schematic sectional view of the semiconductor substrate part of Fig. 8A after forming a sacrificial oxide layer. Fig. Figure 8C is a schematic cross-sectional view of the semiconductor substrate portion of Fig. 8B after removal of the sacrificial oxide layer. Fig. 8D is a schematic cross-sectional view of the semiconductor substrate part of Fig. 8C after formation of a field oxide layer. Fig. 8E is a schematic cross-sectional view of the semiconductor substrate portion of Fig. 8B after application or deposition of a field dielectric layer. Fig. 8F is a schematic sectional view of the semiconductor substrate part of Fig. 8E after application or deposition of a field electrode material. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which is shown, for purposes of illustration, specific embodiments in which the invention may be practiced. The drawings are not to scale and are for illustration purposes only. For clarity, like elements are indicated by corresponding reference characters throughout the various drawings unless otherwise noted.

[0014] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" encompasses the possibility of one or more intermediate elements configured for signal transmission being provided between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0015] The figures illustrate relative doping concentrations by indicating “ - " or " + “ is closest to the doping type “n” or “p”. For example, “n -” a doping concentration that is lower than the doping concentration of an “n” doping region, while an “n + "-doping region has a higher doping concentration than an "n"-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doping regions can have the same or different absolute doping concentrations.

[0016] The Fig. 1A and Fig. 1B refer to a semiconductor device 500 comprising a plurality of identical IGFET (Insulated Gate Field Effect Transistor) cells TC. The semiconductor device 500 may be or comprise an IGFET, for example, a MOSFET (Metal Oxide Semiconductor FET) in the usual sense, including FETs with metal gates as well as FETs with non-metal gates. According to another embodiment, the semiconductor device 500 may be an IGBT.

[0017] The semiconductor device 500 is based on a semiconductor body 100 made of a single-crystal semiconductor material, such as silicon (Si), silicon carbide (SiC), germanium (Ge), a silicon-germanium crystal (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), or any other A III B V -Semiconductor.

[0018] The semiconductor body 100 has a first surface 101, which may be approximately planar or defined by a plane spanned by coplanar surface portions, and a planar second surface 102 parallel to the first surface 101. A distance between the first and second surfaces 101, 102 is defined by a specific voltage blocking capability and may be at least 20 µm. According to other embodiments, the distance may be in a range of several hundred micrometers. A lateral surface 103, which is inclined to the first and second surfaces 101, 102, connects the first and second surfaces 101, 102.

[0019] In a plane parallel to the first surface 101, the semiconductor body 100 may have a rectangular shape with an edge length of a few millimeters. A normal to the first surface 101 defines a vertical direction, and directions orthogonal to the vertical direction are horizontal directions.

[0020] Each transistor cell TC comprises a field electrode structure 160 extending from the first surface 101 into the semiconductor body 100 down to a ground plane BPL. Each field electrode structure 160 comprises a conductive spike-shaped or needle-shaped field electrode 165 and a field dielectric 161 surrounding the field electrode 165.

[0021] The field electrode 165 comprises or consists of a heavily doped polycrystalline silicon layer and / or a metal-containing layer. The field dielectric 161 separates the field electrode 165 from the surrounding semiconductor material of the semiconductor body 100 and comprises or consists of a thermally grown silicon oxide layer. According to one embodiment, the field dielectric 161 may further comprise an applied or deposited silicon oxide layer, for example, a silicon oxide layer based on TEOS (tetraethyl orthosilicate).

[0022] A vertical extension of the field electrode structures 160 is smaller than a distance between the first surface 101 and the second surface 102, so that a continuous section CS of the semiconductor body 100 is formed between the field electrode structures 160 and the second surface 102. The vertical extension of the field electrode structures 160 can be in a range from 0.5 µm to 50 µm, for example, in a range from 0.6 µm to 4.0 µm.

[0023] A first horizontal dimension of the field electrode 165 may be at most three times or at most twice as large as a second horizontal dimension orthogonal to the first horizontal dimension. The horizontal dimensions may be in a range of 0.4 µm to 10 µm, for example, in a range of 0.6 µm to 4.0 µm.

[0024] The cross-sectional areas of the field electrodes 165 and the field electrode structures 160 can be ellipses, ovals, rectangles, or regular or distorted polygons, each with or without rounded and / or beveled corners. According to one embodiment, the first and second horizontal dimensions are approximately equal, and the cross-sectional areas of the field electrodes 165 and the field electrode structures 160 are circles or regular polygons, such as octagons, hexagons, or squares, each with or without rounded or beveled corners.

[0025] The field electrode structures 160, which are centered on a horizontal center point CP of the transistor cells TC, are equally spaced and can be arranged in a matrix-like manner in rows and columns in a cell array 610. According to other embodiments, the field electrode structures 160 can be arranged in shifted lines, with the odd lines shifted relative to the even lines by half a distance between the field electrode structures 160. Semiconducting parts of the transistor cells TC are formed in cell mesas 170 of the semiconductor body 100, with the cell mesas 170 protruding from the continuous section CS of the semiconductor body 100, surrounding the field electrode structures 160, and forming a grid, with the field electrode structures 160 arranged in the meshes.

[0026] The cell mesas 170 comprise a second drift zone section 121b of the first conductivity type directly adjacent to a first drift zone section 121a having the same conductivity type and formed in the continuous section CS of the semiconductor body 100 between the bottom plane BPL and the second surface 102. A dopant concentration in the second drift zone section 121b may be the same as a dopant concentration in the first drift zone section 121a. An average dopant concentration in a drift zone 121 including the first and second drift zone sections 121a, 121b may be between 1E15 cm -,3 and 1E17 cm- 3 , for example in a range of 5E15 cm -,3 up to 5E16 cm- 3 , be.

[0027] Outer edges of the outermost field electrode structures 160 define the contour of the cell array 610. The cell array 610 may include a central portion 611 having functional transistor cells TCF having source zones of the first conductivity type and body zones of a second, complementary conductivity type, wherein the body zones separate the source zones from the second drift zone portion 121b. The functional transistor cells TCF further include portions of a gate structure including a gate electrode capacitively coupled to the body zones by a gate dielectric.

[0028] The cell array 610 may further comprise a transition region 619 comprising non-functional transistor cells TCN. In the non-functional transistor cells TCN, the cell mesas 170 may be free of source zones or may be free of source zones and body zones, i.e., both zones, so that in the cell mesas 170 of the transition region 619, the second drift zone section 121b directly adjoins the first surface 101. The non-functional transistor cells TCN may or may not be free of gate electrode structures. The transition region 619 may completely surround the central part 611 and have a uniform width.

[0029] A termination structure 180 completely surrounds the cell array 610 in the horizontal plane. The termination structure 180 extends in an edge region 690 surrounding the cell array 610 from the first surface 101 into the semiconductor body down to at least the bottom plane BPL. The termination structure 180 comprises a termination electrode 185 and a termination dielectric 181 surrounding the termination electrode 185.

[0030] The termination electrode 185 comprises or consists of a heavily doped polycrystalline silicon layer and / or a metal-containing layer. The termination dielectric 181 separates the termination electrode 185 from the surrounding semiconductor material of the semiconductor body 100 and comprises or consists of a thermally grown silicon oxide layer. According to one embodiment, the termination dielectric 181 may further comprise an applied or deposited silicon oxide layer, for example, a TEOS-based silicon oxide. The vertical extent of the termination structure 180 is equal to or greater than the vertical extent of the field electrode structures 160. A width of the termination structure 180 may be equal to or greater than a horizontal extent of the field electrode structures 160.

[0031] The termination and field dielectrics 181, 161 have the same thickness and the same configuration. In other words, the termination and field dielectrics 181, 161 have the same layered structure. For example, if both termination and field dielectrics 181, 161 are made of thermally grown semiconductor oxide, such as silicon oxide, the thickness w2 of the field dielectrics 161 is equal to the thickness w1 of the termination dielectric 181. If the termination and field dielectrics 181, 161 include a deposited oxide layer, the thickness of the deposited oxide layer is the same in the field and termination dielectrics 161, 181.

[0032] A termination mesa 190 separates the termination structure 180 from the cell array 610. A width dT of the termination mesa 190 is greater than a width dF of the cell mesas 170.

[0033] The cell mesas 170 and the termination mesa 190 may result from a semiconductor layer, for example, an epitaxial layer with an initial background doping. The thermal growth of the field and termination dielectrics 161, 181 releases dopants from the consumed portions of the semiconductor body 100. The amount of dopants released from the vertical sidewalls of the field and termination dielectrics 161, 181 during oxide growth is the same in the cell mesas 170 and the termination mesa 190, i.e., in both mesas. Because the termination mesa 190 is wider, the same amount of additional dopants diffuses into a larger volume in the termination mesa 190 than in the cell mesa 170. The resulting average dopant concentration in the termination mesa 190 is lower than the resulting average dopant concentration in the second drift zone portion 121b in the cell mesas 170.

[0034] If the blocking capability of a field electrode structure 160 comprising a needle-shaped field electrode 165 is adapted to the blocking capability of a strip cell with the same vertical extent and the same mesa width of both cells, the field electrode structure 160 with the needle-shaped field electrode requires a thinner field dielectric 161 at a higher dopant concentration in the cell mesa associated with the needle-shaped field electrode.

[0035] On the contrary, the further termination structure 180 according to the embodiments allows the blocking capability of the more strip-shaped termination structure 180 to be adapted to that of the needle-shaped field electrode structures 160, so that avalanche breakdown occurs primarily in the more robust cell field 610 instead of along the termination mesa 170. This effect is achieved with the field dielectric 161 and the termination dielectric 181 having the same thickness w1=w2, so that the field and termination dielectrics 161, 181 emerge from the same processes and without an additional lithography-based patterning process. In addition, by using segregation of dopants during oxide growth, the embodiments allow a difference between the dopant concentration in the termination mesa 190 and the dopant concentration in the cell mesas 170 to be achieved without performing a lithography-based patterning step.

[0036] The Fig. 2A and Fig. 2B refer to a configuration of spike-shaped field electrode structures 160 and a strip-shaped termination structure 180 similar to that shown in Fig. 1B, wherein in the central part 611 of the cell array 610 functional transistor cells TCF comprise a source zone 110, a body zone 115 separating the source zone 110 from the drift zone 121, and a gate structure 150 for controlling an inversion channel through the respective body zone 115.

[0037] Fig. 2B illustrates the distribution of charge carrier generation in the semiconductor body 100 in the event of an avalanche breakdown, where dense shading corresponds to high generation rates and sparse shading corresponds to low generation rates. The higher generation rates occur in the central portion 611. Since the central portion 611 has the larger area fraction, an avalanche breakdown is distributed over a larger portion of the chip area, and the generated heat is distributed over a larger portion of the semiconductor volume. The semiconductor device 500 may recover from the avalanche breakdown more reliably than it would if the avalanche generation occurred only in a small area fraction, for example, along the termination mesa 180.

[0038] In a semiconductor device according to a comparative example having a higher avalanche generation rate in the termination mesa 190 than in the cell mesas 170, the avalanche generation is concentrated in a comparatively small area, and local current filaments may occur, which may locally destroy the semiconductor lattice, so that the respective semiconductor devices are more difficult to recover from the avalanche state over time or are irreversibly destroyed.

[0039] The breakdown voltage BVDSS of stripe-shaped transistor cells can be tested for a given thickness w2 of the field dielectric along the cell mesas as a function of the dopant concentration in the cell mesas and the vertical extent of the field electrode structure up to a stripe-shaped cell mesa width of approximately 1.2 µm. The obtained values can be extrapolated for cell mesa widths beyond 1.5 µm. In this way, process windows for the termination mesa 190 can be obtained for any given thickness w1 of the termination dielectric 181.

[0040] Fig. 3 shows a process window 702 for a target width tdT of the termination mesa 190 by plotting the breakdown voltage BVDSS as a function of the width dT of the termination mesa 190 for a thickness w1 of the termination dielectric of approximately 450 nm. The relevant process window 702 indicates that a deviation of more than ±10% from a target width tdT does not significantly change the nominal breakdown voltage BVDSS_nom in the termination mesa 190. The process window for the width dT of the termination mesa 190 is rather unproblematic.

[0041] The Fig. 4A and Fig. 4B refer to a semiconductor device 500 having a termination structure 180 including a first straight section 80x and a second straight section 180y orthogonal to the first straight section 180x. The termination mesa 190 includes sloped sections connecting each of the two orthogonal straight sections.

[0042] The semiconductor body 100, as shown in detail in FIG. Fig. 1A and Fig. 1B, comprises a drain structure 120 of the first conductivity type and a contact portion 130 of the first conductivity type between the drain structure 120 and the second surface 102. The drain structure 120 comprises a drift zone 121, in which the dopant concentration may increase or decrease gradually or in steps with increasing distance from the first surface 101, at least in parts of its vertical extent. According to other embodiments, the dopant concentration in the drift zone 121 may be approximately uniform. An average dopant concentration in the drift zone 121 may be between 1E15 cm -,3 and 1E17 cm- 3 , for example in a range of 5E15 cm -,3 up to 5E16 cm -3The drain structure 120 may comprise further doped zones, for example, a field stop layer 128 that separates the drift zone 121 from the contact part 130. An average dopant concentration in the field stop layer 128 may be at least five times as high as an average dopant concentration in the drift zone 121 and at most one-fifth of a maximum dopant concentration in the contact part 130.

[0043] The contact portion 130 may be a heavily doped base substrate or a heavily doped layer. Along the second surface 102, a dopant concentration in the contact portion 130 is sufficiently high to form an ohmic contact with a metal directly adjacent to the second surface 102. If the semiconductor body 100 is based on silicon, in an n-conducting contact portion 130, the dopant concentration along the second surface 102 may be at least 1E18 cm -3 , for example at least 5E19 cm -3, wherein in a p-type contact part 130 the dopant concentration is at least 1E18 cm -3 , for example at least 5E18 cm -3 , can be.

[0044] In the cell array 610, the field electrode structures 160 are regularly arranged in rows and columns at equal distances. According to the illustrated embodiment, the field electrode structures 160 are arranged in a matrix-like checkerboard pattern. Along the rows and columns, the field electrode structures 160 are spaced apart by a width dF. For further details of the field electrode structures 160, reference is made to the detailed description in the Fig. 1A and Fig. 1B.

[0045] Transistor cells TC are centered on a horizontal center point CP of the respective field electrode structures 160. Semiconducting portions of the transistor cells TC are formed in cell mesas 170 between the field electrode structures 160. The cell mesas 170 include a second drift zone portion 121b directly adjacent to a first drift zone portion 121a formed in a continuous portion CS of the semiconductor body 100 between the ground plane BPL and the second surface 102.

[0046] Transistor cells TC in a central part 611 are functional transistor cells TCF, wherein the cell mesas 170 comprise source zones 110 and a body zone 115 forming first pn junctions pn1 with the source zones 110 and a second pn junction pn2 with the drift zone 121.

[0047] The source zones 110 may be wells that extend from the first surface 101 into the semiconductor body 100, for example, into the body zones 115. According to one embodiment, a source zone 110 surrounds the field electrode structure 160 of a functional transistor cell TCF in a horizontal plane. The source zone(s) 110 may directly adjoin the respective field electrode structure 160 or may be spaced apart from the field electrode structure 160. According to other embodiments, the field electrode structure 160 of the respective functional transistor cell TC is not completely surrounded by a source zone 110 or comprises several spatially separated rotationally symmetric source zones 110.

[0048] Transistor cells TC in a transition region 619 surrounding the central part 611 are non-functional transistor cells TCN, wherein the cell mesas 170 are free of source zones 110 or free of source and body zones 115. Instead, a part of the drift zone 121 can completely fill the respective cell mesas 170.

[0049] The central part 611 further comprises a gate structure 150 with a conductive gate electrode 155 surrounding transistor sections of the functional transistor cells TCF in a horizontal plane, wherein the transistor sections are parts of the cell mesas 170 comprising the source and body zones 110, 115. According to the illustrated embodiment, the gate structure 150 is spaced from the field electrode structure 160. The gate electrode 155 comprises or consists of a heavily doped polycrystalline silicon layer and / or a metal-containing layer.

[0050] The gate electrode 155 is completely insulated from the semiconductor body 100, wherein a gate dielectric 151 separates the gate electrode 155 at least from the body zone 115. The gate dielectric 151 capacitively couples the gate electrode 155 to channel portions of the body zones 115. The gate dielectric 115 may comprise or consist of a semiconductor oxide, for example, a thermally grown or deposited silicon oxide, a silicon nitride, for example, a deposited or thermally grown silicon nitride, a semiconductor oxynitride, for example, a silicon oxynitride, or a combination thereof.

[0051] The gate structure 150 may be a lateral gate formed outside the semiconductor body 100 along the first surface 101. According to the illustrated embodiment, the gate structure 150 is a trench gate extending from the first surface 101 into the semiconductor body 100.

[0052] In the illustrated embodiments and for the following description, the first conductivity type is n-type, and the second conductivity type is p-type. Similar considerations, as indicated below, also apply to embodiments in which the first conductivity type is p-type, while the second conductivity type is n-type.

[0053] When a voltage applied to the gate electrode 150 exceeds a preset threshold voltage, electrons accumulate in the channel portions directly adjacent to the gate dielectric 151 and form inversion channels that short-circuit the second pn junction pn2 to electrons.

[0054] A vertical extension of the gate structure 150 is smaller than the vertical extension of the field electrode structures 160. According to one embodiment, the vertical extension of the gate structure 150 may be in a range from 400 nm to 1500 nm, for example in a range from 500 nm to 1000 nm.

[0055] According to the illustrated embodiment, the gate structure 150 forms a grid whose meshes surround the field electrode structures 160 and parts of the cell mesas 170, including the source and body zones 110, 115. According to other embodiments, the gate structure 150 may directly adjoin the field electrode structures 160.

[0056] The gate structure 150 may extend into the transition region 619, where the gate structure 150 may include extensions 157 to electrically contact the gate electrode 155 with a metal gate electrode at the front side and outside the vertical projection of the central part 611.

[0057] An interlayer dielectric 210 adjacent to the first surface 101 may electrically insulate the gate electrode 155 from a first load electrode 310 disposed on the front side. Additionally, the interlayer dielectric 210 may be formed in the vertical projection of the field electrode structures 160.

[0058] The interlayer dielectric 210 may comprise one or more dielectric layers of silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass, for example BSG (borosilicate glass), PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass) as an example.

[0059] The first load electrode 310 may form, or be electrically coupled or connected to, a first load terminal, for example, the source terminal S if the semiconductor device 500 is an IGFET. A second load electrode 320, which directly adjoins the second surface 102 and the contact portion 130, may form, or be electrically connected to, a second load terminal, which may be the drain terminal D if the semiconductor device 500 is an IGFET.

[0060] Each of the first and second load electrodes 310, 320 may consist of or contain aluminum (Al), copper (Cu), or alloys of aluminum or copper, for example AlSi, AlCu, or AlSiCu, as a main component or main components. According to other embodiments, at least one of the first and second load electrodes 310, 320 may contain nickel (Ni), tin (Sn), titanium (Ti), tungsten (W), tantalum (Ta), vanadium (V), silver (Ag), gold (Au), platinum (Pt), and / or palladium (Pd) as a main component or main components. For example, at least one of the first and second load electrodes 310, 320 may comprise two or more sublayers, each sublayer containing one or more materials from Ni, Sn, Ti, V, Ag, Au, Pt, W, and Pd as a main component or main components, for example, a silicide, a nitride, and / or an alloy.

[0061] Contact structures 315 extend through openings in the interlayer dielectric 210 and electrically connect the first load electrode 310 to the source and body zones 110, 115 of the transistor cells TC. Auxiliary contact structures 315b may electrically connect the first load electrode 310 to the field electrodes 165 and the termination electrode 185. The contact structures 315, 315b may comprise one or more conductive metal-containing layers, based on titanium (Ti) or tantalum (Ta), for example, and a metal filler, based on tungsten (W), for example. According to other embodiments, the contact structures 315, 315b may comprise heavily doped semiconductor structures, for example, heavily n-doped polycrystalline structures or heavily p-doped columnar single-crystal structures.

[0062] The field electrodes 165 and the termination electrode 185 may be electrically connected to the first load electrode 320, to gate electrodes 155, to another terminal of the semiconductor device 500, to an output of an internal driver circuit, or may be electrically floating.

[0063] The field electrode structures 160 allow higher dopant concentrations in the drift zone 121 without adversely affecting the blocking capability of the semiconductor device 500. The needle-shaped field electrodes 165 increase the available cross-sectional area for the drift zone 121 and therefore reduce the on-resistance RDSon compared to strip-shaped field electrodes. The wide termination mesa 170 ensures that avalanche breakdown occurs primarily in the more robust cell field 610. Field and termination dielectrics 161, 181 with the same thickness w1=w2 reduce process complexity.

[0064] The Fig. 4C and Fig. The semiconductor device 500 illustrated in Figure 4D includes gate structures 150 embedded in the field dielectrics 161. The field dielectrics 161 of the semiconductor devices 500, which are designed for high blocking voltages, are comparatively thick, and embedding the gate structures 150 in portions of the thick field dielectrics 161 may save chip area and / or relax design constraints.

[0065] The Fig. 5A and Fig. 5B refer to a semiconductor device 500 with the termination structure 180, which forms a frame with chamfered corners around the cell array 610. The cell array 610 comprises functional and non-functional transistor cells TCF, TCN arranged in a matrix-like manner in rows and lines orthogonal to the rows. The cross-sectional plane follows a bisector or side bisector of one of the corners of the cell array.

[0066] Fig. 5A shows the electric field distribution in the semiconductor body 100 during avalanche breakdown. The denser the shading of a semiconductor region, the more the potential of the respective semiconductor region approaches the potential of the source electrode. The less shading, the more the respective potential approaches that of the drain electrode. On the first surface 101, the electric field gradually decreases in the horizontal direction between an outer surface 103 of the semiconductor body 100 and the cell array 610.

[0067] In Fig. In Figure 5B, dense shading represents a high generation rate during avalanche breakdown, and sparse shading corresponds to a low generation rate. Chamfered corners of the frame-shaped termination structure 180 keep the width of the termination mesa 180 uniform along the entire perimeter and increase avalanche robustness of the corner portions. Avalanche generation occurs predominantly within the cell array 610.

[0068] Fig. 5C shows a process window for the breakdown voltage BVDSS as a function of the doping NT in the termination mesa, the width dT of the termination mesa 180, and the distance dB of the body zone of the transistor cell from a lateral center of the transistor cell. A first window section 704 records the breakdown voltage BVDSS as a function of the doping NT in the termination mesa on the left side. In the center, a second process window section 706 records the breakdown voltage BVDSS as a function of the width dT of the termination mesa 180. A third window section 708 records the breakdown voltage BVDSS as a function of the distance dB of the body zones from a lateral center of the transistor cell on the right side.

[0069] According to the first process window 704, the breakdown voltage VBDSS changes by less than 2% over a change in the doping concentration NT in the termination mesa by a target value tNT of ±10%. The second process window 706 shows that the breakdown voltage changes by less than 2% over a change in the width of the termination mesa 190 by a target width tdF. The third process window reveals that a deviation from a target value tdB of 10% of the distance dB of the body zones from the center axis of the respective transistor cell can result in a variation in the breakdown voltage BVDSS of more than 10%.

[0070] The Fig. 6A and Fig. 6B refer to layouts with the transistor cells TC and field electrode structures 160 arranged in shifted lines or rows, wherein the odd rows are shifted from the even rows by one half of the distance between two adjacent transistor cells TC or two adjacent field electrode structures 160.

[0071] According to the embodiment of Fig. 6A, the inner outline of the termination structure 180 follows the contour of the cell array 610. A width of the termination structure 180 may vary or may be approximately uniform. As a result, the termination structure 180 includes long straight sections 180y extending parallel to the lines of the array electrode structures 160 and zigzag sections 180z oriented orthogonally to the long straight sections 180y.

[0072] Fig. 6B refers to an embodiment with approximately square field electrode structures 160 and a termination structure 180 with rectangular bulges along the inner outline or the inner contour in the projection of the embossed lines. The inner contour of the frame-like termination structure 180 approximately follows a contour of the cell field 610 by orthogonal lines. According to further embodiments, transitions between orthogonal parts of the termination structure 180 or transitions to inclined, non-orthogonal sections can be rounded.

[0073] Fig. 7 refers to an electronic assembly 510, which may be a motor drive, a switch-mode power supply, a primary stage of a switch-mode power supply, a synchronous rectifier, a primary stage of a DC / AC converter, a secondary stage of a DC / AC converter, a primary stage of a DC / DC converter, or part of a solar energy converter, for example.

[0074] The electronic arrangement 510 may comprise two identical semiconductor devices 500, as described above. The semiconductor devices 500 may be IGFETs, and the load paths of the second semiconductor devices 500 are electrically arranged in series between a first supply terminal A and a second supply terminal B. The supply terminals A, B may apply a DC (direct current) voltage or an AC (alternating current) voltage. The network node NN between the two semiconductor devices 500 may be electrically connected to an inductive load, which may be a winding of a transformer or a motor winding, or to a reference potential of an electronic circuit, for example.The electronic arrangement 510 may further comprise a control circuit 504 that provides a control signal for alternately switching the semiconductor devices 500 on and off, and a gate driver 502 that is controlled by the control circuit 504 and electrically connected to gate terminals of the semiconductor device 500.

[0075] The electronic arrangement 510 may be a motor drive, wherein the semiconductor devices 500 are electrically arranged in a half-bridge configuration and the network node NN is electrically connected to a motor winding and supply terminals A, B providing a DC voltage.

[0076] The Fig. 8A to 8F relate to a method of manufacturing a semiconductor device as described above.

[0077] Fig. 8A shows a semiconductor substrate 500a consisting of or containing a semiconductor layer 100a of a single-crystal semiconductor material. The semiconductor substrate 500a may be a semiconductor wafer from which a plurality of identical semiconductor dies or chips are obtained. The single-crystal semiconductor material of the semiconductor layer 100a may be silicon (Si), for example.

[0078] A normal to a main surface 101a of the semiconductor layer 100a defines a vertical direction, and directions orthogonal to the vertical direction are horizontal directions.

[0079] The semiconductor layer 100a contains dopants of a first conductivity type. For example, the semiconductor layer 100a is based on lightly or weakly n-doped silicon containing phosphorus (P) and / or arsenic (As) atoms. The dopants can be evenly distributed in the semiconductor layer 100a. According to other embodiments, the dopant concentration in the semiconductor layer 100a can gradually decrease or increase with increasing distance from the main surface 101a, at least in sections. An average dopant concentration in the semiconductor layer 100a can be between 1E15 cm -,3 and 1E17 cm -3 , for example in a range of 5E15 cm -,3 up to 5E16 cm -3 , be.

[0080] Field electrode trenches 160a are formed in a cell array 610, extending from the main surface 101a into the semiconductor layer 100a. Outside the cell array 610, a strip-shaped termination trench 180a is formed, completely surrounding the cell array 610. The termination trench 180a and the field electrode trenches 160a can be formed simultaneously by sharing the same lithographic exposure process and using the same etching mask and etching process.

[0081] The Fig. The field electrode trenches 160a shown in Figure 8A may be needle-shaped trenches arranged in rows and columns in a matrix-like manner. A horizontal cross-section of a field electrode trench 160a may be a circle or a polygon with or without rounded or beveled corners, for example, a square, a hexagon, or an octagon with or without beveled corners.

[0082] A vertical extension of the termination and field electrode trenches 180a, 160a may be in a range from 0.5 µm to 50 µm, for example, from 0.6 µm to 4 µm. A horizontal width of the termination and field electrode trenches 180a, 160a may be in a range from 0.4 µm to 10 µm, for example, in a range from 0.6 µm to 4 µm. The termination and field electrode trenches 180a, 160a may have the same width. According to other embodiments, the termination trench 180a may be wider and / or deeper than the field electrode trenches 160a.

[0083] Portions of the semiconductor layer 100a that separate the field electrode trenches 160a from one another form cell mesas 170. A portion of the semiconductor layer 100a that separates the outermost field electrode trenches 160a of the cell array 610 from the termination trench 180a forms a termination mesa 190. The cell mesas 170 and the termination mesa 190 protrude from a contiguous section CS of the semiconductor substrate 500a. A width dT of the termination mesa 190 is greater than a width dF of the cell mesas 170.

[0084] According to one embodiment, a sacrificial oxide layer 202 may be formed by thermal oxidation, for example, heating the semiconductor substrate 500a in an oxygen-containing environment.

[0085] Fig. 8B shows the sacrificial oxide layer 202 uniformly lining the termination and field electrode trenches 180a, 160a. Dopant atoms 140 from portions 104 of the semiconductor layer 100a, consumed by the formation of the sacrificial oxide layer 202, diffuse into the adjacent termination and cell mesas 190, 170. Because the dopant atoms 140 diffused from vertical portions of the sacrificial oxide layer 202 are distributed over a larger volume, the resulting total dopant concentration nT1 in the termination mesa 190 is lower than the resulting total dopant concentration nC1 in the cell mesas 170. The sacrificial oxide layer 202 is then removed.

[0086] As in Fig. As illustrated in Figure 8C, formation and removal of the sacrificial oxide layer 202 rounds edges at the openings and at the bottoms of the termination and field electrode trenches 180a, 160a. Other embodiments may be configured without formation and removal of a sacrificial oxide layer 202.

[0087] A field oxide layer 161a may be formed by thermal oxidation, for example, by heating the semiconductor substrate 500a in an oxygen-containing environment.

[0088] Fig. 8D shows the field oxide layer 161a lining the rounded termination and field electrode trenches 180a, 160a. Dopant atoms contained in oxidizing portions of the semiconductor layer 100a segregate and contribute to final dopant concentrations nC, nT in the cell mesas 170 and the termination mesa 190. A dopant concentration difference between a final first dopant concentration nC in the cell mesas 170 and a final second dopant concentration nT in the termination mesa 190 may be proportional to a ratio of a width dF of the cell mesas 170 to a width dF of the termination mesa 190.

[0089] According to one embodiment, a conformal field dielectric layer 161b of a uniform layer thickness may be deposited on the field oxide layer 161a by means of a predominantly conformal deposition or deposition process.

[0090] Fig. 8E shows the conformal field dielectric layer 161b of a uniform layer thickness. The field dielectric layer 161b may, for example, be a deposited silicon oxide, such as silicon oxide obtained using TEOS (tetraethyl orthosilicate) as a precursor material. According to other embodiments, the field dielectric layer 240 may comprise a silicon nitride layer, a silicon oxynitride layer, or another dielectric material. A layer thickness of the field dielectric layer 161b may be in a range of 10% to 90% of the total oxide thickness, for example, in a range of 40% to 60%.

[0091] The layer stack comprising the field oxide layer 161a and the field dielectric layer 161b may be removed from at least a central portion 611. Gate trenches may be formed in the cell mesas 170 and may be lined with a gate dielectric 151. A conductive material may be deposited and undeveloped to fill the gate trenches, the termination trenches 180a, and the field electrode trenches 160a. Impurities may be implanted to form heavily doped source regions 110 and oppositely doped body regions 115.

[0092] Fig.8F shows transistor cells TC with a gate electrode structure 150 having a gate electrode 155 and a gate dielectric 151 separating the gate electrode 155 from the semiconductor layer 100a. In the central part 611, a body zone 115 forms first pn junctions pn1 with source zones 110 and a second pn junction pn2 with a drift zone 121 formed by further parts of the doped semiconductor layer 100a. The applied conductive material forms field electrodes 165 in the field electrode trenches 160a, a termination electrode 185 in the termination trench 180a, and a gate electrode 155 in the gate trenches 150a. Further processes are applied to the semiconductor substrate 500a. Finally, a plurality of identical semiconductor devices, as described with reference to the other figures, are obtained by dividing the semiconductor substrate 500a into a plurality of identical semiconductor dies.

[0093] Formation of the sacrificial oxide layer 202, the field oxide layer 161a, and the field dielectric layer 161b can be used to set the final second dopant concentration nT in the termination mesa 190, which is lower than the final first dopant concentration in the cell mesas 170, for a given total thickness of the field oxide layer 161a and the field dielectric layer 161b, to ensure that the avalanche occurs within the cell array 610. By providing the concentration difference, segregation of dopant atoms from the growing oxide layers is utilized.

[0094] If a field oxide layer 161a that is thinner than the final field dielectric is sufficient to create the desired dopant difference, a deposited field dielectric layer can complement the field oxide layer 161a to the final field dielectric without further increasing the dopant difference. If a field oxide layer 161a with the final field dielectric thickness is insufficient to create the desired dopant difference, forming and removing a sacrificial oxide layer can contribute to the dopant difference without further increasing the thickness of the final field dielectric.

Claims

[1] A semiconductor device comprising: a cell array (610) comprising a gate structure (150), a plurality of field electrode structures (160) arranged in rows, and cell mesas (170) separating adjacent individual field electrode structures of the field electrode structures (160) from one another, each field electrode structure (160) comprising a needle-shaped field electrode (165) and a field dielectric (161) separating the field electrode (165) from a semiconductor body (100), wherein the cell array (610) has a central part (611) with functional transistor cells (TCF) and a transition region (619) with non-functional transistor cells (TCN), wherein the functional transistor cells (TCF) each have at least one of the field electrode structures (160), a source zone (110) of a first conductivity type and a body zone (115) of a second, complementary conductivity type, wherein the non-functional transistor cells (TCN) each have one of the field electrode structures (160), and wherein source zones (110) are missing in cell mesas that separate the field electrode structures (160) of non-functional transistor cells (TCN) from one another, a termination structure (180) surrounding the cell field (610), wherein the termination structure (180) extends from a first surface (101) into the semiconductor body (100) and has a termination electrode (185) and a termination dielectric (181) separating the termination electrode (185) from the semiconductor body (100), wherein the termination and field dielectrics (181, 181) have the same thickness, and a termination mesa (190) which is wider than the cell mesas (170) and separates the termination structure (180) from the transition region (619) of the cell field (610). [2] A semiconductor device according to claim 1, wherein an average dopant concentration in the termination mesa (190) is lower than an average dopant concentration in a second drift zone portion (121b) in the cell mesas (170), the second drift zone portion (121b) directly adjoining a first drift zone portion (121a) formed in a continuous portion (CS) of the semiconductor body (100) between the field electrode structures (160) and a second surface (102) opposite the first surface (101). [3] A semiconductor device according to claim 1 or 2, further comprising: the gate structure (150) surrounds the field electrode structures (160) and has a gate electrode (155) and a gate dielectric (151) separating the gate electrode (155) from the semiconductor body (100). [4] A semiconductor device according to claim 3, wherein parts of the cell mesas (170) are each formed between the gate structure (150) and the field electrode structures (160). [5] A semiconductor device according to claim 4, wherein the gate structure 150 forms a grid embedding transistor sections (TS) of a plurality of transistor cells (TC), each transistor cell (TC) being associated with a field electrode structure (160). [6] A semiconductor device according to claims 1 to 5, wherein a width of the field electrode structures (160) is equal to a width of the termination structure (180). [7] A semiconductor device according to claims 1 to 6, wherein a width (dT) of the termination mesa (190) is uniform along straight portions of the termination mesa (190). [8] A semiconductor device according to claims 1 to 7, wherein a width (dT) of the termination mesa (190) is uniform along tapered parts between orthogonal straight portions of the termination mesa (190). [9] A semiconductor device according to claims 1 to 8, wherein a distance between the termination structure (180) and the cell array (610) is uniform. [10] Semiconductor device according to claims 1 to 9, wherein the field electrode structures (160) are arranged in a matrix-like manner in rows and lines perpendicular to the lines and the termination mesa (190) has at least four straight sections along four sides of a rectangular cell field. [11] A semiconductor device according to claim 10, wherein the termination mesa (190) has respective inclined portions connecting two orthogonal straight portions. [12] A semiconductor device according to claims 1 to 9, wherein the field electrode structures (160) are arranged in shifted rows and the termination mesa (190) has straight sections parallel to the shifted rows and zigzag sections orthogonal to the shifted rows. [13] A semiconductor device according to claim 12, wherein the zigzag portions of the termination mesa (190) comprise bulges in the longitudinal projection of embossed rows of the field electrode structures (160). [14] A semiconductor device according to claim 12, wherein the zigzag portions have a uniform width. [15] Electronic device comprising: a semiconductor device according to any one of the preceding claims. [16] A method of manufacturing a semiconductor device, the method comprising: Forming, in a cell field (610) of a dopant-containing semiconductor layer (100a), needle-shaped field electrode trenches (160a) arranged in rows and separated by cell mesas (170) formed by parts of the semiconductor layer (100a), Forming in the semiconductor layer (100a) a termination trench (180) surrounding the cell field (610), wherein a part of the semiconductor layer (100a) between the cell field (610) and the termination trench (100a) forms a termination mesa (190) which is wider than the cell mesas (170), and Forming a field oxide layer (161a) which uniformly lines the field electrode and termination trenches (160a, 180a) by thermal oxidation, wherein dopants contained in oxidizing parts of the semiconductor layer (100a) separate and contribute to final dopant concentrations in the cell mesas (170) and the termination mesa (190), and a dopant concentration difference between a first average dopant concentration in the cell mesas (170) and a second average dopant concentration in the termination mesa (190) is proportional to a ratio of a total volume of the cell mesas (170) to a total volume of the termination mesa (190), and Forming functional transistor cells (TCF) in a central part (611) of the cell array (610) and non-functional transistor cells (TCN) in a transition region (619) of the cell array (610), wherein the functional transistor cells (TCF) each have at least one field electrode structure (160), a source zone (110) of a first conductivity type and a body zone (115) of a second, complementary conductivity type, wherein the non-functional transistor cells (TCN) each have at least one field electrode structure (160), and wherein source zones (110) are missing in cell mesas that separate the field electrode structures (160) of non-functional transistor cells (TCN) from one another. [17] The method of claim 16, further comprising: Forming and removing, before forming the field oxide layer (161a), a sacrificial oxide layer (202) uniformly lining the field electrode and termination trenches (160a, 180a). [18] Method according to claims 16 to 17, wherein the field electrode trenches (160a) and the termination trench (180a) are formed simultaneously. [19] Method according to claims 16 to 18, further comprising: Applying or depositing a field dielectric layer (161b) on the field oxide layer (161a).

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