Voltage regulator and memory controller

Abstract

Memory controller (100) of a memory card comprising: an active controller (111) configured to operate in an active mode and to be inactive in a sleep mode; an active logic (120) configured to receive a drive voltage (VDD_A); a power gating switch (114) configured to connect the active controller (111) to the active logic (120) after a transition state (TS) of the active mode, where the transition state (TS) is an initial time period of the active mode; and a charging circuit (113; 113a; 113b; 113c) configured to charge the active logic (120) during the transition state (TS).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This non-provisional U.S. patent application claims priority to Korean Patent Application No. 10-2013-0153985, filed December 11, 2013, the entire contents of which are hereby incorporated by reference. BACKGROUND

[0002] Inventive concepts relate to semiconductor devices such as a voltage regulator, a memory controller, and power supply methods therefor.

[0003] The use of mobile devices such as smartphones, tablet PCs, digital cameras, MP3 players, e-books, and so on is increasing. As the amount of data processed by mobile devices increases, higher processing speeds are being adopted in mobile devices. Additionally, high-performance, high-capacity non-volatile storage media is being used in mobile devices. For example, built-in memory such as an Embedded Multimedia Card (eMMC) is used as a storage medium of a mobile device.

[0004] An embedded multimedia card (eMMC) is a multi-chip package (MCP) embedding a memory controller and a plurality of memory chips. Power supply capacitors mounted in an embedded multimedia card (eMMC) are gradually removed to improve yield and achieve lower weight and size. A multilayer ceramic chip capacitor is primarily used as a power supply capacitor. A power supply capacitor can be mounted on the outside of an embedded multimedia card (eMMC).

[0005] A stable power supply improves the operational reliability of a semiconductor device including a mobile device. SUMMARY

[0006] Inventive concepts provide a voltage regulator, a memory controller, and a memory system that provide a stable power supply that does not depend on a power supply capacitor.

[0007] At least some embodiments of the inventive concept provide a memory controller. The memory controller may include an active regulator configured to operate in an active mode and be inactive in a sleep mode, active logic configured to receive a drive voltage, a power gating switch configured to connect the active regulator to the active logic after a transition state of the active mode, wherein the transition state is an initial period of the active mode, and a charging circuit configured to charge the active logic during the transition state.

[0008] An embodiment of the inventive concepts provides a voltage regulator of a semiconductor device. The voltage regulator may include a first regulator configured to operate in an active mode and to be inactive in a sleep mode; a second regulator configured to operate in the sleep mode and in the active mode, the second regulator configured to generate a sleep voltage, the second regulator and the first regulator having a common output terminal; active logic configured to receive a drive voltage; sleep logic configured to operate based on the sleep voltage, the sleep voltage and the drive voltage having a same voltage level; a power gating switch configured to connect the common output terminal to a power input terminal of the active logic based on a state of the active mode;and includes a charging circuit configured to charge the power input terminal to a reference voltage level during an active mode transient state;

[0009] An embodiment of the inventive concepts provides a method for supplying power in a mobile memory card having an active regulator configured to operate in an active mode and to be inactive in a sleep mode, active logic configured to operate in the active mode, and a power gating switch located between an output terminal of the active regulator and a power input terminal of the active logic.The power supply method may include detecting an operating mode change from the sleep mode to the active mode, enabling the active regulator based on detecting charging of the power input terminal of the active logic by a charging circuit, disabling the charging circuit when a voltage of the power input terminal reaches a reference voltage, and enabling the power gating switch when the voltage of the power input terminal reaches the reference voltage.

[0010] At least one embodiment discloses a memory controller comprising: active logic configured to operate based on a drive voltage, the active logic configured to control an external memory device; sleep logic configured to operate based on a sleep voltage, the sleep logic configured to detect a change in an operating mode of the memory controller; and a voltage regulator including a charging circuit configured to supply the drive voltage to the active logic based on the detected change, and an active regulator configured to supply the drive voltage to the active logic when the drive voltage is greater than a reference voltage. SHORT DESCRIPTION OF THE CHARACTERS

[0011] Embodiments of the inventive concepts are described in more detail below with reference to the accompanying drawings. However, embodiments of the inventive concepts may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Like reference numerals refer to like elements throughout.

[0012] Fig. 1 is a block diagram illustrating a memory system according to an embodiment of the inventive concepts.

[0013] Fig. 2 is a block diagram showing a voltage regulator from Fig. 1 represents.

[0014] Fig. 3 is a drawing showing a structure of the voltage regulator of Fig. 2 in further detail.

[0015] Fig. 4 is a timing diagram showing an operation of the voltage regulator of Fig. 3 represents.

[0016] Fig. 5 is a circuit diagram showing a state of the voltage regulator in a sleep mode under operating sections of Fig. 4 represents.

[0017] Fig. Figure 6 is a circuit diagram illustrating a state of the voltage regulator in a transient state TS.

[0018] Fig. Figure 7 is a circuit diagram showing a state of the voltage regulator after the transient state TS is over.

[0019] Fig. 8 is a circuit diagram illustrating a voltage regulator according to another embodiment of the inventive concepts.

[0020] Fig. 9 is a timing diagram showing an operation of the voltage regulator of Fig. 8 represents.

[0021] Fig. 10 is a block diagram illustrating a voltage regulator according to yet another embodiment of the inventive concepts.

[0022] Fig. 11 is a block diagram illustrating a voltage regulator according to yet another embodiment of the inventive concepts.

[0023] Fig. 12 is a block diagram illustrating a memory controller mounted on a memory card according to an embodiment of the inventive concepts.

[0024] Fig. 13 is a block diagram illustrating a card system including an embedded multimedia card (eMMC) according to an embodiment of the inventive concepts.

[0025] Fig. 14 is a block diagram illustrating a mobile device according to an embodiment of the inventive concepts. DETAILED DESCRIPTION OF EMBODIMENTS

[0026] Embodiments of the inventive concepts will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. Inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.

[0027] Fig. 1 is a block diagram illustrating a memory system according to an embodiment of the inventive concepts. Referring to Fig. 1 a storage system includes a storage controller 100 and a storage device 200 . The memory controller 100 contains a voltage regulator 110 , an active logic 120 and a sleep logic 130 .

[0028] The voltage regulator 110 is supplied externally with an external voltage Vext and an operating mode signal OP_Mode. The voltage regulator 110 converts a level of the external voltage Vext to supply the active logic 120 and sleep logic 130 with the converted voltage as drive voltages VDD_A and VDD_S. The voltage regulator 110can be used in a mobile device and can separately contain a regulator for a sleep mode and a regulator for an active mode. The memory system waiting in the sleep mode changes its operating mode to an active mode in a situation such as a wake-up. During a wake-up, it requires a certain period of time for an associated active mode regulator, which consumes a relatively high current, to output a desired drive voltage and a desired drive current. Thus, when the operating mode is changed from the sleep mode to the active mode, instability of a drive voltage due to a load increase should be eliminated. In addition, the voltage regulator generates 110 a drive voltage VDD_A before a start time of the active load of the active logic 120 . The voltage regulator 110can eliminate drive voltage instability that occurs when an operation mode is changed without depending on a backup power capacitor.

[0029] The active logic 120 is supplied with a drive voltage VDD_A from the voltage regulator 110 . The active logic 120 can perform various operations to control the storage device 200 The active logic 120 For example, a processing unit can control the memory controller 110 , a buffer memory and an error correction code (ECC) engine. This means that the active logic 120 all circuits and devices for accessing and controlling the storage device 200 If the active logic 120 is activated, a data transfer and interface operations to perform the data transfer occur. If the active logic 120activated, a relatively large load occurs. Thus, in the sleep mode in which the active logic 120 is essentially not used, a power management is carried out by interrupting the drive voltage VDD_A to the active logic 120 .

[0030] The logic of sleep 130 contains circuits and devices for minimal input / output and control in the memory controller 100 This means that in the sleep mode in which the active logic 120 is switched off, only the sleep logic 130 is enabled to prepare for a wake-up or memory access request from the outside. When a wake-up request is received from the outside, the request is processed by the sleep logic 130 and a preparation operation to activate the active logic 120 begins. The sleep logic 130 may include minimal circuitry and equipment for standby operation.

[0031] The storage device 200 stores data and provides stored data to the memory controller 100 under the control of the memory controller 100 ready. The storage device 200 may be a non-volatile storage device that retains its stored data even when its power supply is interrupted. The storage device 200 may include, for example, an EEPROM, FRAM, PRAM, MRAM, RRAM, NAND flash memory, etc. The storage device 200 is not limited to the non-volatile memory device described above and may include a volatile memory device.

[0032] The storage system contains the voltage regulator 110 that can provide a stable voltage when an operating mode is changed without relying on a backup power capacitor for power stability. The voltage regulator 110When an operating mode is changed to the active mode, the drive voltage VDD_A can be set before a load start time of the active logic 120 and provide the drive voltage VDD_A.

[0033] Fig. 2 is a block diagram showing a voltage regulator 110 out of Fig. 1. Referring to Fig. 2 the voltage regulator 110 an active controller 111 , a sleep regulator 112 , a charging circuit 113 and a power gating switch (PGSW) 114 contain.

[0034] The active controller 111 can be activated or deactivated in response to an operating mode OP_Mode. In the case that an operating mode OP_Mode is an active mode, the active controller generates 111 the drive voltage VDD_A to drive the active logic 120 . Meanwhile, the active controller 111inactive in sleep mode. This means that the active controller 111 can be switched off in sleep mode. When the operating mode OP_Mode is changed from sleep mode to active mode, the active controller generates 111 the drive voltage VDD_A.

[0035] The active controller 111can be a low-dropout (LDO) regulator. A voltage regulator can be divided into a linear regulator and a switching regulator. A DC-DC converter is a type of switching regulator. The DC-DC converter has high conversion efficiency. However, the noise characteristic of the linear regulator is greater than the noise characteristic of the switching regulator. The LDO regulator is a type of linear regulator. The LDO regulator has low conversion efficiency but has a high response speed. An output voltage of the LDO regulator contains a small amount of noise compared to an output voltage of the DC-DC converter. Thus, the LDO regulator can be used to compensate for the disadvantages of the DC-DC converter. In particular, the LDO converter can be used to supply power to a noise-sensitive device as well as to a device that needs to be driven at high power.

[0036] The sleep regulator 112 is activated in active mode and sleep mode. The sleep controller 112 remains switched on in sleep mode and supplies a DC voltage in active mode. The current supply capability of the sleep controller 112 is relatively low compared to the active controller 111 This is a consequence of the fact that in the sleep mode of the memory controller 100 only a minimal load current needs to be supplied for standby operation. The sleep controller 112 can be an LDO regulator, which uses the same voltage conversion method as the active regulator 111 has.

[0037] The charging circuit 113 can provide a power connection of the active logic 120 according to the operating mode. The charging circuit 113 can connect the power supply of the active logic 120 charge when an operating mode is changed. The charging circuit 113can connect the power input terminal N2 of the active logic 120 charge when an operating mode is changed from sleep mode to active mode, that is, before the power gating switch 114 is switched on. Before an output of the active controller 111 reaches a sufficient level, a level of the active voltage VDD_A applied to the power input terminal N2 of the active logic 120 is set to a certain level.

[0038] When a level of the active voltage VDD_A reaches a desired level through the charging circuit 113 reached, the charging circuit 113 deactivated and the power gating switch 114 is switched on. This means that the charging circuit 113 the power input terminal N2 of the active logic 120 can load in a transition state section in which the operating mode is changed from sleep mode to active mode.

[0039] The power gating switch 114 connects a common output terminal N1 of the active controller 111 and the sleep regulator 112 with the power input terminal N2 of the active logic 120 according to an operating mode OP_Mode. The power gating switch 114 is switched off in sleep mode. The power gating switch 114 is also turned off in the transition state section in which a mode change occurs in the active mode. After the power input terminal N2 of the active logic 120 charged to a desired level by the charging circuit 113 in the transition state section, the power gating switch 114 This means that the power gating switch 114 is only switched on after an operating mode has been changed from sleep mode to active mode and the transition state section has ended.

[0040] To the power gating switch 114 A first switching control signal SC1 is supplied to perform the switching control. Based on the switching control signal SC1, the power gating switch holds 114 maintains a power-off state in the transition connection section, in which the operating mode is changed from sleep mode to active mode. After the transition state section is completed, the power gating switch can 114 The first switching control signal SC1 can be generated by a control logic within the memory controller 100 or a control circuit within the voltage regulator 110 .

[0041] The voltage regulator 110 switches the power gating switch 114 and loads the power input terminal N2 of the active logic 120in the transition state section in which the operating mode is changed from sleep mode to active mode. After the power input terminal N2 of the active logic 120 is charged to the desired level, the common output terminal N1 of the active regulator 111 and the sleep regulator 112 electrically connected to the power input terminal N2 of the active logic 120 By controlling the transition state section, instability of the logic connected to the active 120 provided drive voltage VDD_A, and the active logic 120 can be activated.

[0042] Fig. 3 is a drawing showing the voltage regulator 110 out of Fig. 2 in further detail. Referring to Fig. 3 the voltage regulator 110 a power gate control logic 115which generates the first switching control signal SC1. The power gate control logic 115 can generate the first switching control signal SC1 according to the operating mode OP_Mode and a signal from the charging circuit 113 generated second switching control signal SC2 is received.

[0043] The charging circuit 113 can be a power source 116 , a charging switch 118 and a comparator 119 included. The charging circuit 113 loads the power input terminal N2 of the active logic 120 during the transition state (TS), in which the operating mode changes from sleep mode to active mode. The transition state TS is an initial period of the active mode when the operating mode changes from sleep mode to active mode. This means that the transition time TS is a section in which the operating mode changes from sleep mode to active mode, but the active controller 111is not sufficiently activated. Thus, the charging circuit 113 the power input terminal N2 of the active logic 120 in advance during the transition state TS and sets the power input terminal N2 of the active logic 120 to a desired voltage.

[0044] The charging circuit 113 transmits a charging current Ic, which is supplied from the power source 116 is generated to charge the power input terminal N2 during the transient state TS. The current source 116 can be, for example, a variable current source that can change the amplitude of the charging current Ic. The amplitude of the charging current Ic supplied by the current source 116 supplied can be determined by a user. The power source 116 loads the power input terminal N2 of the active logic 120 in the transition state TS to increase a level of the drive voltage VDD_A.

[0045] The charging switch118 transfers the charging current Ic to the power input terminal N2 of the active logic 120 in response to the second switching control signal SC2. The charging switch 118 can control the charging current Ic supplied by the power source 116 provided in response to the second switching control signal SC2. A section in which the charging switch 118 is switched on, the transition state TS is in which the sleep mode is ended and the operating mode enters the active mode. Thus, the charging switch 118 switched off after the power input terminal N2 of the active logic 120 was sufficiently charged from the beginning of the active mode.

[0046] The comparator 119 generates the second switching control signal SC2 for switching the charging switch 118 . A level of the drive voltage VDD_A of the power input terminal N2, which is charged by the charging current IC, is applied to the comparator119 The comparator 119 compares a reference voltage REF with the one applied to the comparator 119 fed back drive voltage VDD_A to generate the second switching control signal SC2. In the event that a level of the drive voltage VDD_A charged by the charging current Ic is lower than the reference voltage REF, the comparator generates 119 the second switching control signal SC2 to switch on the charging switch 118 . In the case that a level of the drive voltage VDD_A charged by the charging current Ic is equal to or higher than the reference voltage REF, the comparator generates 119 the second switching control signal SC2 to switch off the charging switch 118 . The comparator 119 operates based on the operating mode OP_Mode. Thus, the comparator 119 be activated in active mode. In addition, the comparator 119 be inactive in sleep mode.

[0047] The power gate control logic 115 generates the first switching control signal SC1 with respect to the operating mode OP_Mode and the second switching control signal SC2. In the case that the operating mode OP_Mode corresponds to the sleep mode, the power gate control logic switches 115 the power gating switch 114 The power gate control logic 115 holds the power gating switch 114 still in a powered-off state even at the moment when the operating mode OP_Mode is changed from sleep mode to active mode. The power gate control logic 115 switches the power gating switch 114 at a time when the voltage supplied by the charging circuit 113 provided second switching control signal SC2 the charging switch 118 This means that the power gate control logic 115 the power gating switch 114switches on after the active mode has started and the transition state TS has ended. To control the power gating switch 114 Using the method described above, the power gate control logic generates 115 the first switching control signal SC1.

[0048] The drive voltage VDD_A supplied by the voltage regulator 110 to the active logic 120 can be delivered at a stable level even if the operating mode OP_Mode is changed. The power gating switch 114 and the charging switch 118 can be a P- or N-channel high-power transistor, but the inventive concepts are not limited to this example.

[0049] Fig. 4 is a timing diagram showing an operation of the voltage regulator 110 out of Fig. 3 represents.

[0050] Referring to Fig. 3 and Fig. 4 can be controlled according to a switching operation of the power gating switch 114 and the charging switch 118 a charge during the transition state TS and a switching with the active controller 111 This means that the power input terminal N2 of the active logic 120 during the transition state TS by the charging circuit 113 can be loaded and after the transition state TS by the active controller 111 can be loaded.

[0051] The storage system 100 is driven in sleep mode from time T0 to time T1. The active controller 111 is switched off in sleep mode. The sleep controller 112 maintains a power-on state in sleep mode and a minimum power to maintain a standby state of the memory controller 100 is delivered. This means that the sleep controller 112generates a drive voltage VDD_S to supply the generated drive voltage VDD_S to the sleep logic 130 . A level of the drive voltage VDD_S is the same as that of the drive voltage VDD_A, but the level of the sleep regulator 112 The amount of power supplied is relatively small. This minimizes the power consumed in sleep mode. The power gating switch 114 and the charging switch 118 maintain a switched-off state in the sleep mode. This means that in the sleep mode, the first switching control signal SC1, which controls the power gating switch 114 and the second switching control signal SC2, which controls the charging switch 118 controls, kept at a low level.

[0052] At time T1, sleep mode ends and active mode begins. This means that when a command is sent to the memory controller 100is delivered, the sleep mode must be exited according to a wake-up operation. The memory controller 100 changes the operating mode OP_Mode to the active mode to perform an externally requested operation. Then the active controller 111 activated and starts generating a voltage. However, the power gating switch 114 still maintains a power-off state and the charging circuit 113 is activated.

[0053] At time T1 the comparator activates 119 the second switching control signal SC2 to switch on the charging switch 118 . Then the drive voltage VDD_A of the power input terminal N2 of the active logic 120 by supplying the charging current Ic from the power source 116 . The charging operation of the charging circuit 113 continues until time T2 when a level of the drive voltage VDD_A reaches the reference voltage REF.

[0054] At time T2, a level of the drive voltage VDD_A reaches the reference voltage REF through the charging circuit 113 . Then the second switching control signal SC2 falls to a low level L through the comparator 119 , and the charging switch 118 is interrupted. In response to the transition of the second switching control signal SC2 to the low level L, the power gate control logic 115 the first switching control signal SC1 to a high level H. In response to the transition of the first switching control signal SC1, the power gating switch 114 switched on. The active controller 111 supplies the generated voltage to the power input terminal N2 of the active logic 120 which has been charged to the above reference voltage. At time T2, a voltage and a current supplied by the active regulator 111 generated current set to a level sufficient to drive the active logic 120. Thus, a voltage of the power input terminal N2 of the active logic 120 maintained at a level that ensures stable circuit operation.

[0055] An operating state of the voltage regulator 110 can be defined by three states, ie a first state ST1, a transition state TS and a second state ST2. The first state ST1 corresponds to the sleep mode. In the first state ST1, the power gating switch 114 and the charging switch 118 switched off and only the sleep controller 112 is switched on. The transition state TS corresponds to an initial section of the active mode. In the transition state TS, the power gating switch 114 switched off and the charging switch 118 switched on. In the second state ST2, a drive voltage is applied to the active controller 111 delivered and the charging circuit 113is deactivated. The transition state TS corresponds to an initial phase in which the mode change from sleep mode to active mode occurs.

[0056] Power gating switch operations 114 that the active controller 111 and the power input terminal N2 of the active logic 120 interrupt, and the charging circuit 113 which connects the power input terminal N2 of the active logic 120 Although the power input terminal N2 of the active logic 120 a relatively large load, it can be supplied with the stable drive voltage VDD_A by setting the transition state TS. In addition, the sleep logic 130 when the operating mode OP_Mode is changed, are supplied with the stable drive voltage VDD_S without depending on a capacitor for an auxiliary power supply.

[0057] Fig. 5 is a circuit diagram showing the voltage regulator 110 in a sleep mode or a first state ST1 of process sections Fig. 4. With reference to Fig. 5 are in sleep mode the active controller 111 switched off and the power gating switch 114 and the charging switch 118 interrupted. In sleep mode, only the sleep controller 112 maintained in an on state.

[0058] As shown, the voltage regulator 110 Maintain standby power in an idle state by accessing the storage device 200 does not occur and switches the power of the active logic 120 and the active controller 111 If a wake-up request occurs in the idle state, the sleep logic 130 driven to detect the wake-up request and change the operating mode OP_Mode to active mode.

[0059] During sleep mode, the active controller 111 inactive. This means that the active controller 111 is switched off. In sleep mode, the power gating switch 114 interrupted and the charging circuit 113 becomes inactive. In a state where the power gating switch 114 is interrupted and the charging circuit 113 is inactivated, the sleep regulator generates 112 continuously the drive voltage VDD_S using an external voltage Vext. The sleep logic 130 operates using the drive voltage VDD_S supplied by the sleep controller 112 as a power supply is provided.

[0060] Fig. 6 is a circuit diagram showing a state of the voltage regulator 110 in a transition state TS. Referring to Fig. 6, in the transition state TS, in which the sleep mode is ended and the active mode begins, a process is shown in which the power input terminal N2 of the active logic is charged by the charging circuit 113 is raised. In the transition state TS the active controller 111 an on state. The active controller 11 performs a voltage generation operation to provide the drive voltage VDD_A using the external voltage Vext. However, since in the transition state of the power gating switch 114 is still held in an interrupted state, the output terminal N1 of the active controller holds 111 one from the power input terminal N2 of the active logic 120 electrically isolated state.

[0061] When the sleep mode is ended and the operating mode OP_Mode enters the transition state of the active mode, the charging circuit 113First, the charging circuit activates 113 the second switching control signal SC2 in response to the mode change. Then the charging switch 118 switched on. As soon as the charging switch 118 is switched on, the voltage from the power source 116 generated charging current Ic to the power input terminal N2 of the active logic 120 A voltage level of the power input terminal N2 of the active logic 120 increases based on the charging current Ic. An increase in the level of the drive voltage VDD_A of the power input terminal N2 is fed back to the comparator 119 , which in the charging circuit 113 is included. When the drive voltage VDD_A of the power input terminal N2 increases to the reference voltage REF, the active mode transition state TS is terminated.

[0062] Fig. 7 is a circuit diagram showing a state of the voltage regulator 110after the transition state TS has ended. With reference to Fig. 7, when the transition state TS is completed, the power gating switch 114 switched on. The charging switch 118 the charging circuit 113 is interrupted. In this state, a signal from the active controller 111 and the sleep controller generated voltage to the active logic 120 and the sleep logic 130 be delivered.

[0063] A level of the drive voltage VDD_A applied to the power input terminal N2 of the active logic 120 in the transition state TS is already raised above the reference voltage REF. In addition, although a voltage generation mode is activated and thereby the power gating switch 114 is switched on, the active controller 111 a load due to the active logic 120Thus, a level of the drive voltage VDD_S, which is present at an input terminal of the sleep logic 130 provided, even if the power gating switch 114 is switched on does not change much.

[0064] Although the active controller 111 is activated immediately after the sleep mode is ended, it is activated by the active logic 120 through the power gating switch 114 During the transition state TS, a level of the drive voltage VDD_A, which is supplied by the charging circuit 113 to the power input terminal N2 of the active logic 120 When the drive voltage VDD_A of the power input terminal N2 increases above the reference voltage REF, the power gating switch 114 switched on, and the output terminal N1 of the active controller 111can be connected to the power input terminal N2 of the active logic 120 be connected.

[0065] By setting up the transition state TS, the power input terminal N2 of the active logic 120 through the charging circuit 113 supplied with the drive voltage VDD_A, which is equal to or higher than the reference voltage REF. The active regulator 111 can be used with the active logic 120 be connected after the active controller 111 in a section in activation to have load capability during the transient state TS. Thus, drive voltage instability caused by a load increase that occurs when changing an operating mode can be resolved.

[0066] Fig. 8 is a circuit diagram illustrating a voltage regulator according to another embodiment of the inventive concepts. Referring to Fig. 8 contains a voltage regulator110 a charging circuit 113a which generates a first switching control signal SC1 and a second switching control signal SC2. The charging circuit 113a can generate the first switching control signal SC1 and the second switching control signal SC2 with reference to an operating mode OP_Mode and an output of a comparator 119a .

[0067] The charging circuit 113a can be a power source 116 , a switching control logic 117 , a charging switch 118 and the comparator 119a included. The charging circuit 113a loads the power input terminal N2 of the active logic 120 during the transition state TS, by changing the operating mode from sleep mode to active mode. An output voltage of the active regulator 111 may not be at a desired level in the transition state TS. Therefore, the charging circuit 113athe power input terminal N2 of the active logic 120 to set it in advance to a desired level (i.e., to or higher than the reference level REF) during the transient state TS.

[0068] The charging circuit 113a supplies a charging current Ic, which is supplied by the power source 116 is generated at the power input terminal N2 of the active logic 120 through the charging switch 118 to carry out charging during the transition state TS.

[0069] The switching control logic 117 generates the first and second switching control signals SC1 and SC2 with respect to the operating mode OP_Mode and an output of the comparator 119a . The switching control logic 117 generates the first and second switching control signals SC1 and SC2, so that the power gating switch 114 and the charging switch 118are interrupted in the sleep mode. When the operating mode is changed from the sleep mode to the active mode during the transition state TS, the switching control logic generates 117 the first and second switching control signals SC1 and SC2 to control the power gating switch 114 off and the charging switch 118 When the transition state TS is completed, the switching control logic switches 117 the power gating switch 114 and switches the charging switch 118 out of.

[0070] To meet the operating condition, the switch control logic generates 117 the first and second switching control signals SC1 and SC2 with respect to the operating mode OP_Mode and a comparison result signal Comp of the comparator 119a .

[0071] Due to the arrangement described above, the voltage regulator switches 110a the active controller 111 and the active logic 120in the transition state TS, which corresponds to a start time of the active mode. The voltage regulator 110a loads the voltage input terminal N2 of the active logic 120 through the charging circuit 113a during the transition state TS. Then the voltage input terminal N2 of the active logic 120 raised to a level equal to or higher than the reference voltage REF. When the transition state TS is completed, the voltage regulator switches 110a the charging switch 118 off and switches the power gating switch 114 As a result, the active controller 111 and the active logic 120 connected to each other.

[0072] Fig. 9 is a timing chart showing an operation of the voltage regulator 110a out of Fig. 8. With reference to Fig. 9 generates the switching control logic 117the first and second switching control signals SC1 and SC2 with respect to the operating mode OP_Mode and an output of the comparator 119a .

[0073] The switching control logic 117 outputs the first and second switching control signals SC1 and SC2 at a low level from a time T0 to T1, which corresponds to the sleep mode. This means that the switching control logic 117 in sleep mode the power gating switch 114 and the charging switch 118 turns off.

[0074] At the time T1, from which the active mode starts, the switching control logic 117 the first switching control signal SC1 at a low level L and the second switching control signal SC2 at a high level H. Then the power gating switch holds 14 still maintains an off state. By activating the second switching control signal SC2, the charging switch 118 switched on. By switching the charging switch 118is switched on, the charging current Ic flows from the voltage source 116 into the power input terminal N2 of the active logic 120 . Thus, a level applied to the power input terminal N2 of the active logic 120 set drive voltage VDD_A. Charging operation by the charging circuit 113a lasts until time T2, when a level of the drive voltage VDD_A reaches the reference voltage REF. A period between time T1 and time T2 corresponds to the transition state TS.

[0075] At the time T2 at which a charging operation is performed by the charging circuit 113a is terminated, a level of the drive voltage VDD_A reaches the reference voltage REF. Then the comparator generates the comparison result signal Comp at a high level H. This means that when the voltage generated by the charging circuit 113a charged drive voltage VDD_A increases to the reference voltage REF, the switching control logic 117the charging switch 118 off and the power gating switch 114 turns on.

[0076] In the timing diagram, operations of the active controller 111 and the sleep regulator 112 in each operating section the same as those from Fig. 4.

[0077] Fig. 10 is a block diagram showing a voltage regulator 110b according to yet another embodiment of the inventive concepts. Referring to Fig. 10 can be a charging circuit 113b a hysteresis comparator 119b included. The voltage regulator 110b can detect a level of the drive voltage VDD_A, which is charged by the charging circuit 113b , compare with a reference voltage range REF1–REF2 to control the charging switch 118 . The active controller 111 , the sleep regulator 112 , the power gating switch 114and the power gate control logic 116 the same as those from Fig. 3. Therefore, a description of it is omitted.

[0078] The hysteresis comparator 119b is supplied with a drive voltage VDD_A and reference voltages REF1 and REF2 through its input terminals. The hysteresis comparator 119b can apply different reference voltages when the second switching control signal SC2 transitions from a low level L to a high level H, and when the second switching control signal SC2 transitions from the high level H to the low level L. This means that through the hysteresis comparator 119b a relatively large range can be obtained with respect to a change in the drive voltage VDD_A.

[0079] Fig. 11 is a block diagram showing a voltage regulator 110c according to yet another embodiment of the inventive concepts. Referring to Fig. 11 can be a voltage regulator 110c a programmable charging circuit 113c contain.

[0080] The charging current Ic supplied by the charging circuit 113c and the reference voltage REF, which is compared with the drive voltage VDD_A, can be programmed by a user. To perform the function, the charging circuit 113c a programmable logic 150 included. In Fig. 11 is the programmable logic 150 but inventive concepts are not limited thereto. The programmable logic 150 can be implemented by various backup option circuits included in a memory controller.

[0081] The programmable logic 150 Contains logic arrays that can be programmed by a user. An amplitude of the current source 116provided charging current is determined according to the programmable logic 150 stored data. A level of the reference voltage REF, which is generated by the comparator 119c provided can also be set according to the programmable logic 150 stored data.

[0082] Fig. 12 is a block diagram illustrating a memory controller mounted on a memory card according to an embodiment of the inventive concepts. Referring to Fig. 12 the memory card contains a memory controller 300 and a non-volatile storage device 400 with at least one chip. The memory card can be connected to an external capacitor 600 for a power supply or an internal capacitor 500 for the power supply. An active controller 111 , a sleep regulator 112 , a charging circuit 113, a power gating switch 114 , an active logic 120 and a sleep logic 130 are the same as those used in Fig. 1 and Fig. 2. Thus, descriptions of these will be omitted.

[0083] In case the memory card is provided in the form of a multi-chip package (MCP), the capacitor 500 or 600 for a power supply inside or outside the multi-chip package (MCP). The capacitor 500 for a power supply is mounted inside the MCP. In the case that the capacitor 500 for a supply voltage is mounted inside the MCP, the sleep logic is located 130 near the power input terminal VDD_S. Thus, the capacitor built into the multi-chip package MCP 500for a power supply to help solve voltage instability of the transient state. However, in the case that the capacitor 500 for a power supply is built into the multi-chip package MCP, an extension of the multi-chip package MCP and an extension of the manufacturing process step occur.

[0084] According to the memory controller 300 , high power supply stability can be provided without dependence on the capacitor 500 and 600 to be dependent on a power supply, through a charge in a transient state and a delayed power gating process.

[0085] Fig. 13 is a block diagram illustrating a card system with an embedded multimedia card (eMMC) according to an exemplary embodiment of the inventive concepts. Referring to Fig. 13 contains the card system 1000 a host 1100 and a memory card1200 . The host 1100 contains a host controller 1110 and a host connection unit 1120 . The memory card 1200 contains a card connection unit 1210 , a card controller 1220 and a flash memory 1230 .

[0086] The host connection unit 1120 and the card connection unit 1210 are a plurality of pins. The pins may include a command pin, a data pin, a clock pin, and a power pin. The number of pins may vary depending on the type of memory card. 1200 be different.

[0087] The host 1100 writes data to the memory card 1200 or reads the memory card 1200 stored data. The host controller 1110transmits a command (e.g. a write command), a clock generator in the host 1100 generated clock signal CLK and data DATA to the memory card 1200 by the host connection unit 1120 .

[0088] The card controller 1220 stores data in the flash memory 1230 in synchronization with a clock generator in the card controller 1220 generated clock signal CLK in response to a signal from the card connection unit 1210 received write command. The flash memory 1230 stores from the host 1100 transmitted data. In the event that the host 1100 a digital camera, the flash memory stores 1230 Image data.

[0089] The memory card 1200 can be an Embedded Multimedia Card eMMC. The card controller 1220 contains a voltage regulator 1225 . The voltage regulator 1225contains the charging circuit and the power gating switch described in embodiments of the inventive concepts (e.g. voltage regulator 110 ).

[0090] Thus, the voltage regulator 1225 load the power input terminal of the active logic while interrupting the power gating switch in the transition state section where an operating mode is changed from a sleep mode to an active mode. Since the power gating switch is turned on after the active regulator is sufficiently enabled, a stable voltage can be supplied when changing an operating mode.

[0091] The card connection unit 1210is configured to communicate with the outside world (e.g., a host) through one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-E), Serial Attached Small Computer System Interface (SCSI) (SAS), Serial Advanced Technology Attachment (SATA), Parallel ATA (PATA), SCSI, Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0092] Fig. 14 is a block diagram illustrating a mobile device according to an embodiment of inventive concepts. Referring to Fig. 14 can be a mobile device 2000 a battery 2100 , a power supply circuit 2200 , an application processor 2300 , an input / output interface 2400 , a random access memory (RAM) 2500 , an analog baseband chipset 2600 , an advertisement 2700and a non-volatile memory 2800 contain.

[0093] The power supply circuit 2200 converts a power supply voltage Vin supplied by the battery 2100 provided into different levels Vout1–Vout6 to output them to different driver units. The power supply circuit 2200 contains a voltage regulator 2250 , such as the voltage regulator 110 , 110a or 110b . Thus, the power supply circuit 2200 have stable and high performance efficiency.

[0094] The system-on-chip according to inventive concepts can be mounted using various types of packages. For example, the memory controller or the memory device can be mounted using various types of packages, such as: E.g., PoP (package-on-package), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die-in-waffle pack, die-in-wafer form, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), thin quad flat pack (TQFP), system-in-package (SIP), multi-chip package (MCP), a wafer-level fabricated package (WFP) and a wafer-level processed stack package (WSP).

[0095] According to embodiments of the inventive concepts, a voltage regulator is provided that can solve power supply instability that occurs when changing an operation mode without depending on a power supply capacitor, as well as a memory controller and a memory system including the voltage regulator.

[0096] The above-disclosed subject matter is intended to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, improvements, and further embodiments as fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent permitted by law, the scope of the inventive concepts is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and is not to be restricted or limited by the foregoing detailed description. QUOTES CONTAINED IN THE DESCRIPTION

[0097] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0098] KR 10-2013-0153985

[0001]

Claims

[1] Memory controller ( 100 ) a memory card with: an active controller ( 111 ) that is configured to operate in an active mode and to be inactive in a sleep mode; an active logic ( 120 ) configured to receive a drive voltage (VDD_A); a power gating switch ( 114 ) that is configured to connect the active controller ( 111 ) with the active logic ( 120 ) after a transition state (TS) of the active mode, wherein the transition state (TS) is an initial period of the active mode; and a charging circuit ( 113 ; 113a ; 113b ; 113c ), which is configured to load the active logic ( 120 ) during the transition state (TS). [2] Memory controller ( 100 ) according to claim 1, wherein the charging circuit ( 113 ; 113a ; 113b 113c) is configured to load the active logic ( 120 ) until a voltage of the power input terminal (N2) of the active logic ( 120 ) a reference voltage (REF; REF1, REF2) is reached. [3] Memory controller ( 100 ) according to claim 2, wherein the transient state (TS) begins when the active mode begins, and the transient state (TS) ends when the voltage of the power input terminal (N2) reaches the reference voltage (REF; REF1, REF2). [4] Memory controller ( 100 ) according to claim 1, wherein the memory controller ( 100 ) is configured to close the power gating switch ( 114 ) when the charging circuit ( 113 ; 113a ; 113b ; 113c ) is inactive. [5] The memory controller of claim 2, wherein the charging circuit comprises: a programmable logic circuit ( 150) for setting a level of the reference voltage (REF) or an amplitude of a charging current (Ic) from the charging circuit ( 113c ). [6] The memory controller of claim 1, further comprising: a sleep regulator ( 112 ), which is configured to work in sleep mode and active mode, with the sleep controller ( 112 ) is configured to generate a sleep voltage (VDD_S); and a sleep logic ( 130 ) which is configured to operate based on the sleep voltage (VDD_S). [7] The memory controller of claim 1, further comprising: a power gate control logic ( 115 ; 117 ) that is configured to open the power gating switch ( 114 ) during the transition state (TS) and to close the power gating switch ( 114 ) in response to the charging circuit ( 113 ; 113a ; 113b ; 113c ). [8] Memory controller according to claim 1, wherein the charging circuit ( 113a ) has: a switch control logic ( 117 ) that is configured to open the power gating switch ( 114 ) during the transition state (TS) and to close the power gating switch ( 114 ) based on a voltage of the power input terminal (N2) of the active logic ( 120 ). [9] Voltage regulator ( 110 ; 110a ; 110b ; 110c ) a semiconductor device comprising: a first controller ( 111 ) that is configured to operate in an active mode and to be inactive in a sleep mode; a second controller ( 112 ), which is configured to work in the sleep mode and in the active mode, with the second controller ( 112 ) is configured to generate a sleep voltage (VDD_S), with the second regulator ( 112 ) and the first controller (111 ) have a common output terminal (N1); an active logic ( 120 ) configured to receive a drive voltage (VDD_A); a sleep logic ( 130 ) configured to operate based on the sleep voltage (VDD_S), wherein the sleep voltage (VDD_S) and the drive voltage (VDD_A) have an equal voltage level; a power gating switch ( 114 ) configured to connect the common output terminal (N1) to a power input terminal (N2) of the active logic ( 120 ) based on a state of the active mode; and a charging circuit ( 113 ; 113a ; 113b ; 113b) configured to charge the power input terminal (N2) to a reference voltage (REF; REF1, REF2) during a transient state (TS) of the active mode, wherein the transient state (TS) is an initial period of the active mode. [10] Voltage regulator ( 110 ; 110a ; 110b ; 110c ) according to claim 9, wherein the voltage regulator ( 110 ) is configured to control the charging circuit ( 113 ) when the power input terminal (N2) has reached the reference voltage (REF; REF1, REF2). [11] Voltage regulator ( 110 ; 110a ; 110b ; 110c ) according to claim 10, wherein the voltage regulator ( 110 ; 110a ; 110b ; 110c ) is configured to use the power gating switch ( 114 ) when the charging circuit ( 113 ) is inactive. [12] Voltage regulator ( 110 ; 110a ; 110b ; 110c) according to claim 9, wherein the charging circuit comprises: a power source ( 116 ) configured to generate a charging current (Ic) for charging the power input terminal (N2); a charging switch ( 118 ) that is configured to supply the power source ( 116 ) to the power input terminal (N2); and a comparator ( 119 ; 119a ; 119b ; 119c ), which is configured to close the charging switch ( 118 ) during the transition state (TS) and to open the charging switch ( 118 ) based on a reference voltage (REF; REF1, REF2) and a voltage of the power input terminal (N2). [13] Voltage regulator ( 110 ; 110a ; 110b ; 110c ) according to claim 12, wherein the charging circuit is configured to control the charging switch ( 118) when the voltage of the power input terminal (N2) increases above the reference voltage (REF; REF1, REF2). [14] Voltage regulator ( 110 ; 110a ; 110b ; 110c ) according to claim 12, wherein the power source comprises: a programmable variable current source ( 116 ) configured to change an amplitude of a charging current (Ic) for the active logic ( 120 ). [15] Voltage regulator ( 110c ) according to claim 12, wherein the voltage regulator ( 110c ) is configured to change the reference voltage (REF). [16] Memory controller ( 100 ) with: an active logic ( 120 ) configured to operate based on a drive voltage (VDD_A), with the active logic ( 120 ) is configured to support an external storage device ( 200 ) to control; a sleep logic ( 130) configured to operate based on a sleep voltage (VDD_S), with the sleep logic ( 130 ) is configured to detect a change in an operating mode of the memory controller ( 100 ) and a voltage regulator ( 110 ; 110a ; 110b ; 110c ) with: a charging circuit ( 113 ; 113a ; 113b ; 113c ), which is configured to supply the drive voltage (VDD_A) to the active logic ( 120 ) based on the detected change, and an active controller ( 111 ), which is configured to supply the drive voltage (VDD_A) to the active logic ( 120 ) when the drive voltage (VDD_A) is greater than a reference voltage (REF; REF1, REF2). [17] Memory controller according to claim 16, wherein the charging circuit ( 113 ; 113a ; 113b ; 113c ) a charging switch ( 118) which is configured to disconnect the charging circuit ( 113 ; 113a ; 113b ; 113c ) from the active logic ( 120 ) based on the drive voltage (VDD_A) and the reference voltage (REF; REF1, REF2). [18] The memory controller of claim 17, further comprising: a power gating switch ( 114 ) that is configured to connect the active controller ( 111 ) with the active logic ( 120 ) based on a state of the charging switch ( 118 ). [19] The memory controller of claim 18, wherein the power gating switch ( 114 ) is configured to close when the charging switch ( 118 ) is opened. [20] The memory controller of claim 19, wherein the power gating switch ( 114 ) is configured to open when the charging switch ( 118 ) is closed.

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