Semiconductor device with a structure having a positive temperature coefficient

Abstract

Bipolar transistor with insulated gate, comprising: an emitter terminal (E) on a first surface (103) of a semiconductor body (105); a collector terminal (C) on a second surface (107) of the semiconductor body (105);a drift zone (121) of a first conductivity type in the semiconductor body (105) between the first and second surfaces (103, 107), a collector injection structure (131) between the drift zone and the second surface in a transistor cell region, a structure (115) with a positive temperature coefficient that is part of an emitter contact structure on the first surface (103), wherein above a maximum operating temperature (Tmax) specified for the semiconductor device, a specific resistance of the structure (115) with a positive temperature coefficient increases by at least two orders of magnitude within a temperature range of at most 50 K, and the structure (115) with a positive temperature coefficient is embedded in a porous part of a metallization layer that electrically couples the semiconductor body (105) and a first load terminal (L1).

Description

BACKGROUND In semiconductor power applications, such as power diode or power transistor applications, overcurrents or peak currents can occur, caused, for example, by low-inductance short circuits. These short circuits can be caused by drive disturbances, semiconductor failure, or short circuits in loads. Typically, a maximum overcurrent is specified in datasheets for semiconductor power devices as a maximum peak rated current. Exemplary semiconductor devices for switching high currents are known from German patent applications DE 10 2014 100 522 A1, DE 10 2014 104 061 A1, CN 1 03 268 888 A, and JP 2014 - 103 376 A. The maximum peak rated current depends on the energy injected by the overcurrent, i.e., pulse duration, peak current magnitude, and voltage drop across the device.Semiconductor switches, such as insulated-gate bipolar transistors (IGBTs), insulated-gate field-effect transistors (IGFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or bipolar junction transistors, can actively limit short-circuit currents to protect the overall application and peripheral devices from damage. Avoiding damage to the semiconductor switches requires rapid shutdown in a short-circuit mode due to high electrical losses in the semiconductor caused by the applied full intermediate voltage. It is desirable to provide a semiconductor device that has improved overcurrent or peak current capability. SUMMARY The problem is solved by the teachings of the independent claims. Further embodiments are given in the dependent claims. The expert will recognize additional features and advantages after reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are enclosed to provide a further understanding of the invention and are incorporated into and form part of the disclosure of the invention. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the principles of the invention. Other exemplary embodiments of the invention and intended advantages are immediately appreciated, as they are better understood with reference to the following detailed description. Fig. 1A is a schematic sectional view illustrating a semiconductor device comprising a structure with a positive temperature coefficient. Figs. 1B to 1E are schematic top views illustrating various layouts or configurations of the structure with a positive temperature coefficient.Figure 2A is a schematic sectional view of a semiconductor diode without the positive temperature coefficient structure. Figures 2B to 2D are schematic views of semiconductor devices that include a positive temperature coefficient structure and a mesar edge termination or a planar edge termination. Figures 3A to 3C are sectional views of embodiments of insulated-gate bipolar transistors that include the positive temperature coefficient structure as part of an emitter contact structure. Figures 4A to 4D are sectional views of embodiments of insulated-gate bipolar transistors that include the positive temperature coefficient structure between a collector terminal and a collector injection structure in an active device region. DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings. The drawings are not to scale and serve only for illustrative purposes. For clarity, the same elements are marked with corresponding reference symbols in the various drawings, unless otherwise stated. The expressions "have," "contain," "comprise," "exhibit," and similar expressions are open-ended, indicating the presence of the identified structures, elements, or features without excluding additional elements or features. Indefinite and definite articles should encompass both the plural and singular unless the context clearly indicates otherwise. The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more intermediate elements suitable for signal transmission may be provided between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" indicates a doping concentration lower than that of an "n" doping area, while an "n+" doping area has a higher doping concentration than an "n" doping area. Doping areas with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping areas can have the same or different absolute doping concentrations. The terms "wafer," "substrate," "semiconductor body," or "semiconductor substrate" used in the following description can encompass any semiconductor-based structure having a semiconductor surface. Wafer and structure are to be understood as including silicon (Si), silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor substrate, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor can equally be silicon-germanium (SiGe), germanium (Ge), or gallium arsenide (GaAs). According to other embodiments, silicon carbide (SiC) or gallium nitride (GaN) can form the semiconductor substrate material. The term "horizontal," as used in this description, is intended to describe an orientation or alignment essentially parallel to a first or main surface of a semiconductor substrate or body. This could be, for example, the surface of a wafer, a die, or a chip. The term “vertical”, as used in the present description, is intended to describe an orientation that is essentially perpendicular to the first surface, i.e. parallel to the normal direction of the first surface of the semiconductor substrate or body. In this description, a second surface of a semiconductor substrate or semiconductor body is considered to be formed by the bottom or back surface, while the first surface is considered to be formed by the top, front, or main surface of the semiconductor substrate. The terms "above" and "below," as used in this description, therefore describe the relative position of one structural feature to another. In this description, n-doped refers to a first conductivity type, while p-doped refers to a second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relationships, so that the first conductivity type can be p-doped and the second conductivity type n-doped. An embodiment of a semiconductor device 100 is illustrated in the schematic sectional view of Fig. 1A. The semiconductor device 100 comprises a first load terminal L1 on a first surface 103 of a semiconductor body 105. A second load terminal L2 is located on a second surface 107 of the semiconductor body 105 opposite the first surface 103. An active device region 110 is surrounded by an edge termination region 111. Load terminal contacts 113 are electrically connected to the semiconductor body 105 in the active device region 110 on the first surface 103. The semiconductor device 100 further comprises a structure 115 with a positive temperature coefficient between at least one terminal from the first and second load terminals L1, L2 and a corresponding surface from the first and second surfaces 103, 107. Above orAbove a maximum operating temperature specified for the semiconductor device, the specific resistance of the structure with a positive temperature coefficient increases by at least two orders of magnitude within a temperature range of at most 50 K. According to exemplary embodiments, the maximum operating temperature or maximum transition / junction temperature is 125 °C, 150 °C, or 175 °C. The degree of area or surface coverage with the structure 115 with a positive temperature coefficient is greater in the edge closure area 111 than in the active device area 110, which is shown by way of example in the top view of Fig. 1B for the specific case of full area or surface coverage of the edge closure area 111 with the structure 115 with the positive temperature coefficient and partial coverage of the active device area 110 with the structure 115 with a positive temperature coefficient. It should be noted that the schematic representation of Fig. 1B shows only one specific example of setting an area or surface coverage, where the structure 115 with a positive temperature coefficient is larger in the edge closure area 111 than in the active device area 110. Other embodiments include various layouts or configurations.Designs to satisfy the above relationship between the area coverage with the structure 115 having a positive temperature coefficient in the edge termination area 111 and the active device area 110. According to one embodiment, a diode comprises the structure 115 with a positive temperature coefficient either on a surface of the anode or on a surface of the cathode. According to another embodiment, an IGBT comprises the structure 115 with a positive temperature coefficient on a surface of the collector. According to one embodiment, the structure 115 with a positive temperature coefficient covers less than 5% or 10% or 20% of the active device area 110. According to another embodiment, the structure 115 with a positive temperature coefficient covers more than 50% or 60% or 70% of the edge termination area 111. According to one embodiment, a lateral extension l of the structure 115 with a positive temperature coefficient extends from a transition between the edge termination region 111 and the active device region 110 into the active device region 110 in a range of 0.12 xd <= l <= 3 xd, or in a range of 0.32 xd <= l <= 2 xd, or in a range of 0.52 xd <= l <= d, where d is a thickness of the semiconductor body 105. According to one embodiment, the structure 115 with a positive temperature coefficient comprises one or more separate continuous parts, and each of the continuous parts may include no, one or more vias or openings. For example, the structure 115 illustrated in the top view of Fig. 1B with a positive temperature coefficient can be viewed as a continuous structure with a positive temperature coefficient that has a via or opening in the middle of the active device area 110. Further exemplary embodiments of layouts or configurations of the structure 115 with a positive temperature coefficient are illustrated in the top view of Fig. 1C for ring-shaped parts. The schematic top view of Fig. 1D shows strip-shaped parts of the structure 115 with a positive temperature coefficient, and the schematic top view of Fig. 1E shows a pattern or structure of separate islands of the structure 115 with a positive temperature coefficient. The islands of the structure 115 with a positive temperature coefficient shown in Fig. 1E are circular and can have the same or different dimensions. According to other embodiments, the islands have different shapes, such as polygons, triangles, squares, and circles, and any combination thereof.A combination of any number and shape of parts of the structure 115 with a positive temperature coefficient can be used, provided that the area coverage with the structure 115 with a positive temperature coefficient is greater in the boundary closure area 111 than in the active device area 110. According to one embodiment, the structure with a positive temperature coefficient is manufactured or made from a part consisting of a first part 1150 between the first load connection L1 and the first surface 103 and a second part 1151 between the second load connection L2 and the second surface 107. In the semiconductor body 105, a variety of functional semiconductor regions are formed, depending on the type of semiconductor device. According to one embodiment, the semiconductor device 100 is a diode comprising an anode region in the active device area 110 on the first surface 103 and a cathode region on the second surface 107. The first load terminal L1 is electrically connected to the anode region, and the second load terminal L2 is electrically connected to the cathode region. According to another embodiment, the semiconductor device 100 is an insulated-gate bipolar transistor (IGBT) comprising an emitter on the first surface 103 and a collector on the second surface 107. The first load terminal L1 is electrically connected to the emitter, and the second load terminal L2 is electrically connected to the collector. The purpose of the edge termination area 111 is to reduce electric field peaks at the edge or periphery of the semiconductor device 100. According to one embodiment, the edge termination region 111 comprises a planar edge termination structure. Examples of planar edge termination structures include field plates, ring structures such as floating or potential-free guard rings or ring segments, junction termination extensions (JTE) structures, and structures with varying lateral doping (VLD). In the case of a planar edge termination structure on the first surface 103, contacts on the semiconductor body 105 on the first surface 103, which electrically connect the semiconductor body 105 to the first load terminal L1, are confined to the active device region 110 and are absent in the edge termination region 111. In the case of a diode, contacts that electrically connect the anode region on the first surface 103 to the load terminal L1 are confined to the active device region 110 and are absent in the edge termination region 111.In the case of an IGBT, contacts that electrically connect the source area on the first surface 103 with the first load terminal L1 are limited to the active device area 110 and are absent in the edge termination area 111. According to another embodiment, the edge termination region 111 comprises a mesar edge termination structure. The mesar edge termination structure can include a multiple junction termination extension (MJTE) or slanted edge terminations, such as a positive slanted edge termination structure or a negative slanted edge termination structure. The arrangement of the structure 115 with a positive temperature coefficient, as illustrated in Figures 1A to 1E, allows for an improved overcurrent capability of the semiconductor device 100 due to an optimized edge termination. In normal operating mode, temperatures in the edge termination region 111 are too low to cause a significant increase in the resistance of the structure 115 with a positive temperature coefficient. Thus, current injection from the edge termination region 111 can occur unimpeded. If the temperature exceeds a critical temperature, for example, due to heating caused by overcurrent, the resistance of the structure 115 with a positive temperature coefficient increases significantly. As a result, current injection from the edge termination region 111 into the semiconductor body 105, for example, into a drift zone of the semiconductor device 100 in the active device region 110, is hindered and thus reduced.In the case of a diode, current crowding in an anode boundary region, caused by current injection from the cathode into the edge termination region 111, can be reduced. Similarly, current crowding in an emitter boundary region of an IGBT, caused by collector current injection from the edge termination region 111, can be reduced. Since current crowding in an emitter boundary region of an IGBT or in an anode boundary region of a diode can be destructive or a damaging event resulting from an overcurrent, the semiconductor device 100 exhibits improved overcurrent capability. According to one embodiment, the structure 115 with a positive temperature coefficient comprises a material of at least one phase-change material having a critical temperature of phase change between a crystalline phase and an amorphous phase of greater than 175 °C, a semiconducting polycrystalline ceramic, polymeric matrix metal particle composites, or a polymer coated with carbon or with electrically conductive particles. Examples of phase-change materials are chalcogenides, for example Ge2Sb2Te5. In structures with a positive temperature coefficient, made from semiconducting polycrystalline ceramics, a boundary layer typically forms at grain boundaries, leading to an increase in resistance at a characteristic temperature, for example, in a range between 80 °C and 130 °C. BaTiO3 is an example of a semiconducting polycrystalline ceramic. According to another embodiment, structures with a positive temperature coefficient, made from polymer-matrix-metal particle composites, can contain 15 to 25 volume percent (vol%) of conductive metal particles with a length or diameter in the range of 15 nm to 5 µm. Depending on a force / pressure on the metal particles caused by the polymer matrix, the conductivity of the polymer-matrix-metal particle composites can change. A phase transition between a crystalline phase and an amorphous phase, or between an amorphous phase and a viscoelastic phase of the polymer matrix, can lead to a significant decrease in the modulus of elasticity, resulting in an increase in resistance.Suitable polymer systems that exhibit high temperature stability, for example up to 500 °C for polyimides, include thermosetting plastics such as epoxy compounds or acrylic resins, as well as high-temperature thermoplastics such as polyphenylene sulfide (PPS), polyether ether ketone (PEEK), polyamide imide (PAI), polyethersulfone (PES), polysulfone (PSU), polyetherimide (PEI), or liquid crystal polymers (LCP). All of these examples have a melting point or glass transition temperature above 260 °C, which is a typical value for a common maximum soldering temperature. Examples of metal particles include silver (Ag) and copper (Cu). The structure with a positive temperature coefficient can also be a crystalline or partially crystalline polymer coated with electrically conductive carbon or another conductive material. The crystalline structure allows for a dense layer of carbon particles or particles of another conductive material on the polymer surface, enabling current flow through the conductive carbon layer or the other conductive material. Heating, for example, as a result of overcurrents, leads to an increase in the temperature of the crystalline or partially crystalline polymer. When a phase transition temperature of the polymer is exceeded, the crystalline or partially crystalline polymer becomes amorphous. This phase change is accompanied by a slight increase in volume, resulting in separation or partial separation of the conductive coating, which leads to an increase in resistance.Partially crystalline polymers, such as PEEK, PAI, or PES, which have a glass transition temperature (Tg) of approximately 225 °C, can be used. For higher critical temperatures, polyimide (PI), which has a glass transition temperature in the range of approximately 250 °C to 400 °C, can be used. For lower critical temperatures, polysulfone (PSU), which has a glass transition temperature (Tg) of 187 °C, can be used. Fig. 2A is a schematic sectional view of a semiconductor diode 140 without a structure with a positive temperature coefficient in the edge termination region 111 on the second surface 107. An n-doped drift zone 121 is part of the semiconductor body 105. A p-doped anode region 122 borders the first surface 103 and is electrically connected to the first load terminal L1 via an anode contact 123. An n+-doped cathode region 124 borders the second surface 107 and is electrically connected to the second load terminal L2 via a collector contact 125. The edge termination region 111 comprises a planar edge termination with guard rings 1260, 1261, 1262, which adjoin a passivation layer 127 on the first surface 103. The edge termination region 111 may also include other planar edge termination structures or mesa termination structures. The edge termination region 111 may further include a channel stopper 128. During an overcurrent event, a current pushing into an edge region 130 of the p-doped anode region 122 is caused by current injection from the n+-doped cathode region 124 into the edge termination region 111. A current pushing into the edge region 130 is illustrated in a simplified manner in Fig. 2A by current flow lines. The current that is forced into the boundary area 130 at the first surface 103 can lead to a device failure or device destruction, which is caused, for example, by overcurrent. Fig. 2B is a sectional view of an embodiment of a semiconductor diode 150, which, in addition to the elements of the semiconductor diode 140 shown in Fig. 2A, has the structure 115 with a positive temperature coefficient on the second surface 107 in the edge termination region 111. The degree of surface coverage with the structure 115 with a positive temperature coefficient is greater in the edge termination region 111 than in the active device region 110. Thermal heating of the structure 115 with a positive temperature coefficient, for example caused by an overcurrent event, leads to a significant increase in the resistance of the structure 115 with a positive temperature coefficient, which results in a decrease or suppression of current injection from the n+-doped cathode region 124 into the edge termination region 111.This allows for the avoidance or reduction of current pushing in the boundary region 130 of the p-doped anode area 122 at the first surface 103. Thus, the probability of device failure, device degradation, or device destruction caused by current pushing in the boundary region 130 due to an overcurrent can be reduced. Therefore, the structure 115 with a positive temperature coefficient allows for an improvement in the overcurrent strength. Fig. 2C is a sectional view of an IGBT 160, which has the structure 115 with a positive temperature coefficient in the edge termination region 111 on the second surface 107. The IGBT 160 further comprises a p+-doped collector injection structure 131 adjacent to the second surface 107. The structure 115 with a positive temperature coefficient and a collector contact 132 are electrically connected to the second load terminal L2. A p-doped body region 133 and an n+-doped source region 134 are adjacent to the first surface 103 and are electrically connected to the first load terminal L1 via an emitter contact 135. A gate dielectric 136 and a gate electrode 137 are formed in a trench 138, respectively. The gate electrode 137 is electrically connected to a gate terminal G. Similar to the semiconductor diode 150 shown in Fig. 2B, the structure 115 with a positive temperature coefficient in the edge termination region 111 of the IGBT 160 allows the risk of a current pushing into the boundary region 130 of the p-doped body area 133 due to excessive current injection from the collector injection structure 131 into the edge termination region 111 to be avoided or reduced. Fig. 2D is a sectional view of a semiconductor diode 165, which includes the structure 115 with the positive temperature coefficient in the edge termination region 111 on the first surface 103. Unlike the embodiments shown in Figs. 2A to 2C, which have planar edge terminations, the semiconductor diode 155 includes a mesar edge termination in the form of a positively inclined edge termination structure. The technical advantages achieved by the structure 115 with a positive temperature coefficient in the edge termination region 111 are similar to those explained above with reference to Figs. 2B and 2C. The schematic sectional views in Figures 3A to 3C illustrate exemplary embodiments of a bipolar transistor 170 with an insulated gate. The IGBT 170 comprises an emitter terminal E on the first surface 103 of the semiconductor body 105. A collector terminal C is located on the second surface 107 of the semiconductor body 105. A drift zone 121 of a first conductivity type, for example, an n-type, is located in the semiconductor body 105 between the first and second surfaces 103 and 107. A collector injection structure 131 is located between the drift zone 121 and the second surface 107 in a transistor cell region. A structure 115 with a positive temperature coefficient is part of an emitter contact structure 181 on the first surface 103. In the IGBT 170, the gate electrode 137 is electrically coupled to a gate terminal G, and another electrode 139 is electrically coupled to a source terminal S. In the embodiment of the IGBT 170 shown in Fig. 3A, the structure 115 with a positive temperature coefficient is part of a filling of a contact opening 182 in a dielectric layer 183, which adjoins the first surface 103. According to one embodiment, a barrier or blocking layer can be arranged between the semiconductor body 105 and the structure 115 with a positive temperature coefficient. In the embodiment of the IGBT 170 shown in Fig. 3B, the structure 115 with a positive temperature coefficient is part of a porous region of the emitter contact structure 181. The thermal and electrical conductivity of the emitter contact structure 181 above a critical temperature can be adjusted by the degree of porosity. A foamy distribution of the structure 115 with a positive temperature coefficient can ensure a rapid and complete phase change of the structure with a positive temperature coefficient above the critical temperature. In the embodiment of the IGBT 170 shown in Fig. 3C, the structure 115 with a positive temperature coefficient abuts the source region 134, and another part of the filling, different from the structure 115 with a positive temperature coefficient, abuts the body region 133 of the IGBT 170. An additional voltage drop caused by a temperature-dependent change in the resistance of the structure 115 with a positive temperature coefficient is limited to the source region 134. This allows for a further reduction of the saturation current caused by current confinement between an n-type channel and the p-doped body region 133, similar to a junction field-effect transistor (JFET). Furthermore, latch-up effects during overcurrent shutdown of an excessively heated device can be reduced. Apart from a short-circuit function, the embodiments allow for the protection of a parallel connection of circuit devices, such as transistor cells, against overheating. Beyond reducing saturation currents in a short-circuit mode, the embodiments shown in Figures 3A to 3C result in an increase in the emitter-collector voltage of the cells exceeding a critical temperature. Consequently, the current flow decreases in the overheated cells and increases in those cells that do not exceed the critical temperature. This prevents premature damage to weak device components, for example, caused by solder or cooling deficiencies or weaknesses resulting from overload operation. The transistor cells of Figures 3A to 3C can be uniformly distributed within the active device area 110 of an IGBT device, or they can constitute the only active cells of the IGBT device, or they can be mixed with additional transistor cells lacking the structure 115 and having a positive temperature coefficient. The overall ratio of the cells of Figures 3A to 3C and the second transistor cells can vary across the device, for example, being higher near an edge termination region 111 than in a central region of the active device area 110. The schematic sectional views in Figures 4A to 4D show exemplary embodiments of a bipolar transistor 170 with an insulated gate. The IGBT 190 comprises the collector terminal C on the second surface 107 of the semiconductor body 105. The active device area 110 is surrounded by the edge termination area 111. The structure 115 with a positive temperature coefficient is located between the collector terminal C and the collector injection structure 131 on the second surface 107. The structure 115 with a positive temperature coefficient at least partially covers the active device area 110 on the second surface 107. In normal operating mode, for example at operating temperatures below 175 °C, the structure 115 with a positive temperature coefficient in the active device region 110 has low resistance. Thus, hole injection from the collector injection structure 131 into the semiconductor body 105 is unimpeded. During a short circuit or other extreme conditions, high temperatures occur, for example, temperatures above 175 °C, and the structure 115 with a positive temperature coefficient in the active device region 110 becomes highly resistive. This hinders hole injection from those parts of the collector injection structure 131 that are covered by the structure 115 with a positive temperature coefficient. As a result, the saturation current is reduced, which prevents a destructive or damaging overcurrent in the device.Dimensions and distances between different parts of the structure 115 with a positive temperature coefficient can be chosen such that overheating / melting due to high currents in the area between the parts during a short circuit is avoided, achieving a sufficient reduction of hole injection. According to one embodiment, the degree of area or surface coverage of the structure with a positive temperature coefficient in the active device area is greater than 50%. Unlike the IGBTs shown in Fig. 4A and Fig. 4B, the IGBTs 170 shown in Fig. 4C and Fig. 4D are backward conducting (RC) IGBTs that have n-doped short-circuit regions 156 that connect to the collector contact between parts of the structure 115 with a positive temperature coefficient. In the embodiments shown in Figs. 4B and 4D, one conductivity type of the doped region 153 is identical to the conductivity type of the collector injection structure 131, while one conductivity type of the doped region 154, shown in Figs. 4A and 4C, differs from the conductivity type of the collector injection structure 131. The doped regions 153 and 154 enable high dynamic robustness (HDR). Highly doped contact areas can, for example, be arranged between the n-doped short-circuit areas 115 and the collector contact 132 to reduce contact resistance.

Claims

Bipolar transistor with insulated gate, comprising: an emitter terminal (E) on a first surface (103) of a semiconductor body (105); a collector terminal (C) on a second surface (107) of the semiconductor body (105);a drift zone (121) of a first conductivity type in the semiconductor body (105) between the first and second surfaces (103, 107), a collector injection structure (131) between the drift zone and the second surface in a transistor cell region, a structure (115) with a positive temperature coefficient that is part of an emitter contact structure on the first surface (103), wherein above a maximum operating temperature (Tmax) specified for the semiconductor device, a specific resistance of the structure (115) with a positive temperature coefficient increases by at least two orders of magnitude within a temperature range of at most 50 K, and the structure (115) with a positive temperature coefficient is embedded in a porous part of a metallization layer that electrically couples the semiconductor body (105) and a first load terminal (L1). Bipolar transistor with insulated gate, comprising: an emitter terminal (E) on a first surface (103) of a semiconductor body (105), a collector terminal (C) on a second surface (107) of the semiconductor body (105); an active device region (110) surrounded by an edge termination region (111), wherein emitter contacts are electrically connected to the semiconductor body (105) in the active device region (110) on the first surface (103), and further comprising: a structure (115) with a positive temperature coefficient between the collector terminal and a collector injection structure on the second surface (107), wherein the structure (115) with a positive temperature coefficient at least partially covers the active device region on the second surface (107), and wherein above a maximum operating temperature (Tmax) specified for the semiconductor device,a specific resistance of the structure (115) with a positive temperature coefficient increases by at least two orders of magnitude within a temperature range of at most 50 K, and further comprising a doped region (153) adjacent to the second surface (107) in the edge termination region (111) surrounding the active device region, wherein a dose of doping the doped region (153) is smaller than a dose of doping the collector injection structure of the opposite conductivity type. Bipolar transistor with insulated gate according to claim 2, wherein a degree of area or region coverage of the structure (115) with a positive temperature coefficient in the active device area (110) is greater than 50%. Bipolar transistor with insulated gate according to one of claims 2 to 3, wherein the bipolar transistor with insulated gate is a backward conducting bipolar transistor with insulated gate comprising short-circuit regions electrically connected to a collector contact on the second surface (110), wherein the short-circuit regions have a conductivity type different from the conductivity type of the collector injection structure. Bipolar transistor with insulated gate according to one of claims 1 to 4, wherein the structure (115) with positive temperature coefficient comprises a material comprising at least one material consisting of a phase change or phase transition material having a critical temperature of a phase change between a crystalline phase and an amorphous phase of greater than 175 °C, a semiconducting polycrystalline ceramic, polymer matrix metal particle composites, a polymer coated with carbon or with electrically conductive particles. Bipolar transistor with insulated gate, comprising: an emitter terminal (E) on a first surface (103) of a semiconductor body (105), a collector terminal (C) on a second surface (107) of the semiconductor body (105); an active device region (110) surrounded by an edge termination region (111), wherein emitter contacts are electrically connected to the semiconductor body (105) in the active device region (110) on the first surface (103), and further comprising: a structure (115) with a positive temperature coefficient between the collector terminal and a collector injection structure (131) on the second surface (107), wherein the structure (115) with a positive temperature coefficient at least partially covers the active device region on the second surface (107), and wherein above a maximum operating temperature (Tmax) specified for the semiconductor device,a specific resistance of the structure (115) with a positive temperature coefficient increases by at least two orders of magnitude within a temperature range of at most 50 K, and wherein short-circuit regions (156) adjoin a contact to the collector injection structure (131) on the second side (107) between parts of the structure (115) with a positive temperature coefficient.

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