Semiconductor device with metal silicide barrier region and method for its fabrication

Abstract

Semiconductor device comprising: a gate stack (130) on a semiconductor substrate (110); a source region (150) and a drain region (150) in the semiconductor substrate (110) and next to the gate stack (130); a resistor (160) on the semiconductor substrate (110), wherein the resistor (160) comprises a silicon material; a metal silicide layer (180) on at least one of the following areas or stacks: source area (150), drain area (150) and gate stack (130); and a first blocking region (230a) in an upper part of the resistor (160) to block or reduce the formation of the metal silicide layer (180) on the resistor (160), wherein the first blocking region (230a) comprises first dopants and second dopants with a smaller atomic radius than that of the first dopants, further comprising: an insulation structure (120) in the semiconductor substrate (110), wherein the resistor (160) is arranged above the insulation structure (120), the semiconductor device further comprising: a second barrier region (230b) in an upper part of the isolation structure (120), wherein the second barrier region (230b) comprises third dopants and fourth dopants, wherein the third dopants and the first dopants are the same, and wherein the fourth dopants and the second dopants are the same, wherein the second blocking area (230b) is arranged next to the resistor (160). still comprehensive: a third blocking region (230c) in an upper part of the semiconductor substrate (110) and next to the insulating structure (120), wherein the third blocking region (230c) comprises fifth dopants and sixth dopants, wherein the fifth dopants and the first dopants are identical, and wherein the sixth dopants and the second dopants are identical, the first dopants and second dopants preventing the metal atoms from coming into contact with or reacting with the resistor (160), the insulating structure (120) and the semiconductor substrate (110) in and / or below the blocking regions (230a, 230b, 230c).

Description

BACKGROUND

[0001] The semiconductor integrated circuit industry has grown rapidly. Technological advances in integrated circuit (IC) materials and IC design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have also increased the complexity of IC processing and manufacturing.

[0002] US 2013 / 0200466 A1 relates to integrated circuits with silicide block resistors made of polycrystalline silicon and methods for their production.

[0003] US 2010 / 0193867 A1 relates generally to semiconductor devices and methods, and more particularly, in a particular embodiment, to a silicide semiconductor structure and a method for its manufacture.

[0004] US 2006 / 0035426 A1 relates to methods and apparatus for forming polysilicon resistors.

[0005] Over the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line or wire) that can be produced using a manufacturing process) has decreased. This downscaling process offers inherent advantages due to increasing production efficiency and decreasing associated costs.

[0006] However, device processes can negatively impact the execution of other neighboring devices. Therefore, avoiding negatively impacting the execution of other neighboring devices is a challenge. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a better understanding of the embodiments and their advantages, reference is now made to the following descriptions together with the accompanying drawings. Fig. 1A to 1G illustrate cross-sectional views of various stages of a process for fabricating a semiconductor device according to some embodiments. Fig. 2 illustrates a cross-sectional view of a semiconductor device according to some embodiments. Fig. 3A to 3B illustrate cross-sectional views of various stages of a process for manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0008] The making and using of embodiments of the disclosure are explained in detail below. However, it should be appreciated that the embodiments may be practiced in a wide variety of specific contexts. The specific embodiments discussed are merely exemplary and do not limit the scope of the disclosure.

[0009] It should be appreciated that the following disclosure provides many different embodiments or examples for carrying out different features of the disclosure. To simplify the present disclosure, specific examples of components and arrangements are described below. These are understood to be merely examples and are not intended to be limiting. Moreover, performing a first process before a second process that follows in the description may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes are performed between the first and second processes. For simplicity and clarity, many features are drawn at arbitrary sizes.Furthermore, the formation of a first element over or on a second feature in the following description includes embodiments in which the first and second elements are formed in direct contact, and also embodiments in which additional elements may be formed between the first and second elements such that the first element and the second element do not have to be in direct contact.

[0010] Some variations of the embodiments are described. Like reference numerals are used to refer to like elements throughout the various views and exemplary embodiments.

[0011] The Fig. 1A to 1G illustrate cross-sectional views of various stages of a process for manufacturing a semiconductor device 100 according to some embodiments. As in Fig. 1A, a semiconductor substrate 110 is provided. According to some embodiments, the semiconductor substrate 110 is a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer.

[0012] In some embodiments, the semiconductor substrate 110 is made of a basic semiconductor material, including silicon or germanium, having a single-crystal, polycrystalline, or amorphous structure. In some other embodiments, the semiconductor substrate 110 is made of a semiconductor compound, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, a semiconductor alloy, such as SiGe or GaAsP, or combinations thereof. According to some embodiments, the semiconductor substrate 110 also includes multilayer semiconductors, semiconductor-on-insulator (SOI) (such as silicon-on-insulator or germanium-on-insulator), or combinations thereof.

[0013] An isolation structure 120 is formed in the semiconductor substrate 110 to define various active areas in the semiconductor substrate 110 and to electrically isolate adjacent devices (e.g., transistors) from each other. According to some embodiments, the isolation structure 120 is made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-K dielectric material, other suitable materials, or combinations thereof. According to some embodiments, the isolation structure 120 is formed using an isolation technology, such as localized semiconductor oxidation (LOCOS), shallow trench isolation (STI), or the like.

[0014] In some embodiments, forming the isolation structure 120 includes patterning the semiconductor substrate 110 using a photolithographic process, etching a trench into the semiconductor substrate 110 (e.g., using a dry etch, wet etch, or plasma etch process, or combinations thereof), and filling the trench (e.g., using a chemical vapor deposition process) with dielectric material. In some embodiments, the filled trench has a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

[0015] As in Fig. 1A, a gate stack 130 is formed over the semiconductor substrate 110 to define active regions in the semiconductor substrate 110. The gate stack 130 includes a gate dielectric layer 132 and a gate electrode 134 formed on the gate dielectric layer 132. The gate dielectric layer 132 is made of silicon oxide, silicon oxynitride, a high-k material, or combinations thereof. In some embodiments, the gate electrode 134 may be made of polysilicon, other silicon-containing materials, or other suitable gate materials.

[0016] Spacers 142 are formed over the sidewalls of the gate stack 130. According to some embodiments, the spacers 142 are made of a dielectric material, such as a silicon nitride layer, a silicon oxynitride layer, or combinations thereof. In some embodiments, a sealing or caulking layer 144 is formed between the spacers 142 and the gate stack 130. In some embodiments, the caulking layer 144 is made as a dielectric layer (e.g., silicon nitride).

[0017] In some embodiments, doped regions are formed in the semiconductor substrate using a suitable process, such as an ion implantation process. In some embodiments, doped regions 150 are a highly doped source region and a highly doped drain region, which may be formed after spacers 142 are formed. In some embodiments, gate stack 130, spacers 142, sealing layer 144, and doped regions 150 form a transistor.

[0018] According to the invention, a semiconductor element is formed over the semiconductor substrate 110, namely a resistor 160 or other semiconductor elements in or on which the formation of metal silicides is to be prevented. According to the invention, the resistor 160 is formed over the isolation structure 120. The resistor 160 comprises a silicon material. The silicon material comprises, for example, polysilicon. In some embodiments, the resistor 160 comprises bulk polysilicon 162. In some embodiments, the resistor 160 has a similar structure to the gate stack 130. The resistor 160 comprises bulk polysilicon 162 and a dielectric layer 164. In some embodiments, the bulk polysilicon 162 and the gate electrode 134 are formed in the same evaporation process, and the dielectric layer 164 and the gate dielectric layer 132 are formed in the same evaporation process.In some embodiments, the dielectric layer 164 and the gate dielectric layer 132 comprise the same materials.

[0019] In some embodiments, resistor 160 further includes spacers 166 formed over sidewalls of bulk polysilicon 162 and dielectric layer 164. In some embodiments, spacers 166 are made of a dielectric material, such as a silicon nitride layer, a silicon oxynitride layer, or combinations thereof. If desired, resistor 160 may also include a sealing layer 168 formed between spacers 166 and bulk polysilicon 162 and dielectric layer 164. In some embodiments, sealing layer 168 is made of a dielectric material (e.g., silicon nitride).

[0020] As in Fig. As shown in Figure 1A, a buffer layer 210 is formed over the semiconductor substrate 110, for example, using a chemical vapor deposition process. The buffer layer 210 covers the transistor T, the resistor 160, and the isolation structure 120. The buffer layer 210 is configured to buffer subsequent implantation processes. In some embodiments, the buffer layer 210 comprises oxides (e.g., SiO2) and nitrides (e.g., SiN). In some embodiments, the buffer layer 210 has a thickness K of about 150 to about 200.

[0021] Then, as in Fig. As shown in Figure 1B, a mask layer 220 covering the transistor T is formed on a portion of the buffer layer 210. The mask layer 220 is configured to shield the transistor T from dopants during subsequent implantation processes. In some embodiments, the mask layer 220 is a photoresist layer.

[0022] Afterwards, as in Fig. As shown in Figure 1C, a first implantation process is performed to implant first dopants into upper regions of the bulk polysilicon 162 and the isolation structure 120. In some embodiments, the first dopants comprise germanium or other suitable materials. According to some embodiments, the first implantation process comprises a germanium implantation process.

[0023] Subsequently, a second implantation process is performed to implant second dopants into the upper regions of bulk polysilicon 162 and isolation structure 120. The second dopants have a smaller atomic radius than the first dopants. In some embodiments, the second dopants comprise carbon or other suitable materials. In some embodiments, the second implantation process comprises a carbon implantation process.

[0024] According to some embodiments, the buffer layer 210 is used in the first implantation process and the second implantation process to control the doping depth and the doping concentration by selecting the material and the thickness K of the buffer layer 210.

[0025] In embodiments according to the invention, the first implantation process and the second implantation process form barrier regions 230a and 230b in the respective upper regions of the bulk polysilicon 162 and the isolation structure. In embodiments according to the invention, the first implantation process and the second implantation process further form barrier regions 230c in the upper regions of the semiconductor substrate 110 adjacent to the isolation structure 120. Each of the barrier regions 230a, 230b, and 230c contains first dopants and second dopants. In embodiments according to the invention, the barrier region 230b is adjacent to the resistor 160, and the barrier region 230c is adjacent to the isolation structure 120.

[0026] In some embodiments, within the barrier regions 230a, 230b, and / or 230c, the first dopants (e.g., germanium) implanted first with a larger radius block or retain the subsequently implanted second dopants (e.g., carbon) with a smaller radius. In some embodiments, the second dopants accumulate at or near the surface of the bulk silicon 162, the isolation structure 120, and / or the semiconductor substrate 110.

[0027] According to embodiments of the invention, the first and second dopants in the barrier regions 230a, 230b, and 230c block or halt the diffusion of metal atoms during subsequent metal silicide processes by adjusting the implantation energies and doses or dosages of the first and second implantation processes. Thus, according to some embodiments, the first and second dopants prevent the metal atoms from contacting or reacting with the bulk silicon 162, the isolation structure 120, and the semiconductor substrate 110 in and / or beneath the barrier regions 230a, 230b, and 230c.

[0028] In some embodiments, the barrier regions 230a, 230b, and 230c are also referred to as metal silicide barrier regions. According to embodiments of the invention, the metal silicide barrier regions prevent or suppress the formation of metal silicides in the bulk polysilicon 162, the isolation structure 120, and the semiconductor substrate 110 in and / or below the barrier regions 230a, 230b, and 230c. In some embodiments, the resistance of the resistor 160 decreases when metal silicides are formed in the resistor 160. The barrier regions 230a, 230b, and 230c therefore contribute to maintaining the resistance of the resistor 160 within a suitable range.

[0029] In some embodiments, the implantation energy of the first implantation process is in a range of about 10 keV to about 40 keV. In some embodiments, the implantation energy of the first implantation process is in a range of about 20 keV to about 30 keV. In some embodiments, the implantation dose for the first dopant of the first implantation process is in a range of about 1E14 cm -2 up to about 1E16 cm -2 .

[0030] In some embodiments, the implantation energy of the second implantation process is in a range of about 1 keV to about 15 keV. In some embodiments, the implantation energy of the second implantation process is in a range of about 5 keV to about 10 keV. In some embodiments, the implantation dose of the second dopant of the second implantation process is in a range of about 1E14 cm -2 up to about 1E16 cm -2.

[0031] In some embodiments, the implantation energy of the first implantation process is greater than the implantation energy of the second implantation process. In some embodiments, the difference in implantation energy between the first implantation process and the second implantation process is in a range from about 9 keV to about 39 keV. In some embodiments, the difference in implantation energy between the first implantation process and the second implantation process is in a range from about 9 keV to about 25 keV.

[0032] In some embodiments, the ratio between the implantation energy of the first implantation process and that of the second implantation process is in a range from about 0.67 to about 40. In some embodiments, the ratio of the implantation energy of the first implantation process and that of the second implantation process is in a range from about 2.37 to about 10.

[0033] According to some embodiments, one of the doping depths D1, D2 and D3 of the barrier regions 230a, 230b and 230c is in a range of about 0.1 to about 20. In some embodiments, the second dopant concentration of the barrier regions 230a, 230b and 230c is in a range of about 1E13 cm -3 up to about 1E16 cm -3 . The second dopant concentration of the barrier regions 230a, 230b and 230c is, for example, in a range of 1E14 cm -3 up to about 1E16 cm -3 .

[0034] In some embodiments, the first dopant concentration of the barrier regions 230a, 230b or 230c is in a range of about 1E13 cm -3 up to about 1E16 cm -3 For example, the first dopant concentration of the barrier regions 230a, 230b or 230c is in a range of about 1E14 cm -3 up to about 1E16 cm -3 .

[0035] In some embodiments, each of the barrier regions 230a, 230b, or 230c contains one or more of the elements boron, fluorine, and arsenic. In some embodiments, the buffer layer 210 is not required.

[0036] Then, as in Fig. As shown in Figure 1D, the mask layer 220 and the buffer layer 210 are removed. The buffer layer 210 is removed, for example, by a wet etching process. Because the buffer layer 210 is removed using only a wet etching process without using a dry etching process, the present embodiments prevent the transistor T from being damaged by a dry etching process and reduce manufacturing costs.

[0037] A metal silicide process is then carried out (as described in the Fig. 1E and Fig. 1F). As shown in Fig. 1E, a metal layer 104 is formed on the semiconductor substrate 110, for example, using physical vapor deposition. The metal layer 104 comprises, for example, nickel, cobalt, titanium, or the like. In some embodiments, the doped regions 150 and the gate electrode 134 are in direct contact with the metal layer 104. Subsequently, according to some embodiments, an annealing or annealing process is performed to form a metal silicide layer 180 between the metal layer 104 and the doped regions 150 and / or between the metal layer 104 and the gate electrode 134. In some embodiments, the barrier region 230c is adjacent to the metal silicide layer 180.

[0038] In some embodiments, the first dopants and second dopants in the barrier regions 230a, 230b, and 230c isolate the metal layer 104 from the bulk silicon 162 of the isolation structure 120 and / or a portion of the semiconductor substrate 110 in and / or below the barrier regions 230a, 230b, and 230c, respectively. Thus, according to some embodiments, the first dopants and second dopants prevent the formation of metal silicides in (or on) the bulk silicon 162, the isolation structure 120, and / or a portion of the semiconductor substrate 110 below the barrier regions 230a, 230b, and 230c, respectively.

[0039] Then, as in Fig. 1F, the metal layer 104 that has not reacted with the semiconductor substrate 110 and the gate electrode 134 is removed. Then, as shown in Fig. 1G, a contact etch stop layer 240 is deposited over the semiconductor substrate 110, for example, using chemical vapor deposition. The contact etch stop layer 240 covers the transistor T, the resistor 160, and the isolation structure 120. In some embodiments, the contact etch stop layer 240 is made of a dielectric material, such as silicon nitride. In some embodiments, the contact etch stop layer 240 is not required.

[0040] As in Fig. 1G, an insulating layer 250 is then deposited over the semiconductor substrate 110, according to some embodiments. According to some embodiments, the insulating layer 250 is made of any suitable insulating material, such as silicon oxynitride, silicon oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a low-k material, a porous dielectric material, or combinations thereof. According to some embodiments, the insulating layer 250 is deposited by any suitable process, for example, by a CVD process, a HDPCVD process, a spin-on process, a sputtering process, or combinations thereof.

[0041] Subsequently, in some embodiments, the insulation layer 250 and the contact etch stop layer 240 are patterned to form a contact opening 260 exposing a portion 180a of the metal silicide layer 180. Subsequently, in some embodiments, a contact plug or contact post 270 is formed in the contact opening 260 to electrically connect the portion 180a of the metal silicide layer 180 and the doped region 150 below the portion 180a of the metal silicide layer 180. The contact post 270 is made, for example, of tungsten or other suitable conductive materials.

[0042] Fig. 2 is a cross-sectional view of a semiconductor device 200 according to some embodiments. As shown in Fig. 2, the semiconductor device 200 according to some embodiments is similar to the semiconductor device 100 of Fig. 1G, except that the semiconductor device 200 additionally includes a thin metal silicide layer 181 on the barrier region 230a.

[0043] According to some embodiments, the barrier region 230a reduces the formation of metal silicides on (or in) the bulk polysilicon 162. As a result, in some embodiments, the thickness H1 of the thin metal silicide layer 181 on the barrier region 230a is less than the thickness H2 of the metal silicide layer 180 on the doped regions 150 of the gate electrode 134.

[0044] When the thickness H1 of the thin metal silicide layer 181 is reduced, the resistance of the resistor 160 is increased. Therefore, in some embodiments, the resistance of the resistor 160 can be adjusted by adjusting the thickness H1 of the thin metal silicide layer 181. According to some embodiments, the thickness H1 of the thin metal silicide layer 181 is adjusted by selecting a dopant (or dopant mixture), by the number of implantation processes performed, and / or by adjusting the implantation energies and doses of the implantation process(es) (as in Fig. 1C and also described herein). In some embodiments, the thickness H1 is in a range from about 0.1 nm to about 10 nm. In some embodiments, the thickness H1 is in a range from about 0.1 nm to about 5 nm.

[0045] Fig. 3A to 3B are cross-sectional views of various stages of a process for forming or manufacturing a semiconductor device 300 according to some embodiments. In some embodiments, as in Fig. 3A, after the step of Fig. 1C, a removal process is performed to remove a portion of the buffer layer 210 covering the transistor T. As a result, the buffer layer 210 covers only the resistor 160 and the isolation structure 120 (and / or a portion of the semiconductor substrate 110).

[0046] Subsequently, a metal layer 104 is formed on the semiconductor substrate 110. An annealing process is then performed to form a metal silicide layer between the metal layer 104 and the doped regions 150 and between the metal layer 104 and the gate electrode 134.

[0047] As in Fig.3B, the metal layer 104 that has not reacted with the semiconductor substrate 110 and the gate electrode 134 is then removed. A contact etch stop layer 240 is then deposited over the semiconductor substrate 110. Subsequently, in some embodiments, an insulating layer 250 is deposited over the semiconductor substrate 110. Subsequently, the insulating layer 250 and the contact etch stop layer 240 are patterned to form a contact opening 260 exposing a portion 180a of the metal silicide layer 180. Then, in some embodiments, a contact plug 270 is formed in the contact opening 260 to electrically connect the portion 180a of the metal silicide layer 180 and the doped region 150 below the portion 180a of the metal silicide layer 180.

[0048] In embodiments of the invention, only one implantation process is performed to form the barrier region(s). In some embodiments, the only one implantation process is performed using carbon or germanium as a dopant. In some embodiments, only two implantation processes are performed to form the barrier region(s). In some embodiments, only three implantation processes are performed to form the barrier region(s). In some embodiments, at least two implantation processes are performed to form the barrier region(s). In some embodiments, at least one of the barrier regions requires fewer implantation processes than the other barrier region(s). In some embodiments, at least one of the barrier regions requires one or more fewer implantation processes than the other barrier region(s).In some embodiments, the implantation processes are performed with one or more of the same or different dopants. In some embodiments, the implantation processes are performed with dopants of progressively smaller radii. In some embodiments, the implantation processes are performed with one or more dopants of a similar or substantially similar atomic radius.

[0049] In some embodiments, a method of forming a semiconductor device comprises the steps of: forming a semiconductor layer over a substrate, the semiconductor layer having a first portion and a second portion; implanting one or more dopants into the first portion; forming a metal-containing layer over the semiconductor layer; and forming a metal silicide layer over the semiconductor layer, wherein a thickness of the metal silicide layer over the first portion is less than a thickness of the metal silicide layer over the second portion, or no metal silicide layer is formed on the first portion. In some embodiments, different dopants are implanted into the first portion. In some embodiments, the different dopants are implanted separately. In some embodiments, the dopants comprise one or more atoms. In some embodiments, the atoms are the same or different from one another.

[0050] Embodiments of mechanisms for forming a semiconductor device according to the invention, as described above, form a barrier region in an upper portion of the semiconductor element, wherein the barrier region contains first dopants and second dopants with a smaller atomic radius than that of the first dopants. The first dopants and second dopants can block or reduce the diffusion of metal atoms during a silicide process, thereby preventing the formation of metal silicides on (or in) the semiconductor element.

[0051] According to some embodiments, a semiconductor device is provided. The semiconductor device comprises a gate stack on a semiconductor substrate. The semiconductor device further comprises a source region and a drain region in the semiconductor substrate and adjacent to the gate stack. The semiconductor device further comprises a resistor on the semiconductor substrate, wherein the resistor includes a silicon material. The semiconductor device comprises a metal silicide layer on at least one of the following regions or stacks: source region, drain region, and gate stack. The semiconductor device also includes a barrier region in an upper portion of the resistor to block or reduce the formation of a metal silicide layer on the resistor, wherein the barrier region comprises first dopants and second dopants having a smaller atomic radius than that of the first dopants.

[0052] According to some embodiments, a semiconductor device is provided. The semiconductor device comprises a gate stack on a semiconductor substrate. The semiconductor device also comprises a source region and a drain region in the semiconductor substrate and adjacent to the gate stack. The semiconductor device further comprises a semiconductor element on the semiconductor substrate, wherein the semiconductor element comprises a silicon material. The semiconductor device comprises a metal silicide layer on at least one of the following regions or stacks: source region, drain region, and gate stack. The semiconductor device also comprises a barrier region in an upper part of the semiconductor element to block or reduce the formation of a metal silicide layer on the semiconductor element. The barrier region comprises first dopants and second dopants having a smaller atomic radius than that of the first dopants.

[0053] According to some embodiments, a method of manufacturing a semiconductor device is provided. The method includes forming a gate stack and a semiconductor element on a semiconductor substrate, wherein the semiconductor element comprises a silicon material. The method further includes forming a source region and a drain region in the semiconductor substrate and adjacent to the gate stack. The method includes forming a mask layer covering the gate stack, the source region, and the drain region. The method also includes performing a first implantation process to implant first dopants into an upper portion of the semiconductor element. The method includes performing a second implantation process to implant second dopants into the upper portion to form a barrier region in the upper portion after the first implantation process.The barrier region comprises the first dopants and the second dopants with a smaller atomic radius than that of the first dopants. The method includes removing the mask layer and forming a metal silicide layer on at least one of the following regions or stacks: source region, drain region, and gate stack.

Claims

[1] A semiconductor device comprising: a gate stack (130) on a semiconductor substrate (110); a source region (150) and a drain region (150) in the semiconductor substrate (110) and adjacent to the gate stack (130); a resistor (160) on the semiconductor substrate (110), the resistor (160) comprising a silicon material; a metal silicide layer (180) on at least one of the following regions or stacks: source region (150), drain region (150) and gate stack (130); and a first barrier region (230a) in an upper part of the resistor (160) to block or reduce the formation of the metal silicide layer (180) on the resistor (160), the first barrier region (230a) comprising first dopants and second dopants having a smaller atomic radius than that of the first dopants, further comprising: an isolation structure (120) in the semiconductor substrate (110), wherein the resistor (160) is arranged above the isolation structure (120), the semiconductor device further comprising: a second barrier region (230b) in an upper part of the isolation structure (120), wherein the second barrier region (230b) comprises third dopants and fourth dopants, wherein the third dopants and the first dopants are the same, and wherein the fourth dopants and the second dopants are the same, wherein the second blocking region (230b) is arranged next to the resistor (160) still comprehensive: a third barrier region (230c) in an upper part of the semiconductor substrate (110) and adjacent to the isolation structure (120), wherein the third barrier region (230c) comprises fifth dopants and sixth dopants, wherein the fifth dopants and the first dopants are the same, and wherein the sixth dopants and the second dopants are the same, wherein the first dopants and second dopants prevent the metal atoms from contacting or reacting with the resistor (160), the isolation structure (120) and the semiconductor substrate (110) in and / or below the barrier regions (230a, 230b, 230c). [2] A semiconductor device according to claim 1, wherein the first dopants comprise germanium and the second dopants comprise carbon. [3] A semiconductor device according to claim 2, wherein a carbon concentration in the first barrier region (230a) is in a range of about 1E13 cm -3 up to about 1E16 cm -3 lies. [4] A semiconductor device according to claim 2, wherein a germanium concentration of the first barrier region (230a) is in a range of about 1E13 cm -3 up to about 1E16 cm -3 lies. [5] A semiconductor device according to claim 1, wherein the third barrier region (230c) is disposed adjacent to the metal silicide layer (180). [6] The semiconductor device according to claim 1, wherein a doping depth of the first barrier region (230a) is in a range of about 0.1 to about 20. [7] Semiconductor device comprising: a gate stack (130) on a semiconductor substrate (110); a source region (150) and a drain region (150) in the semiconductor substrate (110) and adjacent to the gate stack (130); a semiconductor element (160) on the semiconductor substrate (110), the semiconductor element (160) comprising a silicon material; a metal silicide layer (180) on at least one of the following regions or stacks: source region (150), drain region (150) and gate stack (130); and a barrier region (230a) in an upper part of the semiconductor element (160) for blocking or reducing the formation of the metal silicide layer (180) on the semiconductor element (160), the barrier region (230a) comprising first dopants and second dopants having a smaller atomic radius than that of the first dopants, further comprising: an isolation structure (120) in the semiconductor substrate (110), wherein the semiconductor element (160) is arranged above the isolation structure (120), the semiconductor device further comprising: a second barrier region (230b) in an upper part of the isolation structure (120), the second barrier region comprising third dopants and fourth dopants, the third dopants and the first dopants being the same, and the fourth dopants and the second dopants being the same, wherein the second blocking region (230b) is arranged next to the semiconductor element (160) still comprehensive: a third barrier region (230c) in an upper part of the semiconductor substrate (110) and adjacent to the isolation structure (120), wherein the third barrier region (230c) comprises fifth dopants and sixth dopants, wherein the fifth dopants and the first dopants are the same, and wherein the sixth dopants and the second dopants are the same, wherein the first dopants and second dopants prevent the metal atoms from contacting or reacting with the semiconductor element (160), the insulation structure (120) and the semiconductor substrate (110) in and / or below the barrier regions. [8] A semiconductor device according to claim 7, wherein the first dopants comprise germanium and the second dopants comprise carbon. [9] A semiconductor device according to claim 8, wherein a carbon concentration of the barrier region is in a range of about 1E13 cm -3 up to about 1E16 cm -3 lies. [10] A semiconductor device according to claim 8, wherein a germanium concentration of the barrier region is in a range of about 1E13 cm -3 up to about 1E16 cm -3 lies. [11] A method of forming a semiconductor device, comprising: Forming a gate stack (130) and a semiconductor element (160) on a semiconductor substrate (110), wherein the semiconductor element (160) comprises a silicon material; Forming an isolation structure (120) in the semiconductor substrate (110) before the semiconductor element (160) is formed, wherein the semiconductor element (160) is formed on the isolation structure (120); Forming a source region (150) and a drain region (150) in the semiconductor substrate (110) adjacent to the gate stack (130); Forming a mask layer (220) covering the gate stack (130), the source region (150) and the drain region (150); Performing at least one implantation process to implant first and second dopants into an upper part of the semiconductor element (160), the isolation structure (120) and the semiconductor substrate (110); to form a first barrier region in the upper part of the semiconductor element (160), a second barrier region in the upper region of the insulation structure (120) and in upper regions of the semiconductor substrate (110) which are adjacent to the insulation structure (120), wherein the barrier regions comprise first dopants and second dopants having a smaller atomic radius than that of the first dopants; Removing the mask layer (220); and Forming a metal silicide layer (180) on at least one of the following regions or stacks: source region (150), drain region (150) and gate stack (130), wherein the barrier regions (230a, 230b, 230c) suppress the formation of metal silicides in the semiconductor element (160), the insulation structure (120) and the semiconductor substrate (110) in and / or under the barrier regions (230a, 230b, 230c). [12] A method of forming a semiconductor device according to claim 11, wherein the first implantation process comprises a germanium implantation process, and wherein the second implantation process comprises a carbon implantation process, wherein the first dopants comprise germanium and wherein the second dopants comprise carbon. [13] A method of forming a semiconductor device according to claim 11, further comprising: Forming a buffer layer (210) covering the semiconductor element (160), wherein the formation of the buffer layer (210) takes place before the first implantation process and the second implantation process. [14] A method of forming a semiconductor device according to claim 13, further comprising: Removing the buffer layer (210) which takes place after the first implantation process and the second implantation process. [15] A method of forming a semiconductor device according to claim 11, wherein the second barrier region (230b) comprises germanium and carbon.

Images