Method for manufacturing a large number of semiconductor chips

Abstract

Method for producing a plurality of semiconductor chips comprising the following steps: - providing a substrate (1), - applying a semiconductor layer sequence (2) to the substrate (1), - creating a plurality of recesses (6) in the semiconductor layer sequence (2) from the side of the semiconductor layer sequence (2) facing away from the substrate (1), - removing the substrate (1) from the semiconductor layer sequence (2), - thinning the semiconductor layer sequence (2) from the side facing the substrate (1) before removing the substrate (1), wherein the recesses (6) do not completely penetrate the semiconductor layer sequence (2) before thinning the semiconductor layer sequence (2) and the recesses (6) completely penetrate the semiconductor layer sequence (2) after thinning the semiconductor layer sequence (2).

Description

[0001] Publication WO 2010 / 036326 A1 describes a method for manufacturing a semiconductor chip as well as a radiation-emitting semiconductor chip.

[0002] One task to be solved is to specify a semiconductor chip that can be manufactured particularly cost-effectively.

[0003] Another task to be solved is to specify a method for manufacturing such a semiconductor chip.

[0004] A method for manufacturing a semiconductor chip, in particular a plurality of semiconductor chips, is described. The semiconductor chip can be, in particular, an optoelectronic semiconductor chip. It is possible that the semiconductor chip is a radiation-emitting semiconductor chip that emits electromagnetic radiation, for example, light, during operation.

[0005] According to at least one embodiment of the method, a substrate is first provided. The substrate can be a growth substrate onto which semiconductor layers of the semiconductor chips can be epitaxially deposited, for example. The substrate can, for instance, be formed at least partially with a metal, a glass, a ceramic, or a semiconductor material. In particular, the substrate can be a sapphire substrate containing or consisting of sapphire. Furthermore, the substrate can be a silicon substrate containing or consisting of silicon.

[0006] According to at least one embodiment of the method, a sequence of semiconductor layers is deposited onto the substrate. For example, the semiconductor layer sequence is epitaxially deposited onto the substrate. The semiconductor layer sequence can comprise a first region, which is, for example, n-doped. The semiconductor layer sequence can further comprise an active region in which, for example, electromagnetic radiation is generated during operation. Furthermore, the semiconductor layer sequence can comprise a second region, which is, for example, p-doped.

[0007] According to at least one embodiment of the method for manufacturing a plurality of semiconductor chips, a plurality of recesses are created in the semiconductor layer sequence in a subsequent process step. The recesses in the semiconductor layer sequence can be created, for example, by mechanical and / or chemical material removal. In particular, it is possible for the recesses in the semiconductor layer sequence to be created by etching, for example, dry chemical etching.

[0008] The recesses are created, in particular, from the side of the semiconductor layer sequence facing away from the substrate. That is, the recesses extend from the side of the semiconductor layer sequence facing away from the substrate towards the substrate.

[0009] According to at least one embodiment of the method, the substrate is detached from the semiconductor layer sequence in a subsequent process step. This detachment can be achieved, for example, by a laser lifting process, such as laser lift-off. Furthermore, it is possible to detach the substrate using mechanical and / or chemical processes such as polishing and / or etching.

[0010] According to at least one embodiment of the method, in a further process step, the semiconductor layer sequence is thinned from the side facing the substrate before the substrate is detached. That is, the thickness of the semiconductor layer sequence is reduced. The thickness of the semiconductor layer sequence is reduced, for example, in a vertical direction parallel to the growth direction or the stacking direction of the semiconductor layer sequence. The thinning of the semiconductor layer sequence need not be uniform; rather, the semiconductor layer sequence can be structured, in particular roughened, during the thinning process, so that a rough outer surface of the semiconductor layer sequence is created on the side facing the substrate before the substrate is detached.

[0011] Thinning of the semiconductor layer sequence can be achieved through mechanical and / or chemical processes. For example, if the semiconductor layer sequence is based on a nitride compound semiconductor material, such as GaN, thinning can be accomplished by etching the semiconductor layer sequence with KOH.

[0012] According to at least one embodiment of the method for manufacturing a plurality of semiconductor chips, the method comprises the following steps: – Providing a substrate, – Deposition of a sequence of semiconductor layers onto the substrate, – Creating a large number of recesses in the semiconductor layer sequence from the side of the semiconductor layer sequence facing away from the substrate, – Detachment of the substrate from the semiconductor layer sequence, – Thinning of the semiconductor layer sequence from the side facing the substrate before the substrate was detached.

[0013] The procedure can be carried out in the specified order.

[0014] According to at least one embodiment of the method, the recesses do not completely penetrate the semiconductor layer sequence before the thinning of the semiconductor layer sequence, and the recesses do completely penetrate the semiconductor layer sequence after the thinning of the semiconductor layer sequence. That is, at least a large proportion of the recesses, in particular all of the recesses, are only introduced into the semiconductor layer sequence to such a depth that the semiconductor layer sequence is not completely penetrated by the recesses at any point. In this way, for example, between the deepest point of the recesses, measured from the side of the semiconductor layer sequence facing away from the substrate, a residue of the semiconductor layer sequence material remains between the substrate and the deepest point of the recesses, in which the semiconductor layer sequence has a minimum thickness.

[0015] Preferably, this minimum thickness is at least 0.1 µm and at most 1.0 µm, particularly 0.5 µm. Such a residual thickness of the semiconductor layer sequence material has proven optimal with regard to good cutability of the semiconductor layer sequence, wherein the residual thickness is large enough to prevent damage to the substrate during the separation process.

[0016] In other words, the recesses are not made so deep that the substrate is exposed at their base. The semiconductor layer sequence is removed from the side facing away from the substrate only to a depth of the recess such that a residual thickness of the semiconductor layer sequence remains between the deepest point of the recesses and the substrate. After the thinning process, the recesses completely penetrate the semiconductor layer sequence. That is, after the thinning process, the semiconductor layer sequence is isolated, with the isolated areas of the semiconductor layer sequence being laterally bounded by the recesses and any material introduced into the recesses.

[0017] The method described here is based, among other things, on the understanding that making the recesses so deep that the substrate is exposed at their base damages the substrate to such an extent that any potential reuse of the substrate would require complex procedures. Alternatively, the recesses, which are particularly useful for separating the semiconductor layer sequence into individual semiconductor chips, could be made from the side originally facing the substrate, i.e., after the substrate has been removed. In this case, however, wet chemical processes at relatively high temperatures are necessary, requiring, in particular, the use of photographic techniques for structuring the chip grid. This is also disadvantageous compared to the method described here, in which the recesses are created from the side facing away from the substrate to such a depth that a residual thickness of the semiconductor layer sequence remains..

[0018] According to at least one embodiment of the method, the recesses taper towards the substrate before the substrate is detached. That is, in a cross-sectional view transverse or perpendicular to the vertical direction, the recesses have, for example, inclined inner surfaces that converge towards the substrate, so that the recesses have a smaller extent closer to the substrate than further away from it. Thus, a region of the semiconductor layer sequence bounded by recesses widens towards the substrate.

[0019] According to at least one embodiment of the method, the recesses are generated along a chip grid. That is, the recesses are generated, for example, along a plurality of parallel lines and along a plurality of lines perpendicular to these parallel lines in the principal plane of the semiconductor layer sequence, with the spacing between adjacent parallel lines corresponding to the chip grid. The recesses then serve, in particular, to laterally delimit the finished semiconductor chips; that is, the semiconductor layer sequence and other components of the semiconductor chips are separated along the recesses. The recesses are therefore not vias for electrically connecting an n- or p-type region of the semiconductor chips to be manufactured, but rather material removals that serve to separate the semiconductor layer sequence.

[0020] According to at least one embodiment of the method, the thinning of the semiconductor layer sequence is achieved by roughening the semiconductor layer sequence by creating roughening on the side of the semiconductor layer sequence originally facing the substrate.

[0021] Since thinning the semiconductor layer sequence removes the remaining material between the side of the semiconductor layer sequence originally facing the substrate and the recess, the creation of the roughened semiconductor layer sequence and the singulation of the semiconductor layer sequence can be combined into a single process step. Thinning thus creates roughened areas that increase the probability of electromagnetic radiation emitting from the semiconductor chip at the radiation-exit side of the optoelectronic semiconductor chips being manufactured, and removes the remaining material of the semiconductor layer sequence that has not yet been penetrated by the recesses. Creating the roughened areas, and thus thinning, can be achieved, for example, by KOH etching without the use of a mask technique, making this step particularly simple and cost-effective.

[0022] According to at least one embodiment of the method, after the plurality of recesses has been created, an insulating layer sequence is produced which covers the semiconductor layer sequence on its surfaces facing the recesses. The insulating layer sequence is formed by at least one layer. At least one layer of the insulating layer sequence is electrically insulating. The insulating layer sequence can, for example, on its side facing the semiconductor layer sequence, and in particular directly adjacent to the semiconductor layer sequence, comprise a layer formed with or consisting of silicon nitride. A silicon dioxide layer can follow this layer on the side of the silicon nitride layer facing away from the semiconductor layer sequence. Alternatively or additionally, the insulating layer sequence can comprise at least one reflective layer formed, for example, with a metal such as aluminum, rhodium, and / or silver.Alternatively or additionally, it is also possible that the sequence of insulating layers is designed, at least in some places, as a dielectric mirror or Bragg mirror, for example as a sequence of layers with high and low refractive indices.

[0023] According to at least one embodiment of the method, the insulating layer sequence is exposed in certain areas during the thinning of the semiconductor layer sequence. This means that, after thinning the semiconductor layer sequence, the insulating layer sequence can form an outer surface of the semiconductor chips produced by the method in certain areas. In this case, the insulating layer sequence preferably comprises a layer formed with silicon nitride, which is not, or only minimally, affected by, for example, KOH etching.

[0024] According to at least one embodiment of the method, a support is created on the side of the semiconductor layer sequence facing away from the substrate before the substrate is removed. The support serves to mechanically support the semiconductor layer sequence after the substrate has been removed. Furthermore, the support can be a terminal carrier via which the finished semiconductor chips can be electrically contacted. For this purpose, according to at least one embodiment of the method, the support can comprise a plurality of first contacts, a plurality of second contacts, and a molded body, wherein the molded body laterally surrounds the contacts. In other words, the contacts are, for example, embedded in the molded body. The molded body can be formed with an electrically insulating material such as a plastic, a silicone, and / or an epoxy resin.The contacts can be created, for example, electroplated in recesses of the molded part.

[0025] According to at least one embodiment of the method, the shaped body extends into the plurality of recesses and fills them, at least partially. This means that, for example, after the formation of the insulating layer sequence in the recesses, material from the shaped body is introduced into the recesses during the shaping process. The recesses can then be conformally covered by the insulating layer sequence on their side facing the semiconductor body and otherwise filled with material from the shaped body. This has the advantage that the shaped body, and thus a part of the support, is particularly firmly bonded to the semiconductor layer sequence, since the shaped body, and thus a part of the support, projects into the semiconductor layer sequence in the area of ​​the recesses. In other words, the support is then particularly well anchored in the semiconductor layer sequence.

[0026] According to at least one embodiment of the method, the semiconductor chips are separated into a plurality along parting lines, wherein at least some of the parting lines extend through a recess and the mold body, and each separated semiconductor chip is assigned at least one first contact and at least one second contact. As already explained above, the recesses can be formed, in particular, along chip grids and thus serve to separate the semiconductor layer sequence during the separation into individual semiconductor chips. For example, this separation can be carried out by sawing or laser cutting along the recesses, through the recesses and the substrate, so that after separation, each of the semiconductor chips comprises a portion of the semiconductor layer sequence, which is bounded, for example, on four sides by the recesses.

[0027] Each semiconductor chip is assigned at least one first contact and at least one second contact, and it is particularly possible for each semiconductor chip to have exactly one first contact and exactly one second contact configured for n-side and p-side contacting, respectively. This results in a surface-mountable semiconductor chip.

[0028] The method described here is characterized, among other things, by the good reusability of the growth substrate, since the semiconductor layer sequence is not completely severed by creating the recesses in a first step. This prevents damage to the growth substrate during recess formation, and complete severing of the semiconductor layer sequence only occurs in a second step, the thinning of the semiconductor layer sequence, which is carried out after the substrate has been removed. This second step, which is performed, for example, from the n-side of the semiconductor layer sequence, does not require the creation of an etching mask, so this step can also be carried out particularly cost-effectively.

[0029] Furthermore, a radiation-emitting semiconductor chip is disclosed. The radiation-emitting semiconductor chip can be manufactured, in particular, by a method described herein, such that all features disclosed for the semiconductor chip are also disclosed for the method and vice versa.

[0030] The radiation-emitting semiconductor chip is in particular a surface-mountable semiconductor chip in which contacts for n- and p-side contacting are accessible on a bottom side of the semiconductor chip.

[0031] According to at least one embodiment of the radiation-emitting semiconductor chip, the semiconductor chip comprises a sequence of semiconductor layers with an active region in which electromagnetic radiation is generated during operation of the semiconductor chip, and a radiation-emission side from which the electromagnetic radiation generated in the active region is at least partially emitted. A side face of the semiconductor layer sequence, in the direction of the radiation-emission side, first forms a first angle with a vertical direction, the magnitude of which is greater than 90°, and further along the side face in the direction of the radiation-emission side, forms a second angle with the vertical direction, the magnitude of which is less than 90°. The vertical direction is, for example, a direction that is parallel to the growth direction and / or the stacking direction of the semiconductor layer sequence.In other words, the semiconductor body of the radiation-emitting semiconductor chip initially widens towards the radiation-emitting side and then tapers towards the radiation-emitting side.

[0032] Such a design of the semiconductor layer sequence can be achieved in particular by the two-stage separation process described here, in which the recesses in the semiconductor layer sequence, along which the semiconductor layer sequence is separated, do not initially extend completely through the semiconductor layer sequence. If, in this case, the recesses are designed to taper towards the substrate of the semiconductor layer sequence, the semiconductor layer sequence in the finished semiconductor chip exhibits a widening shape in this area towards the substrate and thus towards the radiation-emitting side. Complete separation of the semiconductor layer sequence then takes place in a second step, the thinning of the semiconductor layer sequence. Here, the portion of the semiconductor layer sequence is created that then tapers towards the originally existing substrate and thus towards the radiation-emitting side.

[0033] The side surface of the semiconductor layer sequence is the outer surface of the semiconductor layer sequence, which connects the top surface of the semiconductor layer sequence on the radiation-emitting side with the bottom surface of the semiconductor layer sequence on the opposite side. The outer surface borders the recess over a large area or completely, and thus, for example, an insulating layer sequence that was created on the inner surface of the recess during the manufacturing process.

[0034] According to at least one embodiment of the radiation-emitting semiconductor chip, the side surface exhibits the second, smaller angle in the area of ​​a roughening of the semiconductor layer sequence. That is, in the area where the semiconductor layer sequence has been thinned, for example by roughening, the semiconductor layer sequence in the finished radiation-emitting semiconductor chip exhibits the second, smaller angle, so that the semiconductor layer sequence tapers in this area towards the radiation-emitting surface.

[0035] According to at least one embodiment of the radiation-emitting semiconductor chip, the side surface is at least partially covered by an insulating layer sequence which, on its side facing away from the semiconductor layer sequence, borders a molded body and / or a metal layer sequence. That is, the side surface is partially or completely covered by the insulating layer sequence, which was applied to the inside of the recesses during the manufacturing process. Depending on the material used to fill the recesses, the insulating layer sequence then borders, for example, the molded body of the semiconductor chip substrate and / or a metal layer sequence, which may, for example, be a metal layer sequence that serves to mechanically reinforce the semiconductor layer sequence.

[0036] In particular, it is possible that the insulating layer sequence and / or the shaped body and / or the metal layer sequence are designed to reflect the electromagnetic radiation generated in the active region. In this case, the shape of the side surface as described here proves to be particularly advantageous. The material bounding the side surface forms a reflector in the area where the semiconductor body widens towards the radiation-emitting side, directing incident electromagnetic radiation towards that side. In the upper region of the semiconductor layer sequence, near the radiation-emitting side, the semiconductor body then tapers in places towards the radiation-emitting side, reducing the probability of total internal reflection at radiation emission and thus increasing the intensity of the radiation emitted by the semiconductor chip during operation.

[0037] According to at least one embodiment of the radiation-emitting semiconductor chip, the semiconductor layer sequence extends beyond the insulating layer sequence, at least in the area of ​​the roughening, in the vertical direction. This means that the semiconductor layer sequence extends vertically beyond the insulating layer sequence on the radiation-emitting side, and thus also beyond, for example, the shaped body and / or the metal layer sequence. This allows the electromagnetic radiation to exit the radiation-emitting side, for example through the roughening, with particularly little obstruction, which further increases the intensity of the emitted electromagnetic radiation.

[0038] The following section explains in more detail the method and semiconductor chip described here, using exemplary embodiments and the associated figures.

[0039] In connection with the Fig. 1A, Fig. 1B, Fig. 1C, Fig. 1D, Fig. 1E, Fig. 1F is an embodiment of a method described here, which is explained in more detail.

[0040] In connection with the Fig. 2A, Fig. 2B, Fig. Section 2C provides a more detailed explanation of exemplary embodiments of the radiation-emitting semiconductor chips described here.

[0041] Identical, similar, or similarly effective elements in the figures are marked with the same reference symbols. The figures and the relative sizes of the elements depicted within them are not to be considered to scale. Rather, individual elements may be exaggerated for clarity and / or to improve representation.

[0042] The Fig. 1A to Fig. 1F will explain an exemplary embodiment of a method described here using schematic sectional views.

[0043] In connection with the Fig. Figure 1A schematically shows that first a growth substrate 1 is provided. Regarding the growth substrate 1 It could, for example, be a sapphire substrate. On the growth substrate 1 a semiconductor layer sequence 2 , for example, epitaxially deposited. The semiconductor layer sequence 2 based, for example, on GaN. The semiconductor layer sequence 2 includes a first area 21 , who, for example, is trained in n-conducting, has an active area 22 , in which electromagnetic radiation can be generated during operation, and a second area 23 , which is, for example, designed to be p-conducting.

[0044] At the substrate 1 far side of the semiconductor layer sequence 2 can a first metal layer sequence 3a sequence of metal layers must be formed, comprising at least one layer formed with or containing a metal. For example, the first sequence of metal layers can be 3 contains a reflective metal such as silver.

[0045] In the next procedural step, which is also related to the Fig. As described in 1A, vias are used. 5 and exceptions 6 generated. The vias 5 extend through the first sequence of metal layers 3 , the second area 23 , the active area 22 in the first area 21 In the finished semiconductor chip, these vias serve a purpose 5 for example, for n-sided contacting of the semiconductor chip.

[0046] The cutouts 6 extend into the first area 21 , however, the exceptions extend 6deeper into the first area 21 as the vias 5 and the exceptions 6 are wider in the depicted cross-section of the semiconductor layer sequence. The depth of the recesses 6 For example, the minimum diameter is at least 4 µm and at most 5 µm. The minimum width of the recesses is, for example, at least 20 µm and at most 30 µm, in particular 25 µm.

[0047] The cutouts 6 penetrating the semiconductor layer sequence 2 not completely, but a region of the semiconductor layer sequence with residual thickness D remains, which contains the recesses. 6 from the substrate 1 spaced apart.

[0048] In a further process step, the insulation layer sequence is applied to the side facing away from the substrate. 4 formed, which can be manufactured, for example, using ALD and / or CVD processes. The insulation layer sequence 4This includes, for example, a silicon nitride layer that is directly attached to the first sequence of metal layers. 3 and the semiconductor body 2 borders. Furthermore, the sequence of insulation layers can 4 further semiconductor layers and / or metallic layers and may, for example, be reflective. The insulating layer sequence 4 shows initial openings 41 in the area of ​​vias 5 on, in which the first area 21 the semiconductor layer sequence 2 is accessible. Furthermore, the insulation layer sequence exhibits 4 second openings 42 on, in which the first sequence of metal layers 3 freely accessible. These openings 41 , 42 They serve in the finished semiconductor chip for n- or p-side contacting of the semiconductor chip.

[0049] In a further procedural step, Fig. 1B, a second metal layer sequence will be applied. 7 on the insulation layer sequence 4 applied. The metal layer sequence 7 contacts the first metal layer sequence 3 in the area of ​​the second vias 42 and forms second contacts there 72 In the area of ​​vias 5 contacts the second metal layer sequence 7 the first area 21 the semiconductor layer sequence 2 for n-sided contacting at the first contacts 71 .

[0050] The second metal layer sequence 7 can have a mechanically reinforcing function for the semiconductor body. Furthermore, the second metal layer sequence can 7 at least one layer that serves as a seed layer for creating contacts in the subsequent process. The second metal layer sequence 7It can be formed, for example, with metals such as nickel and / or copper.

[0051] In the Fig. Figure 1B shows that the cutouts 6 either with material from the second metal layer sequence 7 can be filled or remain free of the material of the second metal layer sequence.

[0052] In the next procedural step, Fig. 1C, the carrier 89 This is achieved, for example, by creating the shaped body. 8 produced on the underside facing away from the substrate, whereby the shaped body 8 in some places directly adjacent to the first sequence of metal layers 3 and the second metal layer sequence 7 borders. The shaped body 8 is formed with an electrically insulating material, for example an epoxy resin.

[0053] In the mold body 8 Are recesses created or left open that allow for initial contact with the material? 91and second contacts 92 For example, they can be electroplated. In this process, the second metal layer sequence can be created. 7 at least in some places as a seedbed for contacts 91 , 92 serve this purpose. It is particularly useful when applying the molded part. 8 It is possible that this also extends into the recesses. 6 is introduced so that it is bonded to the material of the molded body. 8 are filled.

[0054] In connection with the Fig. In the process step described in 1D, the growth substrate is 1 for example, by a laser lift-off process from the semiconductor layer sequence 2 replaced.

[0055] In the next procedural step, Fig. 1E, a thinning of the semiconductor layer sequence occurs 2 by KOH etching, which causes the substrate to be damaged 89 roughened surface on the opposite side 24 the semiconductor layer sequence 2to be generated. Furthermore, the semiconductor layer sequence is generated in the process. 2 thinned to such an extent that the recesses 6 and with them, for example, the insulation layer 4 and / or the molded body 8 and / or the second metal layer sequence 7 be exposed.

[0056] In a final procedural step, Fig. 1F, separation into individual semiconductor chips occurs along the dividing lines. 101 , which are characterized by the cutouts and the support 89 extend through it. 2 , metal layer sequences 3 , 7 and carriers 89 on an auxiliary carrier 100 be applied.

[0057] In the Fig. 1A to Fig. 1F does not show that the recesses preferably point towards the support. 89 tapering away so that the semiconductor layer sequence 2towards the roughened areas 24 and thus in the direction of the radiation exit side 2a expands.

[0058] This is explained in detail in the Fig. 2A to Fig. Figure 2C shows cross-sectional views of exemplary embodiments of a radiation-emitting semiconductor chip described here, which has the semiconductor layer sequence. 2 includes the semiconductor layer sequence. 2 includes the active area 22 , in which electromagnetic radiation is generated during the operation of the semiconductor chip, which is emitted at the radiation exit side 2a , which the roughening 24 includes, at least partially exits. The semiconductor layer sequence also has a side surface. 2c on, which in the direction of the radiation exit side 2a, thus initially enclosing a first angle α with the vertical direction R in the vertical direction, the magnitude of which is greater than 90°, and in the further course of the side surface in the direction of the radiation exit side 2a encloses an angle β with the vertical direction R, the magnitude of which is less than 90°.

[0059] In the exemplary embodiment of the Fig. 2A shows that the insulation layer sequence 4 when thinning the semiconductor layer sequence 2 is not attacked, for example because it is equipped with a SiN x is formed, which represents an etch stop for KOH etching. That is, the insulating layer sequence 4 remains unchanged and the differently oriented flanks of the semiconductor layer sequence 2 collide at the contact point 102 In this embodiment, the semiconductor layer sequence is the overall height. 2the insulation layer sequence and the filling of the recess 6 at least in the area of ​​roughening 24 .

[0060] This also applies to the exemplary embodiment of the Fig. 2B the case where the insulation layer sequence 4 The thinning of the semiconductor layer sequence partially removes the insulating layer, exposing the underlying materials. This can lead to a retraction of the insulating layer sequence. 4 come, so that between the filling of the recess 6 , for example the shaped body 8 or second metal layer sequence 7 and the semiconductor body 2 a gap is present.

[0061] In the exemplary embodiment of the Fig. 2C, the semiconductor layer sequence is located at its radiation emission surface. 2a completely below the filling of the recess and the sequence of insulation layers 4That is, in this embodiment, the thinning of the semiconductor layer sequence was 2 The cavity is carried out particularly deeply. In this way, the filling of the recess can, for example, provide mechanical protection for the semiconductor layer sequence. 2 However, the optical properties of such a radiation-emitting semiconductor chip are degraded.

[0062] The invention is not limited to the description provided by means of the exemplary embodiments. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes every combination of features in the claims, even if that feature or combination itself is not explicitly stated in the claims or exemplary embodiments. Reference symbol list 1 substrate 2 Semiconductor layer sequence 2a Radiation exit side 2c side surface 21 first area 22 active area 23 second area 24 Roughening 3 first metal layer sequence 4 Insulation layer sequence 41 first opening 42 second opening 5. Through-hole plating 6 Exclusion 7 second metal layer sequence 71 first contact 72 second contact 8 Molded parts 89 carriers 91 first contact 92 second contact 100 aid workers 101 Dividing line 102 Contact point 103 Guideline α first angle β second angle Minimum thickness R vertical direction QUOTES INCLUDED IN THE DESCRIPTION

[0063] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0064] WO 2010 / 036326 A1

[0001]

Claims

[1] Method for manufacturing a large number of semiconductor chips comprising the following steps: – Providing a substrate ( 1 ), – Deposition of a semiconductor layer sequence ( 2 ) on the substrate ( 1 ), – Creating a large number of cutouts ( 6 ) in the semiconductor layer sequence ( 2 ) from the substrate ( 1 ) opposite side of the semiconductor layer sequence ( 2 ), – Detachment of the substrate ( 1 ) from the semiconductor layer sequence ( 2 ), – Thinness of the semiconductor layer sequence ( 2 ) from the substrate ( 1 ) before the substrate detaches ( 1 ) facing side. [2] Method according to the preceding claim, wherein the recesses ( 6 ) the semiconductor layer sequence ( 2 ) before the thinning of the semiconductor layer sequence ( 2) each do not penetrate completely and the recesses ( 6 ) according to the thinness of the semiconductor layer sequence ( 2 ) each penetrate completely. [3] Method according to one of the preceding claims, wherein before thinning the semiconductor layer sequence ( 2 ) between the lowest point of the recesses ( 6 ) and the substrate ( 1 ) a residue of the material of the semiconductor layer sequence ( 2 ) remains, so that the semiconductor layer sequence ( 2 ) has a minimum thickness (D). [4] Method according to any of the preceding claims, wherein the recesses ( 6 ) before the substrate detaches ( 1 ) in the direction of the substrate ( 1 rejuvenate. [5] Method according to any of the preceding claims, wherein the recesses ( 6 ) are generated along a chip grid. [6] Method according to any one of the preceding claims, wherein the thinning of the semiconductor layer sequence ( 2 ) by roughening the semiconductor layer sequence ( 2 ) is achieved through roughening ( 24 ) at the substrate ( 1 ) originally facing side of the semiconductor layer sequence ( 2 ) are generated. [7] Method according to any of the preceding claims, wherein after producing the plurality of recesses ( 6 ) an insulation layer sequence ( 4 ) is generated, which is the semiconductor layer sequence ( 2 ) at their the openings ( 6 ) facing surfaces covered. [8] Method according to the preceding claim, wherein the insulation layer sequence ( 4 ) in the thinness of the semiconductor layer sequence ( 2 ) is partially exposed. [9] Method according to any of the preceding claims, wherein before the substrate is detached ( 1 ) a carrier ( 89) at the substrate ( 1 ) opposite side of the semiconductor layer sequence ( 2 ) is generated, whereby the carrier has a multitude of first contacts ( 91 ), a large number of second contacts ( 92 ) and a shaped body ( 8 ) includes the shaped body ( 8 ) the contacts ( 91 , 92 ) surrounds the sides. [10] Method according to the preceding claim, wherein the molded body ( 8 ) into the multitude of recesses ( 6 ) extends and fills it at least partially. [11] Method according to one of the two preceding claims, wherein singulation into a plurality of semiconductor chips along separating lines ( 101 ) is done, whereby at least some of the dividing lines ( 101 ) by a cutout ( 6 ) and the shaped body ( 8 ) extend, with each individual semiconductor chip having at least one initial contact (91 ) and at least one second contact ( 92 ) is assigned. [12] Radiation-emitting semiconductor chip with a semiconductor layer sequence ( 2 ) encompassing an active area ( 22 ), in which electromagnetic radiation is generated during the operation of the semiconductor chip, and a radiation output side ( 2a ), in which the active area ( 22 ) generated electromagnetic radiation at least partially escapes, with one side surface ( 2c ) the semiconductor layer sequence ( 2 ) in the direction of the radiation exit side ( 2a ) initially encloses a first angle (α) with a vertical direction (R) whose magnitude is greater than 90°, and in the further course of the side surface ( 2c ) in the direction of the radiation exit side ( 2a ) encloses a second angle (β) with the vertical direction (R), the magnitude of which is less than 90°. [13] Radiation-emitting semiconductor chip according to the preceding claim, wherein the side surface ( 2c ) the second angle (β) in the area of ​​a roughening ( 24 ) the semiconductor layer sequence ( 2 ) exhibits. [14] Radiation-emitting semiconductor chip according to one of the two preceding claims, wherein the side surface ( 2c ) at least partially from a sequence of insulating layers ( 4 ) is covered, which at their semiconductor layer sequence ( 2 ) opposite side to a shaped body ( 8 ) and / or a sequence of metal layers ( 7 borders. [15] Radiation-emitting semiconductor chip according to one of the three preceding claims, wherein the semiconductor layer sequence ( 2 ) the insulation layer sequence ( 4 ) at least in the area of ​​roughening ( 24 ) in the vertical direction.

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