Semiconductor device and method for forming a semiconductor device
The semiconductor device's innovative gate structure with a non-perpendicular second trench design addresses dielectric failure by dispersing electric fields and improving mechanical stability, enhancing reliability and control over gate oxide thickness.
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- INFINEON TECH AUSTRIA AG
- Filing Date
- 2015-07-29
- Publication Date
- 2026-06-11
AI Technical Summary
Semiconductor devices face dielectric failure due to high electric fields and mechanical stresses, particularly at corners of the gate oxide, leading to performance trade-offs between thickness and reliability.
A semiconductor device design with a gate structure featuring a second trench within a first trench, forming a non-perpendicular angle with the semiconductor body, which disperses electric fields and improves mechanical stability by distributing expansion forces over a larger surface area.
The design gradually disperses electric fields, enhances gate oxide thickness control, and improves mechanical stability, reducing the susceptibility to dielectric failure and maintaining performance reliability.
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
TECHNICAL AREA
[0001] The present invention relates generally to semiconductor devices and corresponding formation methods, and in particular to the formation of a gate structure of a semiconductor device that is resistant to high electric fields and mechanical stresses. BACKGROUND
[0002] Semiconductor devices typically contain an electrically conductive gate electrode that is insulated from an adjacent semiconductor body by a gate oxide. During operation of the device, an electrical potential applied to the gate electrode develops across the gate oxide and controls the flow of electric current in a channel region of the semiconductor body.
[0003] Certain applications, such as power switching applications, require significant switching voltages that can cause device failure if not properly addressed. Over time, dielectric materials used to form gate oxides tend to fail when exposed to excessive electric fields. Therefore, the regions of the gate oxide where the electric fields are highest are the regions most susceptible to dielectric failure.
[0004] The problem of dielectric failure can be exacerbated by physical defects in the gate oxide. Some of these defects arise from mechanical stresses exerted on the gate oxide. For example, the high temperatures associated with device manufacturing and operation can lead to undesirable thermal expansion of the material adjacent to the gate oxide. This thermal expansion can deform the gate oxide sufficiently to reduce performance (e.g., through increased leakage currents) or it can cause complete device failure.
[0005] A process technique that addresses the problems described above involves establishing a minimum gate oxide thickness, which is strictly monitored during device fabrication. Gate oxide thickness plays a crucial role in device performance. Thickening the gate oxide reduces capacitance but increases the on-resistance of a device. The threshold voltage (V) t The on-resistance of a device is a function of the gate oxide thickness and the degree of doping of the semiconductor material in the channel region. Therefore, the only way to thicken a gate oxide and achieve a target threshold voltage is to decrease the degree of doping in the channel region, which in turn increases the on-resistance of the device. Thus, adjusting the gate oxide thickness of devices leads to trade-offs between performance and reliability.
[0006] US 2012 / 0061720A1 describes a power transistor with a field electrode arranged in a trench filled with a field oxide. Gate electrodes are arranged on opposite sides of this trench, with gate dielectrics interposed. In contrast, US 7211860B2 describes a semiconductor device in which a gate electrode is arranged in a trench. Along the length of the trench, the gate electrode transitions into a field electrode. CN 101866883A, on the other hand, deals with the fabrication of CMOS semiconductor devices, in which manual optical proximity correction is applied during the exposure of a lithography mask. SUMMARY
[0007] Against this background, a semiconductor device according to claim 1 is disclosed.
[0008] According to one embodiment, the semiconductor device comprises a semiconductor body with a first surface. A first trench is formed in the semiconductor body and includes a first and a second side wall, both extending vertically from the first surface, and a first trench bottom extending between the first and second side walls in a first lateral direction. A field dielectric is present and fills the first trench. A second trench is formed within the first trench in the field dielectric and includes an inner and an outer side wall. The first and second side walls of the first trench and the inner and outer side walls of the second trench extend along the semiconductor body in a second lateral direction, perpendicular to the first lateral direction and perpendicular to the vertical direction.The second trench contains a wide section adjacent to a narrow section in the second lateral direction. In the wide section, the inner and outer side walls run parallel to the first side wall in the second lateral direction. In the narrow section, one of the inner and outer side walls is not perpendicular to and not parallel to the first side wall in the second lateral direction. In the narrow section, the inner side wall is parallel to the first side wall in the second lateral direction, while the outer side wall runs away from the first side wall and towards the inner side wall in the second lateral direction.
[0009] Furthermore, a method for forming a semiconductor device according to claim 8 is disclosed.
[0010] According to one embodiment, the method comprises forming a first trench in a semiconductor body, wherein the first trench has a first and a second side wall, both extending vertically from a first surface of the semiconductor body, and a first trench bottom extending between the first and second side walls in a first lateral direction. The first trench is filled with a field dielectric up to the first surface. A second trench is formed within the first trench in the field dielectric, wherein the second trench has an inner and an outer side wall. The first and second side walls of the first trench and the inner and outer side walls of the second trench are configured to extend along the semiconductor body in a second lateral direction that is perpendicular to the first lateral direction and perpendicular to the vertical direction.Forming the second trench involves creating an expanded section adjacent to a narrow section in the second direction. The inner and outer sidewalls of the expanded section are parallel to the first sidewall in the second direction. The inner sidewall in the narrow section is parallel to the first sidewall in the second direction. The outer sidewall in the narrow section extends away from the first sidewall in the second direction. A first gate oxide is formed in the field dielectric within the second trench after its formation. A first gate electrode is formed in the second trench such that the first gate electrode in the expanded section is insulated from the semiconductor body only by the gate oxide, and the first gate electrode in the narrow section is insulated from the first sidewall by the field dielectric. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The elements are not necessarily to scale with respect to each other. Identical reference numerals denote corresponding, similar parts. Embodiments are shown in the drawings and described in detail below. Fig. 1, the Fig. 1A and Fig. 1B includes a semiconductor device with a gate that is formed in a trench such that the gate oxide forms a perpendicular angle with the trench side wall, according to one embodiment. Fig. 2, the Fig. 2A to 2C includes a semiconductor device with a gate trench in a field dielectric having a widened and a narrow section, wherein a side wall of the trench forms a non-perpendicular angle with a side wall of the semiconductor body, according to one embodiment. Fig. 3, the Fig. 3A to 3B includes a semiconductor device with a gate electrode and a gate oxide formed in the gate groove, according to one embodiment. Fig. Figure 4 represents an alternative configuration of the widened and narrow sections of the gate trench according to one embodiment. Fig. 5, the Fig. 5A to 5C includes a masking step that can be used to form a gate trench that is not perpendicular to a side wall of the semiconductor body, according to one embodiment. Fig. 6, the Fig. 6A to 6B includes a semiconductor device after masked etching of the field dielectric to form the gate trench, according to one embodiment. DETAILED DESCRIPTION
[0012] The embodiments described herein provide a semiconductor device with a gate oxide forming a non-perpendicular and non-parallel angle with the semiconductor body. The semiconductor device can be configured as a trench / gate device, in which the gate electrode is formed within a trench below a first surface of the semiconductor body. This arrangement can be provided by etching a first trench with first and second sidewalls in the first surface, filling the first trench with a field dielectric (i.e., by forming an interlayer dielectric in the trench) up to the first surface, etching a second trench in the field dielectric that exposes one of the first and second sidewalls, forming a gate oxide within the second trench along the exposed sidewall, and forming an electrically conductive gate electrode adjacent to the gate oxide in the second trench.The second trench tapers in such a way that it contains a wide section and a narrow section. From a top-down perspective of the first surface, the side walls of the second trench in the wide section are spaced apart and parallel to each other. In the narrow section, the side walls of the second trench converge. Therefore, the gate electrode and the gate dielectric, which are formed in the second trench, also exhibit a corresponding tapered geometry.
[0013] Favorably, the resulting gate oxide configuration gradually disperses the electric field within the gate oxide at the end of the gate structure. That is, the gradual tapering of the gate electrode and gate oxide at one end of the gate structure eliminates an abrupt corner of the oxide that would be prone to dielectric failure during device operation. Furthermore, the mechanical stability of the gate oxide is improved because expansion forces from the adjacent material are distributed over a larger surface area and across more than two planes. Additionally, the ability to control the gate oxide thickness is enhanced because the non-perpendicular angle of the second trench in the field is less susceptible to gate oxide thinning during oxidation than a perpendicular angle.
[0014] With reference to Fig. Figure 1 shows a semiconductor device 100. Fig. Figure 1A shows a top view of the component 100 over a first surface 102 of the semiconductor body 104, and Fig. Figure 1B shows a cross-sectional perspective of component 100 along line AA', which is in Fig. 1A is indicated.
[0015] The component of Fig. 1 contains a gate electrode 106, which is arranged in a first trench 108 below the first surface 102. The gate electrode can be formed in a second trench 110, which is formed within a field dielectric 112 in the first trench 108. The gate electrode 106 is electrically insulated from the semiconductor body 104 by a gate oxide 114. The semiconductor device of Fig. 1 can be designed as described with reference to Fig. Sections 14A to 14D of US patent application 13 / 307,465 by Blank are described, and are incorporated herein in their entirety by reference.
[0016] As seen in the top-down view from Fig. As shown in Figure 1A, one end 116 of the gate structure, which contains the gate electrode 106 and the gate oxide 114, forms a perpendicular angle with the side walls of the first trench 108. The geometry of the gate structure in Fig. This unfortunately makes the device 100 more susceptible to failure resulting from the highly concentrated electric fields. During operation of the device 100, the highest electrical gradient occurs at the corners of the gate oxide 114, including the corner at the end 116 of the gate structure. This means that the 90-degree corners of the gate oxide 114 represent a region of the device 100 that is most susceptible to dielectric failure. Furthermore, it is extremely difficult to control the thickness of the gate oxide 114 in this region. Due to phenomena such as the 2D (two-dimensional) and 3D (three-dimensional) oxidation effects, it is typically thinner at the corners of the first trench 108 than in the adjacent regions. As a result, the gate oxide 114 is weakened and more susceptible to electrical and / or electrothermal failure.
[0017] With reference to Fig. Figure 2 shows a semiconductor device 200 that excludes the 90-degree angle discussed above. Fig. 2A shows a top view of component 200. Fig. Figure 2B shows a cross-sectional view of component 200 along the cross-sectional line AA', which is in Fig. 2A is specified. Fig. Figure 2C shows a cross-sectional view of component 200 along the cross-sectional line BB', which is in Fig. 2A is specified. The planes AA' and BB' are parallel to each other and spaced apart.
[0018] The semiconductor device 200 is formed in a semiconductor body 202 with a first surface 204, which is vertically spaced from a second surface 206. The first and second surfaces 204, 206 can be parallel to each other.
[0019] The semiconductor device 200 comprises a first trench 208 with first and second sidewalls 210, 212 extending from the first surface 204 into the semiconductor body 202, and a trench floor 214 extending between the first and second sidewalls 210, 212. The three-dimensional geometry of the first trench 208 can be described in terms of a vertical direction (V), a first side direction (L1), and a second side direction (L2). The vertical direction (V) is perpendicular to the first surface 204. The first and second sidewalls 210, 212 extend from the first surface 204 in the vertical direction (V). The first side direction (L1) is perpendicular to the vertical direction (V) and parallel to the first surface 204. The trench floor 214 runs between the first and second side walls 210, 212 in the first lateral direction (L1).The second lateral direction (L2) refers to a direction perpendicular to the vertical direction (V) and perpendicular to the first lateral direction (L1). The first and second sidewalls 210, 212 extend along the semiconductor body 202 in the second lateral direction (L2). In other words, the depth of the first trench 208 is measured in the vertical direction (V), the width of the first trench 208, which refers to the distance between the first and second sidewalls 210, 212, is measured in the first lateral direction (L1), and the length of the trench is measured in the second lateral direction (L2).
[0020] In the context of this disclosure, a surface or plane “extends in a direction” if at least one component of the surface or plane is common to the direction of extension. However, this does not require that the surface or plane be exactly parallel to the direction of extension. For example, the first and second sidewalls 210, 212 extend in the vertical direction (V). However, the first and second sidewalls 210, 212 are not necessarily perpendicular to the first surface 204. Instead, the first and second sidewalls 210, 212 may form an oblique angle (either acute or obtuse) with respect to the first surface 204. In this case, the first and second sidewalls 210, 212 extend along a plane that includes a component of the vertical direction (V) and also a component of the first lateral direction (L1).
[0021] The first trench 208 is filled with a field dielectric 216. According to one embodiment, the field dielectric 216 extends within the first trench 208 to a surface 218 that is coplanar with the first surface 204 of the semiconductor body 202. In other words, the field dielectric 216 can be planarized such that the semiconductor body 202 and the field dielectric 216 form a single plane. The field dielectric 216 can be formed from an interlayer dielectric material, such as silicon dioxide (SiO2), which may be formed from, for example, TEOS, HDP, BSG, thermal oxidation, an oxynitride, other high-k dielectric materials, or any combination thereof. A high-k dielectric material refers to a material with a dielectric constant greater than 3.9. In contrast, a low-K dielectric material refers to a dielectric material with a dielectric constant that is less than or equal to 3.9.
[0022] A second trench 220 is formed adjacent to the first side wall 210 in the field dielectric 216. The second trench 220 is formed within the first trench 208 such that the boundaries of the second trench 220 are coextensive with the first surface 204, the first side wall 210, and the field dielectric 216. As used herein, "coextensive" describes a common plane shared by the two regions of the component 200.
[0023] The second trench 220 contains inner and outer sidewalls 222, 224, which extend along the semiconductor body 202 in the second lateral direction (L2). The second sidewall 224 is located closer to the first sidewall 210 of the first trench 208, while the inner sidewall 222 is located further away from the first sidewall 210 of the first trench 208.
[0024] As in Fig. As shown in Figure 2A, the second trench 220 tapers in the second lateral direction (L2) such that it contains a widened section 226 and a narrow section 228. The widened section 226 is adjacent to the narrow section 228 in the second lateral direction (L2). According to one embodiment, the widened and narrow sections 226 and 228 are directly adjacent to each other, so that they form a continuous trench 220 that runs along the second lateral direction (L2).
[0025] Fig. Figure 2B shows a cross-sectional view of component 100 along plane AA', which intersects the extended section 226. Fig. 2C shows a cross-sectional view of the component along the plane BB' that intersects the narrow section 228.
[0026] In the extended section 226, the inner and outer walls 222, 224 run parallel to the first side wall 210 in the second lateral direction (L2). According to one embodiment, in the extended section 226, the outer side wall 224 of the second trench is coextensive with the first side wall 210. The inner side wall 222 can be coextensive with a planar side surface of the field dielectric 216.
[0027] In the narrow section 228, one of the inner and outer side walls 222, 224 is not perpendicular and not parallel to the first side wall 210 in the second lateral direction (L2). The angle of non-perpendicularity of the inner and outer side walls 222, 224 with respect to the first side wall 210 in the second lateral direction (L2) can be greater or less than 90 degrees (i.e., acute or obtuse). According to one embodiment, the angle of non-perpendicularity is between eleven and fifteen degrees.
[0028] According to one embodiment of Fig. In the extended section 226, the inner side wall 222 remains parallel to the first side wall 210 in the second lateral direction (L2), while in the narrow section 228, the outer side wall 224 extends away from the first side wall 210 and towards the inner side wall 222 in the second lateral direction (L2). According to one embodiment, the inner side wall 222 forms a single plane in the field dielectric 216 in both the extended and narrow sections 226, 228, which extends parallel to the first side wall 210 in the second lateral direction (L2), wherein the outer side wall 224 extends parallel to the first side wall 210 in the second lateral direction (L2) in the extended section 226, and the outer side wall 224 extends along a plane that intersects the plane of the inner side wall 222 in the narrow section 228.
[0029] According to one embodiment, the semiconductor device 200 includes a third groove 230 formed within the first groove 208 opposite the second groove 220. The third groove 230 is formed in the field dielectric 216 and is spaced apart from the second groove 220 in the first lateral direction (L1). The third groove 230 contains an expanded section 232 adjacent to a narrow section 234 in the second lateral direction (L2). In the expanded section 232, the inner and outer side walls 236, 238 of the third groove 230 run parallel to the second side wall 212 in the second lateral direction (L2). In the narrow section 234, one of the inner and outer side walls 236, 238 is neither perpendicular nor parallel to the second side wall 212.The arrangement of the inner and outer side walls 236, 238 of the third trench 230 with respect to the second side wall 212 can be similar to or identical with the arrangement of the inner and outer side walls 222, 224 of the second trench with respect to the first side wall 210. According to one embodiment, the outer side wall 238 of the third trench 230 is coextensive with the second side wall 212 in the extended section 232, and the outer side wall 238 of the second trench forms a non-perpendicular angle with the second side wall 212 in the narrow section 234.
[0030] With reference to Fig. Figure 3 shows a semiconductor device 200 configured as a transistor, such as a MOSFET or an IGBT. The semiconductor device 200 utilizes the second and third trenches 220, 230, as referred to in Fig. 2 described as the gate grooves of the transistor. Fig. Figure 3A shows a cross-sectional view of the component 200 along the plane AA' that intersects the extended section 226 of the second trench 220. Fig. Figure 3B shows a cross-sectional view of the component along the plane BB', which intersects the narrow section 228 of the second trench 220.
[0031] According to one embodiment, a first, electrically conductive gate electrode 240 is arranged in the second groove 220. The first gate electrode 240 is electrically insulated from the semiconductor body 202 by a first gate oxide 242, which is inserted between the first gate electrode 240 and the semiconductor body 202. The first gate oxide 242 can be inserted between the first gate electrode 240 and the first side wall 210 (for example, in the case of a deposited gate oxide 242). Alternatively, the first gate oxide 242 can extend from the first side wall 210 into the semiconductor body 202 (for example, in the case of a thermally grown gate oxide 242). Optionally, a second, electrically conductive gate electrode 244 can be arranged in a third groove 230.The second gate electrode 244 is electrically isolated from the semiconductor body 202 by a second gate oxide 246, which is inserted between the second gate electrode 244 and the semiconductor body 202, in a similar manner to that described above with respect to the first gate electrode 240 and the first gate oxide 242.
[0032] The geometry of the second and third trenches 220, 230 defines the geometry of the first and second gate electrodes 240, 244 and the geometry of the corresponding first and second gate oxides 242, 246. Therefore, the first gate electrode 240 contains an expanded section corresponding to the expanded section 226 of the second trench 220 and a tapered section corresponding to the narrow section 228 of the second trench 220. Similarly, the second gate electrode 244 contains an expanded section corresponding to the expanded section 232 of the third trench and a tapered section corresponding to the narrow section 234 of the third trench 230. The first and second gate electrodes 240, 244 can be continuous structures, with the expanded and tapered sections directly adjacent to each other in the second side direction (L2).
[0033] The first and second gate electrodes 240, 244 can be formed from a conductive material, such as a metal conductor (e.g., aluminum or copper) or a semiconductor material, such as highly doped polysilicon or weakly doped silicon, or any combination thereof. The first and second gate oxides 242, 246 can be formed from any of many gate insulating materials, such as SiO2, oxynitride, aluminum oxide, or a high-k dielectric material.
[0034] In the embodiment of Fig. In Figure 3, the semiconductor device 200 is a vertical transistor configured to control a working current flowing in the vertical direction (V). The device 200 includes an electrically conductive source electrode 248 located on the first surface 204 and an electrically conductive drain electrode 250 located on the second surface 206.
[0035] The vertical transistor component 200 from Fig. The device 200 contains a source region 252, which is adjacent to the first surface 204 and electrically connected to the source electrode 248. The device 200 further contains a drain region 256, which is adjacent to the second surface 206 and electrically connected to the drain electrode 250. A channel region 254 is arranged between the source and drain regions 252 and 256 in the vertical direction (V). The source and drain regions 252 and 256 can have the first doping type (for example, n), while the channel region 254 can have the second doping type (for example, p). Optionally, the device 200 contains a drift region 258 between the channel region 254 and the drain region 256, which has either the first or the second doping type. The gate electrodes 240, 244 are electrically connected to a control terminal of the component 200 in another lateral region of the component 200, which in the cross-sectional perspective of Fig. Figure 3 is not shown. According to one embodiment, the first and second gate electrodes 240, 244 are electrically connected. This electrical connection can be achieved by a conductive metallization and / or polysilicon regions arranged over the first surface 204. In this embodiment, the first and second gate electrodes 240, 244 are configured to provide the gate of a single vertical cell that controls current flowing through the channel region 254. Alternatively, the first and second gate electrodes 240, 244 can be separated from each other to form the gates of two separate transistors.
[0036] Alternatively, the semiconductor device 200 can be configured as a side-mounted transistor in which a working current flows in the second lateral direction (L2). In this embodiment, both the source and drain regions 252, 256 extend to the first surface 204 and electrically connect the electrodes on the first surface 204.
[0037] The component of Fig. 3 is configured such that the gate oxide forms a non-perpendicular angle (acute or obtuse) with the semiconductor body 202 at one end of the gate electrode. This means that the gate oxide is not perpendicular and not parallel to the first trench sidewalls 210, 212 with respect to the second lateral direction (L2) at one end of the gate electrode. According to one embodiment, the gate oxide directly adjacent to the tapered section of the first and second gate electrodes 240, 244 forms a non-perpendicular angle with the first and second sidewalls 210, 212, respectively, in the second lateral direction. This non-perpendicular angle is achieved by forming the gate oxide and the gate electrode in the second and third trenches 220, 230, which are configured as previously discussed.
[0038] According to one embodiment, only the first gate oxide 242 is inserted between the extended section of the first gate electrode 240 and the semiconductor body 202. That is, in a section of the first gate electrode 240 corresponding to the extended section 226 of the second trench 220, the first gate electrode 242 occupies the entire space in the first lateral direction (L1) between the first gate electrode 240 and the semiconductor body 202. In contrast, the field dielectric 216 is inserted between the tapered section of the first gate electrode 240 and the semiconductor body 202. That is, in the sections of the first gate electrode 240 corresponding to the narrow section 228 of the second trench 220, the field dielectric 216 occupies some of the space in the first lateral direction (L1) between the first gate electrode 240 and the first side wall 210.The second gate electrode 244 and the second gate oxide 246 can be configured identically or similarly with respect to the second side wall 212.
[0039] The device 200 can also include a field electrode 260, which is arranged in the first trench 208 between the gate electrodes 240, 244. The field electrode 260 is electrically insulated from the gate electrodes 240, 244 and from the semiconductor body 202 by the field dielectric 216. The field electrode 260 can be made of any conductive material, such as a metallic conductor (for example, aluminum or copper) or highly doped polysilicon. In a generally known manner, the field electrode 260 can be biased such that it compensates for excessive charges in the drift region 258 of the device 200 during operation.
[0040] With reference to Fig. Figure 4 shows an alternative embodiment of the second and third trenches 220, 230. The semiconductor device 200 is identical in every respect to the semiconductor device 200 of Fig. 2 identical, except that the second and third trenches 220, 230 contain curved surfaces 262, 264 in the narrow sections 228, 234. The second and third trenches 220, 230 can be used in a device 200 with gate diodes 240, 244 and gate oxides 242, 246, which has the geometry described in Fig. 4 is compliant. That is, in the embodiment of Fig. 3 is the tapering of the first gate electrode 240 in the narrow section 228 achieved by arranging the inner and outer side walls 222, 224 in the narrow section 228 of the second trench 220 along two intersecting planes, whereas in the embodiment of Fig. 4. The tapering of the first gate electrode 240 in the narrow section is achieved by curving from one of the inner and outer side walls 222, 224 towards the other. According to one embodiment, the outer side wall 224 curves towards the inner side wall 222 in the second lateral direction (L2) in the narrow section 228. Therefore, the non-perpendicular feature of the second trench 220 and first gate oxide 242 with respect to the first side wall 210 is achieved by the curved surface 262, which curves away from the first side wall 210. Similarly, the non-perpendicular feature of the third trench 230 and the second gate oxide 246 with respect to the second side wall 212 can be achieved by the curved surface 264, which curves away from the second side wall 212.
[0041] Fig. 5 to Fig. Figure 6 describes selected process steps for forming the semiconductor device 200, as previously discussed, according to one embodiment. Fig. 5A shows a top view of component 200. Fig. Figure 5B shows a cross-sectional view of component 200 along the cross-sectional line AA', which is in Fig. 2A is specified. Fig. Figure 5C shows a cross-sectional view of component 200 along the cross-sectional line BB', which is in Fig. 5A is indicated. The planes AA' and BB' are parallel to each other and spaced apart.
[0042] According to the method, a semiconductor body 202 is provided. The semiconductor body can be formed from a commonly used semiconductor material, including silicon (Si), silicon carbide (SiC), germanium (Ge), a silicon germanium crystal (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and the like. The first trench 208, the field dielectric 216, and the field electrode 260, as disclosed herein, are formed in the semiconductor body 202. These features can be formed according to known techniques, including the methods discussed in US Patent Application 13 / 307,465 by Blank. Subsequently, the second and third trenches 220 and 230, with the geometry described herein, are formed in the field dielectric 216 within the first trench 208 by providing a mask 266 over the first surface. The mask 266 can be formed from any commonly used photoresist material.The mask is configured to expose an etching area 268 of the first dielectric material 216, which is directly adjacent to the first and second side walls 210, 212.
[0043] The extended section 226 of the second trench 220 can be formed by configuring the mask 266 such that a first section 270 of the etching area 268 exposes both the first dielectric material 216 and the semiconductor body 202. The narrow section 228 of the second trench 220 can be formed by configuring the mask 266 such that a boundary line 274 between the mask 266 and the etching area 268 intersects the first dielectric material 216 and forms a non-perpendicular angle with the first side wall 210 with respect to the second lateral direction (L2). The extended and narrow section 232, 234 of the third trench 230 can be formed by configuring the mask 266 with corresponding third and fourth sections 276, 278 of the etching area 268 and a corresponding boundary line 274, which forms a non-perpendicular angle with the second side wall 212 with respect to the second lateral direction (L2).
[0044] Fig. 6 represents the component of Fig. Figure 5 shows a masked etching step in which the first dielectric material 216 is selectively etched to the semiconductor body 202. In the masked etching step, the exposed sections of the first dielectric material 216 are removed, and the material of the semiconductor body 202 beneath the mask 216 remains essentially intact. According to one embodiment, the etching process is an anisotropic etching process in which the dielectric material 216 is removed only in the vertical direction (V). The etching process can, for example, be chemical wet etching.
[0045] Since the first dielectric material 216 is selectively etched to the semiconductor body 202, the outer sidewalls 224, 238 of the first and second trenches 220, 230 in the extended sections 226, 232 are coextensive with the first and second sidewalls 210, 212. That is, the entire first dielectric material 216, which extends to the first and second sidewalls 210, 212 in the first lateral direction (L1), is exposed by the mask 266 and is therefore removed during etching. Furthermore, since the etching process is an anisotropic etching process, vertical regions 282, 284 of the field dielectric 216 between the outer side walls 224, 238 of the second and third trenches 220, 230 in the narrow sections 228, 234 remain intact.
[0046] After etching the second and third trenches 220, 230, the mask 266 can be removed. Subsequently, the exposed semiconductor body 202 in the second and third trenches 220, 230 can be oxidized to form the first and second gate oxides 242, 246, which are described with reference to Fig. 2, Fig. 3 to Fig. 4. The material used for the first and second gate oxides 242, 246 must conform to strict parameters (e.g., thickness, impurity concentration, etc.) because these parameters contribute significantly to the performance and reliability of the fully fabricated semiconductor device 200. In the sequence described above, the field dielectric 216 is formed in a low-temperature process and may contain material defects. Furthermore, the thickness of the features that can be formed in the field dielectric 216 is limited by the efficiency of an etching process. In contrast, the first and second gate oxides 242, 246 can be formed in a subsequent high-temperature oxidation step. This sequence provides first and second gate oxides 242, 246 that are free of impurities and displacement and have highly controlled thicknesses.After oxidation of the semiconductor body 202, the first and second gate electrodes 240, 244 can be, as above with reference to . Fig. 2, Fig. 3 to Fig. 4 described, are trained.
[0047] Spatial terms such as "under," "below," "lower," "above," "upper," and the like are used here to facilitate description and explain the positioning of one element relative to another. These terms are intended to encompass various orientations of the structural element, in addition to those shown in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe different elements, regions, sections, etc., and are likewise not intended to be restrictive. The same terms consistently refer to the same elements throughout the description.
[0048] As used herein, the terms “exhibit”, “contain”, “include”, “comprise” and the like are open terms that indicate the presence of said elements or features, but do not exclude additional elements or features.
[0049] The term “essentially” encompasses proportions or physical characteristics of the elements that both conform exactly to the requirement and exhibit minor deviations from the requirements due to manufacturing process variations, assembly, and other factors that may cause a deviation from the ideal state.
Claims
[1] Semiconductor device comprising: a semiconductor body (202) with a first surface (204); a first trench (208) formed in the semiconductor body (202), wherein the first trench (208) has a first and a second side wall (210, 212) both extending from the first surface in a vertical direction, and a first trench bottom extending between the first and second side wall (210, 212) in a first lateral direction; a field dielectric (216) that fills the first trench (208); and a second trench (220) formed within the first trench (208) in the field dielectric (216) and having an inner and an outer side wall (222, 224), wherein the first and second sidewalls (210, 212) of the first trench (208) and the inner and outer sidewalls (222, 224) of the second trench (220) extend along the semiconductor body (202) in a second lateral direction that is perpendicular to the first lateral direction and perpendicular to the vertical direction, wherein the second trench (220) has a widened section (226) adjacent to a narrow section (228) in the second lateral direction, wherein in the widened section (226) the inner side wall and the outer side wall (222, 224) run parallel to the first side wall (210) in the second lateral direction, and wherein in the narrow section (228) one of the inner and outer side walls (222, 224) is not perpendicular and not parallel to the first side wall (210) in the second lateral direction, and wherein in the narrow section (228) the inner side wall (222) is parallel to the first side wall (210) in the second lateral direction and the outer side wall (224) runs away from the first side wall (210) and towards the inner side wall (222) in the second lateral direction. [2] Semiconductor device according to claim 1, wherein in the extended section (226) the outer side wall (224) of the second trench (220) is coextensive with the first side wall. [3] Semiconductor device according to one of claims 1 or 2, wherein in the narrow section (228) the outer side wall (224) of the second trench (220) forms a non-perpendicular angle between eleven and fifteen degrees with the first side wall (210) in the second lateral direction. [4] Semiconductor device according to claim 2, wherein the outer side wall (224) of the second trench (220) in the narrow section (228) has a curved surface (262) which curves inwards towards the inner side wall (222) in the second lateral direction. [5] Semiconductor device according to any one of claims 1 to 4, further comprising: a third trench (230) formed within the first trench (208) in the field dielectric (216) and having an inner and an outer side wall (236, 238), wherein the third trench (230) is spaced apart from the second trench (220) in the first lateral direction, wherein the third trench (230) has an expanded section (232) adjacent to a narrow section (234) in the second lateral direction, wherein in the expanded section (232) of the third trench (230) the inner side wall and the outer side walls (236, 238) run parallel to the second side wall (212) in the second lateral direction, and wherein in the narrow section (234) of the third trench (230) one of the inner and outer side walls (236, 238) is not perpendicular and not parallel to the second side wall (212), and wherein the outer side wall (238) of the third trench (230) in the widened section (232) is coextensive with the second side wall (212), and wherein the outer side wall (238) of the third trench (230) in the narrow section (234) forms a non-perpendicular angle with the second side wall (212). [6] Semiconductor device according to one of claims 4 or 5, further comprising: an electrically conductive field electrode (260) between the second and third trench (220, 230), which is electrically insulated by the field dielectric (216); a first, electrically conductive gate electrode (240) which is arranged in the second trench (220) and is electrically insulated from the semiconductor body (202) by a gate oxide (242) which is inserted between the first gate electrode (240) and the semiconductor body (202); and a second, electrically conductive gate electrode (244) which is arranged in the third trench (230) and is electrically insulated from the semiconductor body (202) by a gate oxide (246) which is inserted between the second gate electrode (244) and the semiconductor body (202). [7] Semiconductor device according to any one of claims 4 to 6, wherein the inner side walls of the second and third trench (220, 230) in both the widened and narrow sections (232, 234) are each coextensive with a single plane in the field dielectric (216) that runs parallel to the first and second side wall (210, 212), respectively. [8] Method for forming a semiconductor device, wherein the method comprises: Forming a first trench (208) in a semiconductor body (202), wherein the first trench (208) has a first and a second side wall (210, 212) both extending from a first surface (204) of the semiconductor body (202) in a vertical direction, and a first trench bottom extending between the first and second side walls (210, 212) in a first lateral direction, Filling the first trench (208) up to the first surface (204) with a field dielectric (216); Forming a second trench (220) within the first trench (208) in the field dielectric (216), wherein the second trench (220) has an inner and an outer side wall (222, 224); wherein the first and second sidewalls (210, 212) of the first trench (208) and the inner and outer sidewalls (222, 224) of the second trench (220) are designed such that they extend along the semiconductor body (202) in a second lateral direction that is perpendicular to the first lateral direction and perpendicular to the vertical direction, wherein the formation of the second trench (220) comprises the formation of an expanded section (226) adjacent to a narrow section (228) in the second lateral direction, wherein the inner side wall (222) and the outer side wall (224) of the second trench (220) in the expanded section (226) run parallel to the first side wall (210) in the second lateral direction, wherein the inner side wall (222) of the second trench (220) in the narrow section (228) runs parallel to the first side wall (210) in the second lateral direction, and wherein the outer side wall (224) of the second trench (220) in the narrow section (228) runs away from the first side wall (210) and towards the inner side wall (222) in the second lateral direction, Forming a first gate oxide (242) in the second trench (220) after forming the second trench (220) in the field dielectric (216); and forming a first gate electrode (240) in the second trench (220) such that the first gate electrode (240) in the extended section (226) is insulated from the semiconductor body (202) only by the gate oxide (242), and that the first gate electrode (240) in the narrow section (228) is insulated from the first side wall (210) by the field dielectric (216). [9] Method according to claim 8, wherein the forming of the second trench (220) comprises: Providing a mask (266) over the first surface (204) to expose an etching region of the field dielectric directly adjacent to the first side wall (210), wherein a boundary line between the mask (266) and the etching region forms a non-perpendicular angle in the second lateral direction with respect to the first side wall (210); and Etching of the field dielectric. [10] Method according to claim 9, wherein forming the extended section (226) comprises: such a configuration of the mask (266) such that a first section of the etching area exposes both the field dielectric and the semiconductor body (202); and Etching of the field dielectric selectively to the semiconductor body (202), such that the outer side wall (224) of the second trench (220) is coextensive with the first side wall (210) in the extended section (226). [11] Method according to one of claims 9 or 10, wherein forming the narrow section (228) comprises: such a configuration of the mask (266) such that the boundary line intersects the field dielectric and the first side wall; and Etching of the field dielectric by an anisotropic etching process such that a vertical region of the outer side wall (224) of the second trench (220) between the boundary line and the first side wall (210) remains intact. [12] Method according to any one of claims 8 to 11, further comprising: Forming a third trench (230) within the first trench (208) in the field dielectric (216), which is spaced apart from the first trench (208), wherein the third trench (230) has an inner and an outer side wall (236, 238), wherein the formation of the third trench (230) comprises the formation of an expanded section (226) adjacent to a narrow section (234) in the second lateral direction, wherein the outer side wall (236, 238) of the third trench (230) in the expanded section (226) runs parallel to the second side wall (212) in the second lateral direction, and wherein the outer side wall (224) of the second trench (220) in the narrow section (234) runs away from the second side wall (212) in the second lateral direction; Formation of a gate oxide (246) in the third trench (230) after the formation of the third trench (230) in the field dielectric (216); and forming a second gate electrode (244) in the third trench (230) such that the second gate electrode (244) in the extended section (226) is insulated from the semiconductor body only by the gate oxide (246), and that the second gate electrode (244) in the narrow section (234) is insulated from the first side wall (210) by the field dielectric (216).