Bus system

Abstract

A bus system with a number of bus participants (5) which exchange information via the PCI Express protocol, wherein at least one bus participant (5) forms a simple functional unit (6), wherein this bus participant (5) has a simple functional block (7) with logic of the PCI Express protocol, wherein bus participants (5) consisting of several sub-participants are present and each sub-participant is assigned a unique identification ID and a separate software driver at the operating system level, characterized in that logic blocks are assigned to the simple functional block (7) by means of which the simple functional units (6) are further developed into a multi-participant (11) without changing the simple functional block (7), and in that a revision ID register is provided for assigning a software driver to a sub-participant, wherein the revision ID registers for the individual sub-participants that form the multi-participant,They can have different values, so that different software drivers can be assigned to the individual single participants that make up the multiple participant.

Description

[0001] The invention relates to a bus system according to the preamble of claim 1.

[0002] This type of bus system is a bidirectional, high-speed bus system in which communication between a CPU and other bus participants takes place according to the PCI Express protocol. The PCI Express protocol itself was specified by the PCI Special Interest Group (PCI SIG), a US-based consortium.

[0003] Due to the high data rate of 2.5 Gbit per second and above, this bus system exclusively uses point-to-point connections. To network multiple bus participants, switches (data packet distributors) can be used, to which several bus participants are connected. These switches allow the CPU to assign data packets to the correct bus participant. After the bus system is powered on, the CPU scans all bus participants via the PCI Express interface. During this enumeration phase, the CPU assigns a unique identification ID to each bus participant. Following the enumeration phase, the CPU's operating system assigns a software driver to each bus participant, enabling software to address the peripheral devices connected to that bus participant (e.g., serial interface, Ethernet controller, graphics card, etc.).The communication of the bus system is then enabled, allowing the bus participants to exchange data.

[0004] Such bus systems are used in computer systems of all kinds, especially in desktop or laptop PC systems.

[0005] In the PCI Express bus system, a bus participant can be configured as a single participant, meaning it connects a single peripheral device to the bus system. In this single-participant configuration, the bus participant is assigned an identification ID and a software driver on the operating system side.

[0006] To save on switches and thus construction costs, the PCI Express specification allows for the creation of bus participants consisting of multiple sub-participants. Each sub-participant of the multi-participant connects its own peripheral device to the PCI Express bus system. Each sub-participant of the multi-participant is assigned its own unique identification ID and a separate software driver on the operating system side for operation within the bus system. This configuration of the bus participant is referred to below as a multi-participant. All sub-participants of the multi-participant reside on the same integrated circuit (IC), which is connected to the PCI Express bus system via a point-to-point connection.

[0007] Such PCI Express bus participants (single participants as well as multiple participants) are very often built using FPGA (Field-Programmable Gate Array) devices. Single participants have digital single-function units and Gigabit transceivers, which are implemented as hard-wired hard macro cells and form pre-assembled, certified units within the FPGA structure.

[0008] A disadvantage of such hard macro cells is that their function is largely predefined and cannot be subsequently changed. For a single-user unit configured using a PCI Express hard macro cell, this means that its limitation to a single user cannot be subsequently extended to a multi-user configuration.

[0009] In principle, it would be possible to circumvent this limitation with a commercially available so-called soft IP core by configuring the FPGA structure so that the limiting PCI Express hard macro cell of the single-function unit is not used and the multi-user interface is implemented purely with the programmable logic of the FPGAs. However, this requires a very high number of programmable FPGA logic resources, which leads to large and expensive FPGA packages.

[0010] US Patent 8,645,594 B2 relates to a system in which several physically existing PCI Express individual participants are integrated into a PCI Express bus system in such a way that they are seen by the bus system as a single individual participant in their entirety.

[0011] US 2009 / 0 276 551 A1 concerns a system that operates according to the Single Root I / O Virtualization Specification, which is a supplementary specification to the PCI Express system. In this system, a physically present participant is made visible exactly once in each operating system integrated on a CPU.

[0012] US Patent 7 289 125 B2 concerns a CPU system in which write accesses are automatically distributed among multiple participants. The number of participants visible to the CPU system remains unchanged.

[0013] The invention is based on the objective of expanding a pure PCI Express single participant to a PCI Express multi-participant of the type mentioned above, using minimal additional logic resources.

[0014] The features of claim 1 are provided to solve this problem. Advantageous embodiments and expedient further developments of the invention are described in the dependent claims.

[0015] The invention relates to a bus system with a number of bus participants that exchange information via the PCI Express protocol, wherein at least one bus participant is a single participant. This bus participant comprises a single function block with PCI Express protocol logic, and bus participants consist of several sub-participants. Each sub-participant is assigned a unique identification ID and a separate software driver at the operating system level. New logic blocks are assigned to the single function block, by means of which the single participant is transformed into a multi-participant without modifying the single function block.A revision ID register is provided for assigning a software driver to a sub-participant, whereby the revision ID registers for the individual sub-participants that form the multiple participant can have different values, so that different software drivers can be assigned to the individual single participants that form the multiple participant.

[0016] The basic idea of ​​the invention is therefore to achieve the expansion of a single participant to a multi-participant without excluding the single-function block and completely reprogramming the FPGA structure to provide the multi-participant functionality. Instead, according to the invention, the single-function block is incorporated in its structure completely unchanged to achieve the multi-participant functionality. The multi-participant functionality is achieved by specifically controlling the single-function unit via additional logic blocks, which are implemented with very little digital logic. In particular, this eliminates the need for larger FPGA structures to implement the multi-participant functionality.

[0017] The single-function block is particularly advantageous because it consists of a hard-wired PCI-Express hard macro cell.

[0018] The hard macro cell forming the single-function block is part of an FPGA component.

[0019] In this case, the logic blocks are part of the reconfigurable logic of the FPGA chip.

[0020] The implementation of the aforementioned units in FPGA structures is by no means mandatory. Rather, these units can also be implemented in ASIC structures.

[0021] A key element of the invention is that, by means of additional logic blocks - utilizing the PCI Express hard macro cell present in the single-function block - a configurable number of sub-participants are generated, thereby creating a multi-participant.

[0022] In this process, a number of address ranges of the simple function block are assigned to specific sub-participants using the additional logic blocks - freely selectable within certain limits.

[0023] The elements present in the simple function block, particularly address ranges, are distributed across multiple sub-participants by the additional logic blocks, so that a multi-participant is created solely through the reprogrammed use of the elements of the simple function block by the logic blocks. A key aspect of the logic blocks within the meaning of the invention is, in particular, their ability to modify write or read requests to the configuration area and thus redirect them to predefined sub-participants. This is possible because an incoming write or read request contains the target identification ID and thus the sub-participant number, which can be modified by the logic blocks.

[0024] Another essential aspect of the invention is that response packets to write or read requests are generated only in the single-function block in order to keep the space requirement of the logic blocks as small as possible.

[0025] Another advantage is that the redirection mechanism can be achieved by introducing additional information into the incoming data packets without the need for complex additional storage tables, which in turn leads to a significant saving of space and thus to a very small solution.

[0026] The functionality of the bus participant, which has been expanded from a single participant to a multiple participant, can be further increased by using logic blocks to detect CRC errors in the data transmission and to make quantitative and qualitative statements about the stability of the PCI Express bus connection.

[0027] The assignment of the revision ID register located in the configuration area, for the newly configured single participants, which serves to assign the software driver, is possible in two ways.

[0028] In principle, the revision ID register can have identical values ​​for the individual sub-participants, so that the same software driver is assigned to each individual sub-participant.

[0029] The revision ID register can also have different values ​​for each individual sub-participant of the multi-participant. A key advantage of the invention is that each sub-participant can be assigned its own software driver. These software drivers have a significantly simpler structure compared to a software driver assigned to multiple bus participants. This results in considerably shorter development times for creating software drivers. Furthermore, improved and simplified maintenance of the software drivers is achieved.

[0030] According to a further advantageous embodiment of the invention, a logic block is provided by means of which interrupts can be sent from each sub-participant within the multiple participant to the CPU.

[0031] This leads to improved operational reliability of the bus system, as the logic block allows interrupts to be pre-assigned to the correct sub-participants, thus preventing incorrect control caused by the interrupts.

[0032] The invention will be explained below with reference to the drawings. Fig. 1: Example of a PCI Express bus system. Fig. 2: Schematic diagram of a single functional unit for the PCI Express bus system according to Fig. 1. Fig. 3: Extension of the single-function unit to a multiple-function unit. Fig. 4: Creating a Configuration Space header. Fig.5: Configuration of multiple sub-participants for the Configuration Space header. Fig. 6: Schematic representation of the process when accessing sub-participant 0 according to the representation of Fig. 4. Fig. 7: Schematic representation of the process when accessing sub-participant 1 according to the representation of Fig. 4. Fig. 8: Creating a PCI-Express Configuration Request. Fig. 8a: Structure of the Complete ID of the Configuration Request according to Fig. 4. Fig. 8b: Structure of the Requester ID of the Configuration Request according to Fig. 4.

[0033] Fig. Figure 1 schematically shows the structure of a PCI Express bus system. The PCI Express bus system comprises a CPU 1 (central processing unit) with associated memory units 2 and a PCI Express bus access point 3.

[0034] Several bus participants 5 of the PCI Express bus system can be connected to CPU 1, either directly or via a switch 4. A point-to-point connection is established between CPU 1 and a directly connected bus participant 5. Switch 4 serves to connect multiple bus participants 5 to CPU 1. Switch 4 distributes data packets from CPU 1 to the connected bus participants 5.

[0035] After the PCI Express bus system is switched on, CPU 1 scans all bus participants 5 and assigns each one a unique identification ID. Following this enumeration phase, the operating system running on the CPU assigns a software driver to each bus participant 5. Afterward, the bus participants 5 of the PCI Express bus system can begin exchanging data with each other via the PCI Express protocol.

[0036] Fig.Figure 2 schematically shows a bus participant 5 of the PCI Express bus system configured as a single participant 6. The single participant 6 is implemented in FPGA logic and comprises a single-function block 7, which is implemented as a hard-wired PCI Express hard macro cell in the FPGA structure.

[0037] Furthermore, a Gigabit transceiver 9 is provided for serial / parallel conversion of incoming (RX) and outgoing (TX) data packets via a PCI Express interface 8. This transceiver is also hardwired and implemented as a hard macro. A user interface 10 allows a user to intervene in the data path between the simple function block 7 and the Gigabit transceiver 9.

[0038] Fig. Figure 3 shows the extension of the simple functional unit 6 according to the invention. Fig.2 to a multi-user device 11 within the PCI Express bus system. Like the single-function unit 6, the multi-user device 11 has a single-function block 7, a Gigabit transceiver 9, a PCI Express interface 8, and a user interface 10. In addition, three logic blocks are provided, which are built from the freely configurable logic portion of the FPGA chip.

[0039] Two of the logic blocks form redirection blocks: an RX redirection 12 for incoming data packets and a TX redirection 13 for outgoing data packets. Furthermore, a MIF remap 14 forms a logic block for interrupt mappings.

[0040] The logic blocks extend the functionality of the simple function block 7 to include multi-participant functionality.

[0041] The multiple participant can be configured via a management interface 15.

[0042] The simple function block 7 according to Fig. 2 (as also according to Fig. 3) has a bus participant 5 implemented as a single participant, wherein for this single participant a configuration area that is physically writable / readable via the PCI Express protocol, as in Fig. As shown in Figure 4, the configuration area comprises a predefined number of registers R1-R10 and six specific registers in the form of basic address registers, which are located in Fig. 4 are designated BAR0 to BAR5, with specific address ranges from the 64-bit PCI Express address space assigned to these registers.

[0043] To extend a single-function unit 6 to a multiple participant 11, the number and form of individual sub-participants of the multiple participant are configured via the logic blocks RX redirection 12 and TX redirection 13.

[0044] This is in Fig.Figure 5 is shown schematically, where the physically existing configuration area of ​​the single-function block 7, i.e., the configuration space header, is shown on the left. In this case, three individual participants within a multi-participant, corresponding to three bus participants 5 of the PCI Express bus system, are derived from this configuration space header.

[0045] To form the three sub-participants of the multiple participant, the address range of the basic address registers BAR0 to BAR5 is divided among the three sub-participants. As shown in Fig.As shown in section 5, the first two base address registers, BAR1 and BAR2, of the Configuration Space header are assigned to sub-participant 0 as base address registers BAR1 and BAR2. Base address registers BAR3 and BAR4 of the Configuration Space header are assigned to sub-participant 1 as base address registers BAR0 and BAR1. Base address register BAR4 of the Configuration Space header is assigned to sub-participant 2 as base address register BAR0. Base address register BAR5 of the Configuration Space header is not assigned to any sub-participant.

[0046] Since the Configuration Space header has a total of six base address registers BAR0 to BAR5, a maximum of six sub-participants can be generated within a multi-participant. Because only three sub-participants are generated in this case, the number and assignment of the base address registers BAR0 to BAR5 of the Configuration Space header to the sub-participants can be freely chosen.

[0047] As from Fig.As can be seen in section 5, registers R1, R2, and R4 through R10 remain the same for all individual participants. Only the value of register R3, the so-called revision ID register, is incremented for each sub-participant (N, N+1, N+2). This allows different software drivers to be assigned to individual sub-participants. If the same values ​​are provided for register R3 of all sub-participants, the same software driver is assigned to all sub-participants.

[0048] According to the diagram Fig. 5 corresponds to the sub-participant 0, which already existed originally in the single-function unit 6.

[0049] The further sub-participants 1 and 2 correspond to additionally generated bus participants 5 within the multiple participant.

[0050] For configuration write and read requests received via the PCI Express protocol over the bus system, only the single physical Configuration Space header is used for all single participants within the multi-participant. Nevertheless, configuration write and read requests can be used to specifically access individual sub-participants within the multi-participant, as shown below. Fig. Show 5 to 8.

[0051] For communication with the first bus participant 5 (corresponding to participant 5 of the original simple function unit 6), a configuration write or read request involves accessing sub-participant 0, as described in Fig.Figure 6 illustrates this. The basic address registers BAR0 and BAR1 of single subscriber 0 are accessed, which correspond to the basic address registers BAR0 and BAR1 of the physical configuration space, i.e., the Configuration Space header. Therefore, no redirection is performed using logic blocks RX redirection 12 and TX redirection 13; that is, the request is forwarded unprocessed (arrows I in Fig. 6).

[0052] However, if a request, for example during the enumeration phase, accesses a base address register BAR2 to BAR5 of the Configuration Space header, this request is redirected to a disabled register, in this case to register R8, which defines the address range of an optional expansion ROM. This expansion ROM is disabled in most cases and exhibits the same behavior as a disabled base address register. This redirection is described in Fig.6 marked with arrows II. For communication with another bus participant 5, a write and read request accesses sub-participant 1, as shown in Fig. Figure 7 shows that to ensure access to this sub-subscriber 1, a request with RX redirection 12 results in an RX redirection (arrow I) to the basic address registers BAR2, BAR3, which are assigned as basic address registers BAR0, BAR1 of sub-subscriber 1 ( Fig. 5) Therefore, RX redirection 12 specifically addresses sub-participant 1, which is assigned to the other bus participant 5. The RX redirection performed by RX redirection 12 is then reversed by the TX redirection performed by TX redirection 13 (arrow II). The redirection to register R8 (expansion ROM) when accessing deactivated base address registers (arrows III) is analogous. Fig. 6. How the Fig. 6, Fig.As shown in Figure 7, the data packets for write or read requests are only generated in single-function block 7. The logic blocks modify these data packets appropriately to define and address multiple sub-participants, and thus bus participant 5. This function of the logic blocks RX redirection 12 and TX redirection 13 allows requests to single-function block 7 of the configuration space header to be used unchanged for other sub-participants as well, so that the expansion from a single-function unit 6 to a multi-function unit can be carried out without modifying single-function block 7.

[0053] Fig.Figure 8 shows the structure of a so-called PCI Express configuration request. A configuration request is a read or write request to the configuration space header. This request contains the sub-participant number (included in the completer ID) to be addressed, the memory address (register number of the configuration space header) to be read or written, and the identification ID of the requesting bus participant (requester ID).

[0054] The structure of the Completer ID is in Fig. Figure 8a shows the structure of the Requestor ID. Fig. 8b shown.

[0055] For the configuration request, the system checks which sub-participant is being accessed by evaluating bits 2 and 0 of the sub-participant number from the completer ID of an incoming request. If these three bits show a value other than 0, indicating access to one of the additionally configured sub-participants, these three bits are copied to position 7 and 5 of the bus number of the requester ID, and the three-bit sub-participant number of the completer ID is deleted.

[0056] This redirects all requests to sub-participant 0 so that simple function block 7 can respond correctly. Without this modification, simple function block 7, which only supports a single simple participant 5 with one sub-participant, would respond to the request with an error (an "Unsupported Request").

[0057] Since the Requester ID is output unchanged in the response of the simple function block 7 with the information of the original sub-subscriber number (inserted by the RX redirection block), the TX redirection 13 receives the original sub-subscriber number back and can now copy it back to its original position and set bits 7:5 in the Requester ID to 000.

[0058] Using bits 7 and 5 in the requester ID results in the restriction that no requesting bus participant may use these bits; that is, they are always set to 0. To minimize this restriction, only as many bits as necessary are used, depending on the number of sub-participants. The following table shows how many bits are actually used for each configuration:

[0059] To ensure that the activated and deactivated base address registers (BAR1 to BAR5) of all sub-participants appear in the correct positions in the Configuration Space header of all sub-participants, 12 addresses from the RX redirection block are modified appropriately and further information is encoded in bits 4:2 of the Device ID within the Requester ID.

[0060] The following table shows the meaning of the code contained in these bits. Code number Meaning 000 No change is necessary in the TX redirection block. 001 Show response as access to BAR0 010 Show response as access to BAR1 011 Show response as access to BAR2 100 Show response as access to BAR3 101 Show response as access to BAR4 110 Show response as access to BAR5 111 Marker indicating that the Revision ID Register has been accessed

[0061] By incorporating this additional information, it is now possible to redirect an incoming configuration request by changing the address and to modify the response from the simple function block 7 so that it appears as the response to the original request.

[0062] Since the bits of the device number within the requester ID are used elsewhere, it is essential that no bus participant 5 with a device number greater than three accesses the multifunctional unit 11. However, since the device ID is 00000 in the vast majority of cases, this restriction is acceptable.

[0063] This redirection approach eliminates the need to maintain a list of incoming requests and merge them with the subsequently generated responses from simple function block 7. Instead, each response already contains all the necessary information for post-processing due to the additional data. This results in significant savings in logic resources.

[0064] The PCl Express bus system distinguishes between two different interrupt triggering mechanisms: the legacy interrupt and the MSI interrupt.

[0065] In the so-called legacy interrupt mode, each sub-participant sends the same interrupt, which must be treated by the operating system in conjunction with the associated software driver on the CPU system as a so-called "shared interrupt".

[0066] MSI interrupts require special handling. Since MSI interrupts are triggered by writing a specific data word ("message data register") to the assigned address of the interrupt controller, the so-called message data register must be stored for each sub-participant. This is accomplished by the RX redirection 12, which detects write accesses to the message data register for each sub-participant and stores the specific value of the message data register for each sub-participant in a small SRAM within the FPGA.

[0067] If an MSI interrupt is triggered via the user interface, it is initially held back by MIF Remap 14, and the correct message data register from the aforementioned SRAM is loaded into the simple function block 7. Afterwards, the MSI interrupt is triggered, and the interrupt to user interface 10 is marked as resolved. Expression Explanation in the PCI Express context Inquiry A request is a so-called request, which is sent by the requester to the completer either as a read or as a write request. ASIC Application-specific integrated circuit. This is a custom-designed, hard-wired electronic component. Answer The bus passenger (completer) responds to a request with their answer. This answer is called a completion. Basic Address Register (BAR) Each PCI Express function has 6 base address registers (BARs). BARs are used to define both the size and the location of a memory window within the PCI Express address space. Bus passengers A bus participant is called an endpoint. An endpoint can contain 1-8 PCI Express functions. If only one function is implemented, it is a single participant; if more functions are implemented, it is a multi-participant. Data packet distributor In the PCI Express context, a data packet distributor is referred to as a switch. A switch consists of a number of input and output ports. Output ports. The logic contained in the switch enables incoming data packets to be assigned to the correct output. Simple function block Digital logic unit that handles data exchange according to the rules of the PCI Express protocol for a single-function device. In FPGAs, this logic unit is usually implemented as a hard-wired macro. Single participant This is a so-called single-function device. Enumeration phase The enumeration phase is performed before the PCI Express bus system becomes operational. During the enumeration phase, all Configuration Space Headers are initialized, and in particular, the BARs are set up. FPGA Field Programmable Gate Array. FPGAs are programmable logic devices that contain user-defined logic functions. Hard macro A hard macro is a hard-wired interconnection of logic elements, such as flip-flops and Boolean logic functions. IC Integrated Circuit: Integrated circuit Identification ID The identification ID is a 16-bit word that uniquely identifies a PCI Express bus participant. It consists of three parts: the bus ID, device ID, and function ID. Configuration area Configuration space header. Each function has its own configuration space header, which contains the BAR settings for each function. Multiple participants The multi-user device is referred to as a Multi-Function Device in the PCI Express specification. The configured functions contained within the Multi-Function Device are referred to as sub-users in this patent. PCI Express bus access The CPU communicates with the system via the PCI Express bus access. Bus participants. In the PCIe specification, the PCI Express bus access is referred to as the Root Complex. PCISIG The PCI Special Interest Group (PCISIG) is a US American consortium that advances the specifications and further development of the PCI Express system. Peripheral unit Peripheral devices are input / output units that extend the functionality of the CPU. These can include, for example, graphics cards, serial interfaces, Ethernet controllers, or other devices. Revision ID Register The Revision ID register is located in the Configuration Space header and is used (along with other registers) to assign a software driver (Device Driver) to a PCI Express Function. Shared Interrupt A shared interrupt is an interrupt, meaning a shared interrupt line, that is shared by multiple bus participants. The CPU's interrupt service routine must have a way to identify the bus participant that triggered the interrupt when dealing with shared interrupts. Soft IP Core A soft IP core is a description of a digital functional unit in the form of a hardware description language (e.g., VHDL or Verilog). A logic compiler (also called a synthesis tool) transforms the soft IP core into a digital circuit, which can then be placed and wired in an FPGA or ASIC. Unsupported Request This is the standard response of a PCI Express bus participant when the requested operation is not possible. This occurs, for example, when a sub-participant is requested that does not exist. Reference symbol list 1 PCI Express bus access 2 storage units 3 CPU 4 Switch 5 bus passengers 6 single participants 7 Simple function block 8 PCI Express interface 9 Gigabit transceivers 10 User interface 11 participants who participated multiple times 12 RX rerouting 13 TX diversion 14 MIF diversion 15 Management interface

Claims

[1] Bus system with a number of bus participants (5) which exchange information via the PCI Express protocol, wherein at least one bus participant (5) forms a single-function unit (6), wherein this bus participant (5) has a single-function block (7) with a logic of the PCI Express protocol, wherein bus participants (5) consisting of several sub-participants are present and each sub-participant is assigned a unique identification ID and a separate software driver at the operating system level, characterized bythat logic blocks are assigned to the single-function block (7), by means of which logic blocks the single-function units (6) are further developed into a multiple subscriber (11) without changing the single-function block (7), and that a revision ID register is provided for assigning a software driver to a sub-subscriber, wherein the revision ID registers can have different values ​​for the individual sub-subscribers that form the multiple subscriber, so that different software drivers can be assigned to the individual single subscribers that form the multiple subscriber. [2] Bus system according to claim 1, characterized by that the simple function block (7) consists of a hard-wired hard macro cell. [3] Bus system according to claim 2, characterized by that the hard macro cell forming the simple function block (7) is part of an FPGA component. [4] Bus system according to claim 3, characterized bythat the logic blocks are part of a reconfigurable logic of the FPGA component. [5] Bus system according to one of claims 1 to 4, characterized by that a configurable number of sub-participants is generated by means of the logic blocks using the structure present in the simple function block (7). [6] Bus system according to claim 5, characterized by that a number of base address registers of the simple function block (7) are freely selectable and assigned to specific sub-subscribers by means of the logic blocks. [7] Bus system according to one of claims 1 to 6, characterized by that data packets for configuration write or read requests are only generated in the simple function block (7), and that such data packets are modified by the logic blocks. [8] Bus system according to claim 7, characterized by that a write or read request contains the sub-subscriber number identifying an individual subscriber. [9] Bus system according to claim 8, characterized by that the revision ID registers for each individual node can be configured to have identical values ​​so that each sub-node is assigned the same software driver. [10] Bus system according to one of claims 5 to 9, characterized by that logic blocks designed as redirection blocks are provided, by means of which write or read requests are redirected to predetermined sub-subscribers within the multiple subscriber. [11] Bus system according to claim 10, characterized by that errors in data transmission are reported using the redirection blocks, which can be used to make quantitative and qualitative statements about the stability of the PCI Express bus. [12] Bus system according to claim 11, characterized bythat the logic blocks designed as redirection blocks are described by means of a hardware description language, whereby the number and the form of the individual participants contained in the multiple participant can be determined by means of parameters. [13] Bus system according to one of claims 5 to 12, characterized by that a logic block (14) is provided, by means of which interrupts are sent by predetermined sub-subscribers within the multiple subscriber using the simple function block (7).

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