BIPOLAR SEMICONDUCTOR ELEMENT WITH A CHARGE-BALANCED INTERTRAP STRUCTURE

Abstract

A bipolar semiconductor device (100, 200, 300, 400), comprising: a drift region (114) with a first conductivity type, which is located above an anode layer (110) with a second conductivity type opposite to the first conductivity type; a first and second control trench (120a, 120b) extending through an inversion region (116) with the second conductivity type into the drift region (114), each of the first and second control trenches (120a, 120b) being bounded by a cathodic diffusion (128); and an intermediate trench structure (130) located in the drift region (114) between the first and second control trenches (120a, 120b), wherein the inter-trench structure (130) comprises at least a first conductivity region (134) with the first conductivity type and at least a second conductivity region (136) with the second conductivity type, wherein at least one first conductivity region (134) and at least one second conductivity region (136) have a doping concentration greater than that of the drift region (114), and wherein at least one first conductivity region (134) and at least one second conductivity region (136) are formed to essentially balance the charge of the inter-trench structure (130).

Description

BACKGROUND

[0001] The present disclosure relates to a bipolar semiconductor device and an insulated gate bipolar transistor. STATE OF THE ART

[0002] Bipolar semiconductor devices suitable for use as power switches, such as insulated-gate bipolar transistors (IGBTs), can be implemented in a wide variety of applications. For example, IGBTs can be used as power switches in inverters for motor drives and in direct current (DC-DC) power converters. In these and other power applications, turn-off losses (E OFF ; OFF = OFF) and an on-state voltage drop (V ON ; ON = ON) are typically key operating parameters, so low V IGBTs ON and essentially minimized E OFFduring fast switching are extremely desirable. Corresponding bipolar semiconductor components are proposed, for example, in the publications JP 2006 294 968 A, DE 10 2011 077 841 A1, and US 2012 / 0217555 A1.

[0003] However, as switching speed increases, switching losses, including E OFF , typically represents a significant portion of the total power loss through a bipolar circuit breaker. Furthermore, conventional techniques for minimizing the E OFF during fast switching undesirable consequences for the on-state characteristics of the bipolar circuit breaker, e.g. BV ON , have. SUMMARY

[0004] There is a need to provide an improved concept for a bipolar semiconductor device and an IGBT.

[0005] This need can be met by the subject matter of one of the claims.

[0006] The present disclosure relates to a bipolar semiconductor device having a charge-balanced inter-trench structure substantially as shown in and / or described in connection with at least one of the figures, and as set forth in the claims.

[0007] Some embodiments relate to a bipolar semiconductor device comprising a drift region having a first conductivity type located above an anode layer having a second conductivity type opposite to the first conductivity type; first and second control trenches extending through an inversion region having the second conductivity type into the drift region, each of the first and second control trenches being bounded by a cathode diffusion;and an inter-trench structure located in the drift region between the first and second control trenches, the inter-trench structure comprising at least one first conductivity region having the first conductivity type and at least one second conductivity region having the second conductivity type, the at least one first conductivity region and the at least one second conductivity region having a doping concentration greater than that of the drift region, and the at least one first conductivity region and the at least one second conductivity region being configured to substantially charge balance the inter-trench structure.

[0008] Optionally, the inter-trench structure comprises two first conductivity regions and a second conductivity region, wherein the second conductivity region is located between the two first conductivity regions.

[0009] Again optionally, the inter-trench structure comprises a first plurality of the first conductivity regions and a second plurality of the second conductivity regions, wherein the first plurality is greater than the second plurality.

[0010] Optionally, the inter-trench structure comprises a first plurality of the first conductivity regions and a second plurality of the second conductivity regions, and wherein each of the second conductivity regions is located between two of the first conductivity regions.

[0011] Again optionally, the intermediate trench structure is not located under the first control trench or the second control trench.

[0012] Optionally, the inter-trench structure borders the inversion region.

[0013] Again optionally, the drift region is adjacent to the at least one first conductivity region, but is not adjacent to the at least one second conductivity region.

[0014] Optionally, the bipolar semiconductor device further comprises an enhancement layer having the first conductivity type located between the drift region and the inversion region, wherein the inter-trench structure is adjacent to the enhancement layer.

[0015] Again optionally, the bipolar semiconductor device further comprises a buffer layer having the first conductivity type located between the anode layer and the drift region, wherein the inter-trench structure is spaced from the buffer layer by the drift region.

[0016] Optionally, the bipolar semiconductor device further comprises a buffer layer having the first conductivity type located between the anode layer and the drift region, wherein the inter-trench structure is adjacent to the buffer layer.

[0017] Some embodiments relate to an IGBT comprising a drift region having a first conductivity type located above a collector having a second conductivity type opposite to the first conductivity type; first and second gate trenches extending through a base having the second conductivity type into the drift region, each of the first and second gate trenches being bounded by an emitter diffusion;and an inter-trench structure located between the first and second gate trenches, the inter-trench structure comprising at least one first conductivity region having the first conductivity type and at least one second conductivity region having the second conductivity type, the at least one first conductivity region and the at least one second conductivity region having a doping concentration greater than that of the drift region, and the at least one first conductivity region and the at least one second conductivity region being configured to substantially charge balance the inter-trench structure.

[0018] Optionally, the inter-trench structure comprises the two first conductivity regions and the one second conductivity region, wherein the second conductivity region is located between the two first conductivity regions.

[0019] Again optionally, the inter-trench structure comprises a first plurality of the first conductivity regions and a second plurality of the second conductivity regions, wherein the first plurality is greater than the second plurality.

[0020] Optionally, the inter-trench structure comprises a first plurality of the first conductivity regions and a second plurality of the second conductivity regions, and wherein each of the second conductivity regions is located between two of the first conductivity regions.

[0021] Again optionally, the inter-trench structure is not located under the first gate trench or the second gate trench.

[0022] Optionally, the inter-trench structure borders the base.

[0023] Again optionally, the drift region is adjacent to the at least one first conductivity region, but is not adjacent to the at least one second conductivity region.

[0024] Optionally, the IGBT further comprises an enhancement layer having the first conductivity type between the drift region and the base, wherein the inter-trench structure is adjacent to the enhancement layer.

[0025] Again optionally, the IGBT further comprises a buffer layer having the first conductivity type located between the collector and the drift region, wherein the inter-trench structure is spaced from the buffer layer by the drift region.

[0026] Optionally, the IGBT further comprises a buffer layer having the first conductivity type located between the collector and the drift region, wherein the inter-trench structure is adjacent to the buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates a cross-sectional view showing a portion of an exemplary bipolar semiconductor device with a charge-balanced inter-trench structure, according to one implementation. Fig. 2 illustrates a cross-sectional view showing a portion of an exemplary bipolar semiconductor device with a charge-balanced inter-trench structure, according to another implementation. Fig. 3 illustrates a cross-sectional view showing a portion of an exemplary bipolar semiconductor device with a charge-balanced inter-trench structure, according to yet another implementation. Fig. 4 illustrates a cross-sectional view showing a portion of an exemplary bipolar semiconductor device with a charge-balanced inter-trench structure, according to another implementation. DETAILED DESCRIPTION

[0027] The following description contains specific information related to implementations in the present disclosure. One skilled in the art will recognize that the present disclosure may be implemented other than as specifically discussed herein. The drawings in the present application and its accompanying Detailed Description are directed to exemplary implementations only. Unless otherwise noted, like or corresponding elements may be indicated by like or corresponding reference numerals throughout the figures. Furthermore, the drawings and pictorial representations in the present application are generally not to scale and are not intended to correspond to actual relative dimensions.

[0028] Fig. 1 illustrates a cross-sectional view showing a portion of an exemplary bipolar semiconductor device 100 with a charge-balanced inter-trench structure, according to one implementation. As shown in Fig. 1, the bipolar semiconductor device 100 is implemented as a vertical power device comprising a P-type anode layer 110 on a bottom surface 104 of a semiconductor substrate 102, and an N-type drift region 114 located above the P-type anode layer 110. In addition, a P-type inversion region 116 is located above the N-type drift region 114. As shown in Fig. 1, the bipolar semiconductor device 100 includes an N-type buffer or field stop layer 112 (hereinafter "buffer layer 112") and N-type cathode diffusions 128 and P-type contacts 118 formed in the P-type inversion region 116.

[0029] The bipolar semiconductor device 100 also includes a first control trench 120a and a second control trench 120b, each of which extends from a top surface 106 of the semiconductor substrate 102 through the P-type inversion region 116 and into the N-type drift region 114. As shown in Fig. 1, each of the first control trench 120a and the second control trench 120b is bounded by the N-type cathode diffusions 128 and includes a control trench insulator 122 and a control trench electrode 124. In addition, the bipolar semiconductor device 100 includes an inter-trench structure 130 located in the N-type drift region 114 between the first control trench 120a and the second control trench 120b and extending to a depth 138 below the top surface 106 of the semiconductor substrate 102. As shown in Fig. 1, the inter-trench structure 130 includes one or more N-type regions 134 and one or more P-type regions 136. One or more N-type regions 134 and one or more P-type regions 136 are configured to substantially charge balance the inter-trench structure 130.

[0030] It should be noted that, in operation, the bipolar semiconductor device 100 is configured to create conduction channels through the P-type inversion region 116 in regions below the N-type cathode diffusions 128 and immediately adjacent to the first control trench 120a and the second control trench 120b. Thus, when the bipolar semiconductor device 100 is turned on, conduction channels (as such in Fig. 1 not shown) are created as N-type conduction channels through the P-type inversion region 116 to enable transfer of charge carriers between the N-type cathode diffusions 128 and the P-type anode layer 110.

[0031] It should also be noted that, although the Fig. While the implementation shown in Figure 1 depicts the bipolar semiconductor device 100 as including the P-type anode layer 110, the N-type buffer layer 112, the N-type drift region 114, the P-type inversion region 116, the N-type cathode diffusions 128, and configured to create the N-type conduction channels, this representation is merely exemplary. In other implementations, the described polarities may be reversed. That is, the bipolar semiconductor device 100 may include an N-type layer corresponding to the P-type anode layer 110, a P-type buffer layer, a P-type drift region, an N-type inversion region, P-type diffusions corresponding to the N-type cathode diffusions 128, and may be configured to create P-type conduction channels adjacent to the first control trench 120a and the second control trench 120b.

[0032] According to an example implementation, the bipolar semiconductor device 100 may take the form of an insulated-gate bipolar transistor (IGBT). In this implementation, the P-type anode layer 110 corresponds to a P-type collector layer, the P-type inversion region 116 corresponds to a P-type base, and the N-type cathode diffusions 128 correspond to N-type emitter diffusions of the IGBT. Further, when the bipolar semiconductor device 100 is implemented as an IGBT, the first control trench 120a and the second control trench 120b each correspond to gate trenches of the IGBT, each of which includes a gate dielectric and a gate electrode, each corresponding to a control trench dielectric 122 and the control trench electrode 124.

[0033] The semiconductor substrate 102 may, for example, be a silicon (Si) substrate or a silicon carbide (SiC) substrate. In some implementations, the semiconductor substrate 102 may include the N-type drift region 114 and the P-type inversion region 116 formed in an epitaxial silicon layer of the semiconductor substrate 102. The formation of such an epitaxial silicon layer may, for example, be performed by any suitable method known in the art, such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). More generally, however, the N-type drift region 114 and the P-type inversion region 116 may be formed in any suitable elemental or compound semiconductor layer included in the semiconductor substrate 102.

[0034] Thus, in other implementations, it is not required that the N-type drift region 114 and the P-type inversion region 116 be formed by epitaxial growth and / or be formed from silicon. In an alternative implementation, the N-type drift region 114 and the P-type inversion region 116 may be formed, for example, in a floating-zone silicon layer of the semiconductor substrate 102. In other implementations, the N-type drift region 114 and the P-type inversion region 116 may be formed in either a strained or unstrained germanium layer formed as part of the semiconductor substrate 102. In some implementations, the semiconductor substrate 102 may further include additional layers, such as the N-type buffer layer 112 located between the P-type anode layer 110 and the N-type drift region 114, as shown in Fig. 1 shown.

[0035] The P-type inversion region 116 may be formed by implantation and thermal diffusion. For example, boron dopants (B dopants) may be implanted into the semiconductor substrate 102 and diffused to form the P-type inversion region 116. Furthermore, the P-type contacts 118 of the P-type inversion region 116 may be more highly doped regions of the P-type inversion region 116, using the same dopant species used to form the P-type inversion region 116.

[0036] The control trench insulator 122 may be formed using any material and any technique typically used in the prior art. For example, the control trench insulator 122 may be formed from silicon oxide and may be deposited or thermally grown to line the first control trench 120a and second control trench 120b. The control trench electrodes 124 may also be formed using any material typically used in the prior art. For example, the control trench electrodes 124 may be formed from doped polysilicon or metal. Although this is not Fig. 1 is not explicitly shown, the control trench electrodes 124 can be connected to each other in the third dimension relative to the Fig. 1 shown cross-sectional perspective.

[0037] As in Fig. 1, each of the first control trench 120a and the second control trench 120b is bounded by the N-type cathode diffusions 128. The N-type cathode diffusions 128 may be selectively formed in the P-type inversion region 116 using any conventional techniques known in the art. For example, phosphorus (P) or arsenic (As) dopants may be implanted into the P-type inversion region 116 and diffused to form the N-type cathode diffusions 128. As is the case for the control trench electrodes 124, and although in Fig. 1, the N-type cathode diffusions 128 can be arranged in the third dimension relative to the Fig. 1 shown cross-sectional perspective are electrically connected to each other.

[0038] As noted above, the inter-trench structure 130 includes at least one N-type region 134 and at least one P-type region 136. Further, and as shown in Fig. 1, in some implementations, the inter-trench structure 130 may include a plurality of N-type regions 134 and a plurality of P-type regions 136. However, in no implementation does the inter-trench structure 130 include more P-type regions 136 than N-type regions 134. In other words, while the number of N-type regions 134 may be equal to or exceed the number of P-type regions 136, the number of N-type regions 134 is never less than the number of P-type regions 136.

[0039] For example, in one implementation, the inter-trench structure 130 includes an N-type region 134 adjacent to a P-type region 136. In another example implementation, the inter-trench structure 130 includes two N-type regions 134 and a P-type region 136 located between and adjacent to the two N-type regions 134. In yet another example implementation, the inter-trench structure 130 includes a plurality of N-type regions 134 and a plurality of P-type regions 136, with each P-type region 136 located between two N-type regions 134.

[0040] The N-type regions 134 and the P-type regions 136 of the inter-trench structure 130 may have a doping concentration that is greater than that of the N-type drift region 114 and less than that of the N-type cathode diffusions 128. In one implementation, the N-type regions 134 and the P-type regions 136 may have a doping concentration that is substantially equal to that of the N-type buffer layer 112. For example, the N-type regions 134 and the P-type regions 136 may have a doping concentration of approximately 1×10 15 / cm 3 up to about 1×10 16 / cm 3 while the doping concentration of the N-type drift region 114 is typically approximately 1×10 13 / cm 3 up to about 2×10 14 / cm 3 can be.

[0041] It should be noted that the inter-trench structure 130 is not located under the first control trench 120a or under the second control trench 120b. That is, the inter-trench structure 130 is located between the first control trench 120a and the second control trench 120b, but does not extend under either the first control trench 120a or the second control trench 120b. According to the exemplary Fig. 1, the inter-trench structure 130 further borders the P-type inversion region 116 and terminates in the N-type drift region 114 at depth 138, which is above the N-type buffer layer 112. In other words, in some implementations, the inter-trench structure 130 borders the P-type inversion region 116 while being spaced from the N-type buffer layer 112 by the N-type drift region 114.

[0042] As noted above, the N-type region(s) 134 and the P-type region(s) 136 are configured to substantially charge balance the inter-trench structure 130. This substantial charge balance of the inter-trench structure 130 is achieved when the surface doping density of the N-type region(s) 134, which is equal to the doping density of the N-type region(s) 134 multiplied by the area of ​​the N-type region(s) 134 (i.e., width × depth), is substantially equal to the surface doping density of the P-type region(s) 136, which is calculated accordingly. During turn-off of the bipolar semiconductor device 100, the depletion region rapidly extends from the top of the N-type drift region 114 to the N-type buffer layer 112 due to the two-dimensional rapid depletion of the N-type region(s) 134 and the P-type region(s) 136, which also enables rapid extraction of deep charge carriers.

[0043] Consequently, the delay time and turn-off time of the bipolar semiconductor device 100 can be reduced, while the voltage blocking in the off-state is enabled by the presence of the inter-trench structure 130. During turn-off, the charge-balanced inter-trench structure 130 assists in the removal of charge carriers from the conductivity-modulated N-type drift region 114, thereby significantly improving the switching speed and turn-off behavior of the bipolar semiconductor device 100. In other words, the charge-balanced inter-trench structure 130 enables the bipolar semiconductor device 100 to exhibit lower turn-off losses (E OFF ), a shorter delay time (T d ) and a shorter switch-off time (T f) when compared with conventional bipolar semiconductor devices, e.g., conventional IGBTs. Furthermore, the above advantages can be achieved while the on-state voltage drop (V ON ) of the bipolar semiconductor device 100 is kept at a desirably low level.

[0044] Continuing with Fig. 2, Fig. 2 illustrates a cross-sectional view showing a portion of an exemplary bipolar semiconductor device 200 with a charge-balanced inter-trench structure, according to another implementation. As in Fig. 2, the bipolar semiconductor device 200 is implemented as a vertical power device comprising a P-type anode layer 210 on a bottom surface 204 of a semiconductor substrate 202 and an N-type drift region 214 located above the P-type anode layer 210. In addition, a P-type inversion region 216 is located above the N-type drift region 214. As further shown in Fig. 2, the bipolar semiconductor device 200 includes an N-type buffer layer 212 and N-type cathode diffusions 228 and P-type contacts 218 formed in the P-type inversion region 216.

[0045] The bipolar semiconductor device 200 also includes a first control trench 220a and a second control trench 220b, each of which extends from a top surface 206 of the semiconductor substrate 202 through the P-type inversion region 216 and into the N-type drift region 214. As shown in Fig. 2, each of the first control trench 220a and the second control trench 220b is bounded by the N-type cathode diffusions 228 and includes a control trench insulator 222 and a control trench electrode 224. In addition, the bipolar semiconductor device 200 includes an inter-trench structure 230 located in the N-type drift region 214 between the first control trench 220a and the second control trench 220b. As shown in Fig. 1, the inter-trench structure 230 includes one or more N-type regions 234 and one or more P-type regions 236. One or more N-type regions 234 and one or more P-type regions 236 are configured to substantially charge balance the inter-trench structure 230.

[0046] The bipolar semiconductor device 200 generally corresponds to the bipolar semiconductor device 100 in Fig. 1. That is, the semiconductor substrate 202, the P-type anode layer 210, the N-type buffer layer 212 and the N-type drift region 214 in Fig. 2 generally correspond to the semiconductor substrate 102, the P-type anode layer 110, the N-type buffer layer 112 and the N-type drift region 114 in Fig. 1, and may jointly share any of the characteristics attributed to these corresponding features above.

[0047] In addition, the P-type inversion region 216, the P-type contacts 218 and the N-type cathode diffusions 228 in Fig. 2 respectively generally the P-type inversion region 116, the P-type contacts 118 and the N-type cathode diffusions 128 in Fig. 1 and may share any of the characteristics attributed to these corresponding features above. Furthermore, the first control trench 220a and the second control trench 220b, each of which includes the control trench insulator 222 and the control trench electrode 224, correspond to Fig. 2 respectively generally the first control trench 120a and the second control trench 120b, each of which includes the control trench insulator 122 and the control trench electrode 124, in Fig. 1, and may share any of the characteristics attributed to these corresponding features above. It is further noted that, as the bipolar semiconductor device 100 in Fig. 1, the bipolar semiconductor device 200 in Fig. 2 can take the form of an IGBT.

[0048] As in Fig. 2, the inter-trench structure 230 includes at least one N-type region 234 and at least one P-type region 236. Furthermore, and as shown in Fig. 1, in some implementations, the inter-trench structure 230 may include multiple N-type regions 234 and multiple P-type regions 236. However, in no implementation does the inter-trench structure 230 include more P-type regions 236 than N-type regions 234. In other words, while the number of N-type regions 234 may be equal to or exceed the number of P-type regions 236, the number of N-type regions 234 is never less than the number of P-type regions 236.

[0049] For example, in one implementation, the inter-trench structure 230 may include an N-type region 234 adjacent to a P-type region 236. In another example implementation, the inter-trench structure 230 may include two N-type regions 234 and a P-type region 236 located between and adjacent to the two N-type regions 234. In yet another example implementation, the inter-trench structure 230 may include multiple N-type regions 234 and multiple P-type regions 236, where each P-type region 236 is located between two N-type regions 234.

[0050] The N-type regions 234 and the P-type regions 236 generally correspond to the N-type regions 134 and the P-type region 136 in Fig. 1, and may share any of the characteristics attributed to these corresponding features above. Note that the inter-trench structure 230 is not located beneath the first control trench 220a or beneath the second control trench 220b. That is, the inter-trench structure 230 is located between the first control trench 220a and the second control trench 220b, but does not extend beneath either the first control trench 220a or the second control trench 220b.

[0051] According to the exemplary, in Fig. 2, the inter-trench structure 230 further extends through the N-type drift region 214 to abut the N-type buffer layer 212. In other words, in some implementations, the inter-trench structure 230 abuts the P-type inversion region 216 while also abutting the N-type buffer layer 212. In implementations where the inter-trench structure 230 abuts both the P-type inversion region 216 and the N-type buffer layer 212 and includes more N-type regions 234 than P-type regions 236, the N-type drift region 214 thus abuts the N-type regions 234. Thus, in some implementations where the inter-trench structure 230 is adjacent to both the P-type inversion region 216 and the N-type buffer layer 212 and includes more N-type regions 234 than P-type regions 236, no portion of the inter-trench structure 230 forms a PN junction with the N-type drift region 214.

[0052] As noted above, the N-type region(s) 234 and the P-type region(s) 236 are formed to substantially charge-balance the inter-trench structure 230. During turn-off of the bipolar semiconductor device 200, the depletion region rapidly extends from the top of the N-type drift region 214 to the N-type buffer layer 212 due to the two-dimensional rapid depletion of the N-type region(s) 234 and the P-type region(s) 236, which also enables rapid extraction of deep charge carriers.

[0053] Consequently, the delay time and turn-off time of the bipolar semiconductor device 200 can be reduced, while the voltage blocking in the off-state is enabled by the presence of the inter-trench structure 230. During turn-off, the charge-balanced inter-trench structure 230 assists in the removal of charge carriers from the conductivity-modulated N-type drift region 214, thereby significantly improving the switching speed and turn-off behavior of the bipolar semiconductor device 200. In other words, the charge-balanced inter-trench structure 230 enables the bipolar semiconductor device 200 to have a lower E OFF , a shorter T d and a shorter T f when compared with conventional bipolar semiconductor devices, e.g., conventional IGBTs. Furthermore, the above advantages can be achieved while the V ONof the bipolar semiconductor device 200 is kept at a desirably low level.

[0054] Continuing with Fig. 3, Fig. 3 illustrates a cross-sectional view showing a portion of an exemplary bipolar semiconductor device 300 with a charge-balanced inter-trench structure, according to yet another implementation. As in Fig. 3, the bipolar semiconductor device 300 is implemented as a vertical power device comprising a P-type anode layer 310 at a bottom surface 304 of a semiconductor substrate 302 and an N-type drift region 314 located above the P-type anode layer 310. In addition, a P-type inversion region 316 is located above the N-type drift region 314. As shown in Fig. 3, the bipolar semiconductor device 300 includes an N-type buffer layer 312, as well as N-type cathode diffusions 328 and P-type contacts 318 formed in the P-type inversion region 316. Furthermore, the bipolar semiconductor device 300 includes an N-type enhancement layer 340 located between the N-type drift region 314 and the P-type inversion region 316.

[0055] The bipolar semiconductor device 300 also includes a first control trench 320a and a second control trench 320b, each extending from a top surface 306 of the semiconductor substrate 302 through the P-type inversion region 316, through the N-type enhancement layer 340, and into the N-type drift region 314. As shown in Fig. 3, each of the first control trench 320a and the second control trench 320b is bounded by the N-type cathode diffusions 328 and includes a control trench insulator 322 and a control trench electrode 324. In addition, the bipolar semiconductor device 300 includes an inter-trench structure 330 located in the N-type drift region 314 between the first control trench 320a and the second control trench 320b and extending to a depth 338 below the top surface 306 of the semiconductor substrate 302. As shown in Fig. 1, the inter-trench structure 330 includes one or more N-type regions 334 and one or more P-type regions 336. One or more N-type regions 334 and one or more P-type regions 336 are configured to substantially charge balance the inter-trench structure 330.

[0056] The bipolar semiconductor device 300 generally corresponds to the bipolar semiconductor device 100 in Fig. 1. That is, the semiconductor substrate 302, the P-type anode layer 310, the N-type buffer layer 312 and the N-type drift region 314 in Fig. 3 generally correspond to the semiconductor substrate 102, the P-type anode layer 110, the N-type buffer layer 112 and the N-type drift region 114 in Fig. 1 and may jointly share any of the characteristics attributed to these corresponding features above.

[0057] In addition, the P-type inversion region 316, the P-type contacts 318 and the N-type cathode diffusions 328 in Fig. 3 respectively generally the P-type inversion region 116, the P-type contacts 118 and the N-type cathode diffusions 128 in Fig. 1 and may share any of the characteristics attributed to these corresponding features above. Furthermore, the first control trench 320a and the second control trench 320b, each of which includes the control trench insulator 322 and the control trench electrode 324, correspond to Fig. 3 respectively generally the first control trench 120a and the second control trench 120b, each comprising the control trench insulator 122 and the control trench electrode 124, in Fig. 1 and may share any of the characteristics attributed above. Furthermore, it should be noted that, as the bipolar semiconductor device 100 in Fig. 1, the bipolar semiconductor device 300 in Fig. 3 can take the form of an IGBT.

[0058] As in Fig. 3, the N-type enhancement layer 340 is located between the N-type drift region 314 and the P-type inversion region 316. For example, phosphorus or arsenic dopants may be implanted into the N-type drift region 314 to create the N-type enhancement layer 340, which has a doping concentration of approximately 1×10 15 / cm 3 up to about 1×10 16 / cm 3 has.

[0059] According to the Fig. 3, the inter-trench structure 330 comprises at least one N-type region 334 and at least one P-type region 336. Furthermore, and as shown in Fig. 1, in some implementations, the inter-trench structure 330 may include a plurality of N-type regions 334 and a plurality of P-type regions 336. However, in no implementation does the inter-trench structure 330 include more P-type regions 336 than N-type regions 334. In other words, while the number of N-type regions 334 may be equal to or exceed the number of P-type regions 336, the number of N-type regions 334 is never less than the number of P-type regions 336.

[0060] For example, in one implementation, the inter-trench structure 330 may include an N-type region 334 adjacent to a P-type region 336. In another example implementation, the inter-trench structure 330 may include two N-type regions 334 and a P-type region 336 located between and adjacent to the two N-type regions 334. In yet another example implementation, the inter-trench structure 330 may include multiple N-type regions 334 and multiple P-type regions 336, where each P-type region 336 is located between two N-type regions 334.

[0061] The N-type regions 334, the P-type regions 336, and the depth 338 of the inter-trench structure 330 generally correspond to the N-type regions 134, the P-type regions 136, and the depth 138 of the inter-trench structure 130 in Fig. 1 and may share any of the characteristics attributed to these corresponding features above. It should be noted that the inter-trench structure 330 is not located under the first control trench 320a or under the second control trench 320b. That is, the inter-trench structure 330 is located between the first control trench 320a and the second control trench 320b, but does not extend under either the first control trench 320a or the second control trench 320b. According to the Fig. 3, the inter-trench structure 330 further borders the N-type enhancement layer 340 and terminates in the N-type drift region 314 at depth 338, which is above the N-type buffer layer 312. Stated differently, in some implementations, the inter-trench structure 330 borders the N-type enhancement layer 340 while being spaced from the N-type buffer layer 312 by the N-type drift region 314.

[0062] As noted above, the N-type region(s) 334 and the P-type region(s) 336 are formed to substantially charge-balance the inter-trench structure 330. During turn-on of the bipolar semiconductor device 300, the depletion region rapidly extends from the top of the N-type drift region 314 to the N-type buffer layer 312 due to the two-dimensional rapid depletion of the N-type region(s) 334 and the P-type region(s) 336, which also enables rapid extraction of deep charge carriers.

[0063] Consequently, the delay time and turn-off time of the bipolar semiconductor device 300 can be reduced, while the voltage blocking in the off-state is enabled by the presence of the inter-trench structure 330. During turn-off, the charge-balanced inter-trench structure 330 assists in the removal of charge carriers from the conductivity-modulated N-type drift region 314, thereby significantly improving the switching speed and turn-off behavior of the bipolar semiconductor device 300. In other words, the charge-balanced inter-trench structure 330 enables the bipolar semiconductor device 300 to have a lower E OFF , a shorter T d and a shorter T f when compared with conventional bipolar semiconductor devices, e.g., conventional IGBTs. The above advantages can also be achieved while the V ONof the bipolar semiconductor device 300 is kept at a desirably low level.

[0064] Referring to Fig. 4, Fig. 4 illustrates a cross-sectional view showing a portion of an exemplary bipolar semiconductor device 400 with a charge-balanced inter-trench structure, according to another implementation. As in Fig. 4, the bipolar semiconductor device 400 is implemented as a vertical power element comprising a P-type anode layer 410 at a bottom surface 404 of a semiconductor substrate 402 and an N-type drift region 414 located above the P-type anode layer 410. In addition, a P-type inversion region 416 is located above the N-type drift region 414. As shown in Fig. 4, the bipolar semiconductor device 400 includes an N-type buffer layer 412, as well as N-type cathode diffusions 428 and P-type contacts 418 formed in the P-type inversion region 416. Furthermore, the bipolar semiconductor device 400 includes an N-type enhancement layer 440 located between the N-type drift region 414 and the P-type inversion region 416.

[0065] The bipolar semiconductor device 400 also includes a first control trench 420a and a second control trench 420b, each of which extends from a top surface 406 of the semiconductor substrate 402 through the P-type inversion region 416, through the N-type enhancement layer 440, and into the N-type drift region 414. As shown in Fig. 4, each of the first control trench 420a and the second control trench 420b is bounded by the N-type cathode diffusions 428 and includes a control trench insulator 422 and a control trench electrode 424. In addition, the bipolar semiconductor device 400 includes an inter-trench structure 430 located in the N-type drift region 414 between the first control trench 420a and the second control trench 420b. As shown in Fig. 4, the inter-trench structure 430 includes one or more N-type regions 434 and one or more P-type regions 436. One or more N-type regions 434 and one or more P-type regions 436 are configured to substantially charge balance the inter-trench structure 430.

[0066] The bipolar semiconductor device 400 generally corresponds to the bipolar semiconductor device 100 in Fig. 1. That is, the semiconductor substrate 402, the P-type anode layer 410, the N-type buffer layer 412 and the N-type drift region 414 in Fig. 4 generally correspond to the semiconductor substrate 102, the P-type anode layer 110, the N-type buffer layer 112 and the N-type drift region 114 in Fig. 1 and may jointly share any of the characteristics attributed to these corresponding features above.

[0067] In addition, the P-type inversion region 416, the P-type contacts 418 and the N-type cathode diffusions 428 in Fig. 4 respectively generally the P-type inversion region 116, the P-type contacts 118 and the N-type cathode diffusions 128 in Fig. 1 and may share any of the characteristics attributed to these corresponding features above. Furthermore, the first control trench 420a and the second control trench 420b, each of which includes the control trench insulator 422 and the control trench electrode 424, correspond to Fig. 4 respectively generally the first control trench 120a and the second control trench 120b, each of which includes the control trench insulator 122 and the control trench electrode 124, in Fig. 1, and may jointly share any of the characteristics attributed to these corresponding features above.

[0068] Furthermore, the N-type enhancement layer 440 in Fig. 4 generally the N-type enhancement layer 340 in Fig. 3 and may share any of the characteristics attributed to these corresponding features above. Thus, as the bipolar semiconductor devices 100 and 300 in the respective Fig. 1 and Fig. 3, the bipolar semiconductor device 400 in Fig. 4 take the form of an IGBT.

[0069] According to the Fig. 4, the inter-trench structure 430 comprises at least one N-type region 434 and at least one P-type region 436. Furthermore, and as shown in Fig. 1, in some implementations, the inter-trench structure 430 may include multiple N-type regions 434 and multiple P-type regions 436. However, in no implementation does the inter-trench structure 430 include more P-type regions 436 than N-type regions 434. In other words, while the number of N-type regions 434 may be equal to or exceed the number of P-type regions 436, the number of N-type regions 434 is never less than the number of P-type regions 436.

[0070] For example, in one implementation, the inter-trench structure 430 may include an N-type region 434 adjacent to a P-type region 436. In another example implementation, the inter-trench structure 430 may include two N-type regions 434 and a P-type region 436 located between and adjacent to the two N-type regions 434. In yet another example implementation, the inter-trench structure 430 may include multiple N-type regions 434 and multiple P-type regions 436, where each P-type region 436 is located between two N-type regions 434.

[0071] The N-type regions 434 and the P-type regions 436 generally correspond to the N-type regions 134 and the P-type region 136 in Fig. 1 and may share any of the characteristics attributed to these corresponding features above. Note that the inter-trench structure 430 is not located beneath the first control trench 420a or beneath the second control trench 420b. That is, the inter-trench structure 430 is located between the first control trench 420a and the second control trench 420b, but does not extend beneath either the first control trench 420a or the second control trench 420b.

[0072] According to the Fig.4, the inter-trench structure 430 further extends through the N-type drift region 414 to abut the N-type buffer layer 412. In other words, in some implementations, the inter-trench structure 430 abuts the N-type enhancement layer 440 while also abutting the N-type buffer layer 412. In implementations where the inter-trench structure 430 abuts both the N-type enhancement layer 440 and the N-type buffer layer 412 and includes more N-type regions 434 than P-type regions 436, the N-type drift region 414 thus abuts the N-type regions 434. In some implementations where the inter-trench structure 430 is adjacent to both the N-type enhancement layer 440 and the N-type buffer layer 412 and includes more N-type regions 434 than P-type regions 436, no portion of the inter-trench structure 430 forms a PN junction with the N-type drift region 414.

[0073] The N-type region(s) 434 and the P-type region(s) 436 are configured to substantially charge-balance the inter-trench structure 430, as discussed above by reference to the inter-trench structure 130. Consequently, during turn-off of the bipolar semiconductor device 400, the depletion region rapidly extends from the top of the N-type drift region 414 to the N-type buffer layer 412 due to the two-dimensional rapid depletion of the N-type region(s) 434 and the P-type region(s) 436, which also enables rapid extraction of deep charge carriers.

[0074] Consequently, the delay time and turn-off time of the bipolar semiconductor device 400 can be reduced, while the off-state blocking voltage is enabled by the presence of the inter-trench structure 430. During turn-off, the charge-balanced inter-trench structure 430 assists in the removal of charge carriers from the conductivity-modulated N-type drift region 414, thereby significantly improving the switching speed and turn-off behavior of the bipolar semiconductor device 400.

[0075] Thus, the present application discloses implementations of a bipolar semiconductor device having a charge-balanced inter-trench structure. As disclosed in the present application, incorporating such a charge-balanced inter-trench structure into the bipolar semiconductor device enables the bipolar semiconductor device to have a lower E OFF , a shorter Td and a shorter T f when compared to conventional components, such as conventional IGBTs. Furthermore, these advantages can be achieved while the V ON of the bipolar semiconductor component is kept at a desirably low level.

[0076] From the above description, it is apparent that various techniques may be used to implement the concepts described in the present application without departing from the scope of those concepts. While the concepts have been described with specific reference to particular implementations, one skilled in the art will recognize that changes in form and detail may be made without departing from the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It is to be understood that the present application is not limited to the particular implementations described herein, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.

Claims

[1] A bipolar semiconductor device (100, 200, 300, 400) comprising: a drift region (114) having a first conductivity type located above an anode layer (110) having a second conductivity type opposite to the first conductivity type; first and second control trenches (120a, 120b) extending through an inversion region (116) having the second conductivity type into the drift region (114), each of the first and second control trenches (120a, 120b) being bounded by a cathode diffusion (128); and an intermediate trench structure (130) located in the drift region (114) between the first and second control trenches (120a, 120b), wherein the inter-trench structure (130) comprises at least one first conductivity region (134) having the first conductivity type and at least one second conductivity region (136) having the second conductivity type, wherein the at least one first conductivity region (134) and the at least one second conductivity region (136) have a doping concentration that is greater than that of the drift region (114), and wherein the at least one first conductivity region (134) and the at least one second conductivity region (136) are configured to substantially charge balance the inter-trench structure (130). [2] The bipolar semiconductor device (100, 200, 300, 400) of claim 1, wherein the inter-trench structure (130) comprises two first conductivity regions (134) and a second conductivity region (136), the second conductivity region (136) being located between the two first conductivity regions (134). [3] The bipolar semiconductor device (100, 200, 300, 400) according to claim 1 or 2, wherein the inter-trench structure (130) comprises a first plurality of the first conductivity regions (134) and a second plurality of the second conductivity regions (136), the first plurality being greater than the second plurality. [4] The bipolar semiconductor device (100, 200, 300, 400) according to any one of the preceding claims, wherein the inter-trench structure (130) comprises a first plurality of the first conductivity regions (134) and a second plurality of the second conductivity regions (136), and wherein each of the second conductivity regions (136) is located between two of the first conductivity regions (134). [5] The bipolar semiconductor device (100, 200, 300, 400) according to any one of the preceding claims, wherein the inter-trench structure (130) is not located under the first control trench (120a) or the second control trench (120b). [6] The bipolar semiconductor device (100, 200, 300, 400) according to any one of the preceding claims, wherein the inter-trench structure (130) is adjacent to the inversion region (116). [7] The bipolar semiconductor device (100, 200, 300, 400) according to any one of the preceding claims, wherein the drift region (114) is adjacent to the at least one first conductivity region (134) but not adjacent to the at least one second conductivity region (136). [8] The bipolar semiconductor device (300, 400) according to any one of the preceding claims, further comprising an enhancement layer (340) having the first conductivity type located between the drift region (114) and the inversion region (116), wherein the inter-trench structure (130) is adjacent to the enhancement layer (340). [9] The bipolar semiconductor device (100, 300) according to any one of the preceding claims, further comprising a buffer layer (112) having the first conductivity type located between the anode layer (110) and the drift region (114), wherein the inter-trench structure (130) is spaced from the buffer layer (112) by the drift region (114). [10] The bipolar semiconductor device (200, 400) according to any one of the preceding claims, further comprising a buffer layer (112) having the first conductivity type located between the anode layer (110) and the drift region (114), wherein the inter-trench structure (130) is adjacent to the buffer layer (112). [11] An insulated gate bipolar transistor, IGBT, (100, 200, 300, 400), comprising: a drift region (114) having a first conductivity type located above a collector (110) having a second conductivity type opposite to the first conductivity type; first and second gate trenches (120a, 120b) extending through a base (116) having the second conductivity type into the drift region (114), each of the first and second gate trenches (120a, 120b) being bounded by an emitter diffusion; and an intermediate trench structure (130) located between the first and second gate trenches (120a, 120b), wherein the inter-trench structure (130) comprises at least one first conductivity region (134) having the first conductivity type and at least one second conductivity region (136) having the second conductivity type, wherein the at least one first conductivity region (134) and the at least one second conductivity region (136) have a doping concentration that is greater than that of the drift region (114), and wherein the at least one first conductivity region (134) and the at least one second conductivity region (136) are configured to substantially charge balance the inter-trench structure (130). [12] The IGBT of claim 11, wherein the inter-trench structure (130) comprises two first conductivity regions (134) and a second conductivity region (136), the second conductivity region (136) being located between the two first conductivity regions (134). [13] The IGBT (100, 200, 300, 400) according to claim 11 or 12, wherein the inter-trench structure (130) comprises a first plurality of the first conductivity regions (134) and a second plurality of the second conductivity regions (136), the first plurality being greater than the second plurality. [14] The IGBT (100, 200, 300, 400) according to any one of claims 11 to 13, wherein the inter-trench structure (130) comprises a first plurality of the first conductivity regions (134) and a second plurality of the second conductivity regions (136), and wherein each of the second conductivity regions (136) is located between two of the first conductivity regions (134). [15] The IGBT (100, 200, 300, 400) according to any one of claims 11 to 14, wherein the inter-trench structure (130) is not located under the first gate trench (120b) or the second gate trench (120b). [16] The IGBT (100, 200, 300, 400) according to any one of claims 11 to 15, wherein the inter-trench structure (130) is adjacent to the base. [17] The IGBT (100, 200, 300, 400) according to any one of claims 11 to 16, wherein the drift region (114) is adjacent to the at least one first conductivity region (134) but not adjacent to the at least one second conductivity region (136). [18] The IGBT (300, 400) according to any one of claims 11 to 17, further comprising an enhancement layer (340) having the first conductivity type located between the drift region (114) and the base (116), wherein the inter-trench structure (130) is adjacent to the enhancement layer (340). [19] The IGBT (100, 300) according to any one of claims 11 to 18, further comprising a buffer layer (112) having the first conductivity type located between the collector (110) and the drift region (114), wherein the inter-trench structure (130) is spaced from the buffer layer (112) by the drift region (114). [20] The IGBT (200, 400) according to any one of claims 11 to 19, further comprising a buffer layer (112) having the first conductivity type located between the collector (110) and the drift region (114), wherein the inter-trench structure (130) is adjacent to the buffer layer (112).

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