Layout review system and procedures

Abstract

Method (300) for checking layout, comprising: Assigning (S341) a plurality of groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) indicating layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) of interconnect layers (M1, M2, M3) to a circuit (200) in order to determine layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102) of the circuit (200), wherein a first group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a first terminal in the circuit (200), and the assignment of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprises: assigning, in a first predetermined sequence and within a first region (860, 960, 1060, 1160) of a first element (M1) in the circuit (200), at least one group (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprising the first group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) to the first terminal, wherein the first terminal is a terminal of the first element (M1), and a second group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a second terminal in the circuit (200), and the assignment of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprises: assigning, in a second predetermined sequence and within a second region (861, 961, 1061, 1161) of a second element (M2) in the circuit (200), at least one group (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprising the second group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) to the second terminal, wherein the second terminal is a terminal of the second element (M2), Extracting (S342) a plurality of layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) from a layout design (240, 520) for the circuit (200), Comparing (S343) the layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) with the layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102), and Generating data indicative of the layout design (240, 520) for manufacturing the circuit (200) under a condition that the layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) conform to the layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102).

Description

BACKGROUND

[0001] In semiconductor manufacturing processes, a single layer is sometimes formed using multiple layout structures to increase the spatial resolution of the layer. Each of the multiple layout structures is assigned to different groups. This assignment is performed by a circuit designer or layout designer, for example, by executing a software program.

[0002] US 2013 / 0320555 and US 2015 / 0121317 describe semiconductor manufacturing processes in which layout structures of a single interconnect layer are produced by double or multiple patterning (DPT, MPT). US 9 053 288 B1 describes a method for checking circuit layouts for directly imposed constraints resulting from multiple patterning. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is a schematic diagram of a design system according to various embodiments of the present disclosure; Fig. 2A is a schematic diagram of a circuit according to various embodiments of the present disclosure; Fig. Figure 2B shows a predefined description in a netlist file that describes the circuit in Fig. 2A, according to some embodiments of the present disclosure; Fig. Figure 2C is a schematic diagram showing a layout design corresponding to the circuit in Fig. 2A, according to various embodiments of the present disclosure; Fig. 3 is a flowchart of a design process that illustrates the design system in Fig. 1 used according to various embodiments of the present disclosure; Fig. 4 is a flowchart of an operation of the method in Fig. 3 according to various embodiments of the present disclosure; Fig. Figure 5A shows a predefined description that specifies layout constraints for the circuit in Fig. 2A includes, according to various embodiments of the present disclosure; Fig. Figure 5B is a schematic diagram showing a layout design corresponding to the circuit in Fig. 2A and shows layout structures of the layout design, according to various embodiments of the present disclosure; Fig. Figure 6A shows a predefined description that specifies layout constraints for the circuit in Fig. 2A includes, according to various embodiments of the present disclosure; Fig. Figure 6B is a schematic diagram showing the layout design in Fig. 5B and layout structures of the layout design, according to various embodiments of the present disclosure; Fig. Figure 7A shows a predefined description that specifies layout constraints for the circuit in Fig. 2A includes, according to alternative embodiments of the present disclosure; Fig. Figure 7B is a schematic diagram showing the layout design in Fig. 5B and layout structures of the layout design, according to alternative embodiments of the present disclosure; Fig. Figure 8A shows a predefined description that specifies layout constraints for the circuit in Fig. 2A includes, according to some other embodiments of the present disclosure; Fig. Figure 8B is a schematic diagram showing the layout design in Fig. 2C, in Fig. 5 and layout structures of the layout design, according to some other embodiments of the present disclosure; Fig. Figure 9A shows a predefined description that specifies layout constraints for the circuit in Fig. 2A includes, according to further alternative embodiments of the present disclosure; Fig. Figure 9B is a schematic diagram showing the layout design in Fig. 5B and layout structures of the layout design, according to various embodiments of the present disclosure; Fig. Figure 10A shows a predefined description that specifies layout constraints for the circuit in Fig. 2A includes, according to further various embodiments of the present disclosure; Fig. 10B is a schematic diagram showing the layout design in Fig. 5B and layout structures of the layout design, according to further various embodiments of the present disclosure; Fig. 11A shows a predefined description that specifies layout constraints for the circuit in Fig. 2A includes, according to other various embodiments of the present disclosure; Fig. 11B is a schematic diagram showing the layout design in Fig. 5B and layout structures of the layout design, according to other various embodiments of the present disclosure; and Fig. 12 shows a schematic diagram showing a predetermined description illustrating the circuit in Fig. 2A and displays the layout constraints in a netlist file, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters throughout the various examples.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any terms discussed herein, is merely illustrative and in no way limits the scope and meaning of the disclosure or any term explained as an example. Likewise, the present disclosure is not limited to the various embodiments set forth in this specification.

[0006] Although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be referred to as a second element, and likewise, a second element could be referred to as a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.

[0007] Fig. 1 is a schematic diagram of a design system 100 according to some embodiments of the present disclosure.

[0008] As in Fig. 1 for illustrative purposes, the design system 100 includes a processor 110, a memory 120, and input / output (I / O) interfaces 130. The processor 110 is coupled to the memory 120 and the I / O interfaces 130. In various embodiments, the processor 110 is a central processing unit (CPU), an application-specific integrated circuit (ASIC), a multi-processor, a distributed processing system, or any suitable processing unit. Various circuits or devices for implementing the processor 110 are within the scope of the present disclosure.

[0009] Memory 120 stores one or more program codes to support the development of integrated circuits. For illustration, memory 120 stores program code encoded with a set of instructions for verifying layout structures of the integrated circuits. Processor 110 is capable of executing the program codes stored in memory 120, and the layout verification operations can be performed automatically.

[0010] In some embodiments, memory 120 is a non-transitory, computer-readable storage medium encoded with, i.e., storing, a set of executable instructions for verifying layout structures. To illustrate, memory 120 stores executable instructions for performing operations, for example, operation S340 described in Fig. 4. In some embodiments, the computer-readable storage medium is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, the computer-readable storage medium includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, random access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments that utilize optical disks, the computer-readable storage medium includes a CD-ROM (Compact Disc Read-Only Memory), a CD-RW (Compact Disc Read / Write), and / or a DVD (Digital Video Disc).

[0011] The I / O interfaces 130 receive inputs or commands from various control devices operated, for example, by a circuit designer and / or a layout designer. Accordingly, the design system 100 can be influenced by inputs or commands received via the I / O interfaces 130. In some embodiments, the I / O interfaces 130 include a display configured to indicate the execution status of the program code. In some embodiments, the I / O interfaces 130 include a graphical user interface (GUI). In some other embodiments, the I / O interfaces 130 include a keyboard, keypad, mouse, trackball, trackpad, touchscreen, cursor direction keys, or a combination thereof to communicate information and commands to the processor 110.

[0012] Fig. 2A is a schematic diagram of a circuit 200 according to some embodiments of the present disclosure. To illustrate a layout verification method 300 of Fig. 3, various terms or components related to layout structures are explained with reference to Fig. 2A introduced.

[0013] The circuit 200 includes a switch M1 and a switch M2. For example, in some embodiments, the switch M1 and switch M2 are implemented with N-type metal-oxide-silicon field-effect transistors (MOSFETs). The switch M1 includes four terminals defined as a gate (labeled G1), a drain (labeled D), a source (labeled S1), and a bulk (labeled B1). Similarly, the switch M2 includes four terminals defined as a gate (labeled G2), a drain (labeled D), a source (labeled S2), and a bulk (labeled B2). As illustrated in Fig. As shown in Figure 2A, terminal D of switch M1 is coupled to terminal D of switch M2.

[0014] Now reference is made to both Fig. 2A as well as Fig. 2B taken. Fig. Figure 2B shows a description in a netlist file 220 that describes the circuit 200 in Fig. 2A, according to some embodiments of the present disclosure. In some embodiments, a circuit designer is able to design circuit 200 by describing circuit 200 via netlist file 220. In some embodiments, the contents of netlist file 220 conform to a predetermined syntax type capable of capturing and / or designing a circuit in a descriptive format recognizable by design system 100. In some embodiments, the predetermined syntax type is BERKLEY-SPICE syntax. In some other embodiments, the predetermined syntax type is HSPICE syntax.

[0015] As illustrated in Fig. 2B, the description of the netlist file 220 comprises sections 221 to 223. Section 221, which uses the statement ".subckt", and section 223, which uses the statement ".ends", declare a circuit designated as "200" and its terminals D, G1, G2, S1, S2, B1, and B2. Section 222 further declares that the circuit 200 comprises two N-type transistors M1 and M2 (i.e., switches M1 and M2 in Fig. 2A) by using the parameter "nch," and their connections and sizes by using the parameters "W=3" and "L=1." In some embodiments, the circuit designer is able to create and / or edit the netlist file 220 via the design system 100. In some embodiments, the memory 120 stores one or more program codes that are executed to perform circuit simulations and analysis according to the netlist file 220.

[0016] The circuit 200 in Fig. 2A is provided for illustrative purposes. Various circuits or semiconductor devices for a layout design are within the scope of the present disclosure. Accordingly, the description in the netlist file 220 in Fig. 2B and a layout draft described below are also provided for illustrative purposes.

[0017] Now reference is made to Fig. 2C taken. Fig. Figure 2C is a schematic diagram showing a layout design 240 corresponding to the circuit 200 in Fig. 2A, according to some embodiments of the present disclosure.

[0018] In some embodiments, the layout design 240 includes multiple layout structures corresponding to semiconductor layers or metal layers in a fabrication. To illustrate, as shown in Fig. 2C, the multiple layout structures oxide definition regions (OD regions) 240A-240B, gate regions 240C-240D, interconnect layers 240E, and via plugs 240F are shown. Gate region 240C corresponds to gate G1 of switch M1, and gate region 240D corresponds to gate G2 of switch M2. Region 240A includes two sections 241 and 242 on two sides of gate region 240C, as shown in Fig. 2C. Section 241 of the OD region 240A corresponds to the source S1 of the switch M1. Section 242 of the OD region 240A corresponds to the drain D of the switch M1. The region 240B also includes two sections 243 and 244 on two sides of the gate region 240D, as shown in Fig. 2C. Portion 243 of OD region 240B corresponds to source S1 of switch M2. Portion 244 of OD region 240B corresponds to drain D of switch M2. Interconnect layers 240E and via plugs 240F are formed to electrically couple drain D of switch M1 to drain D of switch M2.

[0019] In some embodiments, the interconnect layers 240E are formed with one or more metal layers. For illustration, the interconnect layers 240E include a metal layer Metal-1 and a metal layer Metal-2. Each of the metal layer Metal-1 and the metal layer Metal-2 is formed with multiple groups of layer structures. For illustration, Fig. 2C, the layout structures for the metal layer Metal-1 are assigned to group M1_A and group M1_B, where the group M1_A and the group M1_B are mutually exclusive. For example, the metal layer Metal-1 is fabricated using a double patterning technology. The metal layer Metal-1 is formed with two separate groups M1_A and M1_B. In some embodiments, the layout structures corresponding to the groups M1_A and M1_B of the metal layer Metal-1 are formed on different masks. The layout structures of the metal layer Metal-2 are assigned to the group M2_A. In various embodiments, the design system 100 uses different color patterns to represent the group M1_A, the group M1_B, and the group M2_A.

[0020] In some applications, the layout design 240 is designed in compliance with certain design rules. For example, a minimum distance between two lines formed with the same group of metal layers is limited. To minimize the area of the circuit 200 in Fig. 2A, the terminal D of the switch M1 is coupled to the switch M2 using a different group of the metal layer. Furthermore, the terminal D of the switch M2 is coupled to the switch M1 using a different group of the metal layer. For illustration, as in Fig. As shown in Figure 2C, terminal D of switch M1 is coupled to terminal D of switch M2 using group M1_A of metal layer Metal-1. Terminal D of switch M2 is coupled to terminal D of switch M1 using group M1_B of metal layer Metal-1.

[0021] In various embodiments, at least one of the I / O interfaces 130 in Fig. 1 the netlist file 220 in Fig. 2B. In some embodiments, a circuit designer and / or a layout designer are able to specify layout constraints for the circuit 200 in Fig. 2A via at least one of the I / O interfaces 130 in Fig. 1. In some embodiments, the layout constraints specify how the multiple layout structures of one or more terminals in the layout design 240 in Fig. 2C. In some embodiments, the processor 110 operates together with the memory 120 in Fig. 1 based on the received netlist file 220 and the layout constraints. Accordingly, the design system 100 is able to convert the multiple layout structures into the layout design 240 into Fig. 2C with the layout constraints to check whether the layout design 240 complies with the Fig. 2C.

[0022] The arrangement of the layout structures in Fig. 2C, which corresponds to the circuit 200 in Fig. 2A are provided for illustrative purposes. Various arrangements of the layout structures are within the scope of the present disclosure.

[0023] In some embodiments, at least one group of the layout structures is associated with at least one of the terminals of the circuit 200 in Fig. 2A. In some embodiments, the terminals of the circuit 200 are assigned to the netlist file 220 in Fig. 2B. In some embodiments, each terminal of circuit 200 is formed with at least one terminal of one or more devices, elements, and / or other suitable semiconductor components. For illustration, as in Fig. 2A, the terminal D of the circuit 200 is formed with the drain terminals D of two switches M1 and M2.

[0024] The above-mentioned definitions and / or arrangements of the circuit terminals are provided for illustrative purposes only. Various definitions and / or arrangements of the circuit terminals are within the scope of the present disclosure.

[0025] Now reference is made to Fig. 3 taken. Fig. 3 is a flowchart of a design process 300 that the design system 100 implements in Fig. 1, according to some embodiments of the present disclosure. For ease of understanding, the design method 300 is described below as an example with reference to Fig. 1 and Fig. 2A to 2C. The design method 300 may also be applied to other embodiments of the present disclosure, including the embodiments in Fig. 5A to 11B, may be applied.

[0026] The design method 300 includes operations S310 to S360. In operation S310, the netlist file and the layout constraints for the circuit are entered into the design system. For illustration, the netlist file 220 is Fig. 2B and the layout constraints for the circuit 200 in Fig. 2A into the design system 100 in Fig. 1 entered.

[0027] In some embodiments, the circuit 200 in the netlist file 220 is described by various circuit simulation tools available in the design system 100. In various embodiments, a predetermined description comprising layout constraints for the circuit 200 is determined by various circuit simulation tools and / or EDA (electronic system design automation) tools available in the design system 100. For illustration, the layout constraints are defined in a predetermined description, for example, 500 in Fig. 5A, Fig. 600 in Fig. 6A, Fig. 700 in Fig. 7A, Fig. 800 in Fig. 8A, Fig. 900 in Fig. 9A, Fig. 1000 in Fig. 10A and Fig. 1100 in Fig. 11A below.

[0028] In operation S320, the layout design corresponding to the circuit is determined and entered into the design system. For illustration, the layout design 240 is Fig. 2C, which corresponds to the circuit 200 in Fig. 2A, and incorporated into the design system 100 in Fig. 1. In some embodiments, the layout design 240 is manually designed by a layout designer using the EDA tools available in the design system 100. In various embodiments, the layout design 240 is generated according to the netlist file 220 by an APR (auto place and route) tool available in the design system 100.

[0029] In operation S330, the design system determines whether a layout versus schematic (LCS) verification has been passed. For illustration, the design system 100 performs Fig. 1 performs a LVS (Layout versus Schematic) verification to check whether the layout design 240 in Fig. 2C with the circuit 200 in Fig. 2A. If so, operation S340 is performed. Otherwise, operation S350 is performed. In some embodiments, the WMS verification is performed by the EDA tool available in the design system 100.

[0030] In some embodiments, LVS verification includes the following operations. The design system 100 extracts the interconnections of circuit 200 from the netlist file 220 and extracts the multiple layout structures from the layout design 240. The design system 100 then determines whether the circuit formed according to the multiple layout structures matches the interconnections of circuit 200. If the circuit formed according to the multiple layout structures matches the interconnections of circuit 200, the processor 110 determines that the LVS verification passed. Otherwise, the processor 110 determines that the LVS verification failed.

[0031] If the LVS verification has been passed, the processor determines at operation S340 whether the multiple layout structures conform to the layout constraints. If so, operation S340 is performed. Otherwise, operation S350 is performed. For illustration, the processor 110 executes Fig. 1 program codes to create layout structures of the circuit 200 from the layout design 240 in Fig. 2C. In some embodiments, the layout structures comprise one or more interconnect layers in the layout design 240. The processor 110 then compares the layout structures of the circuit 200 with the layout constraints to determine whether the layout structures satisfy the layout constraints. The associated operations are described below with reference to Fig. 4 described.

[0032] If the multiple layout structures do not meet the layout constraints, in operation S350, the layout design corresponding to the circuit is revised to pass the LVS verification in operation S330 and / or to meet the layout constraints in operation S340. After operation S350 is performed, the processor 110 returns to perform operation S320. To illustrate, if the layout structures resulting from the layout design 240 in Fig. 2C do not meet the layout constraints, the layout draft 240 is revised to pass the LVS verification and / or meet the layout constraints.

[0033] If the multiple layout structures satisfy the layout constraints, the design system performs an RC extraction (RCE) in operation S360 to analyze the circuit with parasitic effects. For illustration, after the layout constraints have been satisfied, the design system 100 is in Fig. 1 able to perform the RCE to switch the circuit 200 into Fig. 2A using the EDA tool available in the design system 100.

[0034] In some embodiments, RCE includes the following operations. The design system 100 extracts parasitic components of the circuit 200 from the multiple layout structures. The design system 100 then performs circuit simulations and analysis according to the netlist file 220 and the parasitic components. In some embodiments, the EDA tool extracts the parasitic components, including, for example, capacitances, resistances, and inductances, within layers of the layout design 240. Accordingly, at least one parasitic effect in the circuit 200 can be calculated.

[0035] After operation S2340 is performed and if the multiple layout structures satisfy the layout constraints, in some embodiments, the processor 110 generates data that represents the layout design 240 in Fig. 2C. In further embodiments, the data that defines the layout design 240 in Fig. 2C, for at least one tool that implements a semiconductor process for manufacturing the circuit 200 based on the multiple layout structures of the layout design 240 in Fig. 2C. In some embodiments, the tool discussed above includes one or more semiconductor manufacturing devices for performing semiconductor fabrication on a wafer.

[0036] One skilled in the art will recognize that an order of operations in method 300 is adaptable. One skilled in the art will further recognize that additional operations may be included in design method 300 without departing from the scope of the present disclosure.

[0037] To facilitate understanding, the design method 300 is described below as an example with reference to Fig. 5B. In some embodiments, the design method 300 is applicable to multi-layout structures having numerous interconnect layers, where each of the interconnect layers is assigned to multiple groups. To illustrate, the interconnect layers include metal layers Metal-1, Metal-2, and Metal-3, as described below in Fig. 5B. The metal layer Metal-1 is assigned to group M1_A and group M1_B. The metal layer Metal-2 is assigned to group M2_A and a group M2_B. The metal layer Metal-3 is assigned to group M3_A and a group M3_B.

[0038] For illustrative purposes, the following embodiments are described with the metal layers Metal-1, Metal-2, and Metal-3, but the present disclosure is not limited in this regard. The number and configuration of the interconnect layers and groups in the following embodiments are provided for illustrative purposes. Various numbers and configurations of the interconnect layers and groups in the following embodiments are within the scope of the present disclosure.

[0039] Fig. 4 is a flowchart of operation S340 of method 300 in Fig. 3, according to some embodiments of the present disclosure. Fig. 5A shows a predefined description 500 that defines layout constraints for the circuit 200 in Fig. 2A, according to some embodiments of the present disclosure. Fig. 5B is a schematic diagram illustrating a layout design 520 corresponding to the circuit 200 in Fig. 2A, and shows layout structures 540 of the layout design 520, according to some embodiments of the present disclosure. Operations performed in operation S340 in Fig. 4 are described below with reference to Fig. 5A-5B.

[0040] Operation S340 includes sub-operations S341 to S343. In sub-operation S341, the layout constraints are determined by the predefined description. For illustration, in some embodiments, the contents of the predefined description 500 are located in Fig. 5A in a form that can match a given syntax type.

[0041] As in Fig. 5A, the predetermined description 500 includes two coding sections 501 and 502. The coding section 501 is configured to assign the groups of the link layers to the port D of the switch M1 in a predetermined sequence. In other words, the coding section 501 specifies the layout constraints for the port D of the switch M1. For illustration, the coding section 501 specifies that the port D of the switch M1 is sequentially coupled to the group M1_A, the group M2_B, and the group M1_B. With such constraints, the port D of the switch M1 is expected to be coupled to the group M1_A, to the group M2_B via the group M1_A, and further to the group M1_B via the group M1_A and the group M2_B.

[0042] The coding section 502 is configured to assign the link layer groups to the port D of the switch M2 in a predetermined sequence. In other words, the coding section 502 specifies the layout constraints for the port D of the switch M2. For illustration, the coding section 502 specifies that the port D of the switch M2 is sequentially coupled to the group M1_B and the group M2_B. With such constraints, the port D of the switch M2 is expected to be coupled to the group M1_B and to the group M2_B through the group M1_B.

[0043] With further reference to Fig. 4, in suboperation S342, the processor extracts layout structures from the layout design. In suboperation S343, the processor compares the layout structures 540 with the layout constraints. For illustration, the processor 110 extracts in Fig. 1 the layout structures 540 in Fig. 5B from layout draft 520 in Fig. 5B and then compares the layout structures 540 with the layout constraints specified in the given description 500 in Fig. 5A are defined.

[0044] In some embodiments, the layout structures 540 include the interconnect layers that are coupled between the switches M1 and M2 in the layout design 520. For illustrative purposes, extracted as in Fig. 5B, the processor 110 sequentially extracts the groups of interconnect layers connected from the D port of switch M1 to the D port of switch M2, as shown in a portion 541 of the layout structures 540. The D port of switch M1 is coupled to the D port of switch M2 via the groups M1_A, M2_B, M1_B, M2_B, M3_A, M2_B, and M1_B in sequence. The processor 110 also extracts the groups of interconnect layers connected from the D port of switch M2 to the D port of switch M1, as shown in a portion 542 of the layout structures 540.

[0045] In addition, the processor 110 compares the section 541 in Fig. 5B with the coding section 501 in Fig. 5A. To illustrate, in the coding section 501, group M1_A is followed by group M2_B, and group M2_B is followed by group M1_B. In section 541, group M1_A is also followed by group M2_B, and group M2_B is also followed by group M1_B. By comparison, the sequence of the corresponding layout structures described in section 541 matches the sequence of corresponding groups described in the coding section 501. Accordingly, the processor 110 determines that section 541 of the layout structures 540 for switch M1 satisfies the layout constraints because the sequence of the groups in section 541 is the same as that of the groups in the coding section 501.

[0046] The processor 110 also compares the section 542 in Fig. 5B with the coding section 502 in Fig. 5A. For illustration, in the coding section 502, the group M1_B is followed by the group M2_B. In section 542, the group M1_B is also followed by the group M2_B. By comparison, the sequence of the corresponding layout structures described in section 542 matches the sequence of corresponding groups described in the coding section 502. Accordingly, the processor 110 determines that section 542 of the layout structures 540 for the switch M2 satisfies the layout constraints because the sequence of the groups in section 542 is the same as that of the groups in the coding section 502.

[0047] Now reference is made to Fig. 6A and Fig. 6B taken. Fig. 6A shows a predefined description 600 that defines layout constraints for the circuit 200 in Fig. 2A, according to various embodiments of the present disclosure. Fig. 6B is a schematic diagram illustrating the layout design 520 in Fig. 5B and layout structures 640 of the layout design 520, according to various embodiments of the present disclosure.

[0048] In some embodiments, the layout constraints are configured to assign the interconnect layers to the D port of switch M1 and the D port of switch M2, respectively, according to the numerical order of the interconnect layers. To illustrate, as shown in Fig. As shown in Figure 6A, the predetermined description 600 includes two coding sections 601 and 602. Coding section 601 assigns the groups of interconnect layers to the D terminal of switch M1 in ascending numerical order. For example, coding section 601 assigns Metal-1, then Metal-2, then Metal-3, and so on. Coding section 602 similarly assigns the groups of interconnect layers to the D terminal of switch M2 in ascending numerical order.

[0049] For illustration, Fig. 6A, group M1_A and group M2_B are sequentially assigned to terminal D of switch M1. Group M1_B and group M2_B are sequentially assigned to terminal D of switch M2.

[0050] Additionally, in some embodiments, the processor 110 extracts the layout structures 640 from the layout design 520 in ascending numerical order. For example, the processor 110 extracts Metal-1, then Metal-2, then Metal-3, and so on. For illustrative purposes, as in Fig. 6B, the processor 110 determines that the upper group of the interconnect layer on the D terminals of both switches M1 and M2 is M3_A. The processor 110 then extracts the groups of interconnect layers connected from the D terminal of switch M1 to the upper group M3_A in ascending numerical order, as shown in a section 641 of the layout structures 640. The D terminal of switch M1 is coupled to the upper group M3_A via the groups M1_A, M2_B, M1_B, and M2_B. The processor 110 thus sorts these groups in ascending numerical order, as shown in section 641, according to the numerical order of the metal layers Metal-1 through Metal-3.

[0051] The processor 110 also generates a section 642 of the layout structures 640 by extracting the groups of the interconnection layers connected from the section D of the switch M2 to the upper group M3_A in ascending numerical order. Accordingly, the processor 110 is able to divide the coding sections 601 and 602 into Fig. 6A with section 641 or 642 in Fig. 6B to verify whether the layout design 520 complies with the layout constraints.

[0052] To illustrate, in coding section 601, group M1_A is followed by group M2_B. In section 641, group M1_A is also followed by group M2_B via group M1_B. Accordingly, processor 110 determines that section 641 of layout structures 640 for switch M1 satisfies the layout constraints because the sequence of groups in section 641 is the same as that of the groups in coding section 601.

[0053] For further illustration, in coding section 602, group M1_B is followed by group M2_B. In section 641, group M1_A is also followed by group M2_B. Accordingly, processor 110 determines that section 641 of layout structures 640 for switch M1 satisfies the layout constraints because the sequence of groups in section 641 is the same as that of the groups in coding section 601.

[0054] Now reference is made to Fig. 7A and Fig. 7B taken. Fig. 7A shows a predefined description 700 that defines layout constraints for the circuit 200 in Fig. 2A, according to alternative embodiments of the present disclosure. Fig. 7B is a schematic diagram illustrating the layout design 520 in Fig. 5B and layout structures 740 of layout design 520, according to alternative embodiments of the present disclosure.

[0055] Compared with Fig. 6A-6B, in some embodiments, a coding portion 701 of the predetermined description 700 assigns the groups of interconnect layers, in descending numerical order, to the D port of switch M1. For example, the coding portion 701 assigns Metal-3, then Metal-2, then Metal-1, and so on. A coding portion 702 of the predetermined description 700 similarly assigns the groups of interconnect layers, in descending numerical order, to the D port of switch M2.

[0056] For illustration, Fig. 7A, group M2_B and group M1_A are sequentially assigned to terminal D of switch M1. Group M2_B and group M1_B are sequentially assigned to terminal D of switch M2. As shown in Fig. 7B, the processor 110 extracts the groups connected from the upper group M3_A to the terminal D of the switch M1. Then, the processor 110 sorts the groups in the layout structures in descending numerical order, as shown in a section 741 of the layout structures 740. The processor 110 further extracts the groups in the layout structures connected from the upper group M3_A to the terminal D of the switch M2. Then, the processor 110 sorts the groups in the layout structures in descending numerical order, as shown in a section 742 of the layout structures 740. Consequently, the processor 110 is able to code the coding sections 701 and 702 in Fig. 7A with section 741 or 742 in Fig. 7B to check whether the layout design 520 complies with the layout constraints. The manner of checking whether the layout design 520 complies with the layout constraints is described with regard to Fig. 7A and Fig. 7B is similar to the manner discussed above, which is why it will not be discussed further here.

[0057] The predetermined sequences, including ascending numerical order and / or descending numerical order, are provided for illustrative purposes only. Various types of orders are within the scope of the present disclosure.

[0058] Now reference is made to Fig. 8A and Fig. 8B taken. Fig. 8A shows a predefined description 800 that defines layout constraints for the circuit 200 in Fig. 2A, according to some other embodiments of the present disclosure. Fig. Figure 8B is a schematic diagram showing the layout design 240 in Fig. 2C and layout structures 840 of the layout design 240, according to some other embodiments of the present disclosure.

[0059] In some embodiments, the layout constraints are configured to be within a region 860, as in Fig. 8B, to assign a group of one of the connection layers to the terminal D of the switch M1, and to be located within an area 861, as shown in Fig. 8B, another group of one of the interconnect layers is assigned to terminal D of switch M2.

[0060] For illustration purposes, as in Fig. 8A, the predetermined description 800 coding sections 801 and 802. The coding section 801 specifies, using the parameter "approximately 0.1 μm," that the group M1_A of the metal layer Metal-1 is assigned to the terminal D of the switch M1 within the region 860. The parameter "approximately 0.1 μm" specifies that the area of the region 860 is approximately 0.1*0.1 μm. 2 As in Fig. 8B, in some embodiments, the central position of region 860 is set to an intersection point of the gate region 240C and the oxide definition region 240A of the switch M1.

[0061] The coding section 802 specifies, using the parameter "approximately 0.1 μm," that the group M1_B of the metal layer Metal-1 is assigned to the terminal D of the switch M2 within the region 861. Accordingly, the area of the region 861 is specified to be approximately 0.1*0.1 μm. 2In some embodiments, the central position of region 861 is set to an intersection point of the gate region 240D and the oxide definition region 240B of switch M2.

[0062] Compared with Fig. 5B, the processor 110 extracts the layout structures within the regions 860 and 861. For illustration, as in Fig. 8B, the processor 110 sequentially extracts the layout structures connected from the terminal D of the switch M1 to the terminal D of the switch M2 within the region 860, as shown in a portion 841 of the layout structures 840. The processor 110 sequentially extracts the layout structures connected from the terminal D of the switch M2 to the terminal D of the switch M1 within the region 861, as shown in a portion 842 of the layout structures 840. The processor 110 further compares the coding portion 801 in Fig. 8A with section 841 in Fig. 8B, and compares the coding section 802 in Fig. 8A with section 842 in Fig. 8B. Therefore, the processor 110 is able to determine whether the layout design 240 conforms to the layout constraints defined in the predetermined description 800.

[0063] Now reference is made to Fig. 9A and Fig. 9B taken. Fig. 9A shows a predefined description 900 that defines layout constraints for the circuit 200 in Fig. 2A, according to further alternative embodiments of the present disclosure. Fig. 9B is a schematic diagram illustrating the layout design 520 in Fig. 5B and layout structures 940 of layout design 520, according to further alternative embodiments of the present disclosure.

[0064] Compared with Fig. 8A, in some embodiments, the layout constraints are configured to be within a region 960, as in Fig. 9B, to assign groups of the link layers to the port D of the switch M1, and to sequentially within an area 961, as shown in Fig. 9B, groups of the link layers are assigned to the terminal D of the switch M2.

[0065] For illustration purposes, as in Fig. 9A, the predetermined description 900 coding sections 901 and 902. The coding section 901 specifies that the group M1_A and the group M2_B are within the area 960, which has an area of approximately 0.05*0.05 µm 2sequentially coupled in a predetermined sequence to the terminal D of the switch M1. With such restrictions, it is expected that the terminal D of the switch M1 is coupled to the group M1_A, and to the group M2_B via the group M1_A within the area 961. The coding section 902 specifies that the group M1_B and the group M2_B are coupled within the area 961, which has an area of approximately 0.05*0.05 μm. 2 sequentially coupled in a predetermined sequence to terminal D of switch M2. With such constraints, terminal D of switch M2 is expected to be coupled to group M1_B and to group M2_B via group M1_B within region 961.

[0066] In addition, the processor 110 sequentially extracts the layout structures within the regions 960 and 961. For illustration, as in Fig. 9B, the processor 110 sequentially extracts the groups in the layout structures that are connected from the port D of switch M1 to the port D of switch M2 within the region 960, as shown in a portion 941 of the layout structures 940. The processor 110 sequentially extracts the groups in the layout structures that are connected from the port D of switch M2 to the port D of switch M1 within the region 961, as shown in a portion 942 of the layout structures 940. The processor 110 further compares the coding portion 901 with the portion 941, and compares the coding portion 902 with the portion 942. Therefore, the processor 110 is able to determine whether the layout design 520 conforms to the layout constraints defined in the predetermined description 900.

[0067] Now reference is made to Fig. 10A and Fig. 10B taken. Fig. 10A shows a predefined description 1000 that defines layout constraints for the circuit 200 in Fig. 2A, according to further various embodiments of the present disclosure. Fig. 10B is a schematic diagram illustrating layout design 520 in Fig. 5B and layout structures 1040 of the layout design 520, according to further various embodiments of the present disclosure.

[0068] Compared with Fig. 9A, in some embodiments, the layout constraints are configured to be within a region 1060, as shown in Fig. 10B, to assign groups of the link layers to the port D of the switch M2 in ascending numerical order. The layout constraints are further configured to assign groups of the link layers in ascending order within a region 1061, as shown in Fig. 10B, groups of the link layers are assigned to the terminal D of the switch M2.

[0069] For illustration purposes, as in Fig. 10A, the predetermined description 1000 coding sections 1001 and 1002. The coding section 1001 specifies that the group M1_A and the group M2_A are within the area 1060, which has an area of approximately 0.1*0.1 µm 2 sequentially assigned to the terminal D of the switch M1. The coding section 1002 specifies that the group M1_B and the group M2_B are within the area 1061, which has an area of approximately 0.05*0.05 μm 2 be sequentially assigned to terminal D of switch M2.

[0070] In addition, the processor 110 determines the upper groups of the connection layers within the area 1060 and 1061, respectively. For illustration, Fig. 10B, the upper group of interconnect layers within region 1060 is group M3_A, and the upper group of interconnect layers within region 1061 is group M2_B. Processor 110 extracts the groups in the layout structures that are connected from terminal D of switch M1 to the upper group M3_A. Then, processor 110 sorts the groups in the layout structures in ascending numerical order, as shown in a section 1041 of layout structures 1040. As shown in Fig. As shown in Figure 10B, terminal D of switch M1 is coupled to the upper group M3_A via groups M1_A, M2_B, M1_B, and M2_B. Processor 110 sorts these groups in ascending numerical order, as shown in section 1041.

[0071] The processor 110 also generates a section 1042 of the layout structures 1040 by extracting the groups in the layout structures that are connected from the section D of the switch M2 to the upper group M2_B. The processor 110 then sorts the groups in the layout structures in ascending numerical order, as shown in section 1042. Accordingly, the processor 110 is able to divide the coding sections 1001 and 1002 into Fig. 10A each with section 1041 or 1042 in Fig. 10B to verify that the layout design 520 complies with the layout constraints.

[0072] Now reference is made to Fig. 11A and Fig. 11B taken. Fig. 11A shows a predefined description 1100 that defines layout constraints for the circuit 200 in Fig. 2A, according to other various embodiments of the present disclosure. Fig. 11B is a schematic diagram illustrating the layout design 520 in Fig. 5B and layout structures 1140 of layout design 520, according to other various embodiments of the present disclosure.

[0073] In some embodiments, the layout constraints are configured to be within a region 1160, as shown in Fig. 11B, groups of the link layers in descending numerical order to the port D of the switch M1. The layout constraints are further configured to be within a region 1161, as shown in Fig. 11B, groups of the link layers are assigned in descending numerical order to the terminal D of the switch M2.

[0074] For illustration purposes, as in Fig. 11A, the predetermined description 1100 coding sections 1101 and 1102. The coding section 1101 specifies that the group M2_B and the group M1_A are within the area 1160, which has an area of approximately 0.1*0.1 µm 2 are sequentially assigned to the terminal D of the switch M1. The coding section 1102 specifies that the group M2_B and the group M1_B are within the region 1161, which has an area of approximately 0.1*0.1 μm 2 be sequentially assigned to terminal D of switch M2.

[0075] Then, the processor 110 determines the upper group of connection layers within the area 1160 or 1161, respectively. For illustration, Fig. 11B, the upper group of interconnect layers within region 1160 is group M3_A, and the upper group of interconnect layers within region 1161 is group M3_A. The processor 110 then extracts the groups in the layout structures connected from the terminal D of the switch M1 to the upper group M3_A in descending order, as shown in a section 1141 of the layout structures 1060. As shown in Fig. As shown in Figure 11B, terminal D of switch M1 is coupled to the upper group M3_A via groups M1_A, M2_B, and M1_B. Processor 110 sorts these groups in descending order, as shown in section 1141.

[0076] Similarly, the processor 110 generates a section 1142 of the layout structures 1040 by extracting the groups in the layout structures that are connected from the section D of the switch M2 to the upper group M2_B. The processor 110 then sorts the groups in the layout structures in descending numerical order, as shown in section 1142. Accordingly, the processor 110 is able to divide the coding sections 1101 and 1102 into Fig. 11A with section 1141 or 1142 in Fig. 11B to check whether the layout design 520 complies with the layout constraints.

[0077] The arrangements of the layout constraints that are in Fig. 5A to 11A are provided for illustrative purposes. Various arrangements of the layout constraints are within the scope of the present disclosure.

[0078] Now reference is made to Fig. 12 taken. Fig. 12 is a schematic diagram showing a predetermined description showing the circuit in Fig. 2A and displays the layout constraints in a netlist file 1220, according to some embodiments of the present disclosure.

[0079] In some embodiments, the predetermined descriptions 500 to 1100, as illustrated above, are described in an independent file. The independent file is input into the design system 100 to extract the layout constraints. Alternatively, in some other embodiments, the predetermined descriptions 500 to 1100, as illustrated above, are described in the netlist file that includes a description of the circuit 200.

[0080] For illustration purposes, as in Fig. 12, the netlist file 1220 has two descriptions 1221 and 1222. The description 1221 is configured to describe the circuit 200 as described in the netlist file 220 in Fig. 2B. The description 1222 is configured to describe the layout constraints, for example, as shown in Fig. 11A.

[0081] The arrangement of layout constraints in Fig. 12 is provided for illustrative purposes. Various arrangements of the layout constraints are within the scope of the present disclosure.

[0082] In various embodiments, the method 300 and operation S340 thereof may be applied to various layout structures and / or layers, including, for example, back-end-of-line (BEOL), middle-end-of-line (MEOL), and / or front-end-of-line (FEOL).

[0083] For ease of understanding, the above embodiments are provided with an application for manufacturing two switches. The above embodiments can be applied to manufacture a single switch or two or more switches. For illustrative purposes, the above embodiments are described as one implementation of the switches. The present disclosure is not so limited. Various elements can be implemented according to the above embodiments and therefore form the scope of the present disclosure.

[0084] Throughout this document, the term "coupled" may also be referred to as "electrically coupled," and the term "connected" may be referred to as "electrically connected." "Coupled" and "connected" may also be used to indicate that two or more elements cooperate or interact with each other.

[0085] In some embodiments, a method for layout verification includes the following operation. Groups indicating layout structures of interconnect layers are assigned to a circuit to determine layout constraints of the circuit. A first group of the groups is assigned to a first port in the circuit. A second group of the groups is assigned to a second port in the circuit. Assigning the groups includes assigning at least one group of the groups comprising the first group to the first port in a first predetermined sequence and within a first region of a first element in the circuit, and assigning at least one group of the groups comprising the second group to the second port in a second predetermined sequence and within a second region of a second element in the circuit.The first terminal is a terminal of the first element, and the second terminal is a terminal of the second element. Layout structures are extracted from a circuit layout design. The layout structures are compared with the layout constraints. Data for manufacturing the circuit, which indicates the layout design, is generated under the condition that the layout structures conform to the layout constraints.

[0086] Also disclosed is a system for layout verification comprising a memory and a processor. The memory is configured to store computer program code. The processor is configured to execute the computer program code in the memory to extract layout structures from a layout design for a circuit, to extract layout constraints for the circuit to be compared with the layout structures, and to generate data indicative of the layout design for fabricating the circuit under a condition that the layout structures meet the layout constraints. The layout constraints are configured to assign, in a first predetermined sequence, a plurality of groups indicative of layout structures of interconnect layers to the circuit. A first group of the groups is assigned to a first terminal of the circuit.A second group of the groups is assigned to a second terminal in the circuit. The layout constraints are configured to assign at least one group of the groups comprising the first group to the first terminal in the first predetermined sequence and within a first region of a first element in the circuit, and to assign at least one group of the groups comprising the second group to the second terminal in the second predetermined sequence and within a second region of a second element in the circuit. The first terminal is a terminal of the first element, and the second terminal is a terminal of the second element.

[0087] The foregoing outlines features of several embodiments so that one skilled in the art can better understand aspects of the present disclosure. One skilled in the art should recognize that they can readily use the present disclosure as a basis for designing and modifying other processes and structures to perform the same tasks and / or achieve the same advantages of the embodiments presented herein. One skilled in the art should also understand that such equivalent embodiments do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

[1] A method (300) for checking layout, comprising: Assigning (S341) a plurality of groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) indicating layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) of interconnect layers (M1, M2, M3) to a circuit (200) in order to determine layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102) of the circuit (200), wherein a first group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a first terminal in the circuit (200), and the assignment of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprises: assigning, in a first predetermined sequence and within a first region (860, 960, 1060, 1160) of a first element (M1) in the circuit (200), at least one group (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprising the first group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) to the first terminal, wherein the first terminal is a terminal of the first element (M1), and a second group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a second terminal in the circuit (200), and the assignment of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprises: assigning, in a second predetermined sequence and within a second region (861, 961, 1061, 1161) of a second element (M2) in the circuit (200), at least one group (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprising the second group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) to the second terminal, wherein the second terminal is a terminal of the second element (M2), Extracting (S342) a plurality of layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) from a layout design (240, 520) for the circuit (200), Comparing (S343) the layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) with the layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102), and Generating data indicative of the layout design (240, 520) for manufacturing the circuit (200) under a condition that the layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) conform to the layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102). [2] The method (300) of claim 1, wherein a first group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a first terminal in the circuit (200), and assigning the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprises: Assigning, to the first terminal, a first number of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) to be coupled in a predetermined sequence to an upper group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B), wherein the first number of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprises the first link layer. [3] The method (300) of claim 2, wherein a second group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a second terminal in the circuit (200), and assigning the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprises: Assigning, to the second terminal, a second number of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) to be coupled in the predetermined sequence to the upper group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B), wherein the second number of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprises the second group. [4] The method (300) of claim 3, wherein the first number of groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is further assigned within a first region (860, 960, 1060, 1160) of a first element (M1) of the circuit (200), the first terminal is a terminal of the first element (M1), the second number of groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is further assigned within a second region (861, 961, 1061, 1161) of a second element (M2) of the circuit (200), and the second terminal is a terminal of the second element (M2). [5] Method (300) according to one of the preceding claims, wherein extracting the layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) from the layout design (240, 520) comprises: Extracting, within the first region (860, 960, 1060, 1160), at least one layout structure (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) from the layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) from the layout design (240, 520). [6] System (100) for layout checking, comprising: a memory (120) configured to store computer program code, and a processor (110) configured to execute the computer program codes in the memory (120) to: Extracting a plurality of layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) from a layout design (240, 520) for the circuit (200), Extracting layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102) for the circuit (200) to be compared with the layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142), wherein the layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102) are configured to assign, in a first predetermined sequence, a plurality of groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) indicating layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) of interconnect layers (M1, M2, M3) to the circuit (200), wherein a first group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a first terminal of the circuit (200), and the layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102) are configured to, in the first predetermined sequence and within a first region (860, 960, 1060, 1160) of a first element (M1) in the circuit (200), at least one group (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprising the first group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) to the first terminal, wherein the first terminal is a terminal of the first element (M1), and wherein a second group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a second terminal of the circuit (200), and the layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102) are configured to allocate, in a second predetermined sequence and within a second region (861, 961, 1061, 1161) of a second element (M2) in the circuit (200), at least one group (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprising the second group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) to the second terminal, wherein the second terminal is a terminal of the second element (M2), and Generating data indicative of the layout design (240, 520) for manufacturing the circuit (200) under a condition that the layout structures (541, 542, 641, 642, 741, 742, 841, 842, 941, 942, 1041, 1042, 1141, 1142) conform to the layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102). [7] The system (100) of claim 6, wherein a first group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a first terminal in the circuit (200), a second group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) is assigned to a second terminal in the circuit (200), and the layout constraints (501, 502, 601, 602, 701, 702, 801, 802, 901, 902, 1001, 1002, 1101, 1102) are configured to assign to the first terminal a first number of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) that are in the first predetermined sequence with an upper group of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) are to be coupled, and to assign to the second terminal a second number of the groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) which are to be coupled in the first predetermined sequence with the upper group, wherein the first number of groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) comprises the first group, and the second number of groups (M1_A,M1_B, M2_A, M2_B, M3_A, M3_B) comprises the second group., [8] The system (100) of claim 7, wherein the first number of groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) are further assigned within a first region (860, 960, 1060, 1160) of a first element (M1) of the circuit (200), the first terminal is a terminal of the first element (M1), the second number of groups (M1_A, M1_B, M2_A, M2_B, M3_A, M3_B) are further assigned within a second region (861, 961, 1061, 1161) of a second element (M2) of the circuit (200), and the second terminal is a terminal of the second element (M2).

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