Packaging process and associated package structure
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2016-08-14
- Publication Date
- 2026-07-30
AI Technical Summary
Existing eutectic bonding methods for bonding wafers in microelectromechanical systems (MEMS) face challenges with high bonding temperatures and pressing forces that are not compatible with modern semiconductor structures, leading to potential deterioration and incompatibility with CMOS processes.
A Cu-Sn eutectic bonding process is employed, which involves fusion bonding at lower temperatures (240-300°C) and pressures (1-2 MPa) to form a hermetic seal, using a Cu layer and a Sn layer to create a Cu-Sn alloy bond, eliminating the need for separate electrical paths and ensuring mechanical strength.
The Cu-Sn eutectic bond provides a strong, hermetically sealed connection with reduced thermal stress, compatible with CMOS processes, maintaining device performance and reliability over decades.
Abstract
Description
PRIORITY CLAIM AND CROSS-REFERENCE
[0001] This application claims priority over preliminary US application 62 / 273,750, filed on December 31, 2015, which is deemed to have been included in its entirety by reference. GENERAL STATE OF THE ART
[0002] In microelectromechanical systems (MEMS) and in areas of microelectronics, there is often a need to bond wafers together in vacuum cavities or cavities with a controlled atmosphere for the purpose of encapsulating structures. Such systems may need to operate for very long periods, often decades. It may also be desirable to provide an electrical connection between the wafers by means of sealing.
[0003] It is absolutely essential that the connections holding / bonding the wafers together and providing effective cavity sealing deliver a sufficiently good seal that does not deteriorate over time. One of the common bonding methods is eutectic bonding. However, as modern semiconductor structures become increasingly sensitive, the overall thermal balance is so strained that the bonding temperature of existing eutectic bonding materials is no longer acceptable. Furthermore, with the development of modern processes, such as MEMS structures, the pressing force applied during the eutectic bonding process is decreasing.
[0004] Therefore, in areas relevant to the semiconductor manufacturing industry, there is an urgent need for a novel bonding mechanism to meet the aforementioned requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] The developments described in this disclosure are best understood by referring to the detailed description below, when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, the various structures are not drawn to scale. In fact, the dimensions of the various structures may be enlarged or reduced as desired for clarity.
[0006] The Fig. 1– Fig. Figure 11 is a series of cross-sectional views illustrating the process steps involved in the fabrication of a CMOS MEMS device structure. DETAILED DESCRIPTION
[0007] The following disclosure provides many different embodiments or examples of the realization of various features of the invention. To simplify the present disclosure, specific examples of components and devices are described below. These are, of course, only examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which additional features can be formed between the first and second features such that the first and second features cannot be in direct contact. Furthermore, reference numerals and / or symbols may be repeated in the various examples in the present disclosure.This repetition serves to simplify and clarify matters and does not in itself imply any relationship between the various designs and / or configurations discussed.
[0008] Furthermore, spatial relational terms such as "below," "below," "lower," "above," "upper," and the like can be used here for the sake of simplicity to describe the relationship of one element or feature to another element or feature (other elements or features), as illustrated in the figures. These spatial relational terms are intended to encompass various orientations of the component in use or operation, in addition to the orientation shown in the figures. The device can be oriented differently (rotated 90 degrees or in other directions), and the spatial designations used here can be interpreted accordingly.
[0009] Notwithstanding the fact that the numerical ranges and parameters defining the broad scope of the invention are approximations, the numerical values given in specific examples are communicated as accurately as possible. However, any numerical value inherently includes certain errors that necessarily result from the standard deviation found in the corresponding test measurements. Furthermore, the term "circa" as used herein generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, when used by a person skilled in the art, the term "circa" means within a reasonable standard error of the mean. Except in the operating / functional examples, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages, such as...Such values for material quantities, durations, temperatures, operating conditions, ratios, and the like, disclosed herein, shall be understood as being modified in all cases by the term "approximately." Unless otherwise indicated, the numerical parameters given in this disclosure and the appended claims are accordingly approximations that may be modified as desired. At a minimum, each numerical parameter should be interpreted with regard to the disclosed significant figures and by applying ordinary rounding techniques. Ranges may be specified from one endpoint to another or between two endpoints. All ranges disclosed herein include the endpoints unless otherwise indicated.
[0010] The present invention relates generally to bonding, in particular eutectic bonding. The following description is presented to enable a person skilled in the art to carry out and use the invention, and it is provided in conjunction with a patent application and its requirements. For those skilled in the art, various modifications of the preferred embodiment and the generic principles and features described herein will be readily apparent. Thus, the present invention is not intended to be limited to the embodiment shown, but rather to have the broadest possible scope of application compatible with the principles and features described herein.
[0011] In the described embodiments, microelectromechanical systems (MEMS) refer to a class of structures or components fabricated using processes adapted to semiconductors and exhibiting mechanical properties such as the ability to move or deform. MEMS often, but not always, interact with electrical signals. MEMS components include, but are not limited to, gyroscopes, accelerometers, magnetometers, pressure sensors, and radio frequency components. In some embodiments, the MEMS component structure may incorporate several of the aforementioned MEMS components. Silicon wafers incorporating a MEMS component or MEMS component structure are referred to as MEMS wafers.
[0012] In the described embodiments, a MEMS device can refer to a semiconductor device implemented as a microelectromechanical system. A MEMS device structure can refer to any feature associated with an array of multiple MEMS devices. An engineered silicon-on-insulator (ESOI) wafer can refer to an SOI wafer with cavities beneath the silicon device layer or substrate. A cap or handling wafer typically represents a thicker substrate used as a support for the thinner silicon measurement substrate in a silicon-on-insulator wafer. The cap or handling substrate and the cap or handling wafer are interchangeable. In the described embodiments, a cavity can denote an opening or depression, and an inclusion can refer to a completely enclosed space.
[0013] To describe the features of the invention in more detail, a device and manufacturing method for realizing a MEMS device with features including the improved bonding temperature and pressure applied during bonding are disclosed.
[0014] The Fig. 1– Fig. Figure 11 are a series of cross-sectional views illustrating the process steps in the fabrication of a MEMS component assembly or a MEMS component according to an embodiment of the present disclosure. Fig. 1 are a measuring substrate 104 and a cap substrate 101 with a thin dielectric film 103 bonded together in between to form an ESOI substrate 102 to train. It is noted that the measuring substrate 104 and the cap substrate 101In the embodiment of the present disclosure, the substrates are bonded together by fusion bonding at relatively high process temperatures, which allows for a more complete removal of chemical species from the dielectric materials in the substrates before sealing the cavities of the MEMS structures. Both substrates are annealed during bonding, which reduces the outgassing of chemical species during the cavity formation process. The MEMS structures bonded by fusion bonding are mechanically stronger compared to metal bonding due to a higher bond ratio. Furthermore, fusion bonding allows the formation of through-hole vias (TSVs) in the MEMS structures without compromising the yield. However, the basic concept of the present disclosure is not limited to this. A person skilled in the art would recognize many modifications, variations, and alternatives.The basic idea of the present disclosure can also be applied in some embodiments to other types of MEMS device arrangements.
[0015] The thin dielectric film 103 It contains materials such as silicon dioxide or another insulating layer. Along a surface of the cap substrate. 101 Several cavities will be 112 with desired dimensions and shaped accordingly, for example by isotropic etching, which, however, does not constitute a limitation of the present disclosure. An expert would recognize many changes, modifications, and alternatives. The multiple cavities 112 are used to house an adjacent movable seismic mass of a MEMS device being manufactured. The size of each cavity 112can be determined according to the adjacent movable seismic mass and / or the desired performance of the MEMS device. In some embodiments, each cavity can be 112 have a different depth or dimensions than the other cavities.
[0016] The measuring substrate 104 It is then removed using a grinding and / or other thickness reduction process to achieve the desired thickness, as in Fig. Figure 2 illustrates this. To achieve the desired thickness, existing thickness reduction techniques, such as chemical-mechanical planarization (CMP) and / or reactive ion etching (RIE), can be used. Suitable grinding and polishing equipment can be employed for the thickness reduction process. A knowledgeable person would recognize many modifications, alterations, and alternatives. In some other embodiments, the measuring substrate is 104An etch stop layer is integrated to support the precision control of the thickness reduction process. An expert would recognize many changes, modifications, and alternatives.
[0017] With reference to Fig. 3 then becomes a metal layer 302 on the measuring substrate 104 deposited. In this embodiment, the metal layer has 302 a copper (Cu) layer. In particular, the metal layer has a copper (Cu) layer. 302 A thin titanium (Ti) layer is deposited beneath the copper layer. In some embodiments, the metal layer 302 deposited using an electroplating process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process. A knowledgeable person would recognize many changes, modifications, and alternatives. With reference to Fig. 4 is then applied to the metal layer 302 another metal layer 304separated from the metal layer 302 differs. In this embodiment, the metal layer has 304 a tin (Sn) layer is formed. In some embodiments, the metal layer 304 The coating is deposited using electroplating, physical vapor deposition (PVD), or chemical vapor deposition (CVD). An expert would recognize many variations, modifications, and alternatives.
[0018] The next step, which is in Fig. As shown in section 5, this consists of structuring and etching the metal layers. 302 and 304 according to the structure of the MEMS component to be manufactured. The structuring and etching process results in several bonding areas. 402' and 404'for bonding in the following steps, e.g., for eutectic bonding, which is used in the exemplary embodiment. In particular, each bonding area has 402' the metal layers 402 and 406 up, and every bond area 404' exhibits the metal layers 404 and 408 on, whereby the metal layers 406 and 408 as bonding auxiliary metal layers during the bonding process to form the eutectic bond.
[0019] This process involves a photolithographic process in which a photoresist layer is applied to the metal layer. 304The process of depositing and structuring the material to form an etching mask is not shown for clarity. The dimensions of the etching mask can be strictly controlled during photolithography, and the mask can be made of any suitable material resistant to the etching process used to etch the metal layers. In some embodiments, a silicon nitride (Si3N4) etching mask is used. In some other embodiments, a photoresist layer can serve as the etching mask. An expert would recognize many variations, modifications, and alternatives. Although in Fig. 5 shows a one-dimensional cross-section, it is obvious to an expert that in the metal layers 302 and 304 A two-dimensional structure of the desired geometry is formed. In some embodiments, the bond areas can be... 402' and 404'Furthermore, they contain nickel (Ni), germanium (Ge), and aluminum (Al). In other embodiments, other materials, such as gold (Au), indium (In), or other soldering materials that adhere well to underlying layers and exhibit improved wettability, can be used for the bonding areas.
[0020] on the measuring substrate 104 A first shallow cavity etching is selectively performed. During this first shallow cavity etching, shallow cavities are formed to achieve a certain depth, which is determined by the surface of the measuring substrate. 104 from Fig. 5 is measured. After the first shallow cavity etching, several first-step bond mesas remain. 502 and 504 remain and protrude from an etched surface of the measuring substrate 104 out, as from Fig. 6 is evident. To be more precise, the several first-step bonding mesas 502 and 504 are below the bond ranges402' and 404' The multiple first-step bonding mesas 502 and 504 carry the conductive bond areas 402' and 404' , to form a stacked structure. In the exemplary embodiment, the width of the multiple first-step bond mesas can be 502 and 504 essentially equal to or greater than the bond areas 402' and 404' be. The side walls of the multiple first-step bond mesas 502 and 504 They can be vertical or beveled. An expert would recognize many changes, modifications, and alternatives.
[0021] The measuring substrate 104 It is then structured and etched to form the measurement substrate, as described in Fig. Figure 7 shows that the measuring substrate comprises a balanced or unbalanced seismic mass suspended by at least one spring or elastic device, which is free to move in at least one of the x, y, and z directions, with at least one electrode embedded in the at least one spring or elastic device. The at least one spring or elastic device is attached to a support structure that is mounted on the measuring substrate. 104The seismic mass, the support structure, and the at least one electrode are formed in the same semiconductor layers as the drive / measurement circuits. In some embodiments, the at least one spring or elastic device and the support structure form a network of supports. The seismic mass, suspended by means of the network of supports, is free to move in any direction. The MEMS measures or capacitively generates the movement of the seismic mass in any direction. In some embodiments, the direction can include a direction along at least one of the x, y, and z directions.
[0022] In some embodiments, the structuring and etching techniques used to form the measurement substrate can vary depending on the type of MEMS device. For example, the structuring and etching for a MEMS accelerometer differs from that used for a MEMS gyroscope. Existing etching techniques similar to anisotropic etching, RIE, and the like can be used. In some embodiments, the thickness of the measurement substrate can be 104 as a function of position along the length of the measuring substrate, where the length is defined along a direction perpendicular to the thickness of the substrate. For example, the measuring substrate can 104 having a first thickness at one end, a second thickness in the middle, and a third thickness at the other end.
[0023] Next, as in Fig. Figure 8A shows the ESOI substrate. 102 and a complementary metal-oxide-semiconductor (CMOS) wafer 106 pre-cleaned and then aligned before eutectic bonding. In the present disclosure, a CMOS wafer can be referred to as a CMOS substrate. The CMOS wafer 106 can a substrate 812 exhibit the substrate 812 It can have a semiconductor material, such as silicon, although other semiconductor materials can be used. On a surface of the substrate 812 Several CMOS components will be used 814 (such as transistors). Furthermore, a circuit structure is formed. 816 trained to work with CMOS components 814 to connect electrically. The wiring structure 816It can have dielectric layers, which may further include low-k dielectric layers, non-low-k dielectric layers such as passivation layers, and the like. Metallic conductors and vias are formed in the dielectric layers, which may be made of copper, aluminum, and combinations thereof.
[0024] A dielectric coating 810 the wiring structure 816 is structured, and in the dielectric top layer 810 Several openings, including openings, will be created. 802 and 804 , which are the bond areas 402' and 404' They correspond, are trained. As a result, bond areas are defined. 806 and 808 free. Compared to a bond metal with multiple bond areas 806 and 808 of the CMOS substrate 106 the dielectric layer 810exhibit different melting behavior. In the exemplary embodiment, the bond areas show 806 and 808 a copper layer. In particular, the bonding areas exhibit 806 and 808 Furthermore, a thin Ti layer is formed beneath the Cu layer. However, this does not constitute a limitation of the present invention.
[0025] In some other embodiments, a further metal layer is added, which differs from the bond metal of the bond areas. 806 and 808 differs, in terms of the bond areas. 806 and 808 trained for eutectic bonding. Those working in the bonding areas 806 and 808 The formed metal layer contains the same metal as the metal layers. 406 and 408 is. In Fig. 8B shows an embodiment in which metal layers 406' and 408' to the relevant bond areas 806 and 808electroplated. In several other embodiments, which are the same or similar as in Fig. 8B are, for eutectic bonding on the bond areas 806 and 808 Furthermore, another metal layer is formed, which differs from the bond metal of the bond areas. 806 and 808 differs, however, the metal layers 406 and 408 from Fig. 8B can be omitted. One embodiment is described in Fig. 8C is shown, where the Sn layers 406' and 408' to the relevant bond areas 806 and 808 be electroplated and the bond areas of the measuring substrate 104 only the metal layers 402 and 404 exhibit.
[0026] After that, the Bond areas will be 402' and 404' (or the metal layers) 402 and 404 for Fig. 8C) of the ESOI substrate 102through the openings 802 and 804 of the CMOS wafer 106 through into contact with the bond areas 806 and 808 (or the metal layers) 406' and 408' for the Fig. 8B and Fig. 8C). During bonding, both the ESOI substrate and the substrate are exposed to the chemicals. 102 as well as the CMOS wafer 106 heated, and a pressing force is applied to the ESOI substrate 102 and the CMOS wafer 106 to press against each other while the temperature is elevated. In other words, the bonding interface between the ESOI substrate 102 and the CMOS wafer 106 It is heated and subjected to a pressing force to break down the metal that is in the bond areas. 402' and 404' (or the metal layers) 402 and 404 for Fig. 8C) and the corresponding bond areas 806 and 808 (and the metal layers) 406' and 408'for the Fig. 8B and Fig. 8C) of the CMOS wafer 106 The material is present and melts. The pressing force is applied to the ESOI substrate. 102 against the CMOS wafer 106 and / or onto the CMOS wafer 106 against the ESOI substrate 102 applied to create hermetic seals.
[0027] The melting of the metal results in a fusion bond structure that creates an ohmic contact between the ESOI substrate. 102 and the CMOS wafer 106 delivers. In the exemplary embodiment, the bond between the ESOI substrate 102 and the CMOS wafer 106 a eutectic Cu-Sn bond is used. This eliminates the need for a separate electrical path for the signals between the measurement substrate and the CMOS wafer. 106to provide. Eutectic reactions are a triple point in the phase diagram at which solid alloy mixtures directly transform into a liquid phase. The eutectic melting temperature for the Cu-Sn bond is approximately 231 degrees Celsius; to ensure an adequate or sufficient eutectic reaction for the Cu-Sn bond, a bonding temperature provided during the eutectic bonding process may be higher than the eutectic temperature. In this embodiment, a bonding temperature provided during the eutectic bonding process may be in the range of approximately 240 degrees Celsius to approximately 300 degrees Celsius, with a pressing force of approximately 1 MPa to approximately 2 MPa per unit area or less. However, this is not a limitation of the present disclosure.
[0028] Compared to existing eutectic bonds, the disclosed eutectic Cu-Sn bond, through the use of a eutectic Cu-Sn bond, exhibits a lower bonding temperature and lower bonding force. Specifically, some existing eutectic bonds include the Au-In bond, the Au-Sn bond, the Au-Ge bond, the Au-Si bond, and the Al-Ge bond, all of which require a high bonding temperature. The Au-Sn bond has a eutectic melting point of approximately 280 degrees Celsius and requires a bonding temperature in the range of approximately 280 degrees Celsius to approximately 310 degrees Celsius. The Au-Ge bond has a eutectic melting temperature of approximately 361 degrees Celsius and requires a bonding temperature in the range of approximately 380 degrees Celsius to approximately 400 degrees Celsius.The Au-Si bond has a eutectic melting point of approximately 363 degrees Celsius and requires a bonding temperature in the range of approximately 390 degrees Celsius to approximately 415 degrees Celsius. The Al-Ge bond has a eutectic melting point of approximately 419 degrees Celsius and requires a bonding temperature in the range of approximately 430 degrees Celsius to approximately 450 degrees Celsius.
[0029] Although the Au-In-Bond has a eutectic melting point of approximately 156 degrees Celsius and requires a bonding temperature in the range of approximately 180 degrees Celsius to approximately 210 degrees Celsius, which is no higher than that of the disclosed Cu-Sn bond, the Au-In-Bond is considered incompatible with the standard CMOS process. Furthermore, the Au-In-Bond, the Au-Sn bond, the Au-Ge bond, the Au-Si bond, and the Al-Ge bond all exhibit a pressing force exceeding approximately 10 MPa per unit area, which may prove unusable in the case of technical shrinkage.
[0030] During cooling, a microstructure forms, as seen in Fig. Figure 9 shows a material that is both solid and hermetically sealed. Eutectic metal compositions offer several advantages as sealing materials, including the ability to precisely deposit and fix the metals in desired structures, tolerance to surface dimensional variations, roughness, and particles, plus their inherent density and conductivity. The hermetic seal, the degree of airtightness for a vessel or package, is advantageous for MEMS packages because the mechanical and electrical functionality of the device within the package typically depends on critical environmental control. A change in the atmosphere inside the package can lead to a change in performance or even total device failure.
[0031] For the embodiment which according to Fig. 8A is configured, it will be in Fig. 9 through the metal layer 406and at least part of the metal layers 402 and 806 an alloy 1006 formed, and in a similar way through the metal layer 408 and at least part of the metal layers 404 and 808 an alloy 1008 trained. For the embodiment which according to Fig. 8B is configured, it will be in Fig. 9 through the metal layers 406 , 406' and at least part of the metal layers 402 and 806 an alloy 1006 formed, and in a similar way through the metal layer 408 , 408' and at least part of the metal layers 404 and 808 an alloy 1008 trained. For the embodiment which according to Fig. 8C is configured, it will be in Fig. 9 through the metal layer 406' and at least part of the metal layers 402 and 806 an alloy1006 formed, and in a similar way through the metal layer 408' and at least part of the metal layers 404 and 808 an alloy 1008 formed. In particular, the metal layers 406 , 408 , 406' and 408' an essentially complete reaction with the metal layers above or below it 402 , 404 , 802 and 804 received.
[0032] In the exemplary embodiment, the alloys 1006 and 1008 Cu3Sn. It is permissible for some Cu to remain after bonding that has not undergone a reaction. However, it is not desirable for some Sn to remain after bonding that has not undergone a reaction, because Sn is less stable than Cu and Cu3Sn. To minimize the Sn in the metal layers 406 , 408 , 406' and 408'To completely use up the metal layers, a thickness of the metal layers may be required. 406 , 408 , 406' and 408' corresponding to the thickness of the metal layers 402 , 404 , 802 and 804 above or below the metal layers 406 , 408 , 406' and 408' be specified.
[0033] In a subsequent step, a pad opening step is performed. The parts 902 and 904 of the cap substrate 101 are removed, for example, in an etching step or a grinding step, as in Fig. Figure 10 shows the resulting structure. Fig. 11 shown. The bond pads 1002 and 1004 in the CMOS substrate 106 are therefore no longer part of the ESOI substrate 102 covered. The bond pads 1002 and 1004 lie on the CMOS substrate 106from free to accommodate external bonds or wiring. In some embodiments, the etching is anisotropic, and thus the edges of the cap substrate are 101 from Fig. 11 essentially straight. Alternatively, the parts can 902 and 904 removed by a grinding step, using a grinding wheel or plate to remove the parts 902 and 904 to grind away. In some embodiments, the thickness of the measuring substrate can be adjusted. 104 The thickness can be reduced using a grinding and / or other ablation process to achieve a desired thickness before the formation of the package containing the MEMS device is complete.
[0034] The present disclosure provides a method for producing an improved bond of a wafer-level package (WLP) that is widely used in three-dimensional (3D) ICs, chip-scale packages (CSPs), and MEMS device assemblies. The disclosed method, which addresses bonding and related problems, is not limited to WLPs or 3D ICs, CSPs, and MEMS devices. The disclosed bonding process can be integrated into the standard CMOS process, resulting in a simplified, cost-effective solution. Compared to existing eutectic bonds, the disclosed eutectic Cu-Sn bond, through the use of a eutectic Cu-Sn bond, exhibits a lower bonding temperature and lower bonding force.
[0035] Some embodiments of the present disclosure provide a packaging method. The packaging method comprises: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate has a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate has a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate into contact with the bonding region of the second semiconductor substrate, wherein the first and third bonding metal layers have copper (Cu) and the second bonding metal layer has tin (Sn).
[0036] Some embodiments of the present disclosure provide a packaging method. The packaging method comprises: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate has a first bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate has a second bonding layer; bonding the bonding region of the first semiconductor substrate to the bonding region of the second semiconductor substrate using a bonding auxiliary metal; and applying a pressing force of approximately 1 MPa to approximately 2 MPa per unit area or less to press the first and second semiconductor substrates against each other.
[0037] Some embodiments of the present disclosure provide a package structure. The package structure comprises a first semiconductor substrate with a first bonding region on it and a second semiconductor substrate with a second bonding region on it, wherein the first bonding region is bonded to the second bonding region and a bond interface between the first bonding region and the second bonding region comprises Cu3Sn.
[0038] The preceding section briefly outlines the structures of various embodiments to enable those skilled in the art to better understand the embodiments described herein. Those skilled in the art should recognize that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent designs do not deviate from the fundamental concept and scope of this disclosure and that they can generate various modifications, substitutions, and adaptations without deviating from the fundamental concept and scope of this disclosure.
Claims
[1] Packaging processes, including: Providing an initial semiconductor substrate; Forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate comprises a first bonding metal layer and a second bonding metal layer; Providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate has a third bonding layer; and Bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding area of the first semiconductor substrate into contact with the bonding area of the second semiconductor substrate, wherein the first and third bond metal layers contain copper (Cu) and the second bond metal layer contains tin (Sn). [2] The method of claim 1, further comprising: Provision of a bonding temperature in the range of approximately 240 degrees Celsius to approximately 300 degrees Celsius. [3] Method according to claim 1 or 2, further comprising: Apply a pressing force of approximately 1 MPa to approximately 2 MPa per unit area or less to press the first and second semiconductor substrates against each other. [4] Method according to any of the preceding claims, further comprising reacting the Sn present in the second bond metal layer with the Cu present in the first and third bond metal layers to form Cu3Sn until the Sn is substantially completely used up. [5] Method according to any of the preceding claims, wherein the first semiconductor substrate comprises a device with microelectromechanical systems (MEMS). [6] Method according to any one of the preceding claims, further comprising: Removing a portion of the first semiconductor substrates. [7] Packaging processes, including: Providing an initial semiconductor substrate; Forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate has a first bonding metal layer; Providing a second semiconductor substrate having a bonding area, wherein the bonding area of the second semiconductor substrate has a second bonding layer; Bonding the bonding region of the first semiconductor substrate to the bonding region of the second semiconductor substrate using a bonding auxiliary metal, and Apply a pressing force of approximately 1 MPa to approximately 2 MPa per unit area or less to press the first and second semiconductor substrates against each other. [8] Method according to claim 7, wherein the first and second bond metal layers comprise copper (Cu). [9] Method according to claim 7 or 8, wherein the bond auxiliary metal layer comprises tin (Sn). [10] Method according to any one of claims 7 to 9, further comprising: Provision of a bonding temperature in the range of approximately 240 degrees Celsius to approximately 300 degrees Celsius. [11] Method according to any one of claims 7 to 10, further comprising reacting the Sn present in the bond auxiliary metal layer with the Cu present in the first and second bond metal layers to form Cu3Sn until the Sn is substantially completely used up. [12] Method according to any one of claims 7 to 11, comprising bonding the bonding area of the first semiconductor substrate to the bonding area of the second semiconductor substrate using the bonding auxiliary metal layer: Applying the bonding aid layer to the first bonding metal layer before bonding. [13] Method according to any one of claims 7 to 12, comprising bonding the bonding area of the first semiconductor substrate to the bonding area of the second semiconductor substrate using the bonding auxiliary metal layer: Applying the bonding aid metal layer to the second bonding metal layer before bonding. [14] Method according to any one of claims 7 to 13, wherein forming the bond area on the first semiconductor substrate comprises: Deposition of the first bond metal layer onto the first semiconductor substrate; and Etching part of the first bond metal layers to form the bond area. [15] Method according to any one of claims 7 to 14, further comprising: Etching of the first semiconductor substrate to form a bond mesa. [16] Method according to any one of claims 7 to 15, wherein the second semiconductor substrate has an opening on a surface thereof and a metal layer in the second semiconductor substrate is exposed through the opening to form the bonding area of the second semiconductor substrate. [17] Method according to any one of claims 7 to 16, wherein the first semiconductor substrate comprises a device with microelectromechanical systems (MEMS). [18] Method according to any one of claims 7 to 17, further comprising: Removing a portion of the first semiconductor substrates. [19] Package structure with: a first semiconductor substrate with a first bonding area on it; and a second semiconductor substrate with a second bonding area on it, wherein the first bond area is bonded to the second bond area and has a bond interface between the first bond area and the second bond area Cu3Sn. [20] Package structure according to claim 19, wherein the first and second bond areas comprise copper (Cu).