Semiconductor device

Abstract

Semiconductor device comprising: a transistor (10; 20; 30), comprising: an active region (12) in a substrate (18); a structured conductive layer (14; 24) that is a section of an interconnection layer for routing; an insulating layer (32) extending over the substrate (18) and configured to isolate the active region (12) from the structured conductive layer (14; 24), wherein the structured conductive layer (14; 24) and the insulating layer (32) serve as a gate (21; 302) of the transistor (10; 20; 30); and an interconnection feature (28) configured to communicate with a drain / source region (122) in the active region (12), wherein the interconnection feature (28) and the structured conductive layer (14; 24) are in the same interconnection layer.

Description

BACKGROUNDHigh voltage metal oxide semiconductor (HVMOS) devices are widely used in many electrical devices such as input / output (I / O) circuits, power supplies for a central processing unit (CPU), power management systems, and AC / DC (AC / DC) converters. There are various forms of HVMOS devices. A symmetric HVMOS device may have a symmetric structure on the source side and drain side. High voltage may be applied to both the drain and source sides. In contrast, an asymmetric HVMOS device may have asymmetric structures on the source side and drain side.The relevant prior art is given by US 5712492 A and US 2005 / 0116265 A1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1A is a cross-sectional view of a transistor of a semiconductor device according to some embodiments of the present disclosure. FIG. 1B is a design view of the transistor shown in FIG. 1A, in accordance with some embodiments of the present disclosure. FIGS. 1C to 1F are schematic diagrams illustrating a method of manufacturing the transistor of the semiconductor device shown in FIG. 1A according to some embodiments of the present disclosure. FIG. 2A is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 2B is a design view of the semiconductor device shown in FIG. 2, in accordance with some embodiments of the present disclosure. FIG. 3A is a cross-sectional view of a semiconductor device including a first transistor and a second transistor, in accordance with some embodiments of the present disclosure. FIGS. 3B to 3G are schematic diagrams illustrating a method of manufacturing the semiconductor device shown in FIG. 3A according to some embodiments of the present disclosure. FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 5 is a flow diagram illustrating a method of forming a semiconductor device according to some embodiments of the present disclosure.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the disclosure. Specific examples of components and arrangements are described below for the purpose of simplifying the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.FIG. 1A is a cross-sectional view of a transistor 10 of a semiconductor device 1 according to some embodiments of the present disclosure. Referring to FIG. 1A, the transistor 10 includes a gate 11 on a substrate 18 and an active region 12 in the substrate 18.In some embodiments, the substrate 18 includes a semiconductor material such as silicon. In other embodiments, the substrate 18 includes silicon germanium, gallium arsenic, or other suitable semiconductor materials. In some embodiments, the substrate 18 further includes other features, such as a buried layer and / or an epitaxial layer. The buried layer may be doped by ion implantation with antimony (Sb) to a concentration of about 5.0×10 13 to about 1.5×10 14 at an energy between about 70 keV and about 90 keV and to a depth greater than about 2 micrometers. Those skilled in the art will appreciate that other n-type dopants may be used depending on the design requirements of the device. For example, antimony has less self-doping during epitaxy and subsequent heating cycles, but has a lower solubility limit compared to arsenic, which may require higher anneal temperatures to activate the antimony. Moreover, in some embodiments, the substrate 18 is a semiconductor on insulator, such as silicon on insulator (SOI). In other embodiments, the semiconductor substrate 18 includes a doped epi layer, a graded semiconductor layer, and / or further includes a semiconductor layer overlying another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer. In some other examples, a compound semiconductor substrate includes a multi-layered silicon structure, or a silicon substrate may include a multi-layered compound semiconductor structure. In some embodiments, the substrate 18 may include other elemental semiconductors, such as germanium and diamond. In some embodiments, the substrate 18 includes a compound semiconductor such as silicon carbide, gallium arsenic, or indium phosphide.The gate 11 includes a patterned conductive layer 14 serving as its gate electrode and an insulating layer 16 serving as its gate oxide.The patterned conductive layer 14 is disposed on the insulating layer 16, which in turn is disposed on the active region 12. The active region 12 includes a first well 124 where a channel 126 is defined. The first well 124 of a first dopant type is disposed between a second well 120 and a third well 122, both of which are of a second dopant type opposite the first dopant type. The second well 120 serves as a first source / drain region of the transistor 10 and the third well 122 serves as a second source / drain region of the transistor 10. In the present embodiment, the substrate 18 is a p-type substrate, the first well 124 includes a high voltage n-well (HVNW), and both the second well 120 and the third well 122 include a high voltage p-well (HVPW). As a result, the transistor 10 includes a p-type transistor structure. For example, the transistor 10 includes a p-type metal oxide semiconductor (PMOS) transistor or a p-type metal oxide semiconductor field effect transistor (PMOSFET). Although only one gate structure is illustrated, it will be appreciated that transistor 10 may include a variety of gate structures for PMOS transistors, including short channel and long channel transistors.Those skilled in the art will appreciate that the embodiments disclosed herein with respect to a PMOS transistor are also applicable to an NMOS transistor, an n-type metal oxide semiconductor field effect transistor (NMOSFET), and an NPN transistor. For example, the first well 124 includes a high voltage p-well and both the second well 120 and the third well 122 include a high voltage n-well. Additionally, while the dopants are discussed in terms of specific terms and with respect to particular dopants, those skilled in the art will appreciate that alternative doping characteristics may be advantageously employed.Moreover, the patterned conductive layer 14 is formed in, for example, an interconnection layer such as a metal 1 (M1) layer in a semiconductor manufacturing process. Moreover, since the patterned conductive layer 14 is a portion of the metal 1 layer, the patterned conductive layer 14 is free of spacers on its sides, unlike some existing transistors. Consequently, the manufacturing process of the transistor 10 in the present embodiment is relatively simple.In the present embodiment, a layer (such as the patterned conductive layer 14) serving as a gate electrode is in a metal 1 layer. However, the present disclosure is not limited thereto. In another embodiment, a layer in a metal-2 layer serves as a gate electrode of the transistor 10.The insulating layer 16, which serves as another component of the gate 11 of the transistor 10, completely covers the active region. In addition, the insulating layer 16 completely covers the substrate 18 while the patterned conductive layer 14 forms a portion of an interconnection layer. The insulating layer 16 is configured to isolate the active region 12 from the patterned conductive layer 14. Ideally, the active region 16 with the insulating layer 16 is electrically insulated from the patterned conductive layer 14 if there are no interconnect features therebetween to couple them together.In an embodiment, the insulating layer 16 includes an intermediate dielectric (ILD) layer. The insulating layer 16 includes doped silicon glass such as phosphorus silicon glass (PSG) or boron phosphorus silicon glass (BPSG). In some embodiments, the insulating layer 16 includes silicon oxide, silicon nitride, silicon oxynitride, spin-on-glass (SOG), fluorinated silicon dioxide glass (FSG), carbon doped silicon oxide (e.g., SiCOH), BLACK DIAMOND® (Applied Materials of Santa Clara, Calif.), XEROGEL® AEROGEL® amorphous fluorocarbon, parylene, BCB (bis-benzocyclobutene), FLARE® SILK® (Dow Chemical, Midland, Mich.), polyimide, other suitable porous polymeric materials, other suitable dielectric materials, and / or combinations thereof. In some embodiments, the insulating layer 16 includes a high density plasma (HDP) dielectric material (e.g., HDP oxide) and / or a high aspect ratio process (HARP) dielectric material (e.g., HARP oxide).The insulating layer 16 has a thickness T 2 and the patterned conductive layer 14 has a thickness T 1. In an embodiment, the thickness T 2 of the insulating layer 16 is about 1200 angstroms (Å). It is understood that the insulating layer 16 may include one or more dielectric materials and / or one or more dielectric layers.In some existing transistors, a gate structure of a transistor includes a gate oxide and a poly serving as a gate electrode. A total thickness of the gate structure is ideally the sum of the thickness of the gate oxide and the poly. Typically, a dielectric layer is adapted to cover the gate and an active region of the transistor such that the gate and the active region are insulated from a metal layer (such as a metal 1 layer) for routing. To cover the gate of the transistor, the thickness of the gate must not be thicker than that of the dielectric layer. Otherwise, the gate may not be covered by the dielectric layer and thus the gate of the transistor may physically contact a patterned conductive layer for routing. The transistor can accordingly operate abnormally and even be damaged.As semiconductor fabrication continues to develop, dimensions or features of a semiconductor device are becoming smaller and smaller. As a result, the thickness of a dielectric layer in the semiconductor device also shrinks. However, in some applications, such as power supply systems, a semiconductor device is required to withstand relatively high voltage. For example, if such a transistor were to withstand the relatively high voltage, the thickness of a gate oxide of the transistor would become relatively thicker, which is countering the trend of downsizing in semiconductor fabrication. Nevertheless, in such applications, the gate is inevitably thicker than the dielectric layer.In an embodiment, in a high voltage application, the thickness of a gate oxide of a transistor for withstanding the high voltage is about 800 angstroms. Moreover, the thickness of a poly of the transistor is about 800 angstroms. Therefore, a total thickness of the gate on the substrate surface is about 1600 angstroms. For example, in 28 nm manufacturing technology, the design rule limits the thickness of a dielectric layer measured from a substrate surface to not more than about 1200 angstroms. In this case, the gate is thicker than the dielectric layer. As a result, the dielectric layer may not cover the gate of the transistor and, accordingly, may not isolate the gate of the transistor from a patterned metal layer for routing. It is therefore desirable that a transistor structure according to the present disclosure meet the size requirements for the advanced processes (such as the 28 nm manufacturing technology).In the present disclosure, the insulating layer 16 (i.e., the dielectric layer) is taken as a gate oxide of the gate 11 (i.e., as part of the transistor 10). Such an arrangement eliminates the problems of size limitation caused by the existing transistors. In the advanced processes, the insulating layer 16 may have a thickness less than 1200 angstroms (Å). Further, since the insulating layer 16 is typically thicker than the gate oxide of the existing transistors, the transistor 10 according to the present embodiment can withstand a higher voltage than the existing transistors.Moreover, in the existing transistors, a poly serving as a gate electrode is independent of a metal 1 layer for routing. In contrast, in the present embodiment, the patterned conductive layer 14 serving as a gate electrode is a portion of an interconnection layer for routing (such as a metal 1 layer). Taking the patterned conductive layer 14 for a component of the gate 11 from the metal 1 layer does not make the manufacturing process complex. In addition, there is no additional cost. Moreover, since the patterned conductive layer 14 takes advantage of the metal 1 layer, no spacer is required on its sides. In fact, the manufacturing process is simplified.In a high voltage device, a blocking breakdown voltage refers to a breakdown voltage measured under the condition that a gate of a transistor receives a reference ground voltage. In addition, a conductive breakdown voltage refers to a breakdown voltage measured under the condition that a gate of a transistor receives a logic high voltage. The two breakdown voltages are important power indicators of a power transistor. Typically, the conducting and blocking breakdown voltages are determined by the design of an active region (such as the first well 124, the second well 120, and the third well 122 in the present disclosure) of the transistor and are not relative to an arrangement of a gate of the transistor. The design involves placement of the wells in the active region and their associated concentration, depth and width. The present disclosure addresses the aforementioned problems due to size limitation in advanced processes without modifying (or changing) the design of the first well 124, the second well 120, and the third well 122. Therefore, the conducting and blocking breakdown voltages are not affected. The power is maintained substantially unchanged relative to the conducting and blocking breakdown voltages.The present disclosure is applicable to other semiconductor devices where the gate of a transistor may be formed thicker than a dielectric layer.FIG. 1B is a design view of the transistor 10 shown in FIG. 1A, in accordance with some embodiments of the present disclosure. Referring to FIG. 1B, the insulating layer 16, which serves as a gate oxide of the transistor 10, completely covers the substrate 18. The patterned conductive layer 14 overlies the insulating layer 16 and over the second well 120 and the third well 122 in the substrate 18 Based on such a design, for reasons similar to those discussed and illustrated with reference to FIG. 1A, the problem of the gate of the existing transistor being thicker than a dielectric layer is avoided.FIGS. 1C to 1F are schematic diagrams illustrating a method of manufacturing the transistor 10 of the semiconductor device 1 shown in FIG. 1A according to some embodiments of the present disclosure. It is to be understood that FIGS. 1C to 1F have been simplified for clarity. Referring to FIG. 1C, a substrate 18 is obtained. In some embodiments, the substrate 18 includes a p-type substrate.Referring to FIG. 1D, a first well 124, a second well 120, and a third well 122 are defined in the substrate 18 by, for example, a masking process and one or more ion implantation processes followed by a drive-in process. In the present embodiment, the first well 124 serves as a high voltage p-well (PVNW), and each of the second well 120 and the third well 122 serves as a high voltage n-well (HVNW). The first well 124 may be defined first, and then the second well 120 and the third well 122 are defined. Those skilled in the art will appreciate that the order of implementation of the first well 124, the second well 120, and the third well 122 may vary without departing from the spirit of the present disclosure.To provide a vertically controlled profile in a doped region, such as each of the first well 124, the second well 124, and the third well 122, multiple consecutive implants may be performed to create multiple implant regions. The consecutive implants can be used to tailor the doping profile by varying the implant energy, concentration and depth of each implant step. Additionally, the successive implant steps may implant different dopants to further adapt the doping profile for a particular doped region.Referring to FIG. 1E, an insulating layer 16 is formed on the substrate 18 by, for example, a deposition process followed by a planarization process.Referring to FIG. 1F, a patterned conductive layer 14 is formed on the substrate 18 and over the first well 124, the second well 120, and the third well 126 by, for example, a deposition process of depositing a metal 1 layer followed by an etching process.FIG. 2A is a cross-sectional view of a semiconductor device 2 for explaining routing, according to some embodiments of the present disclosure. Referring to FIG. 2A, the semiconductor device 2 is similar to the semiconductor device 1 described and illustrated with reference to FIG. 1A, except that the semiconductor device 2 includes, for example, a transistor 20, an interconnect feature 26, and an interconnect feature 28. Transistor 20 is similar to transistor 10 described and illustrated with reference to FIG. 1A, except that transistor 20 includes, for example, a gate 21 that further includes a patterned conductive layer 24. The interconnect feature 26, which connects the interconnect feature 28 to a second source / drain region 122 of the transistor 20, is configured for routing. Additionally, a heavily doped region (not shown) is formed in the second source / drain region 122 for ohmic contact with the interconnect feature 26. The interconnect feature 26 is formed as a contact in a semiconductor fabrication process, for example. Moreover, the patterned conductive layer 24, which serves as a gate electrode of the transistor 20, and the interconnect feature 28 are in the same interconnect layer, such as a metal 1 (M1) layer, in a semiconductor fabrication process.FIG. 2B is a design view of the semiconductor device 2 shown in FIG. 2, in accordance with some embodiments of the present disclosure. FIG. 2B is shown to better explain an application of the patterned conductive layer 24 and the interconnect feature 28 located in the same interconnect layer. Referring to FIG. 2B, the patterned conductive layer 24 and the interconnect feature 28 are in the same interconnect layer, but independently (or separately) from each other. The interconnect feature 26 and the interconnect feature 28 are in communication with the second source / drain region 122.FIG. 3A is a cross-sectional view of a semiconductor device 3 including a first transistor 30 and a second transistor 31, according to some embodiments of the present disclosure. Referring to FIG. 3A, the semiconductor device 3 is similar to the semiconductor device 1 described and illustrated with reference to FIG. 1A, except that the semiconductor device 3 includes the first transistor 30 operating in a first voltage domain and the second transistor 31 operating in a second voltage domain different from the first voltage domain. More specifically, the first transistor 30 operates in a relatively high voltage domain (such as 3.3 V) and is therefore called a high voltage (HV) transistor. In contrast, transistor 31 operates in a relatively low voltage domain (such as 1.1 V or 1.2 V) and is therefore called a low voltage (LV) transistor. However, the second transistor 31 is not limited thereto and may operate in a voltage domain other than the relatively low voltage domain. For example, the second transistor 31 operates in a normal voltage domain of 2.5 V. In this case, the second transistor 31 is called a normal voltage transistor.The first transistor 30 is similar to the transistor 10 described and illustrated with reference to FIG. 1A, except for an insulating layer 32. Accordingly, the insulating layer 32 covers not only the active region 12 of the first transistor 30 but also an active region 32 of the second transistor 31 In addition, the insulating layer 32 of a gate 302 of the first transistor 30 encapsulates the gate 316 of the second transistor 31. The insulating layer 32 has a thickness T 4 that is greater than a thickness T 3 of the gate 316 of the second transistor 31. In some embodiments, the thickness T 4 is about 1200 angstroms (Å).The active region 12 of the first transistor 30 is defined by a plurality of isolation structures 32. The isolation structure 32 may be filled with an insulator or dielectric material. In an embodiment, the isolation structure 32 includes shallow trench isolation (STI). Alternatively, the isolation structure 32 includes a LOCOS (local oxidation of silicon) configuration. The isolation structure 32 includes silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate (FSG), and / or a low dielectric material as known in the art.Further, the isolation structure 32 further defines the boundary of wells 36. the well 36 serves as a receptacle and is configured for electrical connection of the substrate 18. A voltage may be applied to the substrate 18 via the well 36.The second transistor 31 includes the gate 316 on the substrate 18 and the active region 32 in the substrate 18. the active region 32 includes a well 318, a first doped region 311, and a second doped region 313 in the well 318. Moreover, well 318 is isolated from well 36 by a well 38. Well 38 is of a dopant type opposite to well 318 and well 36.The well 318 includes a first dopant type and the first doped region 311 and the second doped region 313 include a second dopant type opposite the first dopant type. In the present disclosure, the well 318 is a p-well, the first doped region 311, and the second doped region 313 are n-type doped regions. As a result, the second transistor 31 includes an n-type transistor structure. The second transistor 31 includes, for example, an n-type metal oxide semiconductor (NMOS) or an n-type metal oxide semiconductor field effect transistor (NMOSFET). Although only one gate structure is illustrated, it will be appreciated that transistor 31 may include a number of gate structures for NMOSs, including short channel and long channel transistors.Those skilled in the art will appreciate that the embodiments disclosed herein using an NMOS transistor are also applicable to a PMOS transistor, a p-type metal oxide semiconductor field effect transistor (PMOSFET), a PNP transistor, or the like. For example, the well 318 is an n-well and the first doped region 311 and the second doped region 313 are p-type regions. In addition, those skilled in the art will appreciate that while the dopants are discussed in certain terms and with respect to certain dopant materials, concentrations, and doping depths, alternative doping characteristics may be advantageously employed.The gate 316 includes a gate oxide 314 on the substrate 18 and a poly 312 serving as a gate electrode on the gate oxide 314. Gate 316 includes spacers on its sides, but for clarity of illustration, the spacers are omitted herein. Unlike some existing transistors designed for operation at a relatively high voltage, the second transistor 31 operates at a relatively low voltage and a thickness of the gate oxide 314 is therefore relatively thin. Therefore, the thickness T 3 of the gate 316 does not exceed that of a dielectric layer (i.e., in the present disclosure, as shown in FIG. 3A, the thickness T 3 is thinner than the thickness T 4), wherein the dielectric layer is adapted to isolate a gate from a patterned conductive layer for routing. The gate 316 of the second transistor 31 does not experience the problems of existing transistors designed for operation under a relatively high voltage.In the present embodiment, the insulating layer 32 for the second transistor 31 serves as a dielectric layer for insulating the gate 316 and active region 32 from a patterned conductive layer (not shown) for routing. In contrast, the insulating layer 32 for the first transistor 30 serves as a gate oxide for the gate 302.With an insulating layer serving as a gate oxide of a high voltage transistor and serving as a dielectric layer for a low or normal voltage transistor, the high voltage transistor and the low or normal voltage transistor can be easily integrated without making the semiconductor manufacturing process difficult. More specifically, because the insulating layer 32 is taken as a gate oxide of the first transistor 30, a photolithography process is simplified and at least three masks are eliminated.FIGS. 3B to 3G are schematic diagrams illustrating a method of manufacturing the semiconductor device 3 shown in FIG. 3A according to some embodiments of the present disclosure. Referring to FIG. 3B, a substrate 18 is obtained. In some embodiments, the substrate 18 includes a p-type dopant.Referring to FIG. 3C, isolation structures 34 are formed in the substrate 18 by, for example, a deposition process, an etching process, a pulldown process, an annealing process, and a chemical mechanical planarization process, which are performed sequentially in series. In an embodiment, isolation structures 34 include an STI structure.Referring to FIG. 3D, a first well 124, a second well 120, a third well 122, a well 36, wells 38, and a well 318 are defined in the substrate 18 by, for example, an ion implantation process followed by a drive-in process. In some embodiments, the first well 124 serves as a high voltage p-well (HVPWM), the second well 120 serves as a high voltage n-well (HVNOW), the third well 122 also serves as a high voltage n-well, the wells 36 serve as a high voltage p-well, and the well 38 serves as a high voltage n-well.Subsequently, a first doped region 311 and a second doped region 313 are defined in the well 318, for example, by an ion implantation process followed by a drive-in process. In some embodiments, the first doped region 311 and the second doped region 313 serve as n-type doped regions.Referring to FIG. 3E, a gate oxide 314 is formed on the substrate 18 by, for example, a deposition process followed by a photolithography process. Subsequently, a poly 312 is formed on the gate oxide 314 by, for example, a deposition process followed by a photolithography process.Referring to FIG. 3F, an insulating layer 32 is formed on the substrate 18 and the poly 312 by, for example, a deposition process followed by a planarization process such as chemical mechanical polishing (CMP).Referring to FIG. 3G, a patterned conductive layer 14 is formed on the insulating layer 32 over the first well 124, between the second well 120 and the third well 122, for example, by a deposition process followed by an etching process.FIG. 4 is a cross-sectional view of a semiconductor device 4 according to some embodiments of the present disclosure. Referring to FIG. 4, the semiconductor device 4 is similar to the semiconductor device 3 described and illustrated with reference to FIG. 3A, except that, for example, the semiconductor device 4 further includes a patterned conductive layer 42 for routing a second transistor 31. The semiconductor device 4 also includes an interconnect feature 44 in an insulating layer 32 configured to connect a gate 316 of the second transistor 31 to the patterned conductive layer 42. In the present embodiment, the patterned conductive layer 42 for routing the second transistor 31 and a patterned conductive layer 14 for routing the first transistor 30 are located in the same conductive layer (or the same interconnection layer).As discussed in the embodiment of FIG. 3A, in the semiconductor device 4, with the insulating layer 32 serving as a gate oxide of a high voltage transistor 30 and serving as a dielectric layer for a low or normal voltage transistor, the high voltage transistor 30 and the low or normal voltage transistor can be integrated together without making the semiconductor manufacturing process difficult.FIG. 5 is a flow diagram illustrating a method 5 of forming a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 5, a substrate is provided in operation 50. The substrate is similar to the substrate 18 described and illustrated with reference to FIG. 3A.In operation 52, a first active region associated with a first transistor is defined in the substrate and a second active region associated with a second transistor is also defined in the substrate. The first active region associated with the first transistor is similar to the active region 12 described and illustrated with reference to FIG. 3A. In addition, the second active region associated with the second transistor is similar to the active region 32 described and illustrated with reference to FIG. 3A.In operation 54, a second gate associated with the second transistor is formed on the second active region associated with the second transistor. The second gate and the second active region define the second transistor. The second gate associated with the second transistor is similar to gate 316 described and illustrated with reference to FIG. 3A.In operation 56, an insulating layer is formed covering the second gate, the second active region, the first active region, and the support layer. The insulating layer serves as a component of a first gate of a first transistor associated with the first active region. The insulating layer is similar to the insulating layer 32 described and illustrated with reference to FIG. 3A.In operation 58, a patterned conductive layer serving as another component of the first gate of the first transistor is formed on the insulating layer. The first gate and the first active region define the first transistor. The patterned conductive layer is similar to the insulating layer 14 described and illustrated with reference to FIG. 3A.Some embodiments have one or a combination of the following features and / or advantages. In some embodiments, a semiconductor device includes a transistor. The transistor includes an active region in a substrate, a patterned conductive layer that is a portion of an interconnect layer for routing, and an insulating layer extending over the substrate and configured to isolate the active region from the patterned conductive layer. The patterned conductive layer and the insulating layer serve as a gate of the transistor.In some embodiments, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a gate and the gate includes an insulating layer. The second transistor includes a gate covered by the insulating layer of the gate of the first transistor.In some embodiments, a method includes providing a substrate; defining a first active region and a second active region in the substrate; forming a second gate on the substrate, the second gate and the second active region defining a second transistor; and forming an insulating layer covering the second gate, the second active region, and the first active region, the insulating layer serving as a component of a first gate of a first transistor associated with the first active region.wherein,

Claims

A semiconductor device comprising: a transistor (10; 20; 30) including: an active region (12) in a substrate (18); a patterned conductive layer (14; 24) that is a portion of an interconnect layer for routing; an insulating layer (32) extending over the substrate (18) and configured to isolate the active region (12) from the patterned conductive layer (14; 24), wherein the patterned conductive layer (14; 24) and the insulating layer (32) serve as a gate (21; 302) of the transistor (10; 20; 30); and an interconnect feature (28) configured to communicate with a drain / source region (122) in the active region (12), wherein the interconnect feature (28) and the patterned conductive layer (14; 24) are in the same interconnect layer.The semiconductor device according to claim 1, wherein the insulating layer (16; 32) completely covers the active region (12).The semiconductor device of claim 1 or 2, wherein the patterned conductive layer (14; 24) overlies the insulating layer (32) and the insulating layer (32) overlies the active region (12).A semiconductor device according to any preceding claim, wherein the active region (12) is located in the substrate (18) and the insulating layer (16) completely covers the substrate (18).The semiconductor device of any preceding claim, wherein a drain / source region (122) of the active region (12) is connected to the patterned conductive layer (24) via an interconnect feature (26) in the insulating layer (16).The semiconductor device of claim 1, wherein the interconnect feature (28) and the patterned conductive layer (14; 24) are independent of each other.The semiconductor device of any preceding claim, wherein the patterned conductive layer (14; 24) is in one of a metal 1 layer and a metal 2 layer.The semiconductor device of any preceding claim, wherein the active region (12) includes a well (124) where a channel (126) of the transistor (10; 20; 30) is defined, the patterned conductive layer (14; 24) being deposited over the well (24).A semiconductor device comprising: a first transistor (30) having a gate (302) comprising an insulating layer (32) and further comprising a first patterned conductive layer (14); a second transistor (31) comprising a gate (316) covered by the insulating layer (32) of the gate (302) of the first transistor (30); a second patterned conductive layer (42) for routing the second transistor (31), wherein the first patterned conductive layer (14) and second patterned conductive layer (42) are in the same interconnection layer.The semiconductor device of claim 9, wherein the gate (316) of the second transistor (31) is encapsulated by the insulating layer (32) of the gate (302) of the first transistor (30).The semiconductor device according to claim 9 or 10, wherein the insulating layer (32) of the gate (302) of the first transistor (30) is thicker than the gate (316) of the second transistor (31).The semiconductor device according to any one of claims 9 to 11, wherein the second transistor (31) is defined by the gate (316) of the second transistor (31) and an active region (311, 313), the active region (311, 313) being covered by the insulating layer (32) of the gate (302) of the first transistor (30).The semiconductor device of claim 12, wherein the active region (311, 313) of the second transistor (31) includes a well, a first doped region in the well, and a second doped region in the well.The semiconductor device of any of claims 9 to 13, wherein the first patterned conductive layer (14) extends over an active region (12) of the first transistor (30).The semiconductor device of claim 14, further comprising an interconnect feature (44) configured to connect the gate (316) of the second transistor (31) to the second patterned conductive layer (42), wherein the interconnect feature (44) is in the insulating layer (32) of the gate (302) of the first transistor (30).The semiconductor device of claim 9 or 15, wherein the first transistor (30) includes a first well (124), a second well (120), and a third well (122), wherein the first well (124) is between the second well (120) and the third well (122), and wherein one of the first and second wells (124, 122) serves as a drain of the first transistor (30) and the other (122) serves as a source region of the first transistor (30).A method comprising: providing a substrate (18); defining a first active region (12) and a second active region (318) in the substrate (18); forming a second gate (316) on the substrate (18), the second gate (316) and the second active region (318) defining a second transistor (31); and forming an insulating layer (32) covering the second gate (316), the second active region (318) and the first active region (12), the insulating layer (32) serving as a component of a first gate (302) of a first transistor (30), the first transistor (30) being associated with the first active region (12); and forming a patterned conductive layer (14) on the insulating layer (32) as another component of the first gate (302) of the first transistor (30), wherein the first patterned conductive layer (14) and a second patterned conductive layer (42) for routing the second transistor (31) are in the same interconnection layer.

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