METHOD FOR PROCESSING A WAFER AND METHOD FOR PROCESSING A CARRIER

Abstract

A method for processing a wafer, the method comprising: scanning the wafer with a focused laser beam to form a defect structure within the wafer, the defect structure defining a first region of the wafer located at a first side of the defect structure, a second region of the wafer located at a second side of the defect structure opposite the first side, and an edge region laterally surrounding the defect structure and extending from a first surface of the wafer to a second surface of the wafer opposite the first side, wherein a surface area of ​​the first region is larger than a surface area of ​​the edge region, and wherein the second region is connected to the first region by the edge region, and subsequently separating the first region and the second region from each other along the defect structure, the first region remaining in one piece;wherein the focused laser beam scans in a first plane, which has a first distance from the first surface and is aligned parallel to the first surface, and in a second plane, which has a second distance from the first surface and is aligned parallel to the first surface, the second distance being greater than the first distance; and wherein the first plane defines chip regions in the first region and wherein the second plane defines interface regions and chip edge regions, each laterally surrounding the chip regions.

Description

Technical field

[0001] Different embodiments generally relate to a method for processing a wafer and a method for processing a carrier. background

[0002] In general, a wide variety of applications exist in microelectronics, microsystems, biomedicine, and other fields for thin or ultrathin chips, such as those formed on a substrate with a thickness of approximately a few tens of micrometers, for example, on a silicon wafer less than about 50 μm thick. One method for producing such thin or ultrathin wafers is wafer grinding. Wafer grinding techniques based on mechanical treatment of the wafer, as is typically used for wafer thinning, can introduce defects into the wafer and can be difficult to control, potentially leading to yield loss and therefore high costs.However, attempts to manufacture ultrathin chips based on wafer preprocessing may exist, whereby after CMOS processing, each individual chip is separated from the preprocessed wafer using a so-called “pick, crack & place” process, consisting of several ultrathin chips. TM The process can be removed. Summary

[0003] According to various embodiments, a method for processing a wafer can include scanning the wafer with a focused laser beam to create a defect structure within the wafer, wherein the defect structure defines a first region of the wafer located on a first side of the defect structure, a second region of the wafer located on a second side of the defect structure opposite the first side, and an edge region that laterally surrounds the defect structure and extends from a first surface of the wafer to a second surface of the wafer opposite the first surface. A surface region of the first region is larger than a surface region of the second region, and the second region is connected to the first region by the edge region.The procedure can further include separating the first area and the second area from each other along the defect structure, with the first area remaining in one piece. Brief description of the drawings

[0004] In the drawings, the same reference numerals generally refer to the same proportions throughout the different views. The drawings are not necessarily to scale; instead, they generally emphasize the principles of the invention. The following description details various embodiments of the invention with reference to the following drawings, in which:

[0005] Fig. 1 shows a schematic flowchart of a process for processing a wafer according to different embodiments;

[0006] Fig. 2A to Fig. 2C each show a wafer in a schematic view at different processing stages according to different embodiments;

[0007] Fig. 3A to Fig. 3C each show a wafer in a schematic view at different processing stages according to different embodiments;

[0008] Fig. 4A and Fig. 4B each show a wafer in a schematic view at different processing stages according to different embodiments;

[0009] Fig. Figure 5 shows a schematic flowchart of a process for processing a wafer according to different embodiments;

[0010] Fig. Figure 6 shows a schematic flowchart of a process for processing a wafer according to different embodiments;

[0011] Fig. Figure 7A shows a schematic flowchart of a process for processing a wafer according to different embodiments;

[0012] Fig. 7B to Fig. Figure 7G shows wafer processing via a focused laser beam in various schematic views according to different embodiments; and

[0013] Fig. 8A and Fig. Figure 8B shows a wafer and a chip in a schematic view according to different embodiments. Description

[0014] The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments in which the invention can be practiced.

[0015] The following detailed description refers to the accompanying drawings, which illustrate specific details and embodiments in which the invention can be practiced. These embodiments are described with sufficient precision to enable those skilled in the art to practice the invention. Other embodiments may be used, and structural, logical, and electrical modifications may be made without departing from the scope of protection of the invention. The various embodiments are not necessarily mutually exclusive, since some embodiments may be combined with one or more other embodiments to form new embodiments. Various embodiments are described in connection with methods, and various embodiments are described in connection with apparatus.However, it can be understood that embodiments described in connection with embodiments apply similarly to devices, and vice versa.

[0016] The terms “at least one” and “one or more” can be understood to include any integer greater than or equal to one, i.e., one, two, three, four, [...], etc. The term “several” or the expression “one or more” can be understood to include any integer greater than or equal to two, i.e., two, three, four, five, [...], etc.

[0017] The word "over," used here to describe the formation of a feature, e.g., a layer "over" a side or surface, can be used to mean that the feature, e.g., the layer, can be formed "directly on," e.g., in direct contact with, the implied side or surface. The word "over," used here to describe the formation of a feature, e.g., a layer "over" a side or surface, can also be used to mean that the feature, e.g., the layer, can be formed "indirectly on" the implied side or surface, with one or more additional layers positioned between the implied side or surface and the formed layer.

[0018] Similarly, the word "cover," used here to describe a feature that is arranged over another, e.g., a layer that "covers" a side or surface, can be used to mean that the feature, e.g., the layer, can be arranged over and in direct contact with the implied side or surface. The word "cover," used here to describe a feature that is arranged over another, e.g., a layer that "covers" a side or surface, can also be used to mean that the feature, e.g., the layer, can be arranged over and in indirect contact with the implied side or surface, with one or more additional layers arranged between the implied side or surface and the covering layer.

[0019] The term “lateral,” when used in reference to the “lateral” extent of a structure (or structural element) provided on or in a support (e.g., a layer, substrate, or semiconductor workpiece), can be used here to mean an extent or positional relationship along a surface of the support. That is to say, a surface of a support (e.g., a substrate surface, a wafer surface, or a workpiece surface) can serve as a reference, usually referred to as the primary machining surface. Furthermore, the term “width,” when used in reference to the “width” of a structure (or structural element), can be used here to mean the lateral extent of a structure.Furthermore, the term "height," used here in relation to the height of a structure (or structural element), can be understood as meaning the extent of a structure along a direction perpendicular to the surface of a support (e.g., perpendicular to the main working surface of a support). Similarly, the term "thickness," used here in relation to the "thickness" of a layer, can be understood as meaning the spatial extent of the layer perpendicular to the surface of the substrate (the material or material structure) on which the layer is applied. If a surface of the substrate is parallel to the surface of the support (e.g., parallel to the main working surface), the "thickness" of the layer applied to the surface of the substrate can be the same as the height of the layer.The thickness of a wafer or wafer area can be understood as the spatial extent of the wafer perpendicular to a primary processing surface. Generally, a wafer can have a front surface, such as a primary processing surface, and a back surface opposite the front surface. These two surfaces of a wafer are referred to here, without loss of generality, as the first surface and the second surface.

[0020] According to various embodiments, a semiconductor wafer (or any other suitable semiconductor substrate) can be made of or contain silicon. However, other semiconductor materials of various types can be used in a similar manner, e.g., germanium, groups III to V (e.g., SiC), or other types containing, for example, polymers. In one embodiment, a semiconductor layer is a wafer made of silicon (e.g., p-type or n-type doped). In an alternative embodiment, the semiconductor layer is a silicon-on-insulator (SOI) wafer.

[0021] Fig. Figure 1 shows a schematic flowchart of a process 100 for processing a wafer (e.g., a carrier in wafer size and / or wafer shape) according to various embodiments, wherein the method 100 May contain the following: in 110Scanning the wafer with a focused laser beam to create a defect structure (also called a perforation structure) within the wafer, wherein the defect structure defines a first region of the wafer located at a first side of the defect structure, and a second region of the wafer located at a second side of the defect structure opposite the first side, and an edge region that laterally surrounds the defect structure and extends from a first surface of the wafer to a second surface of the wafer opposite the first side, wherein a surface area of ​​the first region is larger than a surface area of ​​the edge region, and wherein the second region is connected to the first region by the edge region, and subsequently in 120 Separating the first area and the second area from each other along the defect structure, with the first area remaining in one piece.

[0022] To illustrate, the edge region can be small compared to the first region, allowing the first region to be used as a thinned wafer after the first and second regions are separated. For example, the wafer might have a round shape, and the edge region could be its outer edge.

[0023] Fig. 2A and Fig. 2B each represent one wafer 200 during processing, e.g. during the process 110 of procedures 100 is executed or after the process 110 of procedures 100 has been carried out, and Fig. 2C provides the wafer 200 during processing, e.g. during the process 120 of procedures 100 is executed or after the process 120 of procedures 100 has been executed. The wafer 200 can be done similarly via the in Fig. 5 presented methods 500 or that in Fig. 6 illustrated procedures 600 to be processed.

[0024] Fig. Figure 2A shows a schematic view of a cross-section of a wafer. 200 , after a defect structure 204 within the wafer 200 It has been formed according to various embodiments. Fig. Figure 2B shows a schematic top view of the wafer. 200 The wafer 200 can a first surface 200s exhibit the first surface 200s This can be a so-called processing surface, main processing surface, or front side of the wafer. 200 be. Furthermore, the wafer can 200 a second surface 200r opposite the first surface 200s exhibit the second surface 200s can be a so-called back surface of the wafer 200 be. The wafer 200 can have a lateral expansion200w , also known as the width or diameter of the wafer 200 designated, along the direction 201 and a vertical extension 200t , also known as wafer thickness 200 designated, along the direction 205 perpendicular to the direction 201 exhibiting various characteristics. According to different embodiments, the lateral extension can 200w of the wafer 200 be larger than approximately 50 mm, e.g., in the range of approximately 50 mm to approximately 450 mm or even larger than 450 mm. According to various embodiments, the vertical extent can be 200t of the wafer 200 be larger than approximately 100 μm, e.g. in the range of approximately 0.1 mm to approximately 2 mm, e.g. in the range of approximately 0.5 mm to approximately 1 mm.

[0025] According to various embodiments, the wafer 200 essentially have a round shape, as for example in Fig. 2B shown. Wafer 200Wafers with a round shape can be used, for example, in semiconductor processing. 200 However, it can have any other suitable plate shape, e.g., a polygonal shape, such as a rectangular or square shape. If the wafer 200 The wafer can have a polygonal shape. 200 have rounded or beveled corners, as used, for example, in photovoltaic devices (e.g., solar cells).

[0026] According to various embodiments, the wafer 200 a defect structure 204 (also known as predetermined fracture structure or defect structure) 204 The defect structure is contained within the wafer. 204This can be achieved using a focused laser beam, as described here. The focused laser beam can be used to locally damage the crystal of the wafer material (e.g., to alter the crystal structure) and thereby change the defect structure. 204 within the wafer 200 to form the defect structure 204 can be a predetermined breaking point (e.g., a predetermined breaking layer) due to a local modification of the wafer. 200 This can be understood through the focused laser beam. The wafer 200 It can contain silicon or can be a silicon wafer containing, for example, single-crystal silicon or made from it. According to various embodiments, the focused laser beam can be used to locally create crystal damage in the single-crystal silicon and thereby define the defect structure. 204 to provide the defect structure 204May contain polycrystalline and / or amorphous wafer material, e.g., polycrystalline and / or amorphous silicon.

[0027] According to various embodiments, a defect structure can 204 a first area 202a of the wafer 200 , that above (or in other words over) the defect structure 204 is arranged, and a second area 202b of the wafer 200 , that below (or in other words under) the defect structure 204 is arranged, define. In other words, the defect structure can be defined. 204 a first area 202a of the wafer 200 , which is located on a first side of the defect structure 204 is located, and a second area 202b of the wafer 200 , which is located on a second side of the defect structure 204 opposite the first page, define. The defect structure is clearly separated. 204 a first area 202a(e.g. a surface area) of the wafer 200 and a second area 202b (e.g. a main area) of the wafer 200 spatially separated. The first area 202 can the first surface 202a included, and the second area 202b can the second surface 202b contain.

[0028] According to various embodiments, the defect structure can 204 Completely through the side of the wafer 200 extend, as in the Fig. 2A to Fig. 2C is shown. In other words, the lateral extent of the defect structure can be 204 be the same as the lateral extension 200w of the wafer 200 In this case, only the defect structure can be determined. 204 the first area 202a and the second area 202b connect with each other before they are separated. Fig. 2C shows a schematic cross-section of the first area. 202a and the second area 202b represent, which along the defect structure 204 are separated from each other. According to various embodiments, the first area can be 202a and the second area 202b by breaking (or in other words splitting) the defect structure 204 They can be separated from each other. For this, the wafer can be used. 200 are subjected to mechanical stress, e.g. by bending the wafer 200 , to break the defect structure 204 to support or effect. According to various embodiments, after separating the first area 202a and the second area 202b each other a part 204a the defect structure 204 in the first area 202 adhere, and another part 204b the defect structure 204 can at the second area 202adhere. Alternatively, after separating the first area, 202a and the second area 202b the defect structure from each other 204 only in the first area 202 or only in the second area 202 adhere.

[0029] If desired, the remaining parts can be removed according to various embodiments. 204a , 204b the defect structure 204 after the division of the first area 202a and the second area 202b They are separated from each other, e.g. by etching, grinding and the like.

[0030] Alternatively to those relating to the Fig. 2A to Fig. In the embodiments described in 2C, the defect structure 204 be formed in such a way that an edge area 302 the defect structure 204 surrounds laterally, as in the Fig. 3A to Fig. Figure 3B is shown. In this case, the lateral extension can307 the defect structure 204 be smaller than the lateral extent 200w of the wafer 200 . Fig. Figure 3A shows a schematic view of a cross-section of a wafer. 200 , after a defect structure 204 within the wafer 200 It has been formed according to various embodiments. Fig. Figure 3B shows a schematic top view of the wafer. 200 dar.

[0031] According to various embodiments, the edge area can 302 from the first surface 200s of the wafer 200 to the second surface 200r of the wafer 200 opposite the first surface 200s extend, as in Fig. 3A is shown. The lateral extent 302w of the edge area 302 can be caused by lateral expansion 307 the defect structure 204 and the lateral expansion 200w of the wafer200 be defined. In the case that the wafer 200 has a round shape, as exemplified in Fig. As shown in 3B, the width can 302w of the edge area 302 half the difference between the diameter 200w of the wafer 200 and the diameter 307 the defect structure 204 be.

[0032] According to various embodiments, the defect structure 204 a lateral expansion 307 exhibiting dimensions larger than approximately 100 μm, e.g., larger than approximately 1 mm, e.g., larger than approximately 1 cm, e.g., larger than approximately 10 cm. The lateral extent 307 the defect structure 204 However, this can be caused by the lateral expansion of the wafer. 200 be limited (e.g. taking into account the width) 302w of the edge area 302 According to various embodiments, the width can 302w of the edge area 302be small compared to its lateral extent 200w of the wafer 200 e.g. the width 302w of the edge area 302 smaller than approximately 10% of the lateral extent 200w of the wafer 200 be.

[0033] According to various embodiments, the surface area of ​​the first region can 202a be larger than a surface area of ​​the edge region 302e The surface area of ​​the first area 202a can be caused by lateral expansion 307 and the shape of the defect structure 204 be defined. Accordingly, the surface area of ​​the edge region can be defined. 302e through lateral expansion 307 and the shape of the defect structure 204 and the lateral expansion 200w and the shape of the wafer 200 be defined. Visually, the surface area of ​​the first region can be the same as the area of ​​the defect structure.204 with reference to (e.g. projected onto) the geometric plane defined by the directions 201 , 203 is spanned, e.g. with reference to the geometric plane defined by the first surface 202a of the wafer. In other words, different areas referred to here can be defined with respect to the geometric plane defined by the surface. 200s of the wafer 200 is defined, can be compared with each other.

[0034] According to various embodiments, the lateral extension can 200w of the wafer 200 in the range of approximately 150 mm to approximately 450 mm, whereby the method 100 not through lateral expansion 200w of the wafer 200 It may be limited. Accordingly, the lateral expansion may be restricted. 307 the defect structure 204 be smaller than the lateral extent 200w of the wafer 200e.g., in the range of approximately 149 mm to approximately 449 mm. According to various embodiments, the surface area of ​​the edge region can be 302 in the range of approximately 0.01% to approximately 20% of the wafer's surface area 200 be, for example, in the range of about 0.1% to about 10%.

[0035] According to various embodiments, the surface area of ​​the first region can 202a be larger than the surface area of ​​the edge region 302 For example, the surface area ratio (area of ​​the first region / area of ​​the edge region) can be greater than 3, or greater than 4, or greater than 5, or greater than 6, or greater than 7, or greater than 8, or greater than 9, or greater than 10, or greater than 20, or greater than 50, or greater than 100, or greater than 200, or greater than 500. In other words, the surface area of ​​the first region can be 202abe as large as possible and the surface area of ​​the edge region 302 can be as small as possible (e.g., by the desired width). 302w of the edge area 302 (limited). As described above, the surface area of ​​the first area can 202a and the surface area of ​​the edge region 302 for example, in relation to the geometric plane defined by the directions 201 , 203 It is stretched out, and can be measured.

[0036] According to various embodiments, the second area can 204b with the first area 204a through the edge area 302 and through the defect structure 204 They must be connected. Therefore, separating the first area can 202a and the second area 202b Breaking of the defect structure from each other 204 , as above with mountain up Fig. 2C described, and severing the connection that passes through the edge area302 is provided, included. According to various embodiments, separating the first area is possible. 202a and the second area 202b Breaking of the defect structure from each other 204 and breaking of the edge region 302 of the wafer 200 e.g. via a mechanical load applied to the wafer 200 is exercised, include (cf. Fig. 3C). Alternatively, a separation structure can be formed to separate the first area. 202a and the second area 202b to support each other (cf. Fig. 4A and Fig. 4B).

[0037] Fig. 3C presents a schematic cross-section of the first area. 202a and the second area 202b represent, which along the defect structure 204 by breaking the defect structure 204 and breaking of the edge region 302 are separated from each other (cf. Fig. 2C).

[0038] Fig. Figure 4A shows a schematic view of a cross-section of a wafer. 200 , after a defect structure 204 within the wafer 200 has been formed and after a separation structure 414 within the wafer 200 It has been formed according to various embodiments.

[0039] According to various embodiments, the separation structure can 414 from the second surface 200r of the wafer 200 in the wafer 200 to the defect structure 204 extend. According to various embodiments, the separation structure can 414 partially or completely the second area 202b of the wafer 200 laterally surrounded. According to various embodiments, the separating structure can 414 containing a trench structure, another defect structure and / or any other structure that divides the first area 202aand the second area 202b mutually supported. According to various embodiments, the separation structure can 414 another defect structure formed by a focused laser beam, as described here.

[0040] If the separation structure is the second area 202b If the area only partially surrounds the second area laterally, a connecting structure may remain, which defines the second area. 202b with the edge area 302 connects. Accordingly, separating the second area can 202b and the first area also includes breaking (e.g. splitting) of the connection structure.

[0041] According to various embodiments, the separation structure can 414 alternatively from the first surface 200s of the wafer 200 in the wafer 200 to the defect structure 204 extend. In this case, the separation structure can 414 the first area 202aof the wafer 200 partially or completely surrounded laterally.

[0042] Fig. Figure 4B shows a schematic cross-section of the first area. 202a and the second area 202b represent, which along the defect structure 204 and along the separation structure 414 are separated from each other. According to various embodiments, the edge area can be 302 with the first area 200s after the division of the first area 202a and the second area 202b They remain connected to each other. The size and shape of the distant second area can be visualized. 202b through the respective position of the defect structure 204 and the separation structure 414 It must be defined. Alternatively, only a portion of the edge area can be defined. 302 with the first area 200s after the division of the first area 202a and the second area 202bstay connected.

[0043] As described above, the procedure can 100 used to establish a first area 202a , which has a thickness that is smaller than the thickness 200t of the wafer 200 , to generate. Therefore, the process can 100 Thinning a wafer 200 up to a desired thickness, which is determined by the vertical extent of the first area 202a is defined, enabling. The first area can be illustrated as follows: 202a as a thinned wafer, as is conventionally processed in the semiconductor industry. The position and size of the defect structure 204 can be selected to be the first area 202a to provide a desired thickness, e.g., less than approximately 50 μm. If the first area 202a The edge area may be too thin for handling the wafer. 302used to determine the shape of the first area 202a to provide mechanical support. The edge area can be visualized as follows: 302 a ring support structure that forms the first area 202 surrounds and stabilizes in a similar way to a so-called TAIKO wafer.

[0044] Furthermore, a cutting tape can be used to cut the first area. 202a to support or to secure the first area 202a from the second area 202b to separate. The cutting belt can be applied to the first surface. 200s of the wafer 200 It must be laminated. After separating the first area. 202a and the second area 202b The first area can adhere to the cutting belt.

[0045] After the defect structure 204 in the wafer 200 Once formed, any suitable process can be used to develop the second area. 202b from the first area 202a to remove. The second area202b can from the first area 202a be removed in one piece.

[0046] The surface area of ​​the first area 202a (which may be a new processing area, created by the first area) 202a (provided as a thin or ultrathin support or wafer) can be essentially as large as the surface area of ​​the initial wafer. 200 , from which the first area 202a has been formed, e.g. the surface area of ​​the first area 202a larger than at least 80% of the wafer's surface area 200 be, or the surface area of ​​the first area 202a can be larger than at least 90% of the wafer's surface area 200 be, or the surface area of ​​the first area 202a can be larger than at least 95% of the wafer's surface area 200 be, or the surface area of ​​the first area 202acan be larger than at least 99% of the wafer's surface area 200 This can enable an efficient process for wafer thinning, or in other words, for creating a thin or ultrathin substrate. 202a to provide. The removal of the second area can be illustrated. 202b from the first area 202a as the thinness of the wafer 200 be understood. The diluted wafer 202a is through the first area 202a provided during production, i.e., until the first area is cut 202a into several chips, can remain in a single piece.

[0047] According to various embodiments, the first area can 202a and the second area 202bby using any suitable tool or processing method, e.g., a punch or plate covered by a wafer strip or adhesive tape, according to various embodiments. Commonly used cutting processes such as laser cutting, sawing, etching, and the like can also be employed after the defect structure has been defined. 204 is formed to cover the first area 202a and the second area 202b to separate them.

[0048] According to various embodiments, the first area can 202a multiple chip areas. Furthermore, the multiple chip areas can be separated into multiple chips after the first area 202a and the second area 202b have been separated from each other.

[0049] Fig. Figure 5 shows a schematic flowchart of a procedure. 500 to process a carrier 200(e.g., a carrier in wafer size and / or wafer shape) according to various embodiments, wherein the method 500 May contain the following: in 510 Formation of a defect structure 204 (also known as perforation structure or predetermined breaking structure) within the carrier 200 by scanning a focus area of ​​a laser beam within the carrier 200 , wherein the defect structure 204 a first area 202a of the carrier 200 , which is located on a first side of the defect structure 204 is located, and a second area 202b of the carrier 200 , which is located on a second side of the defect structure 204 opposite the first side, and an edge area 302 , which is the defect structure 204 surrounds laterally and is separated from a first surface 200s of the carrier 200 to a second surface 200r of the carrier 200opposite the first surface 200s extends, defined, whereby the defect structure 204 under more than 80% of the first surface 200s is formed and the second area 202b with the first area 202a through the edge area 302 is connected, and subsequently in 520 Separating the first area 202a and the second area 202b from each other by breaking the defect structure 204 , whereby at least the first area remains in one piece. Furthermore, the second area can also be 202b during the separation of the second area 202b and the first area 202a They remain intact. The edge area 302 can the first area 202a and the second area 202b also surrounded on the sides.

[0050] According to various embodiments, the focus area of ​​the laser beam can be located within the carrier. 200along a two-dimensional fracture plane (cf. Fig. 2A to Fig. 4B) or along a three-dimensional fracture pattern (see Fig. 8) Scan the edge area. 302 can the first area 202a mechanically support after the second area 202b from the first area 202a and the edge area 302 has been removed.

[0051] Fig. Figure 6 shows a schematic flowchart of a procedure. 600 to process a wafer 200 (e.g., a carrier in wafer size and / or wafer shape) according to various embodiments. The method 600 may contain the following: in 610 Formation of a defect structure 204 within the wafer 200 by scanning a focus area of ​​a laser beam within the wafer 200 , whereby the defect structure 204 laterally through the wafer 200 extends and a first area 202aof the wafer 200 , which is located above the defect structure 204 is located, and a second area 202b of the wafer 200 , which is located below the defect structure 204 is located, defined, and subsequently in 620 Separating the first area 202a and the second area 202b from each other by breaking the defect structure 204 , the first area 202a remains in one piece. Furthermore, the second area can also 202b during the separation of the first area 202a and the second area 202b They remain in one piece.

[0052] According to various embodiments, the focus area of ​​the laser beam can be located within the carrier. 200 along a two-dimensional fracture plane (cf. Fig. 2A to Fig. 4B) or along a three-dimensional fracture pattern (see Fig. 8) Scan. According to various embodiments, a laser can be controlled to define the focus area of ​​the laser beam within the carrier. 200 to scan along a predefined plane or pattern. A feedback loop can be used to control whether the generated defect structure is correct. 204 is aligned with the predefined plane or pattern. Any deviations that may occur can be compensated for by adjusting the position of the laser beam's focus area accordingly. According to various embodiments, the defect structure can be 204 under more than 80% of a machining surface 200s of the wafer 200 be formed (cf. Fig. 3A to Fig. 4B). The defect structure 204 can also be formed in such a way that it extends completely laterally through the wafer (cf. Fig. 2A to Fig. 2C).

[0053] According to various embodiments, a focused laser beam can be used to thin a wafer. 200 (or any other suitable carrier) by forming a defect structure 204 (also known as perforation structure) within the wafer 200 can be used. The defect structure 204 can be used to establish a first area 202a (e.g., a thin surface area) of the wafer 200 from the rest (e.g., from a main area) of the wafer 200 to separate. The generation of the focused laser beam and the control of a laser to generate and direct the focused laser beam are described in more detail below.

[0054] In general, wafer thinning can be a very challenging discipline within a chip manufacturing process. In this application area, the increasing demand for silicon wafers with a thickness below, for example, 20 μm and high performance (e.g., with a total thickness variation, TTV, of less than about 1 μm) can push conventional thinning methods, such as grinding, to their physical limits.

[0055] To date, significant effort has been invested in the further development of mechanical thinning processes. Gains in performance of just a few percent are typically accompanied by a substantial increase in costs and complexity. In any case, high-performance wafer thinning can involve mounting support systems such as a ribbon, glass support, or silicon wafer onto the production wafer, followed by grinding, defect removal, and delamination procedures. Therefore, conventionally used wafer thinning processes can involve expensive support / bond systems and / or high operating costs (e.g., due to ribbons, glass, disks, chemicals, etc.). Furthermore, conventionally used wafer thinning processes can pose a high risk of wafer rejects due to mechanical processing and / or the handling of thin wafers.Furthermore, conventionally used wafer thinning processes can exhibit increased front- and back-side defect density, poor final thickness, and / or poor overall thickness variation performance. Conventionally used high-performance TTV procedures can be even more complex and expensive, including, for example, ribbon leveling, mounting glass, ribbon-on-glass, ribbon flattening, silicon grinding, and ribbon removal.

[0056] According to various embodiments, the wafer thinning method described here can involve forming a defect structure in a commercially available thick wafer (e.g., with a thickness of about 700 μm or greater) to separate the wafer into a thin surface region (e.g., with a thickness of less than about 50 μm or less than about 20 μm) and a main region. The thin surface region can be used to fabricate one or more electronic devices using semiconductor technology.

[0057] Fig. 7A presents a process flow in a schematic view, which relates to the processing of a wafer. 200 or carrier, as described here. According to various embodiments, a bare wafer can be 200 at an initial processing stage 710 be provided. Alternatively, the wafer can be 200one or more electronic circuit structures in this initial processing stage 710 included. In the case of the wafer 200 contains one or more electronic circuit structures located on the first surface 200s of the wafer, and one or more electronic circuit structures can influence the laser beam used to create the defect structure. 204 When used, the laser beam can be designed so that it is directed from the back. 200r in the wafer 200 penetrates, e.g. through the second surface 200r of the wafer 200 .

[0058] As in Fig. As shown in 7A, a defect structure can be 204 in the wafer 200 in the processing stage 720 (also referred to as perforation or perforation process) are formed, as described here, e.g. with reference to Fig. 2A, Fig. 3A and / or Fig. 8.

[0059] Furthermore, the final thickness of the first area can be 202a in the processing stage 730 This can be confirmed according to various embodiments. The final thickness of the first area 202a can be considered the final thickness of the diluted wafer that passes through the first area 202a It is provided, to be understood.

[0060] Furthermore, one or more chip manufacturing processes can be included in the processing stage. 740 They can be implemented according to various embodiments. For example, one or more integrated circuit structures, sensor structures, light-emitting devices, etc., can be located in the first area. 202a can be formed. According to various embodiments, any desired structure can be formed in the first area. 202a of the wafer 200 to be processed, e.g. before the first area 202a and the second area 202bThey are separated from each other. In this processing stage 740 can the wafer 200 already prepared for thinning, i.e., the wafer 200 The defect structure contains 204 , but the first area 202a and the second area 202b can still be connected to each other. Therefore, the wafer 200 still easy to handle.

[0061] According to various embodiments, the second area can 202b in the processing stage 750 be removed. In this case, the first area will be removed. 202a from the second area 202b separately 302 (e.g., an edge region) 302 ) stay in the first area, which is the first area 202a mechanically supported, as described above, see for example Fig. 4B.

[0062] According to various embodiments, one or more backside manufacturing processes can be performed on the exposed backside surface of the first area. 202a in one processing stage 750 to be carried out after the second area 202b has been removed. Backside manufacturing processes may include polishing and / or etching and / or layering (e.g., forming a metallization layer) and the like.

[0063] According to various embodiments, several integrated circuit structures can be placed in the first area. 202 be formed before the first area 202a and the second area 202b They can be separated from each other. The wafer can be used to manufacture the multiple integrated circuit structures. 200 be made of silicon or any other suitable semiconductor material. To avoid recrystallization processes after the defect structure has been created. 204Once formed, the multiple integrated circuit structures can only be created via low-temperature processing, e.g., at temperatures lower than the recrystallization temperature of silicon (or the respective semiconductor material of the wafer). In other words, high-temperature processes above the respective recrystallization temperature of the wafer material are necessary between processing stages. 720 and 750 , i.e., after the formation of the defect structure 204 and before the first area was divided 202a and the second area 202b from each other, should be avoided. Since recrystallization effects defects of the defect structure 204 can temper in such a way that the first area 202a and the second area 202b of the wafer 200 They can no longer be separated. The defect structure can be clearly illustrated. 204This can be removed via high-temperature annealing due to recrystallization effects. However, this can be avoided after separating the first region. 202a and the second area 202b of the wafer 200 used from each other, cf. Fig. 2C, Fig. 3C or Fig. 4B.

[0064] Fig. 7B presents a schematic view of a process flow relating to the perforation process, as described here (see, for example, processing stage). 720 in Fig. 7A). According to various embodiments, a tightly focused laser beam can be generated. 720a A focus area of ​​the focused laser beam can be provided with a high power density and be small enough to target the defect structure. 204 in the wafer 200to form with the desired accuracy. The focused laser beam can be provided by operating a suitably configured laser (e.g., a laser system or laser array). The focused laser beam can be generated with a high power density, a small Rayleigh length (e.g., less than about 1 μm), and a well-defined beam waist (e.g., less than about 1 μm), cf. Fig. 7C and Fig. 7D. The beam waist is measured perpendicular to the optical axis (e.g., perpendicular to the direction of propagation of the laser beam). The highest power densities of the laser beam are present at the position where the focused laser beam has the smallest waist, i.e., in the focus region.

[0065] To create the defect structure 204 within the wafer 200The position of the smallest waist (also called the focus area) can be measured and adjusted accordingly. According to various embodiments, a laser can be used to generate the focused laser beam. The laser can include optical elements (e.g., at least one lens or at least one mirror) to provide a focus area of ​​the focused laser beam at a desired z-position along a z-direction (and optionally also at a desired position within the xy-plane). Furthermore, a wafer stage can be used to prepare the wafer. 200 to position the wafer relative to the focus area of ​​the focused laser beam and to move the wafer within the xy-plane (and optionally also in the z-direction) perpendicular to the z-direction. The wafer arrangement 200 The position of the focus area of ​​the focused laser beam can be controlled in such a way that the focused laser beam remains within the wafer.200 is provided to analyze the defect structure 204 between the first and second surface 200s , 200r of the wafer 200 to form.

[0066] The focused laser beam is provided in such a way that energies are directed onto the wafer. 200 Damage can be transferred above the damage threshold of the respective wafer material (e.g., silicon). This can result in a localized shell of damaged crystal within the wafer. 200 cause. The locally damaged wafer material can provide the defect structure. The locally damaged wafer material (e.g., the defect structure) 204 ) may have a different refractive index than the refractive index of the undamaged wafer material.

[0067] The wafer arrangement 200The position of the focus area of ​​the focused laser beam can be controlled in such a way that the focused laser beam remains within the wafer. 200 is moved to remove the defect structure 204 to provide the laser beam within the wafer in accordance with a predefined pattern. To illustrate, the focused laser beam can... 200 Scanning. The focused laser beam is positioned so that the focus area is located within the wafer and scans within the wafer. According to various embodiments, the laser can scan in any geometric pattern that corresponds to the desired shape and size of the defect structure. 204 caused. As an example, the laser can scan in such a way as to detect a defect structure. 204 with a flat shape or with a three-dimensional pattern that extends laterally within the wafer 200 extends to form. Also the position of the defect structure. 204relative to the surfaces 202s , 202r of the wafer 200 can be controlled.

[0068] During wafer scanning 200 The focused laser beam can be used to determine the thickness and / or position of the defect structure. 204 within the wafer 200 The laser beam can be measured, and the focused laser beam can be adjusted if necessary.

[0069] According to various embodiments, a pulsed and tightly focused laser beam can be used to define the defect structure. 204 to generate, as described here. Therefore, a high energy dose can be delivered to a localized area of ​​the wafer. 200Surface effects can occur (in other words, be introduced), leading to effects in the main part of the crystal (e.g., localized shells with crystal damage). However, surface effects can be avoided, as they can cause delamination, melting, splitting, evaporation, and other undesirable effects. In transparent media, linear absorption of light is suppressed compared to nonlinear effects such as photoionization (multiphoton ionization, tunnel ionization) or avalanche ionization. These nonlinear effects excite electrons from the valence band to the conduction band, which absorbs photons that gain energy and scatter at the lattice, resulting in impact ionization.

[0070] While thermal diffusion must be considered for long laser pulse durations (tau), short pulses (e.g., less than 1 ns (ns, nanosecond)) lead to a permanent restructuring of the main material with low thermal diffusion. According to various embodiments, thermal effects or local heating of the wafer can be mitigated. 200 not to the formation of the defect structure 204 as described here. The key to creating a perforation plane or perforation pattern within the main material of the wafer. 200 It is short pulses (e.g., shorter than about 1 ns), high power densities above the damage threshold of the main material (e.g., for silicon greater than 1 E10 W / cm²). 2 e.g. in the range of approximately 1 E10 W / cm² 2 up to approximately 1 E15 W / cm² 2 e.g. in the range of approximately 1 μL 1 W / cm² 2 up to approximately 1 E14 W / cm² 2 e.g. in the range of approximately 1 E13 W / cm² 2up to about 5 E13 W / cm 2 ), a short Rayleigh length (e.g., less than about 10 μm, less than about 5 μm, less than about 1 μm) and a small minimum waist (e.g., less than about 10 μm, less than about 5 μm, less than about 1 μm) for precise localization and generation of the defect structure. 204 to use.

[0071] For example, in Fig. As shown in Figure 7C, a beam path for a focused laser beam can be described using the Gaussian beam model. The waist (also called the Gaussian beam width), w, of a focused laser beam varies along the direction of propagation. 705of the focused laser beam (e.g., along the z-axis in a Cartesian coordinate system). A focus region of the focused laser beam can be defined by a minimum waist, w0, and therefore also by a minimum cross-sectional area of ​​the focused laser beam. The Rayleigh length (also called Rayleigh region), z R , can be achieved by two positions (see w0, w2 in Fig. 7C) along the z-axis; the first position, w0, is defined by the smallest cross-sectional area of ​​the focused laser beam (measured perpendicular to the z-direction, i.e., at a smallest waist), and at the second position, the cross-sectional area of ​​the laser beam is twice the cross-sectional area of ​​the smallest beam waist. The Rayleigh length can also be a depth of focus, d f , define (cf. Fig. 7C). Furthermore, the focused laser beam can exhibit total angular scattering, Θ, and a predefined beam quality parameter, M.

[0072] The Rayleigh length of a laser beam that stays within a wafer 200 The focus can be estimated as follows: where lambda is the wavelength of the focused laser beam, f is the focal distance of the lens or lens system used to focus the laser beam, D is the diameter of the laser beam at the lens or lens system, and where n is the refractive index of the wafer material (i.e., about 3.6 for silicon).

[0073] Because of surface effects during the creation of the defect structure 204 To avoid these issues, a wavelength for the focused laser beam can be selected in a region where the wafer material is essentially transparent to the laser beam. 200For example, if silicon is present, the wavelength must be in the infrared range, e.g. greater than about 800 nm, e.g. in the range of about 800 nm to about 1500 nm, e.g. in the range of about 1000 nm to about 1100 nm.

[0074] Fig. 7D establishes a laser intensity profile around the focus area. 720f a focused laser beam. The laser intensity (also called power density) in the focus area 720f The laser intensity may be above the damage threshold for the respective wafer material. Laser intensity outside the focus area 720f It may be below the damage threshold. Therefore, the wafer material can only be damaged in the focal area. 720f be damaged. According to various embodiments, a focused laser beam can damage the wafer. 200 scan so that the focus area 720f the defect structure 204 in the wafer 200 generated as described here.

[0075] According to various embodiments, the extent of the focus area can be 720f be below one micrometer. Furthermore, the extent of the focal area can 720f still above the diffraction limit. The desired extent of the focal area 720f This could refer to a small Rayleigh length and a small, minimal waist.

[0076] Because of surface effects during the creation of the defect structure 204 To avoid these issues, the laser can be operated in a pulsed mode, which generates a pulsed focused laser beam.

[0077] According to various embodiments, the focused laser beam can be pulsed with a pulse frequency greater than approximately 1 kHz, e.g., in the range of approximately 1 kHz to approximately 20 kHz. Furthermore, the focused laser beam can be pulsed with a pulse duration of less than 1 ns, e.g., less than approximately 100 ps, ​​e.g., in the range of approximately 1 ps to approximately 1 ns.

[0078] As an example, the laser can provide a continuous beam power of approximately 10 W and can also be operated in pulsed mode. The generated pulsed focused laser beam can have a pulse frequency of approximately 10 kHz and a pulse duration of approximately 20 ps. The pulsed focused laser beam can be generated with a wavelength of approximately 1064 nm. For example, using these operating parameters, surface effects can be avoided and defects in the main part can be created to define the defect structure. 204 to form.

[0079] Fig. 7E and Fig. Figures 7F each show a schematic view of the generation of the defect structure. 204 within the wafer 200 through a focused laser beam 740 The focused laser beam can be within a plane. 740p (also referred to as perforation plane or defect plane) scan. An infrared inline thickness measurement. 730 can be used to determine the position and / or extent of the defect structure 204 to check during the scanning process. Based on this measurement, the final thickness of the first area can be determined. 202 be determined (e.g., confirmed). A lens 750 or a lens arrangement 750 (which contains, for example, several lenses) can be used to focus the laser beam 740 to focus. By moving 750m the lens 750 or lens arrangement 750 along the z-axis (e.g. perpendicular to the first surface) 200s of the wafer200 ) can determine the z-position of the focus area 720f can be changed. Therefore, the position and / or shape of the defect structure can be altered. 204 in the wafer 200 to be controlled. To move the lens. 750 or lens arrangement 750 A fast actuator can be used, e.g. a piezo actuator.

[0080] According to various embodiments, an infrared laser can be used for infrared inline thickness measurement. 730 Infrared inline thickness measurement can be used based on a change in the refractive index, n, of the wafer material after it passes through the focused laser beam. 740 has been damaged, based on the infrared inline thickness measurement. 730 and the focused laser beam 740 can be provided in a confocal setup.

[0081] According to various embodiments, the formation of the defect structure can 204 by scanning the wafer 200The focused laser beam must include at least one of the following process requirements: a high-power laser configured to generate short laser pulses, an in-situ measurement system (e.g., an IR interferometer, e.g., in a confocal setup), a feedback loop for aligning the laser light spot (focus area), and a fast actuator for aligning the laser light spot (e.g., a high-speed ultrasonic piezo actuator).

[0082] The dimensions of the defect structure 204 can be defined by the laser geometry. Inline (IR) measurement of wafer placement and the position and / or extent of the defect structure. 204 These measurements can be performed in a confocal setup. However, the focused laser beam can travel in front of the measurement spot of the (IR) measuring laser.

[0083] According to various embodiments, the measurement results provided by (IR) measurement can be used to control the actuation variable. 750m for the positioning lens 750 provide the laser light spot. The wafer 200 can be moved below the laser and the (IR) measurement setup.

[0084] Fig. Figure 7G shows a schematic view of how to create the separation structure. 414 within the wafer 200 through a focused laser beam 740 , cf. for example Fig. 4A and Fig. 4B. The focused laser beam can travel along the edge region 302 , which is the second area 202b surrounds laterally, can be moved (e.g. in a circular motion), and the separating structure 414 can be achieved by changing the z-position of the focus area 720f be formed. The separation structure 414 can deviate from the defect structure 204 to the second surface 200r(e.g. the back) of the wafer 200 extend as described here.

[0085] According to various embodiments, a rear cover can be open, and the cover (e.g., the separate second area) 202b ) can be lifted for back-side processing. The edge area 302 can optionally be used to create a support ring for the thin first area 202a similar to Taiko processing. Therefore, greater handling stability can be achieved if necessary. Alternatively, the first area can be 202a via a cutting belt that is attached to the first area 202a It is attached, it will be processed.

[0086] Fig. 8A places the wafer 200 in a cross-sectional view, e.g. after the process 110 of procedures 100 The defect structure has been implemented according to various embodiments. 204It can exhibit a three-dimensional pattern. The defect structure 204 However, it can migrate laterally within the wafer. 200 extend, as exemplified above for a planar (i.e., two-dimensional) defect structure 204 is described.

[0087] According to various embodiments, the focused laser beam can be directed in a first plane 800a , which establish an initial distance 805a from the first surface 200s of the wafer 200 exhibits, scan. The first level 800a can parallel to the first surface 200s of the wafer 200 be aligned. Furthermore, the focused laser beam can be aligned in a second plane. 800b , which have a second distance 805b from the first surface 200s exhibits, scan. The second level 800b can parallel to the first surface 200s be aligned. The second distance 805bcan be larger than the first distance 805a .

[0088] According to various embodiments, the first level 800a several chip areas 202c in the first area 202a define. Furthermore, the second level can 800b several joint areas 202k and / or chip edge regions 802e in the first area 202 Define the joint areas. 202k surround the chip areas 202c Each sideways. After separating the multiple chip areas. 202c into individual chips 802 along the cut joint areas 202k can any chip 802 a chip edge region 802e containing the respective chip 802 surrounds laterally, as in Fig. 8B schematically depicted. The chip edge region. 802e can be accessed from the back of the chip 802r , which is achieved by removing the second area 202b from the first area 202ais exposed, protrudes.

[0089] According to various embodiments, any desired defect structure can be achieved in a similar way. 204 in which wafers are formed to create the first area 202a and the second area 202b to separate them.

[0090] As described here, a procedure can 100 , 500 , 600 It must be provided that allows for the separation of two wafer areas. 202a , 202b enabled, so that one of the wafer areas 202a , 202bThe process achieves a desired final thickness, enabling its use as a substrate for semiconductor processing similar to a thin or ultrathin wafer. The method described here allows for precise control of the final thickness and total thickness variation (TTV). The final thickness can be pre-validated on the bare wafer. A ring support system can be easily integrated into the processing. The process can lead to reduced operating costs, as no support system (e.g., strips, glasses, bonds, etc.) may be required. Furthermore, no support system reprocessing procedures may be necessary. The method described here can be used as an alternative to conventional grinding processes, for example, to avoid wheel consumption.Furthermore, the method described here can exhibit a low risk of wafer rejects due to the handling of thin wafers and a low risk of wafer rejects due to defect density induced by standard procedures. Additionally, the throughput factor can be reduced, as many process steps can be eliminated compared to conventional high-quality mechanical wafer thinning. Furthermore, the method described here can provide high flexibility. Additionally, the perforated chip grid may lead to reduced edge chipping. Furthermore, profiling of the backside substrate may be possible.

[0091] Before manufacturing semiconductor structures, a perforated film can be applied to the wafer. Using a laser beam, the surface (opposite the semiconductor structures) is irradiated precisely to the required depth, such that both the silicon beneath the perforated film and the perforated film itself can be removed.

[0092] Example 1 is a method for processing a wafer, wherein the method comprises: scanning the wafer with a focused laser beam to form a defect structure within the wafer, the defect structure defining a first region of the wafer located on a first side of the defect structure, a second region of the wafer located on a second side of the defect structure opposite the first side, and an edge region laterally surrounding the defect structure and extending from a first surface of the wafer to a second surface of the wafer opposite the first side, wherein a surface region of the first region is larger than a surface region of the edge region, and wherein the second region is connected to the first region by the edge region, and subsequently separating the first region and the second region from each other along the defect structure, the first region remaining in one piece.

[0093] In Example 2, the procedure of Example 1 may optionally include separating the first area and the second area from each other and further lifting the second area in one piece from the first area.

[0094] In Example 3, the procedure from Example 1 or 2 may optionally include that the first surface is a main processing surface of the wafer.

[0095] In Example 4, the procedure of one of Examples 1 to 3 may optionally include that the defect structure is formed under more than 80% of the first surface of the wafer.

[0096] In Example 5, the method of one of Examples 1 to 4 can optionally include the scanning of the wafer with the focused laser beam further comprising controlling a focus position of the focused laser beam relative to the first surface of the wafer. The focus position can be the position along the propagation direction of the focused laser beam where the focused laser beam exhibits the minimum waist. The focus position can define the focus region.

[0097] In Example 6, the procedure from Example 5 can optionally include scanning the wafer with the focused laser beam and further controlling the orientation of the wafer relative to the focus position.

[0098] In Example 7, the procedure from Example 6 can optionally include controlling the focus position of the focused laser beam and controlling the orientation of the wafer relative to the focus position. Measuring includes at least one of the following properties: a position of the defect structure; an extent of the defect structure; a placement of the wafer.

[0099] In Example 8, the procedure from Example 7 can optionally include the scanning of the wafer with the focused laser beam being controlled via a feedback loop based on at least one of the measured properties. The feedback loop can be configured to check whether a pattern of the generated defect structure is aligned with a predefined pattern.

[0100] In Example 9, the method of Example 7 or 8 may optionally include measuring at least one of the position of the defect structure and the extent of the defect structure using an infrared measurement setup.

[0101] In Example 10, the procedure from Example 9 can optionally include the infrared measurement setup and the focused laser beam being provided in a confocal setup.

[0102] In Example 11, the method of one of Examples 1 to 10 may optionally include the focused laser beam scanning in a single plane aligned parallel to the first surface of the wafer to form a planar defect structure.

[0103] In Example 12, the method of one of Examples 1 to 11 may optionally include the focused laser beam scanning in a first plane having a first distance from the first surface and aligned parallel to the first surface, and in a second plane having a second distance from the first surface and aligned parallel to the first surface, the second distance being greater than the first distance.

[0104] In Example 13, the procedure from Example 12 can optionally include the first level defining chip regions of the first region and the second level defining interface regions and chip edge regions that laterally surround the chip regions.

[0105] In Example 14, the procedure of one of Examples 1 to 13 may optionally include that the thickness of the first region is smaller than the thickness of the second region.

[0106] In Example 15, the method of one of Examples 1 to 14 may optionally include that the thickness of the first region is less than about 50 μm.

[0107] In Example 16, the method of one of Examples 1 to 15 may optionally include the scanning of the wafer with the focused laser beam involving the operation of a laser in a pulsed mode, which defines a pulse frequency, a pulse duration and a power density.

[0108] In Example 17, the procedure of Example 16 may optionally include that the wafer contains a material that has a power density damage threshold, and that the pulse energy is selected to provide the focused laser beam with a power density greater than the power density damage threshold.

[0109] In Example 18, the method from Example 17 can optionally include that the material is silicon. Example 18 can further include that the power density is greater than approximately 1 × 10⁻⁶. 10 W / cm 2 .

[0110] In Example 19, the procedure of one of Examples 16 to 18 may optionally include that the pulse duration is less than about 1 ns.

[0111] In Example 20, the procedure of one of Examples 16 to 19 may optionally include that the pulse frequency is greater than approximately 1 kHz.

[0112] In Example 21, the method of one of Examples 1 to 20 may optionally include that the focused laser beam has an infrared wavelength.

[0113] In Example 22, the method of one of Examples 1 to 21 may optionally include that the focused laser beam has a Rayleigh length of less than about 10 μm.

[0114] In Example 23, the method of one of Examples 1 to 22 may optionally further include the following: prior to separating the first region and the second region from each other, forming a separation structure extending from the second surface of the wafer into the wafer to the defect structure, the separation structure completely surrounding the second region laterally.

[0115] In Example 24, the procedure of one of Examples 1 to 23 may optionally include separating the first region and the second region from each other by: forming a separation structure extending from the second surface of the wafer into the wafer to the defect structure, the separation structure partially surrounding the second region laterally, with a connecting structure linking the second region to the edge region, and subsequently removing the second region from the first region and the edge region, thereby splitting the connecting structure.

[0116] In Example 25, the procedure from Example 23 or 24 may optionally include the separation structure containing a trench structure and / or another defect structure.

[0117] In Example 26, the procedure of one of Examples 1 to 25 may optionally include separating the first region and the second region from each other and subjecting the wafer to a mechanical load in order to break the defect structure.

[0118] In Example 27, the method of one of Examples 1 to 26 may optionally include that the wafer contains single-crystal silicon.

[0119] In Example 28, the procedure from Example 27 can optionally include the defect structure containing disordered silicon. Disordered silicon can, for example, contain polycrystalline silicon and / or amorphous silicon.

[0120] In Example 29, the procedure of one of Examples 1 to 28 may optionally further include the following: before separating the first region and the second region from each other and after forming the defect structure within the wafer, forming several integrated circuit structures in the first region of the wafer.

[0121] In Example 30, the procedure of Example 29 may optionally include that the wafer is not subjected to high-temperature treatment after the formation of the defect structure within the wafer and before the separation of the first region and the second region from each other.

[0122] In Example 31, the process of one of Examples 1 to 30 may optionally further include the following: after separating the first area and the second area from each other, forming a backside metallization on an exposed backside surface of the first area.

[0123] Example 32 is a method for processing a substrate, wherein the method comprises: forming a defect structure within the substrate by scanning a focus region of a laser beam within the substrate, wherein the defect structure defines a first region of the substrate located at a first side of the defect structure, and a second region of the substrate located at a second side of the defect structure opposite the first side, and an edge region laterally surrounding the defect structure and extending from a first surface of the substrate to a second surface of the substrate opposite the first surface, wherein the defect structure is formed under more than 80% of the first surface and wherein the second region is connected to the first region by the edge region, and subsequently separating the first region and the second region from each other by breaking the defect structure.where at least the first area remains intact.

[0124] In Example 33, the procedure from Example 32 can optionally include the edge region mechanically supporting the first region after the second region has moved away from the first region.

[0125] In Example 34, the procedure from Example 32 or 33 may optionally include that the support is a wafer.

[0126] In Example 35, the procedure of one of Examples 32 to 34 may optionally include that the first area contains multiple chip areas.

[0127] In Example 36, the procedure of Example 35 may optionally further include: separating the multiple chip areas into multiple chips after separating the first area and the second area from each other.

[0128] Example 37 is a method for processing a wafer, wherein the method comprises: forming a defect structure within the wafer by scanning a focus region of a laser beam within the wafer, wherein the defect structure extends laterally through the wafer and defines a first region of the wafer located above the defect structure and a second region of the wafer located below the defect structure, and subsequently separating the first region and the second region from each other by breaking the defect structure, wherein the first region remains in one piece.

[0129] In Example 38, the procedure of Example 37 may optionally further include: forming multiple integrated circuit structures into the first region before separating the first region and the second region from each other.

[0130] In Example 39, the procedure of Example 38 may optionally include that the wafer is made of silicon and that forming the multiple integrated circuit structures includes only one or more low-temperature treatments at temperatures lower than the recrystallization temperature of silicon.

[0131] In Example 40, the procedure of one of Examples 37 to 39 may optionally include that the defect structure is formed under more than 80% of the processing surface of the wafer.

[0132] In Example 41, the procedure can optionally include one of Examples 37 to 40, such that the defect structure extends laterally completely through the wafer.

[0133] Although the invention has been shown and described in particular with reference to specific embodiments, it is understood by those skilled in the art that various changes to its form and details can be made without departing from the spirit and scope of the invention as defined by the accompanying claims. The scope of the invention is thus specified by the accompanying claims, and all modifications that fall within the meaning and equivalence of the claims are therefore intended to be included.

Claims

[1] Method for processing a wafer, the method comprising: Scanning the wafer with a focused laser beam to form a defect structure within the wafer, wherein the defect structure defines a first region of the wafer located on a first side of the defect structure, and a second region of the wafer located on a second side of the defect structure opposite the first side, and an edge region that laterally surrounds the defect structure and extends from a first surface of the wafer to a second surface of the wafer opposite the first side, wherein a surface area of ​​the first region is larger than a surface area of ​​the edge region, and wherein the second region is connected to the first region by the edge region, and subsequently Separating the first area and the second area from each other along the defect structure, with the first area remaining in one piece. [2] Method according to claim 1, wherein separating the first region and the second region from each other further comprises lifting the second region off the first region in one piece. [3] Method according to one of claims 1 to 2, wherein the defect structure is formed under more than 80% of the first surface of the wafer. [4] Method according to any one of claims 1 to 3, wherein scanning the wafer with the focused laser beam further comprises controlling a focus position of the focused laser beam and controlling an orientation of the wafer relative to the focus position. [5] Method according to claim 4, wherein the scanning of the wafer with the focused laser beam is controlled via a feedback loop configured to check whether a pattern of the generated defect structure is aligned with a predefined pattern. [6] Method according to claim 4 or 5, wherein the scanning of the wafer with the focused laser beam is controlled via an infrared measuring arrangement. [7] Method according to any one of claims 1 to 6, wherein the focused laser beam scans in a single plane aligned parallel to the first surface of the wafer to form a planar defect structure. [8] Method according to any one of claims 1 to 6, wherein the focused laser beam scans in a first plane which has a first distance from the first surface and is aligned parallel to the first surface, and in a second plane which has a second distance from the first surface and is aligned parallel to the first surface, wherein the second distance is greater than the first distance. [9] Method according to claim 8, wherein the first level defines chip regions in the first region and wherein the second level defines cut-off regions and chip edge regions that laterally surround the chip regions. [10] Method according to any one of claims 1 to 9, wherein the thickness of the first region is less than about 50 μm. [11] Method according to any one of claims 1 to 10, wherein scanning the wafer with the focused laser beam comprises operating a laser in a pulsed mode which defines a pulse frequency, a pulse duration and a power density. [12] Method according to claim 11, wherein the wafer comprises a material having a power density damage threshold, and wherein the pulse energy is selected to provide the focused laser beam with a power density greater than the power density damage threshold. [13] Method according to claim 12, wherein the material is silicon and wherein the power density is greater than about 1·10 10 W / cm 2 . [14] Method according to any one of claims 11 to 13, wherein the pulse duration is less than about 1 ns. [15] Method according to any one of claims 11 to 14, wherein the pulse frequency is greater than about 1 kHz. [16] Method according to any one of claims 1 to 15, further comprising: before separating the first region and the second region from each other, forming a separation structure extending from the second surface of the wafer into the wafer to the defect structure, wherein the separation structure laterally surrounds the second region. [17] Method according to claim 16, wherein the separation structure comprises a further defect structure. [18] Method according to any one of claims 1 to 17, wherein separating the first region and the second region from each other comprises subjecting the wafer to a mechanical load in order to break the defect structure. [19] Method for processing a carrier, the method comprising: Forming a defect structure within the support by scanning a focus region of a laser beam within the support, wherein the defect structure defines a first region of the support located at a first side of the defect structure, and a second region of the support located at a second side of the defect structure opposite the first side, and an edge region that laterally surrounds the defect structure and extends from a first surface of the support to a second surface of the support opposite the first surface, wherein the defect structure is formed under more than 80% of the first surface, and wherein the second region is connected to the first region by the edge region, and subsequently Separating the first area and the second area from each other by breaking the defect structure, whereby at least the first area remains in one piece. [20] Method for processing a carrier, the method comprising: Forming a defect structure within the support by scanning a focus area of ​​a laser beam within the support, wherein the defect structure extends laterally through the support, and defining a first region of the support located above the defect structure and a second region of the support located below the defect structure, and subsequently Separating the first area and the second area from each other by breaking the defect structure.

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