Method for manufacturing a static direct access storage device

Abstract

Method for manufacturing an SRAM device comprising multiple SRAM cells (SR1-SR4), the method comprising: forming an insulating layer (250) over a substrate (10); Forming first dummy structures (325) over the insulating layer (250); Forming sidewall spacer layers (330) as second dummy structures (330) on sidewalls of the first dummy structures (325); Removing the first dummy structures (325), leaving the second dummy structures (330) above the insulating layer (250); after removing the first dummy structures (325), dividing each of the second dummy structures (330) into several pieces (335) of the second dummy structures (330); Forming a mask layer (350) over the insulating layer (250) and between the several pieces (335) of the second dummy structures (330); after forming the mask layer (350), removing the several pieces (335) of the second dummy structures (330), thereby forming a hard mask layer (350) which has openings (360) corresponding to the several pieces (335) of the second dummy structures (330); Structuring the insulating layer (250) using the hard mask layer (350) as an etching mask, thereby forming via openings (375) in the insulating layer (250); and Filling the via openings (375) with a conductive material, thereby forming contact rails (380).

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor device and, more particularly, to a method of manufacturing a SRAM (Static Random Access Memory) device having fin field effect transistor (FinFET) devices. GENERAL STATE OF THE ART

[0002] As the semiconductor industry advances into nanometer-scale process nodes to achieve higher device density, higher performance, lower power consumption, and lower costs, challenges from both manufacturing and design issues have led to the development of three-dimensional designs such as a fin field-effect transistor (FinFET). In a FinFET device, it is possible to utilize additional sidewalls and suppress a short-channel effect. WO 2008 / 108921 A1 describes methods for fabricating semiconductor structures, in particular for forming polymer spacers along sacrificial material and using the polymer spacers as masks during the fabrication of integrated circuits.These processes enable the simultaneous formation of high-density and low-density structures with a single photomask by exploiting differences in the thickness of the polymer over large and small sacrificial structures. US 7 390 750 B1 describes a method for patterning elements within a semiconductor topography, in which a hard mask is formed adjacent to a patterned sacrificial layer, the patterned sacrificial layer is selectively removed, and the exposed regions of the lower layer are etched in alignment with the hard mask. The method enables the fabrication of semiconductor structures with very small dimensions, smaller than those achievable using conventional photolithography techniques. US 9 041 115 B2 describes a FinFET structure that enables improved control over the channel area and a reduction in leakage current.The FinFETs have a rectangular shape from a cross-sectional view and are designed so that the gate encloses the active region on three sides, which increases gate control over the channel area and improves the performance and reliability of the memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The invention is defined in the independent claims. The dependent claims relate to various embodiments. The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that various features are not drawn to scale, in accordance with standard industry practice, and are used for illustrative purposes only. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. Figure 1 is an example circuit diagram of an SRAM unit cell. Fig. 2 is an exemplary configuration of an SRAM unit cell according to an embodiment of the present disclosure. Fig. 3 is an exemplary arrangement of several SRAM unit cells. Fig. 4 is an exemplary arrangement of a plurality of SRAM unit cells according to an embodiment of the present disclosure. Fig. Figure 5A shows an exemplary perspective view of a fin field effect transistor. Fig. 5B shows an exemplary sectional view along the line X1-X1 in Fig. 2. Fig. Figure 5C is an example cross-sectional view illustrating vertical layers. Fig. 6 and Fig. 7 are exemplary configurations of an SRAM unit cell according to another embodiment of the present disclosure. Fig. 8A to 12C illustrate exemplary sequential processes for fabricating fin assemblies for an SRAM device according to an embodiment of the present disclosure. Fig. 13 to 17B illustrate exemplary sequential processes for fabricating gate structures for an SRAM device according to an embodiment of the present disclosure. Fig. 18 to 28B illustrate exemplary sequential processes for fabricating contact bar assemblies for an SRAM device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0004] It should be understood that the following disclosure provides many different embodiments or examples for carrying out various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired device proportions.Furthermore, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. For simplicity and clarity, various features may be drawn at different scales.

[0005] Furthermore, spatially-related terms such as "beneath," "beneath," "underneath," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially-related terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially-related descriptive terms used herein may also be interpreted accordingly. Furthermore, the term "consisting of" can mean either "comprising" or "consisting of."

[0006] Furthermore, the design structures shown in the present disclosure are conceptual designs and do not necessarily depict exact physical structures fabricated as a semiconductor device.

[0007] Fig. 1 is an exemplary circuit diagram of an SRAM unit cell. An SRAM unit cell includes two cross-coupled inverters with a data storage node and a complementary data storage node. The output of the first inverter is coupled to the input of the second inverter, and the output of the second inverter is coupled to the input of the first inverter. The SRAM further includes a first pass-gate FET device PG1 coupled to the output of the first inverter and the input of the second inverter, and a second pass-gate FET device PG2 coupled to the output of the second inverter and the input of the first inverter.The gates of the first and second pass-gate FET devices are coupled to a word line WL, a source / drain of the first pass-gate FET device PG1 is coupled to a first bit line BL, and a source / drain of the second pass-gate FET device PG2 is coupled to a second bit line BLB, which is the complement of the first bit line BL. In the present disclosure, a source and drain of an FET device can be used interchangeably.

[0008] The first inverter includes a first FET device of a first conductive type PU1 and a first FET device of a second conductive type PD1. The second inverter includes a second FET device of a first conductive type PU2 and a second FET device of a second conductive type PD2. The first pass gate device PG1 and the second pass gate device PG2 are second conductive type devices. In the embodiment, the first conductive type is a P-type and the second conductive type is an N-type. Of course, in another embodiment, it is possible for the first conductive type to be an N-type and the second conductive type to be a P-type, and in such a case, the remaining elements in the SRAM are appropriately modified according to common knowledge in the art.

[0009] The SRAM further includes a first P-type well PW1, a second P-type well PW2, and an N-type well NW. As shown in Fig. 1, the first pass gate device PG1 (N-type) and the first N-type FET device PD1 are arranged in the first P-type well PW1, the second pass gate FET device PG2 (N-type) and the second N-type FET device PD2 are arranged in the second P-type well PW2, and the first P-type FET device PU1 and the second P-type FET device PU2 are arranged in the N-type well NW.

[0010] Fig. 2 is an exemplary design of an SRAM unit cell according to an embodiment of the present disclosure. in Fig. 2 shows only some of the elements of the lower layer.

[0011] The SRAM unit cell is defined by a cell boundary CELB and includes first to fourth fin assemblies F1, F2, F3, and F4, each extending in the Y direction (column direction) and arranged in the X direction (row direction). The four fin assemblies F1, F2, F3, and F4 are arranged in this order in the X direction. The cell boundary CELB has a bottom side extending in the X direction, a top side extending in the X direction and opposite the bottom side, a left side extending in the Y direction, and a right side extending in the Y direction and opposite the left side.

[0012] The SRAM unit cell includes six transistors. The first pass gate device PG1 is a fin field effect transistor (FinFET) (PG1) formed by a first gate electrode GA1 and the first fin structure F1. The first N-type FET device PD1 is a FinFET formed by a second gate electrode GA2 and the first fin structure F1. The first P-type FET device PU1 is a FinFET formed by the second gate electrode GA2 and the third fin structure F3. The second pass gate device PG2 is a FinFET formed by a third gate electrode GA3 and the second fin structure F2. The second N-type FET device PD2 is a FinFET formed by a fourth gate electrode GA4 and the second fin structure F2. The second P-type FET device PU2 is a FinFET formed by the fourth gate electrode GA4 and the fourth fin structure F4.Each of the six FinFETs in the SRAM unit cell comprises only one active fin structure that acts as a channel and source / drain.

[0013] The SRAM unit cell of the embodiment further includes a first contact bar CB1 formed over the source of the FinFET PD1, which includes an epitaxial source / drain (S / D) layer formed over the first fin structure, and a second contact bar CB2 formed over the source of the FinFET PD2, which includes an epitaxial S / D layer formed over the second fin structure. The first and second contact bars CB1 and CB2 are electrically connected to a first power supply line, for example, Vss. The epitaxial S / D layer consists of one or more layers of SiP, SiC, SiCP, Si, Ge, or a group III-V material. The contact bars may consist of one or more layers of Cu, W, Al, AlCu, TiN, TiW, Ti, Co, Ni, TaN, Ta, or another refractory metal, or combinations thereof.

[0014] As in Fig. As shown in Figure 2, the first and second fin assemblies F1 and F2 extend in the Y direction from a bottom surface of the cell boundary CELB and an upper surface of the cell boundary CELB opposite the bottom surface. The third fin assembly F3 extends in the Y direction from the bottom surface of the cell boundary CELB and is shorter than the first and second fin assemblies. The fourth fin assembly F4 extends in the Y direction from the top surface of the cell boundary CELB and is shorter than the first and second fin assemblies.

[0015] The SRAM unit cell further includes third to eighth contact bars (contact plugs) CB3 to CB8. The third contact bar CB3 connects a drain of the FinFET PG1 and a drain of the FinFET PD1 to a drain of the FinFET PU1 and is electrically connected to the word line. The fourth contact bar CB4 connects a drain of the FinFET PG2 and a drain of the FinFET PD2 to a drain of the FinFET PU2 and is electrically connected to the word line. The fifth contact bar CB5 is arranged over a source of the FinFET PG1 and is electrically connected to a bit line. The sixth contact bar CB6 is arranged over a source of the FinFET PU1 and is electrically connected to a second power supply line, for example, Vdd. The seventh contact bar CB7 is arranged over a source of the FinFET PU2 and is electrically connected to the second power supply line.The eighth contact rail CB8 is arranged above a source of the FinFET PG2 and is electrically connected to a complementary bit line.

[0016] The SRAM comprises several SRAM unit cells arranged in the X (row) and Y (column) directions. Fig. Figure 3 shows an exemplary configuration of four SRAM unit cells, a first to fourth SRAM unit cell SR1, SR2, SR3 and SR4. The first SRAM SR1, for example, has the Fig. 2. The second SRAM SR2 has a configuration that is a configuration of the first SRAM SR1 horizontally inverted with respect to an axis parallel to the Y direction. The third SRAM SR3 has a configuration that is a configuration of the first SRAM SR1 vertically inverted with respect to an axis parallel to the X direction. The fourth SRAM SR4 has a configuration that is a configuration of the third SRAM SR3 horizontally inverted with respect to an axis parallel to the Y direction. A plurality of first SRAMs SR1 and a plurality of third SRAMs SR3 are alternately arranged along the column direction (Y).

[0017] Fig. Figure 4 shows an SRAM array comprising three rows and two columns. The individual SRAM unit cells have the design structure of Fig. 2 and its inverted superstructures as described above.

[0018] As in Fig. As shown in Figure 4, the first contact bar CB1 is located at a first side (the left side) of the cell boundary CELB of an SRAM unit cell (e.g., SR1) and electrically connects the source of the FinFET PD1 in the SRAM unit cell and the sources of the FinFETs PD1 in the adjacent SRAM unit cells (e.g., SR2 to SR4). The second contact bar CB2 is located at a right side and an upper side of the cell boundary CELB of an SRAM unit cell (e.g., SR1) and electrically connects the source of the FinFET PD2 in the SRAM unit cell and the sources of the FinFETs PD2 in the adjacent SRAM unit cells (e.g., SR2 to SR4). The first and second contact bars CB1 and CB2 are shared by the adjacent four SRAM unit cells.

[0019] The fifth contact bar CB5 is located on the upper side of the cell boundary in an SRAM unit cell (e.g., SR1) and connects the source of the FinFET PG2 in the SRAM unit cell and the source of the FinFET PG2 in the neighboring SRAM unit cell in the Y direction. The sixth contact bar CB6 is located on the lower side of the cell boundary in an SRAM unit cell (e.g., SR1) and connects the source of the FinFET PU1 in the SRAM unit cell and the source of the FinFET PU1 in the neighboring SRAM unit cell in the Y direction. The seventh contact bar CB7 is located on the upper side of the cell boundary in an SRAM unit cell (e.g., SR1) and connects the source of the FinFET PU2 in the SRAM unit cell and the source of the FinFET PU2 in the neighboring SRAM unit cell in the Y direction. The eighth contact rail CB8 is located at the bottom of the cell boundary in an SRAM cell (e.g.SR1) and connects the source of the FinFET PG2 and the source of the FinFET PG2 in the adjacent SRAM unit cell in the Y direction.

[0020] Alternatively, it can be said that the first and second contact bars CB1 and CB2 are arranged at corners where four adjacent SRAM unit cells SR1 to SR4 meet and are commonly used by four SRAM unit cells, and the fifth to eighth contact bars CB5 to CB8 are commonly used by adjacent SRAM units in the Y direction.

[0021] Fig. 5A shows an exemplary perspective view of a FinFET. The FinFET 1 includes, among other features, a substrate 10, a fin structure 20, a gate dielectric 30, and a gate electrode 40. In this embodiment, the substrate 10 is a silicon substrate. Alternatively, the substrate 10 may comprise another elemental semiconductor such as germanium; a compound semiconductor including group IV-IV compound semiconductors such as SiC and SiGe; group III-V compound semiconductors such as GaAs, GaP, GAN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The fin structure 20 is disposed over the substrate. The fin structure 20 may be made of the same material as the substrate 10 and may extend continuously from the substrate 10. In this embodiment, the fin structure is made of Si.The silicon layer of the fin structure 20 may be intrinsic or suitably doped with an n-type impurity or a p-type impurity.

[0022] The lower part of the fin structure 20 below the gate electrode 40 is called the well region, and the upper part of the fin structure 20 is called the channel region. Below the gate electrode 40, the well region is embedded in the isolation insulating layer 50, and the channel region protrudes from the isolation insulating layer 50. Spaces between the fin structures 20 and / or a space between a fin structure and another element formed above the substrate 10 are filled with an isolation insulating layer 50 (or a so-called "trench isolation (STI)") containing an insulating material. The insulating material for the isolation insulating layer 50 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material.

[0023] The channel region protruding from the insulating layer 50 is covered by a gate dielectric layer 30, and the gate dielectric layer 30 is further covered by a gate electrode 40. A portion of the channel region not covered by the gate electrode 40 acts as the source and / or drain of the MOSFET.

[0024] In certain embodiments, the gate dielectric layer 30 comprises a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titania, hafnium dioxide-alumina (HfO2-Al2O3), other suitable high-k dielectric materials, and / or combinations thereof.

[0025] The gate electrode 40 comprises any suitable material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate structure can be formed using a "gate last" or "replacement gate" methodology.

[0026] In some embodiments, one or more work function regulation layers (not shown) may be inserted between the gate dielectric layer and the gate electrode. The work function regulation layers are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, NiSi, PtSi, or TiAlC, or any other suitable materials, or a multilayer of two or more of these materials. For the n-channel FinFET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi, or any other suitable materials, are used as the work function regulation layer, and for the p-channel FinFET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co, or any other suitable materials, are used as the work function regulation layer.The work function regulation layer can be formed separately for the n-channel FinFET and the p-channel FinFET, which can use different metal layers.

[0027] The source and drain regions are formed by appropriately doping impurities into the source and drain regions or epitaxially growing a suitable material also in the fin structure 20 not covered by the gate electrode 40. An alloy of Si or Ge and a metal such as Co, Ni, W, Ti, or Ta can be formed on the source and drain regions.

[0028] Fig. 5B shows an exemplary sectional view along the line X1-X1 in Fig. 2. An epitaxial S / D layer 25 is formed on each of the fin structures F1, F4, and F2. Furthermore, the second contact bar CB2 is formed on the S / D layers of the second fin structure F2. The fifth and seventh contact bars CB5 and CB7 are formed on the first fin structure F1 and the fourth fin structure F4, respectively.

[0029] Fig. 5C shows an exemplary cross-sectional view illustrating a vertical layer arrangement of the SRAM. Fig. 5 does not necessarily show a specific cross-section of the SRAM unit cell, which is Fig. 2 to 4.

[0030] The fin structures and the source / drain structures are arranged in the substrate layer. Gate structures comprising gate electrodes and gate dielectric layers are arranged in the gate layer. The gate contact layer is located above the gate layer. The contact rails are arranged in the contact rail layer, which extends from the gate layer to the gate contact layer. First vias are arranged in the first via layer, which is located above the gate contact layer and the contact rail layer. The first metal wirings are arranged in the first metal layer. The second vias are arranged in the second via layer. Second metal wirings are arranged in the plane of the second metal layer.

[0031] Fig. 6 and Fig. 7 show an exemplary configuration of the upper layer of an SRAM unit cell according to the embodiment of the present disclosure.

[0032] As in Fig. 6, the SRAM unit cell further comprises first to fourth gate contacts GC1 to GC4. The first gate contact GC1 is arranged on the first gate electrode GA1, and a second gate contact GC2 is arranged on the third gate electrode GA3. The third gate contact GC3 is arranged above the fourth gate electrode GA4 and the third contact bar CB3 and electrically connects the fourth gate electrode GC4 and the third contact bar CB3. The fourth gate contact GC4 is arranged above the third gate electrode GA3 and the fourth contact bar CB4 and electrically connects the third gate electrode GA3 and the fourth contact bar CB4. As shown in Fig. As shown in Figure 6, the first and second gate contacts GC1 and GC2 are located on the cell boundary CELB and are shared by adjacent SRAM unit cells.

[0033] The SRAM unit cell further comprises first to eighth vias V1 to V8. The first via V1 is arranged over the first gate contact GC1, and the second via V2 is arranged over the second gate contact GC2. The third via V3 is arranged over the first contact bar CB1, and the fourth via V4 is arranged over the second contact bar CB2. The fifth via V5 is arranged over the fifth contact bar CB5, the sixth via V6 is arranged over the sixth contact bar CB6, the seventh via V7 is arranged over the seventh contact bar CB7, and the eighth via V8 is arranged over the eighth contact bar CB8. As shown in Fig. As shown in Figure 6, the vias V1 to V8 are located on the cell boundary CELB and are shared by neighboring SRAM unit cells. The vias V1 to V8 are in the first via layer, which is shown in Fig. 5C is shown.

[0034] Fig. 6 also shows the bit line BL, the second power supply line VDD, and the complementary bit line BLB extending in the Y direction across multiple SRAM unit cells. The bit line BL is electrically connected to the source of the FinFET PG1 (formed on the first fin structure F1) through the fifth via V5 and the fifth contact bar CB5, and the complementary bit line BLB is electrically connected to the source of the FinFET PG2 (formed on the second fin structure F2) through the eighth via V8 and the eighth contact bar CB8. The second power supply line VDD is electrically connected to the source of the FinFET PU1 (formed on the third fin structure F3) and the source of the FinFET PU2 (formed on the fourth fin structure F4) through the sixth and seventh vias V6 and V7 and the sixth and seventh contact bars CB6 and CB7, respectively.

[0035] In addition, first to fourth local plates LP1 to LP4 are provided. The first local plate LP1 is electrically connected to the first gate electrode through the first via V1 and the first gate contact GC1, and the second local plate LP2 is electrically connected to the third gate electrode GC3 through the second via V2 and the second gate contact GC2. The third local plate LP3 is electrically connected to the source of the FinFET PD1 through the third via V3 and the first contact bar CB1, and the fourth local plate LP4 is electrically connected to the source of the FinFET PD2 through the fourth via V4 and the second contact bar CB2. The bit line BL, the complementary bit line BLB, the second power supply line VDD, and the first to fourth local plates are formed in the first metal layer formed in Fig. 5C is shown.

[0036] Fig. 7 shows an exemplary configuration of an upper layer of an SRAM unit cell. A word line WL extending in the X direction is provided and electrically connected to the first and second local plates LP1 and LP2 through a first upper via VA1 and a second upper via VA2. Also provided are two first power supply lines VS1 and VS2 extending in the X direction and connected to the third and fourth local plates LP3 and LP4, respectively, through a third upper via VA3 and a fourth upper via VA4.

[0037] As in Fig. As shown in Figure 7, the first and second upper vias VA1 and VA2 are located on the cell boundary CELB and are shared by adjacent SRAM unit cells, and the third and fourth upper vias VA3 and VA4 are located at the corner of the cell boundary CELB and are shared by four adjacent SRAM unit cells. Fig. As shown in Fig. 5C, the upper vias VA1 to VA4 are formed in the second via layer, and the word lines WL and the first power supply lines VS1 and VS2 are formed in the second metal layer.

[0038] The via and metal layers consist of one or more layers of Cu, W, Al, AlCu, TiN, TiW, Ti, Co, Ni, TaN, Ta, or another refractory metal, or combinations thereof.

[0039] Fig. 8A to 12C illustrate exemplary sequential processes for fabricating fin assemblies for an SRAM device according to an embodiment of the present disclosure. Fig. 8A, Fig. 9A, ... 12A are all the same figure and illustrate the fin stack design in four subsequently formed adjacent SRAM unit cells. Fig. 8B, Fig. 9B, ... 12B show plan views at each manufacturing stage, and Fig. 8C, Fig. 9C, ... 12C show sectional views along X1-X1 or X2-X2 in Fig. 8B, Fig. 9B, ... 12B at every stage of production. It is understood that before, during and after the processes carried out by Fig. 8A to 12A, additional acts may be provided, and some of the acts described below may be replaced or eliminated in additional embodiments of the method.

[0040] Fig. Figure 8A shows the fin stack design in four subsequently formed adjacent SRAM unit cells. The design of the four SRAM unit cells is the same as in Fig. 4.

[0041] In an SRAM unit cell, for example SR1, there are four fin assemblies 22, 24, 26 and 28, which respectively correspond to the first to fourth fin assemblies of Fig. 2. The fin structures extend in the second direction (Y direction) and are arranged in the first direction (X direction).

[0042] In a cell, that is, within a cell boundary, the first fin structure 22 extends between a bottom surface of the cell boundary and an upper surface of the cell boundary opposite the bottom surface. The second fin structure 24 extends between the bottom surface of the cell boundary and the upper surface of the cell boundary opposite the bottom surface. The third fin structure 26 extends from the bottom surface and is shorter than the first fin structure. The fourth fin structure 28 extends from the top surface and is shorter than the second fin structure. The first to fourth fin structures are arranged at a predetermined pitch in the X direction. In this embodiment, the predetermined pitch is constant. The pitch between the first and third fin structures may be different from the pitch between the third and fourth fin structures.

[0043] The width of the fin structures is in a range of about 5 nm to about 30 nm in some embodiments, and is in a range of about 7 nm to about 15 nm in other embodiments. The spacing S1 between adjacent fin structures is in a range of about 20 nm to about 50 nm in some embodiments and in a range of about 30 nm to about 40 nm in other embodiments.

[0044] As in Fig. 8B and Fig. As shown in Figure 8C, a first dummy structure 110 is formed over a substrate 10. The first dummy structure 110 is made of inorganic materials such as silicon oxide and / or silicon nitride. A cap layer made of a first material is formed over the substrate 10, and then a patterning operation, including a lithography process and / or an etching operation, is performed to form the first dummy structures 110.

[0045] When the first dummy structure 110 is made of an inorganic material, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) may be used to form the capping layer.

[0046] The first dummy structures 110 are formed in a line- and step-like manner so as to extend in the Y direction. The width of the first dummy structure 110 is substantially equal to the distance S2. As shown in Fig. 8A and Fig. 8B, the left edge of the first dummy structure 110 substantially corresponds to the right edge of the third fin assembly 26, and the right edge of the first dummy structure 110 substantially corresponds to the left edge of the fourth fin assembly 28. The first dummy structures, including dummy structures 111, 112, 119, 114, and 117 extending in the Y direction, are formed in this order in the X direction.

[0047] The thickness of the first dummy structure 110 is in a range from about 100 nm to about 300 nm.

[0048] Then, a second cap layer 120 made of a second material is formed over the first dummy structures 110. The second material is an inorganic material such as silicon oxide and silicon nitride and is different from the first material. In this embodiment, silicon oxide formed by CVD is used. The thickness of the second material from the top surface of the substrate 10 is in a range of about 5 nm to about 20 nm.

[0049] Since the thickness of the second material layer is sufficiently smaller than the spaces 121, 123, 127 and 129 of the first dummy structures, the second material layer does not completely fill the spaces and is formed surface-true over the first dummy structures.

[0050] Next, an anisotropic etch is performed on the top layer of the second material. As shown in Fig. 9B and Fig. As shown in Figure 9C, the second material remains as a sidewall spacer on the left and right sides of the first dummy structures, and mask structures 121B, 122A, 123A, 125B, 124A, and 127A are formed after the removal of the first dummy structures.

[0051] The width of each of the mask structures 121B, 122A, 123A, 125B, 124A, and 127A is substantially equal to or slightly larger than the width of the subsequently formed fin structures. The width ranges from about 7 nm to about 20 nm.

[0052] By regulating the thickness and / or dimensions of the cover layers of the first and second materials and the first dummy structures, the desired width and the desired locations of the mask structure can be obtained.

[0053] Next, the mask structures are created as shown in Fig. 10B and Fig. 10C, a resist structure 130 with openings 135 is formed. Fig. 10C is a sectional view along the line X2-X2 in Fig. 10B. A portion of the mask structures 122A and 124B is exposed via the openings 135.

[0054] Then, the exposed portions of the mask structures are removed by etching operations and the resist structure 130 is removed. As in Fig. 11B and Fig. As shown in Figure 11C, the mask structures 121B, 122A, 122B, 123A, 125B, 124A, 124B, and 127A, which correspond to the fin structures to be formed, remain on the substrate 10. In this embodiment, the distance between adjacent mask structures within the cell boundary is constant.

[0055] Using the mask structures 121B, 122A, 122B, 123A, 125B, 124A, 124B and 127A as etching masks, a trench etch is performed on the substrate 10, whereby as in Fig. 12B and Fig. 12C shows how the fin structures 20 are formed. Finally, the mask structures are removed.

[0056] Fig. 13 to 17B show exemplary sequential processes for fabricating gate structures for an SRAM device according to an embodiment of the present disclosure. Fig. Figure 13 illustrates SRAM unit cells arranged in two rows and three columns.

[0057] After the formation of the fin structures 20, an insulating layer 200 (see Fig. 14B) such that upper portions of the fin structures are exposed from the insulating layer 200. Then, cap layers for a gate dielectric layer (not shown) and a gate electrode layer 210 (see Fig. 14B) was formed.

[0058] Then, as in Fig. 13, second dummy structures 220 are formed over the gate electrode layer 210. Fig. 13 is a top view (a plan view), and for the purpose of explaining the relative locations of the fin structure and the gate structures, one of the SRAM unit cells has the underlying fin structures 20 shown.

[0059] A cap layer made of a third material is formed over the gate electrode layer, and a patterning operation is performed to obtain the second dummy structures 220 made of the third material. The third material is one or more layers of silicon oxide and / or silicon nitride.

[0060] In the patterning operation, design data with a thin rectangular structure extending within an SRAM unit cell in the X direction is prepared, and a photomask with opaque structures corresponding to the thin rectangular structure is prepared (when a positive photoresist is used). In the present embodiment, the thin rectangular structure is arranged on the center line CL of the SRAM unit cell in the Y direction. In other words, only one structure is included on the photomask (or in the design data) in an SRAM unit cell. Using this photomask, resist structures corresponding to the dummy structures 220 are formed on the cap layer made of the third material, and the second dummy structures 220 are obtained by a dry etching operation.

[0061] After the formation of the second dummy structures 220, a cap layer made of a fourth material is formed over the second dummy structures 220 and the gate electrode layer 210, and an anisotropic etch is performed on the fourth cap layer, thereby obtaining a first hard mask layer 230 as sidewall spacer layers, as shown in Fig. 14A and Fig. 14B shown. Fig. 14A is a plan view, and Fig. 14B is a sectional view taken along lines Y1-Y1 in Fig. 14A.

[0062] Then, as in Fig. 15A and Fig. 15B, the second dummy structures 220 are removed, leaving the first hard mask structures 230. Fig. 15A is a plan view, and Fig. 15B is a sectional view taken along lines Y1-Y1 in Fig. 15A. The width of the first hard mask structure 230 at its bottom is in a range from about 5 nm to about 15 nm.

[0063] As in Fig. 16, a patterning operation is performed to “cut” or “split” the first hard mask structures into a plurality of pieces of first hard mask structures 235 to correspond to the desired gate electrode structure.

[0064] Using the “cut” first hard mask structure 235, the gate electrode layer 210 is patterned into a gate electrode structure 215 by dry etching, as shown in Fig. 17A and Fig. 17B is shown. Fig. 17A is a plan view, and Fig. 17B is a sectional view taken along lines X3-X3 in Fig. 17A. As in Fig. As shown in Figure 17B, the gate dielectric layer 217 is disposed over the exposed fin structures 20 and the gate electrode 215 is disposed over the gate dielectric layer 217.

[0065] When a gate replacement technology is used, the gate electrode 215 and the gate dielectric layer 217 are treated as dummy layers, which are subsequently replaced by an actual gate electrode and an actual gate dielectric layer.

[0066] After the formation of the gate electrodes 215, portions of the fin structures 20 not covered by the gate structure are recessed, and epitaxial source / drain (S / D) layers 25 are formed in and over the recessed portions.

[0067] Fig. 18 to 28B illustrate exemplary sequential processes for fabricating contact rail assemblies for an SRAM device according to an embodiment of the present disclosure. Fig. Figure 18 illustrates SRAM unit cells arranged in two rows and three columns.

[0068] After the formation of the gate structures and the epitaxial S / D layers, an interlayer dielectric layer (ILD) 250 is formed over the gate structures and the epitaxial S / D layer. Fig. 18 is a sectional view taken along the line Y2-Y2 in Fig. 17A. Furthermore, a cap layer 300 for a second hard mask layer is formed over the ILD layer 250, and a cap layer 320 for a third dummy structure is further formed over the layer 300. The thickness of the ILD layer 250 is in a range from about 20 nm to about 600 nm in some embodiments and in a range from about 50 nm to about 300 nm in other embodiments.

[0069] For example, the ILD layer 250 is comprised of one or more layers of a low-k dielectric material. Low-k dielectric materials have a k-value (dielectric constant) of less than about 4.0. Some low-k dielectric materials have a k-value of less than about 3.5 and may have a k-value of less than about 2.5. The materials for the ILD layer 250 may include compounds comprising Si, O, C, and / or H, such as SiCOH and SiOC. Organic materials such as polymers may be used for the ILD layer 250. For example, in certain embodiments, the ILD layer 250 is comprised of one or more layers of a carbonaceous material, organosilicate glass, a porogen-containing material, and / or combinations thereof.The ILD layer 250 may be formed using, for example, plasma enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), and / or spin-on technology.

[0070] The second hard mask layer 300 includes one or more layers of dielectric materials or metal materials, such as TiN, poly-Si, amorphous Si, silicon oxide, or silicon nitride. The thickness of each layer of layer 300 ranges from about 2 nm to about 200 nm in some embodiments and from about 5 nm to about 50 nm in other embodiments.

[0071] Third dummy layer 330 includes one or more layers of dielectric materials or metal materials, such as TiN, poly-Si, amorphous Si, silicon oxide, or silicon nitride. The thickness of each layer of layer 330 ranges from about 2 nm to about 200 nm in some embodiments and from about 5 nm to about 50 nm in other embodiments.

[0072] The layers 300, 320 and 330 can be formed using, for example, physical vapor deposition (PVD), sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD) and / or atomic layer CVD (ALCVD).

[0073] Then, as in Fig. 19 shows the third dummy structures 325 formed. Fig. 19 is a top view (a plan view), and for the purpose of explaining the relative locations of the fin structure and the gate structures, the underlying fin structures 20 and gate electrodes 215 are shown in one of the SRAM unit cells. A patterning operation including lithography and dry etching is performed to obtain the third dummy structures 325.

[0074] In the patterning operation for the third dummy pattern 325, design data having a thin rectangular pattern extending within an SRAM unit cell in the X direction is prepared, and a photomask having opaque patterns corresponding to the thin rectangular pattern is prepared (when a positive photoresist is used). In the present embodiment, the thin rectangular pattern is arranged in the lower half of the SRAM unit cell in the Y direction. In other words, only one pattern is included on the photomask (or in the design data) in an SRAM unit cell. Using this photomask, resist patterns corresponding to the third dummy patterns 325 are formed on the cap layer 300, and the third dummy patterns 325 are obtained by a dry etching operation.

[0075] After the formation of the third dummy structures 325, a cap layer made of a fifth material for a dummy hard mask layer is formed over the third dummy structures 325 and the ILD layer 250, and an anisotropic etch is performed on the fifth cap layer, thereby obtaining a second hard mask layer 330 as a sidewall spacer layer, as shown in Fig. 20. The thickness of the fifth material layer is in a range of about 2 nm to about 70 nm in some embodiments.

[0076] Then, as in Fig. 21, the third dummy structures 325 are removed, leaving the dummy hardmask structures 330 above the ILD layer 250. The width of the dummy hardmask structure 330 at its bottom in the Y direction is in a range from about 2 nm to about 70 nm in some embodiments and in a range from about 10 nm to about 40 nm in other embodiments.

[0077] As in Fig. As shown in Figure 21, the dummy hard mask patterns are formed on the cell boundary CELB in the X direction (upper and lower sides of the cell boundary) and inside each SRAM unit cell. In other words, each SRAM unit cell includes one dummy hard mask pattern with a full width and two dummy hard mask patterns with half the full width.

[0078] As in Fig. 22, Fig. 23A and Fig. 23B, a patterning operation is performed to “cut” or “split” the dummy hard mask structures 330 to correspond to the desired contact rail structure.

[0079] A resist layer is formed over the second hard mask structures 330, and a lithography process is performed on the resist layer to form openings 340, as shown in Fig. 22 is shown.

[0080] In the lithography process, design data having opening patterns substantially corresponding to the openings 360 is prepared, and a photomask having transparent patterns corresponding to the opening patterns is prepared (when a positive photoresist is used).

[0081] Then, a dry etching operation is performed to cut (or split) the dummy hard mask structures 330, thereby forming a final “cut” dummy hard mask structure (multiple pieces of the dummy hard mask structures) 335, as shown in Fig. 23A and Fig. 23B is shown. Fig. 23B is a sectional view taken along the line Y3-Y3 in Fig. 23A. The shapes and locations of the “cut” dummy hard mask structures 335 substantially correspond to the subsequently formed contact rails.

[0082] Then, as in Fig. 24, a reversal layer 350 is formed over the layer 330 and between the dummy hard mask structures 335. The deposition process is designed to keep the upper portion of the dummy hard mask structures 335 exposed, as shown in Fig. 24. The reversal layer 350 comprises one or more layers of silicon oxide, silicon nitride, silicon carbide (SiC), or SiON. Alternatively, the reversal layer 350 may comprise polysilicon, a photoresist, a polymer, a bottom anti-reflective coating (BARC), metals, or other suitable materials. In the present embodiment, the material of the reversal layer 350 is selected to withstand a subsequent etch process to remove the dummy hard mask structure 335. The deposition of the reversal layer 350 is performed by techniques such as CVD, PVD, spin coating, epitaxial growth, thermal growth, or other appropriate deposition techniques.

[0083] To expose the upper portion of the dummy hard mask structure 335, the deposition process may be a selective deposition process with an appropriate target thickness. In the selective deposition process, the reversal layer 350 is formed on the layer 300 between the dummy hard mask structures 335, but not on the dummy hard mask structures 335. And the thickness of the reversal layer 350 is controlled to ensure that the upper portion of the dummy hard mask structure 335 remains exposed. Alternatively, a non-selective deposition process, such as a spin-coating process, may be performed. For example, the upper portion of the dummy hard mask structure 335 may remain exposed with an appropriate target thickness of the spin-coating process.In the spin coating process, the thickness of the spin coated material can be controlled by several factors such as the type of spin coated material and the spin speed.

[0084] As a further alternative, a non-selective and non-spin-coating deposition process may be performed to deposit the reversal layer 350 over the layer 300 and the dummy hard mask structure 335. An etch-back process may be used to remove the excess reversal layer 350 and expose the upper portion of the dummy hard mask structure 335. As one example, a chemical mechanical polishing (CMP) process is performed to remove a portion of the reversal layer 350 such that the dummy hard mask structure 335 is exposed. In the illustrated embodiment, the reversal layer 350 comprises polysilicon, amorphous Si, or a refractory metal formed by a deposition technique such as CVD or PVD. Thereafter, an etch-back or CMP process may be performed to keep the upper portion of the dummy hard mask structure 335 exposed.

[0085] Next, as in Fig. 25A and Fig. 25B, the dummy hard mask structures 335 are removed, forming openings 360. Fig. 25A is a plan view and Fig. 25B is a sectional view along the line Y3-Y3 in Fig. 25A.

[0086] The dummy hardmask structure 335 can be removed by dry etching, wet etching, or a combination thereof. Appropriate etch selectivity of the removal process minimizes the loss of the sidewall of the reversal layer 350 and results in a relatively vertical profile for the openings 360 with substantially the same width as that of the removed dummy hardmask structure 335. The dimensions of the openings 360 essentially define the dimensions of the contact bars in a subsequent process.

[0087] Then, using the reversal layer 350 with the openings 360 as an etch mask, the layer 300 is patterned into a third hard mask layer 305 with openings 365, as shown in Fig. 26. The etching process may be an anisotropic etch, which may be a relatively vertical profile with substantially the same width / length as that of the openings 360, leaving the third hard mask layer 305. Then, the reversal layer 350 is removed by dry etching or wet etching.

[0088] Next, as in Fig. 27A and Fig. 27B, the ILD layer 250 is etched using the third hard mask layer 305 as an etch mask, thereby forming via holes / openings 375 that reach the epitaxial S / D layer 25.

[0089] After the formation of the via holes / openings 375, a conductive material comprising one or more of Cu, W, Al, AlCu, TiN, TiW, Co, Ni, TaN, Ta, or another hard-melting metal is filled into the via holes / openings 375. After a planarization operation such as CMP, the contact bars 380 are formed, as shown in Fig. 28A and Fig. 28B is shown.

[0090] In the above embodiment, layer 300 is formed over ILD layer 250 and subsequently used as a third hard mask layer. In other embodiments, layer 300 is not formed, and ILD layer 250 is etched using reverse layer 350 with openings 360 as an etch mask.

[0091] The various embodiments or examples described herein offer several advantages over the existing art. For example, in the present disclosure, by using two photomasks in two photolithography processes, gate electrode structures and / or openings in the ILD layer for contact bars with smaller dimensions can be uniformly formed.

[0092] It will be understood that not all advantages have necessarily been discussed here, and no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0093] According to one aspect of the present disclosure, a method for manufacturing a static random access memory (SRAM) including a plurality of SRAM cells includes the following operations: An insulating layer is formed over a substrate. First dummy structures are formed over the insulating layer. Sidewall spacer layers are formed as second dummy structures on sidewalls of the first dummy structures. The first dummy structures are removed, leaving the second dummy structures above the insulating layer. After removing the first dummy structures, each of the second dummy structures is divided into a plurality of pieces of the second dummy structures. A mask layer is formed over the insulating layer and between the plurality of pieces of the second dummy structures.After forming the mask layer, the plurality of second dummy structures are removed, forming a hard mask layer having openings corresponding to the plurality of second dummy structures. The insulating layer is patterned using the hard mask layer as an etch mask, forming via openings in the insulating layer. A conductive material is filled into the via openings, forming contact bars.

[0094] According to another aspect of the present disclosure, a method for manufacturing a static random access memory (SRAM) including a plurality of SRAM cells includes the following operations: An insulating layer is formed over a substrate. A first mask layer is formed over the insulating layer. First dummy structures are formed over the first mask layer. Sidewall spacer layers are formed as second dummy structures on sidewalls of the first dummy structures. The first dummy structures are removed, leaving the second dummy structures above the first mask layer. After removing the first dummy structures, each of the second dummy structures is divided into a plurality of pieces of the second dummy structures. A second mask layer is formed over the first mask layer and between the plurality of pieces of the second dummy structures.After forming the second mask layer, the plurality of second dummy structures are removed, forming a first hard mask layer having openings corresponding to the plurality of second dummy structures. The first mask layer is patterned using the first hard mask layer as an etch mask, forming a second mask layer. The insulating layer is patterned using the second hard mask layer as an etch mask, forming via openings in the insulating layer. A conductive material is filled into the via openings, forming contact bars.

[0095] According to another aspect of the present disclosure, a method for manufacturing a static random access memory (SRAM) including a plurality of SRAM cells includes the following operations: A first insulating layer is formed over a substrate. A first layer is formed over the first insulating layer. First dummy structures are formed over the first layer. Sidewall spacer layers are formed as second dummy structures on sidewalls of the first dummy structures. The first dummy structures are removed, leaving the second dummy structures over the first mask layer. After removing the first dummy structures, each of the second dummy structures is divided into a plurality of pieces of the second dummy structures. The first layer is patterned using the plurality of pieces of the second dummy structures as an etch mask, thereby forming gate structures.

Claims

[1] A method of manufacturing an SRAM device comprising a plurality of SRAM cells (SR1-SR4), the method comprising: forming an insulating layer (250) over a substrate (10); Forming first dummy structures (325) over the insulating layer (250); Forming sidewall spacer layers (330) as second dummy structures (330) on sidewalls of the first dummy structures (325); removing the first dummy structures (325), leaving the second dummy structures (330) above the insulating layer (250); after removing the first dummy structures (325), dividing each of the second dummy structures (330) into a plurality of pieces (335) of the second dummy structures (330); Forming a mask layer (350) over the insulating layer (250) and between the plurality of pieces (335) of the second dummy structures (330); after forming the mask layer (350), removing the plurality of pieces (335) of the second dummy structures (330), thereby forming a hard mask layer (350) having openings (360) corresponding to the plurality of pieces (335) of the second dummy structures (330); Structuring the insulating layer (250) using the hard mask layer (350) as an etching mask, thereby forming via openings (375) in the insulating layer (250); and Filling a conductive material into the via openings (375), thereby forming contact rails (380). [2] Method according to claim 1, wherein forming the first dummy structures (325) comprises: - forming a first material layer (320) over the insulating layer (250); - forming a resist layer over the first material layer (320); - structuring the resist layer using a first photomask; and - structuring the first material layer (320) using the structured resist layer as an etching mask, thereby forming the first dummy structure (325), and wherein in the first photomask, in a region corresponding to each of a plurality of SRAM unit cells (SR1-SR4), only one rectangular structure extending in a row direction (X) of the SRAM device is included. [3] The method according to claim 1 or 2, wherein in a region corresponding to each of the plurality of SRAM unit cells (SR1-SR4), one of the second dummy structures (330) is arranged in the region, and two of the second dummy structures (330) are arranged over an upper and a lower boundary of the region extending in a row direction (X). [4] Method according to one of the preceding claims, wherein each of the SRAM unit cells contains six FinFETs (PD1, PD2, PU1, PU2, PG1, PG2); and the contact rails (380) are connected to sources and drains of the FinFETs (PD1, PD2, PU1, PU2, PG1, PG2). [5] Method according to one of the preceding claims, wherein the first dummy structures (325) consist of a different material than the second dummy structures (330). [6] Method according to one of the preceding claims, wherein the second dummy structures (330) consist of a different material than the mask layer (350). [7] A method according to any one of the preceding claims, wherein the via openings (375) are formed using two photomasks in two lithography processes. [8] A method of manufacturing an SRAM device comprising a plurality of SRAM cells (SR1-SR4), the method comprising: forming an insulating layer (250) over a substrate (10); Forming a first mask layer (300) over the insulating layer (250); Forming first dummy structures (325) over the first mask layer (300); Forming sidewall spacer layers (330) as second dummy structures (330) on sidewalls of the first dummy structures (325); removing the first dummy structures (325), thereby leaving the second dummy structures (330) above the first mask layer (300); after removing the first dummy structures (325), dividing each of the second dummy structures (330) into a plurality of pieces (335) of the second dummy structures (330); Forming a second mask layer (350) over the first mask layer (300) and between the plurality of pieces (335) of the second dummy structures (330); after forming the second mask layer (350), removing the plurality of pieces (335) of the second dummy structures (330), thereby forming a first hard mask layer (350) having openings (360) corresponding to the plurality of pieces (335) of the second dummy structures (330); Structuring the first mask layer (300) using the first hard mask layer (350) as an etching mask, thereby forming a second hard mask layer (305); Structuring the insulating layer (250) using the second hard mask layer (305) as an etching mask, thereby forming via openings (375) in the insulating layer (250); and Filling a conductive material into the via openings (375), thereby forming contact rails (380). [9] Method according to claim 8, wherein forming the first dummy structures (325) comprises: - forming a first material layer (320) over the first mask layer (300); - forming a resist layer over the first material layer (320); - structuring the resist layer using a first photomask; and - structuring the first material layer (320) using the structured resist layer as an etching mask, thereby forming the first dummy structure (325), and wherein in the first photomask, in a region corresponding to each of a plurality of SRAM unit cells (SR1-SR4), only one rectangular structure extending in a row direction (X) of the SRAM device is included. [10] The method according to claim 8 or 9, wherein in a region corresponding to each of the plurality of SRAM unit cells (SR1-SR4), one of the second dummy structures (330) is arranged in the region, and two of the second dummy structures (330) are arranged over an upper and a lower boundary of the region extending in a row direction (X). [11] Method according to one of claims 8 to 10, wherein each of the SRAM unit cells (SR1-SR4) contains six FinFETs (PD1, PD2, PU1, PU2, PG1, PG2); and the contact rails (380) are connected to sources and drains of the FinFETS (PD1, PD2, PU1, PU2, PG1, PG2). [12] The method according to any one of claims 8 to 11, wherein the first dummy structures (325) are made of a different material than the second dummy structures (330). [13] Method according to one of claims 8 to 12, wherein the second dummy structures (330) consist of a different material than the first mask layer (300). [14] The method according to any one of claims 8 to 13, wherein the first mask layer (300) is made of a different material than the second mask layer (350). [15] The method of any one of claims 8 to 14, wherein the via openings (375) are formed using two photomasks in two lithography processes. [16] A method of manufacturing an SRAM device comprising a plurality of SRAM cells (SR1-SR4), the method comprising: Forming a first insulating layer (200) over a substrate (10); Forming a first layer (210) over the first insulating layer (200); Forming first dummy structures (220) over the first layer (200); Forming sidewall spacer layers (230) as second dummy structures (230) on sidewalls of the first dummy structures (220); removing the first dummy structures (220), leaving the second dummy structures (230) above the first layer (210); Dividing each of the second dummy structures (230) into a plurality of pieces (235) of the second dummy structures (230); Structuring the first layer (210) using the plurality of pieces (235) of the second dummy structures (230) as an etching mask, thereby forming gate structures (215), the method further comprising: prior to forming the first layer (210), forming fin structures (20) over the substrate (10); after forming the gate structures (215): - forming source / drain regions in the fin structures (20); - forming a second insulating layer (250) over the gate structures (215) and the source / drain regions; - forming a first mask layer (300) over the second insulating layer (250); - forming third dummy structures (325) over the first mask layer (300); - forming sidewall spacer layers (330) as fourth dummy structures (330) on sidewalls of the third dummy structures (325); - removing the third dummy structures (325), leaving the fourth dummy structures (330) above the first mask layer (300); - after removing the third dummy structures (325), dividing each of the fourth dummy structures (330) into a plurality of pieces (335) of the fourth dummy structures (330); - forming a second mask layer (350) over the first mask layer (300) and between the plurality of pieces (335) of the fourth dummy structures (330); - after forming the second mask layer (350), removing the plurality of pieces (335) of the fourth dummy structures (330), thereby forming a first hard mask layer (350) having openings (360) corresponding to the plurality of pieces (335) of the fourth dummy structures (330); - structuring the first mask layer (300) using the first hard mask layer (350) as an etching mask, thereby forming a second hard mask layer (305); - structuring the second insulating layer (250) using the second hard mask layer (305) as an etching mask, thereby forming via openings (375) in the second insulating layer (250); and - filling a conductive material into the via openings (375), thereby forming contact rails (380) which are each in contact with the source / drain regions. [17] The method of claim 16, wherein the formation of the first dummy structures (220) comprises: - forming a first layer of material over the first layer (210); - forming a resist layer over the first material layer; - structuring the resist layer using a first photomask; and - structuring the first material layer using the structured resist layer as an etching mask, thereby forming the first dummy structure (20), and wherein in the first photomask, in a region corresponding to each of a plurality of SRAM unit cells (SR1-SR4), only one rectangular structure extending in a row direction (X) of the SRAM device is included. [18] The method according to claim 16 or 17, wherein in a region corresponding to each of the plurality of SRAM unit cells (SR1-SR4), only one of the first dummy structures (220) is arranged on a center line of the region extending in a row direction (X). [19] The method according to any one of claims 16 to 18, wherein the first layer (210), the first dummy structures (220) and the second dummy structures (230) are formed of materials that are different from each other.

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