Clock generation circuit having an equalization function, and integrated semiconductor circuit having the same

Abstract

Clock generation circuit (100, 100C, 100D) comprising: a clock gating circuit (110) configured to receive a first waveform signal (PH0) in response to an input clock signal (CLKIN) and to generate a first output signal (S1); a flip-flop (120) configured to receive the input clock signal (CLKIN) and a second waveform signal (PH1) and to generate a second output signal (S2); and an OR circuit (130) configured to perform an OR operation on the first output signal (S1) and the second output signal (S2) to generate an output clock signal (CLKOUT) having a period N times that of a period of the input clock signal (CLKIN), where “N” is a positive real number, and wherein the first and second waveform signals (PH0, PH1) are an inverted version of the second output signal (S2).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Korean Patent Application No. 10-2015-0146933, filed on October 21, 2015. BACKGROUND

[0002] Certain embodiments of the inventive concept relate to clock generation circuits having an equalization function. Other embodiments of the inventive concept relate to semiconductor integrated circuit devices (IC devices), such as a system-on-chip (SoC), a memory device, or a processor, which include a clock generation circuit having an equalization function.

[0003] US 2006 / 0 230 302 A1 discloses a programmable clock equalizer that generates an output clock with minimal clock skew. This is achieved by a single series path coupling the input clock to the output clock. The programmable clock equalizer comprises: an output clock generator responsive to the input clock and control information to generate the equalized output clock; and a controller responsive to the input clock to generate the control information for controlling the frequency of the equalized output clock. The programmable clock equalizer can be used to implement a clock tree with various clock outputs for a system-on-chip integrated circuit.

[0004] Semiconductor ICs such as an SoC, a processor, or a memory device often require one or more clock signals. A clock divider can be used to divide the frequency of an input clock signal to generate a clock signal with a required frequency.

[0005] Unfortunately, frequency division of a clock signal can introduce skew. Skew can be understood as the difference between a desired clock signal arrival time (e.g., a clock transition, a rising clock edge, a falling clock edge, etc.) and an actual clock signal arrival time. Clock dividers are often characterized by long latency periods and poor jitter characteristics. Consequently, an equalizer circuit is often required to improve jitter characteristics by eliminating or reducing clock signal skew. It is therefore typical to provide an equalizer circuit together with a clock divider. Unfortunately, the circuitry required to equalize both rising and falling edges of a clock signal currently requires many constituent elements (e.g., flip-flops) and is highly complex in its design and operation. SUMMARY

[0006] The invention is defined in the appended independent claims, and further developments of the invention are set out in the dependent claims.

[0007] According to some embodiments, a clock generation circuit is provided, comprising: a clock gating circuit configured to receive a first waveform signal in response to an input clock signal and to generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period N times that of a period of the input clock signal, where "N" is a positive real number.

[0008] According to some embodiments, a semiconductor integrated circuit device is provided, comprising: a clock generation circuit configured to receive an input clock signal and to generate an output clock signal having a period of N times a period of the input clock signal and having a reduced skew of at least one of a rising edge and a falling edge, where N is a positive real number, and a logic circuit configured to receive the output clock signal, wherein the clock generation circuit comprises: a clock gating circuit configured to receive a first waveform signal in response to the input clock signal and to generate a first output signal, a first flip-flop configured to delay a second waveform signal in response to the input clock signal,to generate a second output signal and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate the output clock signal.,

[0009] According to some embodiments, a clock generation circuit is provided, comprising: a waveform generator configured to generate a first waveform signal and a second waveform signal having a period that is N times a period of an input clock signal, where N is a positive real number, a clock gating circuit configured to gate the input clock signal based on the first waveform signal to generate a first output signal, a flip-flop configured to receive the input clock signal and the second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal.

[0010] According to some embodiments, a clock generation circuit is provided, comprising: a waveform generator configured to generate a first waveform signal and a second waveform signal from an input clock signal, a buffer configured to receive the input clock signal and generate a buffered input clock signal, a clock gating circuit configured to receive the first waveform signal, to gate the first waveform signal in response to the buffered input clock signal, and to generate a first output signal, a flip-flop configured to receive the buffered input clock signal and the second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal.to generate an output clock signal., BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The Fig. 1 to 5 do not show an explicit embodiment with all features of the invention, but rather partial aspects of the inventive concept.

[0012] The above and other features and advantages of the inventive concept will become more apparent by describing exemplary embodiments thereof in detail with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a clock generation circuit according to some embodiments of the inventive concept; Fig. 2 is a circuit diagram of a clock gating circuit used in Fig. 1 according to some embodiments of the inventive concept. Fig. 3 is a circuit diagram of a clock generation circuit according to other embodiments of the inventive concept; Fig. 4 is a waveform timing diagram of signals in the clock generation circuit shown in Fig. 3 are illustrated according to some embodiments of the inventive concept; Fig. 5 is a waveform timing diagram of signals in the clock generation circuit shown in Fig. 3 is illustrated according to other embodiments of the inventive concept; Fig. 6 is a circuit diagram of a clock generation circuit according to still other embodiments of the inventive concept; Fig. 7 is a waveform timing diagram of signals in the clock generation circuit shown in Fig. 6 is illustrated according to some embodiments of the inventive concept; Fig. Figure 8 is a circuit diagram of a modification of the clock generation circuit shown in Fig. 6 is illustrated; Fig. 9 is a waveform timing diagram of signals in the clock generation circuit shown in Fig. 8 is illustrated according to some embodiments of the inventive concept; Fig. 10 is a block diagram of a semiconductor integrated circuit device (SIC device) having a clock generation circuit according to some embodiments of the inventive concept; Fig. 11 is a block diagram of a semiconductor integrated circuit device having a clock generation circuit according to other embodiments of the inventive concept; and Fig. 12 is a block diagram of an electronic system 400 including the SoC according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0013] The inventive concept will now be described in some additional detail with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be considered limited to only the illustrated embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals and designations are used throughout the description and drawings to refer to the same or similar elements.

[0014] Figure 1 is a circuit diagram illustrating a clock generation circuit 100A according to some embodiments of the inventive concept. Fig. 2 is a circuit diagram further showing an example of the clock gating circuit 110 of the Fig. 1. Referring to the Fig. 1 and Fig. 2, the clock generation circuit 100A includes the clock gating circuit 110, a flip-flop 120, and an OR circuit 130.

[0015] The clock gating circuit 110 receives an input clock signal CLKIN and a first waveform signal PH0 and generates a first output signal S1. Here, the clock gating circuit 110 may output the input clock signal CLKIN as the first output signal S1 for only a specific period based on the first waveform signal PH0, so that the input clock signal CLKIN is "masked by the first waveform signal PH0" to generate the first output signal S1.

[0016] For example, the clock gating circuit 110 may latch the first waveform signal PH0 and perform an AND operation on the first waveform signal PH0 and the input clock signal CLKIN during a "low period" in which the input clock signal CLKIN has a first logic level (e.g., a "low" level), and may also perform an AND operation on the previously latched first waveform signal PH0 and the input clock signal CLKIN during a "high period" in which the input clock signal CLKIN has a second logic level (e.g., a "high" level) to generate the first output signal S1. As shown in Fig. 2, the clock gating circuit 110 may be implemented in one example using a latch 112 and an AND gate 114.

[0017] Here, the latch 112 latches the first waveform signal PH0 in response to the input clock signal CLKIN to output a latch signal LS. The input clock signal CLKIN is supplied to a clock terminal of the latch 112, and the first waveform signal PH0 is supplied to an input terminal EN. For example, the latch 112 may pass and output the first waveform signal PH0 as the latch signal LS during the low period of the input clock signal CLKIN, and may not pass the first waveform signal PH0 as the latch signal LS to maintain the preceding latch signal LS during the high period of the input clock signal CLKIN. In other words, the latch 112 may pass a signal supplied to the input terminal EN to an output terminal Q in accordance with a certain logic level of the input clock signal CLKIN.

[0018] In this regard, those skilled in the art will understand that the designation of a particular logic level as "first" or "second"; "low" or "high" is arbitrary and may vary with the design. Thus, the selected use of low / high or first / second with respect to signal levels could be reversed at any time, as dictated by different design objectives.

[0019] The AND gate 114 performs an AND operation on the latch signal LS output from the latch 112 and the input clock signal CLKIN. Consequently, the clock gating circuit 110, which is shown in Fig. 2, latch the input clock signal CLKIN based on (or in response to) the latch signal LS obtained by latching the first waveform signal PH0 in response to the input clock signal CLKIN.

[0020] In the illustrated embodiment of the Fig. 1, a buffer 140 is used to generate a buffered version of the input clock signal. The buffer 140 is individually Fig. 1, but may be included within clock gating circuit 110 or flip-flop 120. Those skilled in the art will recognize that clock gating circuit 110 may be variously implemented in other embodiments of the inventive concept using other, additional, or differently arranged elements. For example, a flip-flop may be used instead of latch 112.

[0021] Flip-flop 120 receives the input clock signal CLKIN (or a buffered version of the input clock signal CLKIN) and a second waveform signal PH1 and generates a second output signal S2. Flip-flop 120 may be, but is not limited to, a DQ flip-flop. The second waveform signal PH1 may be identical to or different from the first waveform signal PH0.

[0022] The OR circuit 130 performs an OR operation on the first output signal S1 and the second output signal S2 to generate an output clock signal CLKOUT having a period N times the period of the input clock signal CLKIN, where "N" is a positive real number. Among the rising and falling edges of the output clock signal CLKOUT, one edge (e.g., the rising edge) may not have an offset, while the other edge (e.g., the falling edge) has an offset. In other words, the clock generation circuit 100A can achieve a single-edge equalization function, eliminating or significantly reducing distortion or offset from either the rising edge or the falling edge of the output clock signal CLKOUT.Accordingly, the clock generation circuit 100A eliminates an offset of at least one of the rising and falling edges of a clock signal obtained by dividing the frequency of the input clock signal CLKIN by N to generate the output clock signal CLKOUT.

[0023] Fig. 3 is a circuit diagram illustrating a clock generation circuit 100B according to other embodiments of the inventive concept. Referring to the Fig. 1 and Fig. 3, the clock generation circuit 100B further comprises a waveform generator 150 compared to the clock generation circuit 100A, which in Fig. 1 is illustrated.

[0024] Waveform generator 150 can be used to generate the first and second waveform signals PH0 and PH1 as outputs in response to the input clock signal CLKIN applied as an input. Waveform generator 150 can divide the frequency of the input clock signal CLKIN by N to generate the first and second waveform signals PH0 and PH1, which, for example, have periods N times longer than the period of the input clock signal CLKIN.

[0025] Fig. 4 is a waveform timing diagram further illustrating various signal relationships used in the clock generation circuit 100B of the Fig. 3. An exemplary operation of the clock generation circuit 100B will be described with reference to Fig. 3 and Fig. 4, where "N" is assumed to be 4 and the first and second waveform signals PH0 and PH1 are assumed to have the same waveform. Accordingly, the first and second waveform signals PH0 and PH1 have a period approximately four times (4×) that of the period of the input clock signal CLKIN. Furthermore, it is assumed that there is an offset in the rising and falling edges of the first and second waveform signals PH0 and PH1.

[0026] The clock gating circuit 110 gates the input clock signal CLKIN based on the first waveform signal PH0 to generate the first output signal S1. The latch 112 of the clock gating circuit 110 passes and outputs the first waveform signal PH0 as the latch signal LS while the input clock signal CLKIN is low (i.e., at the first logic level), and does not pass the first waveform signal PH0 as the latch signal LS, but instead maintains the previous latch signal LS while the input clock signal CLKIN is high (i.e., at the second logic level). Accordingly, the latch 112 can output a high input clock signal CLKIN as the latch signal LS while the input clock signal CLKIN is low, and can maintain the high input clock signal CLKIN that was previously latched while the input clock signal CLKIN is high.

[0027] The AND gate 114 of the clock gating circuit 110 performs an AND operation on the latch signal LS and the input clock signal CLKIN to output the first output signal S1. Accordingly, while the input clock signal CLKIN is low, the AND gate 114 can perform an AND operation on the high latch signal LS and the low input clock signal CLKIN to output a low first output signal S1. While the input clock signal CLKIN is high, the AND gate 114 can perform an AND operation on the high latch signal LS and the high input clock signal CLKIN to output the high first output signal S1.

[0028] Consequently, as in Fig. As shown in Figure 4, the first output signal S1 has a waveform similar to that of the input clock signal CLKIN during two periods (e.g., time T1 to time T3) of the input clock signal CLKIN and is then maintained low for the next two periods (e.g., time T3 to time T5) of the input clock signal CLKIN. However, unlike the first waveform signal PH0, the first output signal S1 has a de-skew or de-skew waveform.

[0029] The flip-flop 120 receives the second waveform signal PH1 and generates the second output signal S2 in response to the input clock signal CLKIN. Accordingly, the flip-flop 120 can delay the second waveform signal PH1 by the period of the input clock signal CLKIN to output the second output signal S2. Accordingly, as shown in Fig. 4, the second output signal S2 lags behind the second waveform signal PH1 by the period of the input clock signal CLKIN and has a similar waveform to the second waveform signal PH1.

[0030] The OR circuit 130 performs an OR operation on the first output signal S1 and the second output signal S2 to generate the output clock signal CLKOUT. Accordingly, the output clock signal CLKOUT can transition from low to high in response to a rising edge of the first output signal S1, and can transition from high to low in response to a falling edge of the second output signal S2. Accordingly, the output clock signal CLKOUT has a waveform similar to the first and second waveform signals PH0 and PH1, but a period four times (4×) longer than the period of the input clock signal CLKIN. The output clock signal CLKOUT has a waveform in which a rising edge skew is eliminated or reduced compared to the first and second waveform signals PH0 and PH1.

[0031] When N is an even number, the clock generation circuit 100B generates the output clock signal CLKOUT, which has a period N times longer than the period of the input clock signal CLKIN and which has eliminated or reduced the skew of a rising edge compared to the input clock signal CLKIN. (See, for example, the embodiment shown in Fig. 4.) However, the falling edge skew may be eliminated or reduced in the output clock signal CLKOUT in other embodiments of the inventive concept. For example, if the clock generation circuit 100B is modified so that the clock gating circuit 110 responds to a high clock signal, the falling edge skew in the output clock signal CLKOUT is eliminated or reduced.

[0032] In the above-described embodiments, the output clock signal CLKOUT is obtained in which the rising edge skew is eliminated or reduced. Consequently, the output clock signal CLKOUT exhibits improved jitter characteristics.

[0033] According to some embodiments of the inventive concept, a clock generation circuit that equalizes either a rising edge or a falling edge requires a relatively small number of elements and thus has a lower complexity compared to conventional clock generation circuits. In other embodiments of the inventive concept, a clock generation circuit can equalize both rising and falling edges.

[0034] Fig. 5 is another waveform timing diagram further illustrating various signal relationships used in the clock generation circuit 100B of the Fig. 3. The operation of the clock generation circuit 100B will be described with reference to Fig. 3 and Fig. 5. In the embodiment shown in Fig. 5, it is assumed that N is 3 and the first and second waveform signals PH0 and PH1 have different waveforms.

[0035] The waveform generator 150 can be used to generate a first waveform signal PH0 that is high for two consecutive periods (e.g., time T0 to time T2) and then low for a single subsequent period (e.g., time T2 to time T3), thereby generating a first waveform signal PH0 over a period that is three times (3×) the period of the input clock signal CLKIN. The waveform generator 150 can also be used to generate the second waveform signal PH1 that is high for a single period (e.g., time T0 to time T1) and low for the following two consecutive periods (e.g., time T2 to time T4), thereby generating a second waveform signal PH1 that has a period that is three times (3×) the period of the input clock signal CLKIN. In the foregoing, each individual "period" (e.g., time T1 to time t2, etc.)) is defined by the period of the input clock CLKIN.

[0036] Consequently, in the illustrated example, the Fig. 5, while each of the first and second waveform signals PH0 and PH1 has a period approximately three times (3×) the period of the input clock signal CLKIN, each of the first and second waveform signals PH0 and PH1 has a different duty cycle. And, as before, there is an offset in the edges of the first and second waveform signals PH0 and PH1.

[0037] The clock gating circuit 110 gates the input clock signal CLKIN based on the first waveform signal PH0 to generate the first output signal S1. The latch 112 of the clock gating circuit 110 passes and outputs the first waveform signal PH0 as the latch signal LS while the input clock signal CLKIN is low, and does not pass the first waveform signal PH0 as the latch signal LS, but maintains the previously latched signal LS while the input clock signal CLKIN is high. Accordingly, the latch 112 will output the high input clock signal CLKIN as the latch signal LS while the input clock signal CLKIN is low, but will maintain the high input clock signal CLKIN, which was previously latched, while the input clock signal CLKIN is high.

[0038] The AND gate 114 of the clock gating circuit 110 performs an AND operation on the latch signal LS and the input clock signal CLKIN to output the first output signal S1. Accordingly, while the input clock signal CLKIN is low, the AND gate 114 can perform an AND operation on the high latch signal LS and the low input clock signal CLKIN to output the low first output signal S1. While the input clock signal CLKIN is high, the AND gate 114 can perform an AND operation on the high latch signal LS and the high input clock signal CLKIN to output the high first output signal S1.

[0039] Consequently, as in Fig. As shown in Figure 5, the first output signal S1 has a similar waveform to the input clock signal CLKIN during two periods (e.g., time T1 to time T3) of the input clock signal CLKIN and is maintained low during the next period (e.g., time T3 to time T4). However, unlike the first waveform signal PH0, the first output signal S1 has a de-skew or de-skew waveform.

[0040] The flip-flop 120 receives the second waveform signal PH1 and generates the second output signal S2 in response to the input clock signal CLKIN. Accordingly, the flip-flop 120 can delay the second waveform signal PH1 by the period of the input clock signal CLKIN to output the second output signal S2. Accordingly, as shown in Fig. 5, the second output signal S2 lags behind the second waveform signal PH1 by the period of the input clock signal CLKIN and has a similar waveform to the second waveform signal PH1.

[0041] The OR circuit 130 performs an OR operation on the first output signal S1 and the second output signal S2 to generate the output clock signal CLKOUT. Accordingly, the output clock signal CLKOUT can transition from low to high in response to a rising edge of the first output signal S1 and can transition from high to low in response to a falling edge of the first output signal S1. Accordingly, the output clock signal CLKOUT has a period three times (3×) longer than the period of the input clock signal CLKIN. The output clock signal CLKOUT has a waveform in which a skew of both a rising edge and a falling edge is eliminated or reduced.

[0042] When N is an odd number, the clock generation circuit 100B generates the output clock signal CLKOUT, which has a period N times longer than the period of the input clock signal CLKIN and which has eliminated or reduced the skew of both the rising and falling edges compared to the input clock signal CLKIN (see, for example, the embodiment shown in Fig. 5 is illustrated).

[0043] Fig. 6 is a circuit diagram illustrating a clock generation circuit 100C according to still other embodiments of the inventive concept. Since the clock generation circuit 100C is similar to the clock generation circuit 100A shown in Fig. 1, the description will focus on differences between the clock generation circuits 100A and 100C to avoid redundancy.

[0044] Referring to Fig. 6, a positive output signal Q of the flip-flop 120 is provided as the second output signal S2, and a negative output signal / Q of the flip-flop 120 is provided as the first and second waveform signals PH0 and PH1. In other words, the negative output signal / Q of the flip-flop 120 is provided as the first and second waveform signals PH0 and PH1 in the embodiment shown in Fig. 6, thereby eliminating the need for a separate curve generator such as the one shown in Fig. 3 is eliminated.

[0045] The clock generation circuit 100C, which is Fig. 6, divides the frequency of the input clock signal CLKIN by two (2) and removes an offset to generate the output clock signal CLKOUT. The clock generation circuit 100C uses a minimal number of constituent flip-flops. Since the clock generation circuit 100C uses the negative output signal / Q of the flip-flop 120 as the first and second waveform signals PH0 and PH1, the clock generation circuit 100C requires the waveform generator 150 included in the clock generation circuit 100B shown in Fig. 3 is not.

[0046] Fig. Figure 7 is yet another waveform timing diagram further illustrating various signal relationships used in the clock generation circuit 100C of the Fig. 6 may exist. Accordingly, the operation of the clock generation circuit 100C will be described in some additional detail with reference to the Fig. 6 and Fig. 7 are described.

[0047] During a reset period in which a reset signal RESET is low (i.e., until the reset signal RESET transitions from low to high at time T2), the clock generation circuit 100C passes and outputs the input clock signal CLKIN as the output clock signal CLKOUT. Accordingly, the output clock signal CLKOUT is the same as the input clock signal CLKIN during the reset period.

[0048] For example, flip-flop 120 outputs a low positive output signal Q and a high negative output signal / Q during the reset period. Accordingly, the first and second waveform signals PH0 and PH1 are high. As a result, clock gating circuit 110 outputs the first output signal S1, which has the same waveform as the input clock signal CLKIN during the reset period. The second output signal S2, which is the positive output signal Q of flip-flop 120, is low. Accordingly, the output signal CLKOUT has substantially the same waveform as the input clock signal CLKIN during the reset period.

[0049] When the reset signal RESET transitions from low to high (or triggers), the flip-flop 120 outputs a D input signal (the same as the negative output signal / Q) as the positive output signal Q in response to the input clock signal CLKIN. Consequently, the positive output signal Q (i.e., the second output signal S2) has a level that changes with each period of the input clock signal CLKIN, and thus has a period that is twice (2×) the period of the input clock signal CLKIN, as shown in Fig. 7 is shown.

[0050] The first and second waveform signals PH0 and PH1 are the negative output signal / Q and therefore have a phase difference (approximately 180 degrees) from the positive output signal Q. Consequently, as shown in Fig. 7, the first and second waveform signals PH0 and PH1 also have a period which is approximately twice (2×) longer than the period of the input clock signal CLKIN, but they may have an offset.

[0051] The clock gating circuit 110 gates the first waveform signal PH0 in response to the input clock signal CLKIN to generate the first output signal S1. The structure and operation of the clock gating circuit 110 may be the same as those described with reference to FIG. Fig. 1 and Fig. 2 described above.

[0052] The first output signal S1 has a similar waveform to the input clock signal CLKIN during one period of the input clock signal CLKIN (for example, time T2 to time T3 or time T4 to time T5) and is maintained low during the next one period of the input clock signal CLKIN (for example, time T3 to time T4 or time T5 to time T6), as shown in Fig. 7. However, unlike the first waveform signal PH0, the first output signal S1 has a de-skew or de-skew waveform.

[0053] The OR circuit 130 performs an OR operation on the first output signal S1 and the second output signal S2 to generate the output clock signal CLKOUT. Accordingly, the output clock signal CLKOUT can transition from low to high in response to a rising edge of the first output signal S1, and can transition from high to low in response to a falling edge of the second output signal S2. Accordingly, the output clock signal CLKOUT has a period that is twice (2×) longer than the period of the input clock signal CLKIN, and a rising edge skew can be eliminated or reduced, but a falling edge skew cannot be eliminated or reduced in the output clock signal CLKOUT.

[0054] Fig. Fig. 8 is a circuit diagram illustrating a clock generating circuit 100D, which is a modification of the clock generating circuit 100C shown in Fig. 6 is illustrated. Fig. 9 is a waveform timing diagram further illustrating various signal relationships used in the clock generation circuit 100B of the Fig. 8 may exist. The operation of the clock generation circuit 100D will be described with reference to the Fig. 8 and Fig. 9 are described.

[0055] The clock generation circuit 100D of the Fig. 8 has an additional clock stop feature compared to the clock generation circuit 100C of Fig. 6. Since the clock generation circuit 100D, which is Fig. 8 is similar to the clock generation circuit 100C shown in Fig. 6, the description will focus on the differences between the clock generation circuits 100C and 100D to avoid redundancy. Compared with the clock generation circuit 100C shown in Fig. 6, the clock generation circuit 100D, which is shown in Fig. 8, further comprises a flip-flop 211, an inverter 213 and an AND element 215.

[0056] Flip-flop 211 receives a clock stop request signal CLKSTOP_REQ and outputs a clock stop response signal CLKSTOP_ACK. With this configuration, flip-flop 211 delays the clock stop request signal CLKSTOP_REQ by one clock cycle to output the clock stop response signal CLKSTOP_ACK. The clock stop request signal CLKSTOP_REQ can be received from a processor or a host (not shown) outside the clock generation circuit 100D. The clock stop response signal CLKSTOP_ACK is a response to the clock stop request signal CLKSTOP_REQ and can be communicated to (or returned to) the processor or host.

[0057] Inverter 213 inverts the clock stop request signal CLKSTOP_REQ. AND element 215 performs an AND operation on an output signal of inverter 213 and the negative output signal / Q of flip-flop 120 to output the first and second waveform signals PH0 and PH1. In other words, AND element 215 is a logic operation element that selectively generates the first and second waveform signals PH0 and PH1 based on the clock stop request signal CLKSTOP_REQ.

[0058] Accordingly, when the clock stop request signal CLKSTOP_REQ transitions to high, the first and second waveform signals PH0 and PH1 transition to low, and thus the output clock signal CLKOUT is not generated, as shown in Fig. 9. When the clock stop request signal CLKSTOP_REQ transitions high, the output signal of inverter 213 transitions low regardless of the negative output signal / Q of flip-flop 120. Accordingly, both the first and second waveform signals PH0 and PH1 transition low. Consequently, the first and second output signals S1 and S2 also transition low. As a result, the output clock signal CLKOUT is not generated.

[0059] However, when the clock stop request signal CLKSTOP REQ transitions from high to low, the output signal of inverter 213 allows the negative output signal / Q of flip-flop 120 to be output to the first and second output signals S1 and S2. In other words, the negative output signal / Q of flip-flop 120 is provided as the first and second waveform signals PH0 and PH1. As a result, the output clock signal CLKOUT is generated.

[0060] Fig. 10 is a block diagram of a semiconductor integrated circuit (IC) device 1A including a clock generation circuit 100 according to one or more embodiments of the inventive concept. Referring to Fig. 1 to 10, the semiconductor IC device 1A includes the clock generation circuit 100 and a logic circuit 30. The clock generation circuit 100 may be the clock generation circuit 100A, 100B, 100C and / or 100D shown in Fig. 1, Fig. 3, Fig. 6 or Fig. 8. Clock generation circuit 100 may receive input clock signal CLKIN and may output output clock signal CLKOUT. Logic circuit 30 may receive output clock signal CLKOUT from clock generation circuit 100 and may operate based on output clock signal CLKOUT.

[0061] Fig. 11 is a block diagram of a semiconductor IC device 1B including the clock generation circuit 100 according to one or more embodiments of the inventive concept. Referring to Fig. 11, the semiconductor IC device 1B may be implemented as a handheld device such as a mobile phone, a smartphone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, or an e-book. The semiconductor IC device 1B may include a system-on-chip (SoC) 300, a memory device 390, and a display device 395.

[0062] The SoC 300 may include a central processing unit (CPU) 310, a read-only memory (ROM) 320, a random access memory (RAM) 330, a graphics processing unit (GPU) 340, the clock generation circuit 100, a display controller 350, a memory interface 370, and a bus 380. The SoC 300 may also include a power management unit (PMU) 360. The SoC 300 may also include other elements. The PMU 360 is within the SoC 360 in the embodiments described in Fig. 11, however, the PMU 360 may be implemented outside of the SoC 300 in other embodiments.

[0063] The CPU 310, which may be referred to as a processor, may process or execute programs and / or data stored in the storage device 390. For example, the CPU 310 may process or execute the programs and / or data in response to a clock signal output from a clock signal generator (not shown). The CPU 310 may be implemented as a multi-core processor. The multi-core processor is a single computing component with two or more independent actual processors (referred to herein as cores). Each of the processors reads and executes program instructions. The multi-core processor may operate a plurality of accelerators at a time, and thus, a data processing system including the multi-core processor may perform multiple acceleration.

[0064] Programs and / or data stored in ROM 320, RAM 330, and storage device 390 can be loaded into the memory in CPU 310 when necessary. ROM 320 can permanently store programs and / or data. ROM 320 can be implemented as an erasable programmable ROM (EPROM) or an electrically erasable programmable ROM (EEPROM).

[0065] RAM 330 can temporarily store programs, data, or instructions. The programs and / or data stored in storage device 390 can be temporarily stored in RAM 330 under the control of CPU 310 or boot code stored in ROM 320. RAM 330 can be implemented as dynamic RAM (DRAM) or static RAM (SRAM).

[0066] The GPU 340 may process data read from the storage device 390 through the memory interface 370 into a signal suitable for display.

[0067] The clock generation circuit 100 may be the clock generation circuit 100A, 100B, 100C or 100D, which in Fig. 1, Fig. 3, Fig. 6 or Fig. 8. The clock generation circuit 100 may provide a clock signal to other modules, i.e., the CPU 310, the ROM 320, the RAM 330, the GPU 340, the display controller 350, and the memory interface 370 in the SoC 300.

[0068] Memory interface 370 is a block for coupling to memory device 390. Memory interface 370 controls the overall operation of memory device 390 and controls the exchange of data between a host and memory device 390. For example, memory interface 370 writes data to memory device 390 or reads data from memory device 390 upon request from the host. Here, the host can be a processing unit such as CPU 310, GPU 340, or display controller 350.

[0069] The storage device 390 is a memory for storing data and may store an operating system (OS) and various types of programs and data. The storage device 390 may be, but is not limited to, a DRAM. For example, the storage device 390 may be a non-volatile memory such as a flash memory, a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FeRAM). In other embodiments, the storage device 390 may be an embedded memory provided within the SoC 300. The elements 310, 320, 330, 340, 350, 360 and 100 can communicate with each other through the bus 380.

[0070] The display device 395 can display image signals output from the display controller 350. The display device 395 can be implemented as a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic LED (OLED), or an active matrix OLED (AMOLED). The display controller 350 controls the operation of the display device 395.

[0071] Fig. 12 is a block diagram of an electronic system 400 including the SoC according to some embodiments of the inventive concept. Referring to Fig. 12, the electronic system 400 may be implemented as a PC, a data server, a laptop computer, or a portable device. The portable device may be a mobile phone, a smartphone, a tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a portable navigation device (PND), a handheld game console, or an e-book device.

[0072] The electronic system 400 includes the SoC 300, a power source 410, a storage device 420, a memory 430, I / O ports 440, an expansion card 450, a network device 460, and a display 470. The electronic system 400 may further include a camera module 480.

[0073] The SoC 300 corresponds to the SoC 300, which is Fig. 11. The SoC 300 may control the operation of at least one of the elements 410 to 480. The power source 410 may supply an operating voltage to at least one of the elements 300 and 420 to 480. The storage device 420 may be implemented by a hard disk drive (HDD) or a solid state drive (SDD).

[0074] The memory 430 may be implemented by a volatile or non-volatile memory. The memory 430 may be similar to the memory 390, which is Fig. 11. A memory interface 370 (shown in Fig.11), which controls a data access operation, such as a read operation, a write operation (or a program operation), or an erase operation on the memory 430, may be integrated or embedded in the SoC 300. Alternatively, the memory interface may be provided between the SoC 300 and the memory 430.

[0075] The I / O ports 440 are ports that receive data transmitted to the electronic system 400 or transmit data from the electronic system 400 to an external device. For example, the I / O ports 440 may include a port that connects to a pointing device such as a computer mouse, a port that connects to a printer, and a port that connects to a USB drive.

[0076] The expansion card 450 can be implemented as a Secure Digital (SD) card or a multimedia card (MMC). The expansion card 450 can be a Subscriber Identity Module (SIM) card or a Universal SIM (USIM) card.

[0077] Network device 460 enables electronic system 400 to be connected to a wired or wireless network. Display 470 displays data output from storage device 420, memory 430, I / O ports 440, expansion card 450, or network device 460.

[0078] The camera module 480 converts optical images into electrical images. Accordingly, the electrical images output by the camera module 480 can be stored in the memory module 320, the memory 430, or the expansion card 450. Likewise, the electrical images output by the camera module 480 can be displayed by the display 470.

[0079] As described above, according to some embodiments of the inventive concept, a clock generation circuit reduces the skew of at least one of the rising and falling edges of a clock signal, thereby improving the jitter characteristics of the clock signal. Additionally, the clock generation circuit requires a relatively small number of constituent elements and low complexity.

[0080] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the inventive concept as defined by the following claims.

Claims

[1] Clock generation circuit (100, 100C, 100D) comprising: a clock gating circuit (110) configured to receive a first waveform signal (PH0) in response to an input clock signal (CLKIN) and to generate a first output signal (S1); a flip-flop (120) configured to receive the input clock signal (CLKIN) and a second waveform signal (PH1) and to generate a second output signal (S2); and an OR circuit (130) configured to perform an OR operation on the first output signal (S1) and the second output signal (S2) to generate an output clock signal (CLKOUT) having a period N times that of a period of the input clock signal (CLKIN), where “N” is a positive real number, and wherein the first and second waveform signals (PH0, PH1) are an inverted version of the second output signal (S2). [2] Clock generation circuit (100, 100C, 100D) according to claim 1, wherein the clock gating circuit (110) comprises: a latch (112) configured to latch the first waveform signal (PH0) in response to the input clock signal (CLKIN); and an AND element (114) configured to perform an AND operation on an output signal of the latch (112) and the input clock signal (CLKIN). [3] Clock generating circuit (100, 100C, 100D) according to claim 1, wherein the flip-flop (120) comprises: a clock terminal configured to receive the input clock signal (CLKIN); an input terminal (D) configured to receive the second waveform signal (PH1); a positive output terminal (Q) configured to output the second output signal (S2); and a negative output terminal ( / Q) configured to output an inverted version of the second output signal (S2), and wherein the output signal of the negative output signal ( / Q) is provided as the first and second waveform signals (PH0, PH1). [4] The clock generating circuit (100, 100C, 100D) according to claim 1, wherein the clock generating circuit (100, 100C, 100D) passes and outputs the input clock signal (CLKIN) as the output clock signal (CLKOUT) in response to a reset signal during a reset period. [5] Clock generation circuit (100, 100D) comprising: a clock gating circuit (110) configured to receive a first waveform signal (PH0) in response to an input clock signal (CLKIN) and to generate a first output signal (S1); a first flip-flop (120) configured to receive the input clock signal (CLKIN) and a second waveform signal (PH1) and to generate a second output signal (S2); and an OR circuit (130) configured to perform an OR operation on the first output signal (S1) and the second output signal (S2) to generate an output clock signal (CLKOUT) having a period N times that of a period of the input clock signal (CLKIN), where "N" is a positive real number; a second flip-flop (211) configured to delay a clock stop request signal (CLKSTOP_REQ) to generate a clock stop response signal (CLKSTOP_ACK); and a logic operation element (215) configured to generate the first and second waveform signals (PH0, PH1) based on the clock stop request signal (CLKSTOP_REQ). [6] A semiconductor integrated circuit device (1A) comprising: a clock generation circuit (100, 100C, 100D) configured to receive an input clock signal (CLKIN) and to generate an output clock signal (CLKOUT) having a period of N times that of a period of the input clock signal (CLKIN) and having a skew of at least one of a rising edge and a falling edge reduced, where N is a positive real number; and a logic circuit (30) configured to receive the output clock signal (CLKOUT), wherein the clock generation circuit (100, 100C, 100D) comprises: a clock gating circuit (110) configured to receive a first waveform signal (PH0) in response to the input clock signal (CLKIN) and to generate a first output signal (S1); a first flip-flop (120) configured to delay a second waveform signal (PH1) in response to the input clock signal (CLKIN) to generate a second output signal (S2); and an OR circuit (130) configured to perform an OR operation on the first output signal (S1) and the second output signal (S2) to generate the output clock signal (CLKOUT), wherein the first flip-flop (120) comprises: a positive output terminal (Q) configured to output the second output signal (S2); and a negative output terminal ( / Q) configured to output an inverted signal of the second output signal (S2), and wherein the first and second waveform signals (PH0, PH1) are based on a signal of the negative output terminal ( / Q) of the first flip-flop (120). [7] The semiconductor integrated circuit device (1A) according to claim 6, wherein the clock generation circuit (100, 100C, 100D) further comprises: a second flip-flop (211) configured to delay a clock stop request signal (CLKSTOP_REQ) to generate a clock stop response signal (CLKSTOP_ACK); and a logic operation element (215) configured to perform an AND operation on an inverted signal of the clock stop request signal (CLKSTOP_REQ) and the signal of the negative output terminal ( / Q) to generate the first and second waveform signals (PH0, PH1).

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