ELECTRONIC CONTROL UNIT

Abstract

Electronic control unit (10) comprising: a multi-core microcomputer (100) equipped with a plurality of cores (C0, C1, C2), each core performing a task in synchronization with a phase of a rotation angle; a first storage unit (31) that stores a kernel number that identifies an output execution kernel that performs a task; and a second memory unit (132) that stores a switching phase, which specifies a phase when the task execution core is switched to another core, wherein: The task execution kernel is switched to another kernel based on the kernel number stored in the first memory unit and the switching phase stored in the second memory unit.

Description

[0001] The invention relates to an electronic control unit including a multi-core microcomputer equipped with a plurality of cores.

[0002] As an electronic control unit provided in a vehicle, an electronic control unit equipped with a multi-core microcomputer with a plurality of cores has been put into practical use. The multi-core microcomputer performs distributed processing of a variety of tasks executed in the control of the plurality of cores. Since the processing load on each of the cores is reduced, complex processing can be executed at a relatively high speed.

[0003] The generic document US 2010 / 00 205 602 A1 discloses a mechanism for scheduling thread execution for fair resource allocation in a multi-threaded and / or multi-core processing system. A thread scheduling mechanism is provided that flexibly enforces performance isolation of multiple threads to mitigate the effects of anti-cooperative execution behavior with respect to a shared resource, such as cache or pipeline hoarding, while leveraging the hardware capabilities of simultaneous multi-threaded (SMT) or multi-core processors.For a plurality of threads running on at least two processors in at least one functional processor group, the occurrence of a rescheduling condition indicating anti-cooperative execution behavior is detected and, if present, at least one of the threads is rescheduled such that the first and second threads no longer execute in the same functional processor group at the same time.

[0004] In context, document DE 10 2016 219 403 A1 relates to parallel processing, a parallelization tool, and a vehicle-mounted device. A parallelization method and a parallelization tool can generate a parallel program that can reduce a wait state, and a vehicle-mounted device can reduce the wait state. A computer generates a parallel program from a single program for a single-core microcomputer by executing an automatic parallelization tool. For each of the processings assigned to cores, the computer assigns a processing with a dependency to a dependent task and a processing that does not have the dependency to a non-dependent task.The computer assigns to the parallel program a function for placing the dependent task in a processing wait state and releasing the processing wait state of the non-dependent task when the tasks are placed in a synchronization wait state.

[0005] Document DE 10 2016 216 298 A1 also describes a parallelization method, a parallelization tool, and a vehicle-mounted device, wherein a parallelization method generates a parallelized program for a multi-core microcomputer from parallelizable processes in a single program for a single-core microcomputer. The processes comprise a preceding and a following process, each assigned to different cores.The parallelization method includes: inserting a save process having a completion state into the parallel program to maintain an execution order of the different cores when the preceding process is completed; inserting a wait process for waiting for the completion state to be saved and switching to execution of the following process when the completion state is saved into the parallel program to maintain the execution order; and inserting a re-save process for controlling the core that executed the save process to re-execute the save process when another process is executed after the preceding process is completed into the parallel program.

[0006] In the context of an electronic control unit of the aforementioned type, according to JP 2014-78078A, a core executing a task is dynamically switched to prevent the processing load on only some of the cores from becoming large.

[0007] For example, when a processing load on a first core assigned to execute a task is large and a processing load on a second core is small, a core executing the task is switched from the first core to the second core.

[0008] Among the tasks performed by the electronic control unit, there is one to be performed in synchronization with the phase of a rotation angle in a control target device (for example, a crank angle of an internal combustion engine). Examples of such a task include a fuel injection timing operation that is started every time the crank angle reaches a predetermined phase, and an ignition timing operation that is also started every time the crank angle reaches a predetermined phase.

[0009] In the above electronic control unit, a task to be executed when the phase of the rotation angle enters a certain phase may not be executed by any of the cores depending on the timing of switching the task execution core at the certain phase. Furthermore, a task to be executed when the phase of the rotation angle enters a certain phase may be duplicated by a plurality of cores.

[0010] Such phenomena are caused by a difference in the time of starting the processing of the task between the cores and the switching of the task execution core, which is performed in asynchronization with or asynchronously to the time of starting the processing of the task.

[0011] An object of the invention is to provide an electronic control unit that reliably prevents a phenomenon in which a task is not executed at a certain phase or a phenomenon in which a task is duplicated in association with switching of a core that executes the task.

[0012] This object is achieved by an electronic control unit having the features of claim 1. Advantageous developments of the invention are the subject of the appended subclaims.

[0013] According to one aspect of the invention, an electronic control unit includes a multi-core microcomputer equipped with a plurality of cores, each core executing a task in synchronization with a phase of a rotation angle; a first storage unit storing a core number indicating an output execution core executing a task; and a second storage unit storing a switching phase indicating a phase when the task execution core is switched to another core. The task execution core is switched to another core based on the core number stored in the first storage unit and the switching phase stored in the second storage unit.

[0014] In the electronic control unit having such a configuration, the task execution core is switched based on information (the core number and the switching phase) that is previously set and stored.

[0015] For example, a core executing a task before the switchover will be switched to a state of not executing the task at the time the phase becomes the switchover phase. A core executing a task after the switchover will also be switched to a state of executing the task at the time the phase becomes the switchover phase.

[0016] In this way, the timing (phases) of state switching can be designed to coincide with each other in all cores. As a result, it is possible to reliably prevent a phenomenon in which a task is not executed by any core at a given phase, or a phenomenon in which a task is executed twice by multiple cores.

[0017] The above electronic control unit reliably prevents a phenomenon in which a task is not executed at a certain stage or a phenomenon in which a task is duplicated in association with the switching of a core that executes the task.

[0018] The above and other objects, features, and advantages of the invention will become more apparent from the following detailed description with reference to the drawings, in which: Fig. 1 is a diagram schematically illustrating the configuration of an electronic control unit according to an embodiment of the invention; Fig. 2 is a timing diagram for describing the switching of a synchronous task execution core implemented in the electronic control unit of Fig. 1 is executed; Fig. 3 is a timing diagram for describing the switching of the synchronous task execution core used in the electronic control unit of Fig. 1 is executed; Fig. 4 is a flowchart showing the sequence of a process in the electronic control unit of Fig. 1 processing carried out; Fig. 5 is a diagram showing a processing load on a core in the electronic control unit of Fig. 1 represents; Fig. 6 a diagram showing processing loads on the cores in the electronic control unit of Fig. 1 represents; Fig. 7 a diagram showing processing loads on the cores in the electronic control unit of Fig. 1 represents; Fig. 8 is a flowchart showing the sequence of a process in the electronic control unit of Fig. 1 processing carried out; Fig. 9 is a diagram illustrating a core state transition when the synchronous task execution core is switched; Fig. 10 is a timing chart for describing switching of a synchronous task execution core executed in an electronic control unit according to a comparative example of the invention; Fig. 11 is a timing chart for describing switching of a synchronous task execution core executed in an electronic control unit according to a comparative example of the invention; Fig. 12 is a timing diagram for describing the switching of a synchronous task execution core executed in an electronic control unit according to a comparative example of the invention; and Fig. 13 is a timing chart for describing switching of a synchronous task execution core executed in an electronic control unit according to a comparative example of the invention.

[0019] An electronic control unit 10 according to the present embodiment is configured as a control unit (engine control ECU) for controlling the operation of an internal combustion engine 20 (engine) in a vehicle. For example, the electronic control unit 10 controls an opening / closing operation of an injector (not shown) in the internal combustion engine 20, that is, fuel injection, in accordance with a signal from a crank angle sensor (not shown) provided in the internal combustion engine 20.

[0020] In the control system, there is a task that is periodically processed by the electronic control unit 10 in synchronization with a change in the phase of a rotation angle (crank angle) of a crankshaft. For example, an operation for determining a fuel injection timing of the injector is processed every 30° increment in phase. In the following description, a task processed in synchronization with the phase of the rotation angle as described above is referred to as a "synchronous task."

[0021] Before describing the processing of the synchronous task performed by the electronic control unit 10, the configuration of the electronic control unit 10 will be described. The electronic control unit 10 is provided with an input circuit 11, an output circuit 12, and a microcomputer 100.

[0022] The input circuit 11 serves as a communication interface for receiving various sensor signals from the internal combustion engine 20 as a control target. The sensor signals include a signal transmitted from the crank angle sensor, that is, a signal indicating the phase of the crank angle.

[0023] The output circuit 12 serves as a communication interface for outputting a drive signal for switching the opening and closing of the injector to the internal combustion engine 20. The output circuit 12 may transmit a drive signal for operating a device other than the injector (for example, a spark plug) together with the above drive signal.

[0024] The microcomputer 100 forms a main part of the electronic control unit 10. The microcomputer 100 is provided with a CPU 110, a ROM 120, a RAM 130, and an input / output interface or I / O interface 140.

[0025] The CPU 110 is a central processing unit for performing an operation required for executing control, i.e., processing tasks. Therefore, the CPU 110 is a so-called multi-core processing unit. That is, the microcomputer 100 is configured as a multi-core microcomputer.

[0026] The ROM 120 is a read-only semiconductor memory. The ROM 120 stores, for example, a program executed by the CPU 110 and various maps or characteristic curves required for controlling the internal combustion engine 20.

[0027] The RAM 130 is a rewritable semiconductor memory. The RAM 130 temporarily stores, for example, an operation result for the controller. In the present embodiment, a first storage unit 131 and a second storage unit 132 are designated as information storage locations in the RAM 130. Information written to and stored in the first storage unit 131 and information written to and stored in the second storage unit 132 will be described below.

[0028] The I / O interface 140 is an interface part for communication between another ECU installed on the vehicle and the microcomputer 100. The communication via the I / O interface 140 is controlled by the CPU 110.

[0029] The configuration of the electronic control unit 10 itself as described above is the same as the configuration of a conventional electronic control unit, except that the first storage unit 131 and the second storage unit 132 are arranged in the RAM 130.

[0030] The electronic control unit 10 performs various tasks in addition to the synchronous task in controlling the operation of the internal combustion engine 20. In the present embodiment, a plurality of tasks, including the synchronous task, are distributedly processed by the core C1 and the core C2.

[0031] Core C0 performs centralized control over the operation of the entire CPU 110. More specifically, core C0 distributes tasks to be processed between core C1 and core C2. Centralized control can be performed by either core C1 or core C2 concurrently with the processing of tasks. In this case, a dedicated core for performing centralized control, such as core C0 in the present embodiments, is not required.

[0032] The tasks are distributed in such a way that a processing load on core C1 and a processing load on core C2 are substantially equal to each other. However, for example, if the speed of internal combustion engine 20 increases with a change in a driving state of the vehicle, increasing the execution frequency of some of the tasks may cause the processing load on either core C1 or core C2 to become significantly greater than the processing load on the other core.

[0033] Processing load imbalance is not desirable in view of efficient utilization of the processing capacity of the CPU 110. Therefore, the CPU 110 has a configuration in which a core executing the processing of the synchronous task is dynamically switched to prevent the processing load of only one of the cores from becoming excessive. For example, if core C1 is executing the processing of the synchronous task and the processing load on core C1 becomes excessive, a core executing the processing of the synchronous task is switched from core C1 to core C2.

[0034] In the following description, either the core C1 or the core C2 that executes the processing of the synchronous task is also referred to as a "synchronous task execution core." The processing executed by the core C0 to switch the synchronous task execution core is also referred to as "switching processing." As described below, in the present embodiment, a timing at which the core C0 performs the switching processing and a timing at which the synchronous task execution core is actually switched do not necessarily coincide with each other.

[0035] Before describing a specific embodiment of the switching processing performed in the present embodiment and an advantage thereof, an embodiment of the conventional switching processing will be described. Fig. 10 to 13 are timing charts each illustrating the flow of switching processing executed in an electronic control unit according to a comparative example (conventional example) of the invention. The hardware configuration of the conventional electronic control unit is the same as the hardware configuration of the Fig. 1 shown electronic control unit 10.

[0036] The following is a description with reference to Fig. 10. Fig. 10 illustrates an example in which switching processing is executed at a time t125 to switch a synchronous task execution core from the core C1 to the core C2.

[0037] A synchronous task is executed every 30° change in the information sent from the crank angle sensor of the internal combustion engine 20 to the electronic control unit, that is, in the phase of the crankshaft rotation angle (hereinafter referred to as a "sensor phase"). More specifically, the synchronous task is executed in the synchronous task execution core every 30° increase in the sensor phase to 60°, 90°, and 150°. The sensor phase returns to 0° when the sensor phase has increased to 720° and increases again by 30° as the operation of the internal combustion engine 20 progresses.

[0038] In the example of Fig. 10, core C1, which serves as the synchronous task execution core before time t125, starts processing the synchronous task at time t110 after the sensor phase becomes 90°. The time at which the sensor phase becomes 90° and the time at which processing of the synchronous task begins (time t110) do not necessarily coincide with each other. Such timing inconsistency is caused by a slight delay in the timing of starting processing of the synchronous task due to the processing of a task other than the synchronous task being performed by core C1. The time between when the sensor phase becomes 90° and when processing of the synchronous task begins varies depending on the processing load on the synchronous task execution core.

[0039] Then, core C0 executes the switching processing at time t125 after time t110. The synchronous task execution core is switched from core C1 to core C2. After that, core C1 enters a state of not executing the synchronous task even if the sensor phase increases by 30° (this state is hereinafter referred to as a "non-execution state"). On the other hand, core C2 enters a state of executing the synchronous task processing every 30° increase in the sensor phase (this state is hereinafter referred to as an "execution state").

[0040] When the sensor phase becomes 120° after time t125, core C1 is in the non-execution state. Therefore, core C1 does not start processing the synchronous task. Fig. Time t130 shown in Fig. 10 indicates a time at which the execution of a synchronous task corresponding to the 120° sensor phase is started if the core C1 is in the execution state.

[0041] Core C2 does not serve as the synchronous task execution core and is therefore in the non-execution state before time t125. Therefore, even if the sensor phase becomes 90°, core C2 does not start processing the synchronous task. Fig. Time t120 shown in Fig. 10 indicates a time at which the core C2 starts executing a synchronous task corresponding to the 90° sensor phase if the core C2 is in the execution state.

[0042] As in Fig. As shown in Figure 10, time t110 and time t120 do not coincide with each other. This is because the time between when the sensor phase becomes 90° and when processing of the synchronous task begins varies depending on the processing load on each of the cores C1 and C2. Fig. Figure 10 shows an example in which the time t120 when core C2 starts processing occurs after the time t110 when core C1 starts processing. However, the before-and-after relationship may be reversed depending on the processing load on core C1 and the processing load on core C2.

[0043] Core C0 executes the switching processing at time t125 after time t120. When the sensor phase becomes 120° after time t125, core C2 is in the execution state. Consequently, core C2 starts processing the synchronous task corresponding to the 120° sensor phase (time t140). In the example of Fig. 10, time t140 occurs after time t130.

[0044] As described above, when core C0 executes the switching processing at time t125, the synchronous task corresponding to the 90° sensor phase is performed only by core C1, and the synchronous task corresponding to the 120° sensor phase is performed only by core C2. As a result, electronic control unit 10 normally controls internal combustion engine 20 similarly to a case where no switching processing has been performed.

[0045] Another example is given below with reference to Fig. 11. The example of Fig. 11 differs from the example of Fig. 10 in that a timing of performing the switching processing is a time t135 which occurs after the time t130 and before the time t140.

[0046] Also in this example, the processing of the synchronous task corresponding to the 90° sensor phase is started in the core C1 (time t110) and not started in the core C2 (time t120).

[0047] At time t130, core C1 serves as the synchronous task execution core and is therefore in the execution state. Therefore, core C1 begins processing the synchronous task corresponding to the 120° sensor phase. Then, at time t135, switchover processing is performed. However, since core C1 has already completed or is currently completing the synchronous task processing, processing is performed continuously without interruption.

[0048] At time t140 after time t135, the synchronous task execution core has been switched to core C2, and thus core C2 is in the execution state. Therefore, core C2 begins processing the synchronous task corresponding to the 120° sensor phase.

[0049] As a result, processing of the synchronous task corresponding to the 120° sensor phase is initiated in both core C1 and core C2. In this case, a certain problem may arise in the control of the internal combustion engine 20 due to the double transmission of a control signal to the internal combustion engine 20.

[0050] In this way, in a conventional electronic control unit, a synchronous task can be processed by a plurality of cores depending on the timing of the switchover processing. Such a phenomenon is also referred to as "processing duplication."

[0051] The switching processing of the electronic control unit in accordance with a comparative example of the invention will be continued with reference to Fig. 12 described. Fig. 12 illustrates an example in which the switching processing is executed at a time t126 to switch the synchronous task execution core from the core C1 to the core C2.

[0052] One in Fig. Time t121 shown in Figure 12 indicates a time at which the core C1 starts processing the synchronous task corresponding to the 90° sensor phase. Fig. Time t111 shown in Figure 12 indicates a time at which the core C2 starts processing the synchronous task corresponding to the 90° sensor phase if the core C2 is in the execution state. In the example of Fig. 12, time t121 occurs after time t111.

[0053] Similarly, there is a Fig. Time t131 shown in Figure 12 indicates a time at which the core C2 starts processing the synchronous task corresponding to the 120° sensor phase. Fig. Time t141 shown in Figure 12 indicates a time at which the core C1 starts processing the synchronous task corresponding to the 120° sensor phase if the core C1 is in the execution state. In the example of Fig. 12, time t141 occurs after time t131.

[0054] Core C1, which serves as the synchronous task execution core before time t126, begins processing the synchronous task at time t121 after the sensor phase becomes 90°. Then, at time t126 after time t121, core C0 executes the switchover processing. Accordingly, the synchronous task execution core is switched from core C1 to core C2.

[0055] When the sensor phase becomes 120° after time t126, core C1 is in the non-execution state. Therefore, core C1 does not start processing the synchronous task at time t141.

[0056] Core C2 does not serve as the synchronous task execution core and is therefore in the non-execution state before time t126. Consequently, even if the sensor phase becomes 90°, core C2 does not begin processing the synchronous task.

[0057] When the sensor phase becomes 120° after time t126, at which core C0 executes the switching processing, core C2 is in the execution state. Therefore, core C2 starts processing the synchronous task corresponding to the 120° sensor phase (time t131).

[0058] As described above, when core C0 executes the switching processing at time t126, the synchronous task corresponding to the 90° sensor phase is performed only by core C1, and the synchronous task corresponding to the 120° sensor phase is performed only by core C2. As a result, similar to the case where no switching operation is performed, electronic control unit 10 controls engine 20 normally.

[0059] Another example is given below with reference to Fig. 13. The example of Fig. 13 differs from the example of Fig. 12 in that a timing of executing the switching processing is a time t136 which occurs after the time t131 and before the time t141.

[0060] Also in this example, the processing of the synchronous task corresponding to the 90° sensor phase is started in the core C1 (time t121) and is not started in the core C2 (time t111).

[0061] At time t131, core C2 is not serving as the synchronous task execution core and is therefore in the non-execution state. Consequently, core C2 does not start processing the synchronous task corresponding to the 120° sensor phase.

[0062] At time t141 after time t136, core C1 is not serving as the synchronous task execution core and is therefore in the non-execution state. Therefore, core C1 does not start processing the synchronous task corresponding to the 120° sensor phase.

[0063] As a result, processing of the synchronous task corresponding to the 120° sensor phase is not initiated in either core C1 or core C2. In this case, a control signal is not transmitted to the internal combustion engine 20. Therefore, a certain error may occur in the control of the internal combustion engine 20.

[0064] In this way, in the conventional electronic control unit, some synchronous tasks may not be processed depending on the timing of the switching processing. Such a phenomenon is also referred to as "processing failure."

[0065] The duplication of processing and the lack of processing described above are caused by the following reasons. When the sensing phase becomes a specific phase, the timing of starting processing of a synchronous task differs between cores according to the specific sensing phase. Furthermore, since the timing of performing switching processing is not specifically defined, switching processing is performed asynchronously with the timing of starting the synchronous task.

[0066] The invention makes it possible to perform the switching processing while reliably preventing duplication of processing and missing processing. An outline of the switching processing in the present embodiment will be described below with reference to FIG. Fig. 2 and Fig. 3 described.

[0067] Fig. 2 is a timing chart illustrating the flow of switching processing executed in the electronic control unit 10. A state of the RAM 130 is schematically illustrated in the upper part of the timing chart.

[0068] The timing of executing a synchronous task in the present embodiment is the same as the timing in the above-mentioned embodiments with reference to the Fig. 10 to 13. This means that in the present embodiment, the synchronous task in the synchronous task execution core is also executed at 60°, 90°, 120°, and 150° with a 30° increase in the sensor phase.

[0069] Fig. Figure 2 illustrates an example in which switching processing is executed at time t35 to switch the synchronous task execution core from core C1 to core C2. Core C1, which serves as the synchronous task execution core before time t35, starts processing the synchronous task at time t10 after the sensor phase becomes 90°. The time at which the sensor phase becomes 90° and the time at which processing of the synchronous task begins do not necessarily coincide with each other due to the reasons already described in the comparative examples.

[0070] The first storage unit 131 of the RAM 130 stores a value (core number) indicating the synchronous task execution core. In the example of Fig. 2, "1", which is a value indicative of the core C1, is stored in the first storage unit 130 in a period before time t 35. In a period after time t 35, "2", which is a value indicative of the core 2, is stored in the first storage unit 131.

[0071] When the sensor phase changes from 90° to 120° after time t10, the core C1 starts processing a synchronous task corresponding to 120° sensor phase (time t30). In the example of Fig. 2, the time t35 at which the switching processing is performed occurs after the time t30 at which the core C1 starts processing the synchronous task.

[0072] The switching processing in the present embodiment is performed by the core C0 by rewriting the core number stored in the first storage unit 131. For example, when the synchronous task execution core is changed from the core C1 to the core C2, the core number stored in the first storage unit 131 is rewritten from 1 to 2.

[0073] Furthermore, the core C0 also rewrites a switching phase stored in the second storage unit 132 simultaneously with rewriting the core number stored in the first storage unit 131. The "switching phase" is a phase indicating a time point at which a state (an execution state or a non-execution state) of each of the cores is to be switched. That is, the switching (change) of the synchronous task execution core is performed not at time t35, which is the time point at which the switching processing is executed, but at the time when the sensor phase coincides with the switching phase stored in the second storage unit 132.

[0074] In the example of Fig. 2, the core number stored in the first storage unit 131 is rewritten from 1 to 2 at time t35. Furthermore, a value of the switching phase stored in the second storage unit 132 is rewritten to 150°.

[0075] In the present embodiment, each of the cores (core C1 and core C2) references the core number stored in the first storage unit 131 before executing the processing of the synchronous task. Furthermore, each of the cores also references the switching phase stored in the second storage unit 132.

[0076] At this time, if the read core number is a core-indicating value, the core will only switch from the non-execution state to the execution state when the sensor phase matches the switching phase. On the other hand, if the read core number is not a core-indicating value, the core will only switch from the execution state to the non-execution state when the sensor phase matches the switching phase.

[0077] At time t30, the core C0 has not yet performed the switching processing, and the core number stored in the first storage unit 131 remains unchanged at 1. Therefore, the core C1 remains in the execution state even after time t30 and starts processing the synchronous task at time t30.

[0078] Then, at time t35, switching processing is performed to rewrite the core number stored in the first storage unit 131. However, since the core C1 is already executing or was in the process of executing the synchronous task, the processing continues to be executed without interruption.

[0079] When the sensor phase becomes 150° after time t35, core C1 again refers to the core number stored in the first storage unit 131 and the switching phase stored in the second storage unit 132 (time t50). At time t50, the core number stored in the first storage unit 131 is 2, and therefore does not match the value (1) indicating core C1.

[0080] Furthermore, the switching phase stored in the second storage unit 132 is 150° and thus coincides with the sensor phase at time t50. Therefore, the core C1 is switched from the execution state to the non-execution state at time t50 and does not start processing the synchronous task at time t50.

[0081] Core C2 does not serve as the synchronous task execution core and is therefore in the non-execution state before time t35. Therefore, even if the sensor phase becomes 90°, core C2 does not start processing the synchronous task. Fig. Time t20 shown in Fig. 2 indicates a time at which the core C2 starts executing a synchronous task corresponding to the 90° sensor phase if the core C2 is in the execution state.

[0082] The core C0 executes the switching processing at time t35 after time t20. When the sensor phase becomes 120°, the core C2 refers to the core number stored in the first storage unit 131 and the switching phase stored in the second storage unit 132 (time t40). In the example of Fig. 2, time t40 occurs after time t35 when the switching processing is executed.

[0083] At time t40, the core number stored in the first storage unit 131 is 2 and thus coincides with the number corresponding to core C2. However, the switching phase stored in the second storage unit 132 is 150° and thus does not coincide with a sensor phase (120°) at time t40.

[0084] Therefore, the core C2 is not switched to the execution state at time t40 and remains in the non-execution state even after time t40.

[0085] Consequently, even if the sensor phase becomes 120°, the core C2 does not start processing the synchronous task at time t40.

[0086] When the sensor phase becomes 150° after time t40, core C2 again refers to the core number stored in the first storage unit 131 and the switching phase stored in the second storage unit 132 (time t60). At time t60, the core number stored in the first storage unit 131 is 2 and thus coincides with the value (2) indicating core C2. Further, the switching phase stored in the second storage unit 132 is 150° and thus coincides with the sensor phase (150°) at time t60. Therefore, core C2 is switched from the non-execution state to the execution state at time t60 and starts processing the synchronous task at time t60.

[0087] In the Fig. 2, the switching processing is executed at time t35 between the time t30 at which the core C1 starts processing the synchronous task corresponding to the 120° sensor phase and the time t40 at which the core C2 starts processing the synchronous task corresponding to the 120° sensor phase. That is, the switching processing is executed at the same time as that in the example described with reference to Fig. 11 described comparative example.

[0088] The duplication of processing, as in the case of Fig. 11, however, does not occur in the present embodiment, and the processing of the synchronous task corresponding to 120° is started only in the core C1.

[0089] Fig. Fig. 3 is also a timing chart showing the flow of switching processing executed in the electronic control unit 10. Similar to the case of Fig. 2, a state of the RAM 130 is schematically shown in the upper part of the timing diagram.

[0090] Fig. 3 illustrates an example in which switching processing is executed at time t16 to switch the synchronous task execution core from core C1 to core C2. At time t16, the core number stored in the first storage unit 131 is rewritten from 1 to 2. Furthermore, the switching phase stored in the second storage unit 132 is rewritten to 120°.

[0091] One in Fig. Time t21 shown in Figure 3 indicates a time at which the core C1 starts processing the synchronous task corresponding to the 90° sensor phase.

[0092] One in Fig. Time t11 shown in Figure 3 indicates a time at which the core C2 starts processing the synchronous task corresponding to the 90° sensor phase if the core C2 is in the execution state. In the example of Fig. 3, time t21 occurs after time t11. Time t16, at which the switching processing is executed, occurs after time t11 and before time t21.

[0093] Similarly, there is a Fig. 3 represents a time t31 at which the core C2 begins processing the synchronous task corresponding to the 120° sensor phase. Fig. Time t41 shown in Figure 3 indicates a time at which the core C1 starts the execution of the synchronous task corresponding to the 120° sensor phase if the core C1 is in the execution state. In the example of Fig. 3, time t41 occurs after time t31.

[0094] When the sensor phase becomes 90°, the core C1 refers to the core number stored in the first storage unit 131 and the switching phase stored in the second storage unit 132 (time t21).

[0095] At time t21, the core number stored in the first storage unit 131 is 2 and therefore does not match the number corresponding to core C1. Therefore, core C1 no longer serves as the synchronous task execution core and is switched from the execution state to the non-execution state.

[0096] However, the switching phase stored in the second storage unit 132 is 120° and therefore does not match the sensor phase (90°) at time t21. Therefore, core C1 is not switched to the non-execution state at time t21 and remains in the execution state thereafter. Consequently, core C1 begins processing the synchronous task at time t21 when the sensor phase is 90°.

[0097] When the sensor phase becomes 120° after time t21, core C1 again refers to the core number stored in the first storage unit 131 and the switching phase stored in the second storage unit 132 (time t41). At time t41, the core number stored in the first storage unit 131 is 2 and therefore does not match the value (1) indicating core C1.

[0098] Furthermore, the switching phase stored in the second storage unit 132 is 120° and thus coincides with the sensor phase at time t41. Therefore, the core switches from the execution state to the non-execution state at time t41 and does not start processing the synchronous task at time t41.

[0099] At time t11, core C2 refers to the core number stored in the first storage unit 131 and the switching phase stored in the second storage unit 132. At time t11, the core number stored in the first storage unit 131 is 1 and therefore does not match the value (2) indicating core 2. Consequently, core C2, which was in the non-execution state, remains in the non-execution state even after time t11. Core C2 does not start processing the synchronous task at time t11.

[0100] When the sensor phase becomes 120°, the core C2 again refers to the core number stored in the first storage unit 131 and the switching phase stored in the second storage unit 132 (time t31). At time t31, the core number stored in the first storage unit 131 is 2 and thus matches the value (2) indicating the core C2.

[0101] Furthermore, the switching phase stored in the second storage unit 132 is 120° and thus coincides with the sensor phase at time t31. Therefore, the core C2 is switched from the non-execution state to the execution state and begins processing the synchronous task at time t31.

[0102] In the Fig. 3, the switching processing is executed at time t16 between time t11 when the core C2 starts processing the synchronous task corresponding to the 90° phase and time t21 when the core C1 starts processing the synchronous task corresponding to the 90° phase. That is, the switching processing is executed at the same time as that in the example described with reference to Fig. 13 described comparative example.

[0103] In the present embodiment, however, the lack of processing as in the case of Fig. 13 does not occur, and the processing of the synchronous task is started accordingly at 90° in the core C1.

[0104] Details of the processing performed in the electronic control unit 10 will be described below with reference to Fig. 4. A number of Fig. The processing steps illustrated in Figure 4 are repeatedly executed in core C0 of microcomputer 100 at every predetermined time period. The processing may be executed in either core C1 or core C2 concurrently with the processing of, for example, a synchronous task.

[0105] In the first step S01, the necessity of switching processing is determined. That is, it is determined whether there is an imbalance in the processing load between core C1 and core C2. The determination is made with reference to Fig. 5 described.

[0106] Fig. Figure 5 illustrates examples of processing load on a single core (for example, core C1) when the electronic control unit 10 controls the internal combustion engine 20. More specifically, Fig. 5 shows examples of the proportion of a time PT1 during which processing other than the processing of the synchronous task is performed, a time PT2 during which the processing of the synchronous task is performed, and an idle time DT during which no processing is performed, in a predetermined time.

[0107] In an example of (A) in Fig. 5, the sum of the time PT1 and the time PT2, i.e., the total time during which any processing is performed in the core, is relatively short. The proportion of the sum of the time PT1 and the time PT2 in the predetermined time is less than a threshold TH. That is, the processing load on the core is relatively small. Therefore, the core can still perform additional processing.

[0108] On the other hand, in an example of (B) in Fig. 5 The sum of the time PT1 and the time PT2 exceeds the threshold TH. This means that the processing load on the core is relatively large. Therefore, the core is close to its processing capacity limit.

[0109] On Fig. 4 Referring back to step S01, switching processing is determined to be necessary only when the proportion of the sum of the time PT1 and the time PT2 in the predetermined time exceeds the threshold TH. In other words, switching processing is determined to be necessary only when the proportion of the idle time DT in the predetermined time is less than a threshold (a value obtained by subtracting the threshold TH from 100%).

[0110] On the other hand, the switching processing is determined to be unnecessary when the proportion of the sum of the time PT1 and the time PT2 in the predetermined time does not exceed the threshold TH. In other words, the switching processing is determined to be unnecessary when the proportion of the idle time DT in the predetermined time is not less than the threshold (the value obtained by subtracting the threshold TH from 100%).

[0111] If the switching processing in step S01 is determined to be unnecessary, the series of processing steps shown in Fig. 4 are terminated. On the other hand, if the switching processing is determined to be necessary, the process proceeds to step S02. In step S02, the core number (execution core number) of a core that executes the synchronous task after the switching processing is determined.

[0112] A method for determining a new execution kernel number after the switchover processing will be described with reference to Fig. 6 and Fig. 7. The Fig. 6 and Fig. 7 illustrate examples of processing loads on the core C1 and the core C2 when the electronic control unit 10 controls the internal combustion engine 20. Similar to Fig. 5 represent the Fig. 6 and Fig. 7 shows examples of the proportion of time PT1 during which processing other than the processing of the synchronous task is performed, the time PT2 during which the processing of the synchronous task is performed, and the idle time DT during which no processing is performed, in a predetermined time.

[0113] In the examples of Fig. 6 and Fig. 7, core C1 serves as the synchronous task execution core. Therefore, core C1 has the time PT1, the time PT2, and the idle time DT. On the other hand, core C2 does not serve as the synchronous task execution core. Therefore, core C2 does not have the time PT2 during which the synchronous task processing is executed.

[0114] The sum of the time PT2 and the idle time DT in the predetermined time is defined as a "total time." A total time T1 in the core C1 is the sum of the time PT2 and the idle time DT. On the other hand, since there is no time PP2 in the core C2, a total time T2 in the core C2 is equal to the idle time DT. In the example of Fig. 6, the total time T2 in the core C2 is longer than the total time T1 in the core C1.

[0115] On Fig. 4 Referring back, in step S02, the total time T1 in the core C1 and the total time T2 in the core C2 are calculated, and a core number representing a core (the core 2 in the example of Fig. 6) corresponding to the longer total time than the new execution kernel number defines.

[0116] That is, the new execution core number is determined such that an idle time DT in the synchronous task execution core after the switchover processing is longer than an idle time DT in the synchronous task execution core before the switchover processing.

[0117] If the total time T1 is longer than the total time T2, as in the Fig. In the example shown in Figure 7, a core corresponding to the longer total time is core C1, which serves as the synchronous task execution core. Thus, if the idle time DT in the synchronous task execution core is shortened by changing the execution core number, the execution core number remains unchanged.

[0118] In step S03 following step S02, it is determined whether the execution core number changes. That is, it is determined whether the execution core number determined in step S02 differs from a core number of the synchronous task execution core before the switching processing is performed.

[0119] If the execution kernel number remains unchanged, the switch processing is unnecessary. Therefore, the Fig. 4 is completed. If the execution kernel number changes, the program proceeds to step S04.

[0120] In step S04, the switching phase is determined. The switching phase is determined based on a phase at the time when the processing of Fig. 4 is performed. More specifically, a phase (in this case 120°) at which a rotation-synchronous task is performed closest to the current sensor phase (for example, 90°) is determined as the switching phase.

[0121] An example of an expression for determining the switching phase (Pn) in the above manner includes the following expression (1). Pn=(((Pc / 30)+1)%24)×30 In the expression (1), Pc denotes the current sensor phase, “ / ” is an operator for calculating a quotient, and “%” is an operator for calculating a remainder.

[0122] A method for determining the switching phase is not limited to the above method. For example, a phase (in this case, 150°) at which a rotation-synchronous task is executed after the phase closest to the current sensor phase or the phase after the current sensor phase (e.g., 90°) can be determined as the switching phase.

[0123] In step S05 following step S04, the switching phase determined in step S04 is written to the second memory unit 132. In step S06 following step S05, the execution kernel number determined in step S02 is written to the first memory unit 131.

[0124] The processing flow executed in the core C1 and the core C2 is described below with reference to Fig. 8. The Fig. The processing shown in Figure 8 is repeatedly executed at every 30° change in the sensor phase in each of the cores C1 and C2. The time at which the sensor phase changes by 30° (the time at which the sensor phase becomes, for example, 90°) and the time at which the processing of Fig. 8 do not necessarily match each other. The reason for this is as already described above in the comparative examples.

[0125] In the first step S11, the core number (execution core number) stored in the first storage unit 131 is read. In the subsequent step S12, the switching phase stored in the second storage unit 132 is read.

[0126] In step S12 following step S13, a state (the execution state or the non-execution state) is thereafter determined and switched based on the read execution core number and switching phase and the current state (the execution state or the non-execution state) of the core.

[0127] As described above, in the present embodiment, in the case where the execution kernel number stored in the first storage unit 131 is a value indicative of the kernel, the kernel is switched from the non-execution state to the execution state only when the sensor phase matches the switching phase stored in the second storage unit 132. On the other hand, in the case where the core number stored in the first storage unit 131 is not a value indicative of the kernel, the kernel is switched from the execution state to the non-execution state only when the sensor phase matches the switching phase stored in the second storage unit 132.

[0128] A specific determination method in step S13 for switching a state in the above manner will be described below with reference to Fig. 9 described. Fig. Figure 9 is a diagram illustrating a state transition in each of the cores C1 and C2.

[0129] The core C1 is described as an example. For example, it is in an initial state before the first switching processing is performed, such as before time t16 in Fig. 3, the core in the execution state (ST1).

[0130] At a time when the sensor phase changes and a synchronous task is to be executed, the core C1 determines in the execution state whether the following condition B is or will be satisfied.

[0131] Condition B is that the read execution core number does not match a core number indicating the core (core C1 in this example) and the switching phase matches the current sensor phase.

[0132] The core C1 is only switched from the execution state (ST1) to the non-execution state (ST2) if condition B is met. For example, at time t21 of Fig. 3, the read execution core number (2) does not match the core number (1) indicating core C1. Therefore, the first half of condition B is met. However, the read switching phase (120°) at time t21 does not match the sensor phase (90°). Therefore, the second half of condition B is not met. Consequently, at time t21, core C1 is not switched from the execution state (ST1) to the non-execution state (ST2).

[0133] At a time when the synchronous task is to be executed again after the core C1 enters the non-execution state, the core C1 determines whether the following condition A is satisfied.

[0134] Condition A is that the read execution core number matches a core number indicating the core (core C1 in this example) and the read switching phase matches the current sensor phase.

[0135] The core C1 is switched from the non-execution state (ST2) to the execution state (ST1) only if condition A is met.

[0136] The same applies to core C2. For example, it is in an initial state before the first switching processing is performed, such as before time t35 in Fig. 2, the core C2 in the non-execution state (ST2).

[0137] At a time when the sensor phase changes and a synchronous task is to be executed, the core C2 in the non-execution state determines whether the above condition A is satisfied. The core C2 will only switch from the non-execution state (ST2) to the execution state (ST1) if the condition A is satisfied. For example, at time t40 of Fig. 2, the read execution core number (2) matches the core number (2) indicating core C2. Therefore, the first half of condition A is met. However, the read switching phase (150°) does not match the sensor phase (120°) at time t40. Therefore, the second half of condition A is not met. Consequently, at time t40, core C2 is not switched from the non-execution state to the execution state (ST1).

[0138] At a time when the synchronous task is to be executed again after core C2 enters the execution state, core C2 determines whether condition B is met. Core C2 will only switch from the execution state (ST1) to the non-execution state (ST2) if condition B is met.

[0139] Reference to Fig. 8, in step S14 following step S13, it is determined whether the core has entered the execution state as a result of step S13. If the core is in the execution state, the synchronous task is executed (step S15). If the core is not in the execution state, the Fig. 8 ends without executing the synchronous task.

[0140] It is noted that a flowchart or the processing of the flowchart in the present application includes sections (also referred to as steps), each of which is represented as, for example, S01. Furthermore, each section may be divided into multiple subsections, while multiple sections may be combined into a single section. Furthermore, each of the sections configured in this way may also be referred to as a device, a module, or a means.

[0141] While the invention has been described with reference to exemplary embodiments thereof, it should be understood that the invention is not limited to the exemplary embodiments and constructions. The invention is intended to cover various modifications and equivalent arrangements. Moreover, notwithstanding the various combinations and configurations, other combinations and configurations, including more, fewer, or only a single element(s), are also within the spirit and scope of the invention.

Claims

[1] An electronic control unit (10) comprising: a multi-core microcomputer (100) equipped with a plurality of cores (C0, C1, C2), each core executing a task in synchronization with a phase of a rotation angle; a first storage unit (31) storing a core number indicating an output execution core that executes a task; and a second storage unit (132) that stores a switching phase indicating a phase when the task execution core is switched to another core, wherein: the task execution core is switched to another core based on the core number stored in the first storage unit and the switching phase stored in the second storage unit. [2] Electronic control unit according to claim 1, wherein: each core is switched to the task execution core when the core number stored in the first storage unit indicates the core, and a phase becomes the switching phase stored in the second storage unit. [3] Electronic control unit according to claim 2, wherein: the switching phase stored in the second storage unit is determined based on a phase at a time when the switching phase is determined. [4] Electronic control unit according to claim 3, wherein: the switching phase stored in the second storage unit is a phase after the phase at the time at which the switching phase is determined. [5] An electronic storage unit according to claim 4, wherein: the switching phase stored in the second storage unit is a phase at which the task is executed next to the phase at the time when the switching phase is determined. [6] Electronic control unit according to claim 1, wherein: the core number stored in the first storage unit is determined based on an operational processing load of each core during a predetermined time interval. [7] Electronic control unit according to claim 6, wherein: the task execution core is only switched to another core if a total idle time of processing of the task execution core during the predetermined time interval is less than a threshold value. [8] Electronic control unit according to claim 6 or 7, wherein: the operational processing load of each core is calculated based on a first time and a second time; the first time is a total time in which the task is executed in the core during the predetermined time interval; and the second time is a total idle time of processing of the core during the predetermined time interval. [9] Electronic control unit according to claim 8, wherein: each core has the same performance; and the first storage unit stores the core number indicating the core corresponding to a longest one of: a sum of the first time and the second time calculated in the output execution core; and the second time calculated in the core other than the task execution core.

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