semiconductor device

Abstract

Semiconductor device (1A, 1C, 1D, 1Fa, 1Fb, 80a) comprising: a storage region (10a, 10b, 40b); a logic region (20a, 20b, 50b); and an element region (30b) of an I / O transistor (30), wherein the memory region (10a, 10b, 40b) contains a first transistor (10, 40, 40c) with: a first gate insulating layer (11, 41) provided over a semiconductor substrate (2, 6a, 6b); a first gate electrode (12, 42) provided over the first gate insulating layer (11, 41); a first sidewall insulating layer (13, 43) provided on a sidewall of the first gate electrode (12, 42) and above the semiconductor substrate (2, 6, 6a); and a first source region (14a, 44a) and a first drain region (14b, 44b) provided in the semiconductor substrate (2, 6a, 6b) on both sides of the first gate electrode (12, 42), wherein the first transistor (10, 40, 40c) stores information by accumulating charge in the first sidewall insulating layer (13, 43), where the logic region (20a, 20b, 50b) contains a second transistor (20, 50) with: a second gate insulating layer (21, 51) provided over the semiconductor substrate (2, 6a, 6b), a second gate electrode (22, 52) provided over the second gate insulating layer (21, 51), a second sidewall insulating layer (23, 53) provided on a sidewall of the second gate electrode (22, 52) and above the semiconductor substrate (2, 6a, 6b); and a second source region (24a, 54a) and a second drain region (24b, 54b) provided in the semiconductor substrate (2, 6a, 6b) on both sides of the second gate electrode (22, 52), wherein a width of the first sidewall insulating layer (13, 43) is greater than a width of the second sidewall insulating layer (23, 53), wherein the I / O transistor has a third gate insulating layer (31) which is equal to the first gate insulating layer (11) of the first transistor (10, 40, 40c), and wherein a thickness of the first gate insulating layer (11, 41) and the third gate insulating layer (31) is greater than a thickness of the second gate insulating layer (21, 51).

Description

AREA

[0001] The embodiments discussed here relate to semiconductor devices. BACKGROUND

[0002] One of the semiconductor devices is a non-volatile memory. For example, a non-volatile memory is known that includes a MOS (metal oxide semiconductor) field-effect transistor as a memory transistor, which stores information by accumulating charges (hot carriers) in the sidewall insulating layer of a gate electrode sidewall.

[0003] For such a non-volatile memory, a technique of increasing the thickness of the sidewall insulating layer of a transistor included in a circuit portion in the periphery of a memory portion having a memory transistor to reduce the hot carrier injection efficiency of the previous transistor is known.

[0004] Consider, for example, publication US 2008 / 0062745 A1, publication JP 2008-244097 A and publication JP 2009-252059 A.

[0005] US 2009 / 0 027 942 A1 relates to a memory unit based on field-effect technology. Hot charge carriers are injected into a multilayer dielectric spacer to achieve the field-effect-induced resistance increase after injection. US 7 187 594 B2 relates to a semiconductor device comprising a logic transistor, a memory transistor with volatile memory, and a memory transistor with non-volatile memory. US 2008 / 0 128 791 A1 also relates to a semiconductor device on which a memory unit and a logic MOS device are provided. The memory unit has a similar functionality to the memory unit disclosed in D1.

[0006] In a non-volatile memory equipped with a memory transistor array that stores information by accumulating hot carriers in a sidewall insulating layer, the speed of the entire non-volatile memory depends on the programming speed of the individual memory transistor. Depending on the capacity of a non-volatile memory, if the programming speed of the individual memory transistor is insufficient, a predetermined programming may not be performed within the time period permitted in a system with the non-volatile memory. SUMMARY

[0007] The above problem is solved according to the invention by the subject matter of the independent claims. Further preferred embodiments are contained in the dependent claims. The following description contains aspects, examples, and preferred embodiments that contribute to an understanding of the subject matter of the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an example of a semiconductor device according to a non-claimed example. Fig. 2 illustrates an example of a semiconductor device according to a non-claimed example. Fig. 3A and Fig. 3B are explanatory views of charge injection into a sidewall insulating layer of a memory transistor according to an unclaimed example. Fig. 4 illustrates an example of a semiconductor device according to a non-claimed example. Fig. 5A to Fig. 5C illustrate the program characteristics of a memory transistor according to the second embodiment. Fig. 6A and Fig. 6B illustrates the program characteristics of a memory transistor according to a comparative example. Fig. 7 is an explanatory view of the evaluation of the program characteristics of the memory transistor according to the second embodiment. Fig. 8 is a view (part 1) illustrating an example of the method for manufacturing a semiconductor device according to a third embodiment. Fig. 9 is a view (part 2) illustrating an example of a method for manufacturing the semiconductor device according to the third embodiment. Fig. 10 is a view (part 3) illustrating an example of the method for manufacturing the semiconductor device according to the third embodiment. Fig. 11 is a view (part 4) illustrating an example of the method for manufacturing the semiconductor device according to the third embodiment. Fig. 12 is a view (part 5) illustrating an example of the method for manufacturing the semiconductor device according to the third embodiment. Fig. 13 is a view (part 6) illustrating an example of the method for manufacturing the semiconductor device according to the third embodiment. Fig. 14 is a view (part 1) illustrating an example of a method for manufacturing a semiconductor device according to a fourth embodiment. Fig. 15 is a view (part 2) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 16 is a view (part 3) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 17 is a view (part 4) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 18 is a view (part 5) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 19 is a view (part 6) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 20 is a view (part 7) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 21 is a view (part 8) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 22 is a view (part 9) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 23 is a view (part 10) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 24 is a view (part 11) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 25 is a view (part 12) illustrating an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Fig. 26 is a view (part 1) illustrating an example of a method for manufacturing a semiconductor device according to a fifth embodiment. Fig. 27 is a view (part 2) illustrating an example of the method for manufacturing the semiconductor device according to the fifth embodiment. Fig. 28 is a view (part 3) illustrating an example of the method for manufacturing the semiconductor device according to the fifth embodiment. Fig. 29 is a view (part 4) illustrating an example of the method for manufacturing the semiconductor device according to the fifth embodiment. Fig. 30 is a view (part 5) illustrating an example of the method for manufacturing the semiconductor device according to the fifth embodiment. Fig. 31 is a view (part 6) illustrating an example of the method for manufacturing the semiconductor device according to the fifth embodiment. Fig. 32 illustrates a first configuration example of a semiconductor device according to a sixth embodiment. Fig. 33 illustrates a second configuration example of the semiconductor device according to the sixth embodiment. Fig. 34 is a view (part 1) illustrating an example of a method for manufacturing a semiconductor device according to a seventh embodiment. Fig. 35 is a view (part 2) illustrating an example of a method for manufacturing the semiconductor device according to the seventh embodiment. Fig. 36 is a view (part 1) illustrating an example of a method for manufacturing a semiconductor device according to an eighth embodiment. Fig. 37 is a view (part 2) illustrating an example of the method for manufacturing the semiconductor device according to the eighth embodiment. Fig. 38 is a view (part 3) illustrating an example of the method for manufacturing the semiconductor device according to the eighth embodiment. Fig. 39 is a view (part 4) illustrating an example of the method for manufacturing the semiconductor device according to the eighth embodiment. Fig. 40 illustrates a memory transistor of a comparative example. Fig. Figure 41 illustrates an example of a twin-bit cell type non-volatile memory. Fig. 42 is an explanatory view of a programming operation of the twin-bit cell type non-volatile memory. Fig. 43 is an explanatory view of a read operation of the twin-bit cell type non-volatile memory. Fig. 44 is an explanatory view of an erase operation of the twin-bit cell type non-volatile memory. Fig. 45 is an explanatory view of the area of ​​the twin-bit cell type non-volatile memory. Fig. 46 illustrates an example of a memory transistor according to an unclaimed example. Fig. 47A to Fig. 47D illustrates an example of the concentration profile when phosphorus is used for the impurity of an LDD (lightly doped drain) region. Fig. 48A to Fig. 48D illustrates an example of the concentration profile when arsenic is used for the impurity of the LDD region. Fig. Figure 49 illustrates an example of the programming characteristics of a memory transistor with an SCR (screen) layer. Fig. 50 illustrates an example of the erase characteristics of the memory transistor with the SCR layer. Fig. 51A and Fig. 51B are views (part 1) showing the LDD region concentration dependence of the Illustrate programming characteristics of the memory transistor with the SCR layer. Fig. 52A and Fig. 52B are views (part 2) illustrating the LDD region concentration dependence of the programming characteristics of the memory transistor with the SCR layer. Fig. 53A and Fig. 53B are views (part 3) illustrating the LDD region concentration dependence of the programming characteristics of the memory transistor with the SCR layer. Fig. 54 is a view (part 1) illustrating the SCR layer concentration dependence and an SD region impurity type dependence of the programming characteristics of the memory transistor with the SCR layer. Fig. 55 is a view (part 2) illustrating the SCR layer concentration dependence and an SD region impurity type dependence of the programming characteristics of the memory transistor with the SCR layer. Fig. 56 illustrates another example of the programming characteristics of the memory transistor with the SCR layer. Fig. 57 illustrates an example of the non-volatile memory using the memory transistor with the SCR layer. Fig. 58A and Fig. 58B are explanatory views of the programming operation of the non-volatile memory using the memory transistor with the SCR layer. Fig. 59A and Fig. 59B are explanatory views of the read operation of the non-volatile memory using the memory transistor with the SCR layer. Fig. 60A and Fig. 60B are explanatory views of the erase operation of the non-volatile memory using the memory transistor with the SCR layer. Fig. 61 is a view (part 1) illustrating an example of the method for manufacturing the non-volatile memory. Fig. 62 is a view (part 2) illustrating an example of the method for manufacturing the non-volatile memory. Fig. 63 is a view (part 3) illustrating an example of the method for manufacturing the non-volatile memory. Fig. 64 is a view (part 4) illustrating an example of the method for manufacturing the non-volatile memory. Fig. 65 is a view (part 5) illustrating an example of the method for manufacturing the non-volatile memory. Fig. 66 is a view (part 1) illustrating another example of the method for manufacturing the non-volatile memory. Fig. 67 is a view (part 2) illustrating another example of the method for manufacturing the non-volatile memory. Fig. 68 is a view (part 3) illustrating another example of the method for manufacturing the non-volatile memory. Fig. 69 is a view (part 4) illustrating another example of the method for manufacturing the non-volatile memory. Fig. 70 is a view (part 5) illustrating another example of the method for manufacturing the non-volatile memory. Fig. 71 is a view (part 6) illustrating another example of the method for manufacturing the non-volatile memory. Fig. 72 is an explanatory view of the memory transistor with the SCR layer. DESCRIPTION OF THE EMBODIMENTS

[0008] Below, some embodiments will be described with reference to the accompanying drawings, wherein like reference numerals refer to similar elements throughout. The invention is defined by the claims, and the description describes merely exemplary embodiments.

[0009] First, a first embodiment will be described.

[0010] Fig. 1 illustrates an example of a semiconductor device according to the first embodiment. Fig. 1 schematically illustrates an exemplary cross section of a main part of the semiconductor device according to the first embodiment.

[0011] One in Fig. The semiconductor device 1A illustrated in FIG. 1 is an example of the non-volatile memory and includes a transistor (memory transistor) 10 provided in a memory region 10a and a transistor (logic transistor) 20 provided in a logic region 20a. The memory transistor 10 and the logic transistor 20 are formed (mixed mounted) on a common p-type or n-type semiconductor substrate 2. Various types of semiconductor substrates, such as a silicon (Si) substrate or a silicon germanium (SiGe) substrate, can be used for the semiconductor substrate 2. A region (element region) in which the memory transistor 10 is formed and a region (element region) in which the logic transistor 20 is formed are defined by an element isolation region 3 formed in the semiconductor substrate 2 using STI (Shallow Trench Isolation), thermal oxidation, or the like.

[0012] Although a memory transistor 10 in Fig. 1, note that the memory region 10a of the semiconductor device 1A may include a plurality of memory transistors 10A or at least one memory transistor 10 and another memory transistor. Although a logic transistor 20 in Fig. 1, the logic region 20a of the semiconductor device 1A may include a plurality of logic transistors 20 or at least one logic transistor 20 and another logic transistor.

[0013] As in Fig. As illustrated in Figure 1, the memory transistor 10 includes a gate insulating layer 11 provided over the semiconductor substrate 2, a gate electrode 12 provided over the gate insulating layer 11, and a sidewall insulating layer 13 provided on the sidewall of the gate electrode 12 and over the semiconductor substrate 2. The memory transistor 10 further includes an impurity region 14a and an impurity region 14b, each provided in the semiconductor substrate 2 on both sides (both sides in the gate length direction) of the gate electrode 12 and functioning as a source region or a drain region. The memory transistor 10 may also include an LDD (Lightly Doped Drain) region 15a and an LDD region 15b on the inside of the impurity region 14a and the impurity region 14b, which function as the source region or drain region, in the semiconductor substrate 2 under the sidewall insulating layer 13.

[0014] Here, various types of insulating materials, such as silicon oxide (SiO2), silicon nitride (Si3N4), and hafnium oxide (HfO2), can be used for the gate insulating layer 11. The layer thickness of the gate insulating layer 11 is determined based on, for example, the threshold voltage specified for the memory transistor 10.

[0015] Metals such as titanium (Ti), tungsten (W) and the nitrides thereof, other than polysilicon, may be used for the gate electrode 12.

[0016] The sidewall insulating layer 13 includes, for example, a stacked structure of an oxide layer 13a and a nitride layer 13b, which are insulating layers. For the oxide layer 13a, for example, silicon oxide is used. For the nitride layer 13b, for example, silicon nitride is used. The oxide layer 13a is provided, for example, to have an L-shaped cross section, on the sidewall of the gate electrode 12 and on the semiconductor substrate 2, and the nitride layer 13b is provided on the oxide layer 13a. Although the sidewall insulating layer 13 is provided with a two-layer structure of the oxide layer 13a and the nitride layer 13b in Fig. 1, the sidewall insulating layer 13 may be formed to have a three-layer structure obtained by further providing an oxide layer over the oxide layer having an L-shaped cross section and the nitride layer, or may be formed to have a stacked structure of four or more layers of insulating layers. Other than this, it is also possible to form the sidewall insulating layer 13 with a single-layer structure of an oxide layer or nitride layer. The sidewall insulating layer 13 is provided such that a width (thickness) W1 in the gate length direction of the gate electrode 12 (in the plane direction of the semiconductor substrate 2) is set larger than a width (thickness) W2 of a sidewall insulating layer 23 (to be described later) of the logic transistor 20.

[0017] The impurity region 14a and the impurity region 14b contain a predetermined concentration of the impurity of a predetermined conductivity type, ie, an n-type impurity such as phosphorus (P) or arsenic (As), or a p-type impurity such as boron (B).

[0018] The LDD region 15a and the LDD region 15b contain the impurity of the same conductivity type as the conductivity type of the impurity contained in the impurity region 14a and the impurity region 14b, in a lower concentration than the impurity region 14a and the impurity region 14b.

[0019] In the memory transistor 10, a region between the impurity region 14a and the impurity region 14b (or between the LDD region 15a and the LDD region 15b) under the gate electrode 12 functions as a channel region 16 in which a carrier (electron or hole) moves.

[0020] The memory transistor 10 is a non-volatile memory transistor that stores information by accumulating charges (electrons or holes) in the sidewall insulating layer 13. In the memory transistor 10 with the sidewall insulating layer 13 including a stacked structure of the oxide layer 13a and the nitride layer 13b, the charge is mainly accumulated in the nitride layer 13b. The nitride layer 13b of silicon nitride or the like has a charge trap level, while the oxide layer 13a of silicon oxide or the like suppresses the leakage of charges accumulated in the nitride layer 13b.

[0021] As in Fig. As illustrated in Figure 1, the logic transistor 20 includes a gate insulating layer 21 provided over the semiconductor substrate 2, a gate electrode 22 provided over the gate insulating layer 21, and a sidewall insulating layer 23 provided on the sidewall of the gate electrode 2 and over the semiconductor substrate 2. The logic transistor 20 further includes an impurity region 24a and an impurity region 24b, which are provided in the semiconductor substrate 2 on both sides (both sides in the gate length direction) of the gate electrode 22, respectively, and which function as a source region or a drain region. The logic transistor 20 may further include an LDD region 25a and an LDD region 25b on the inside of the impurity region 24a and impurity region 24b, which function as the source region or drain region, in the semiconductor substrate 2 under the sidewall insulating layer 23.

[0022] Here, various types of insulating materials, such as silicon oxide, silicon nitride, and hafnium oxide, can be used for the gate insulating layer 21. The layer thickness of the gate insulating layer 21 is determined based on, for example, the threshold voltage specified for the logic transistor 20.

[0023] Metals such as titanium and the nitrides thereof, other than polysilicon, may be used for the gate electrode 22.

[0024] The sidewall insulating layer 23 includes an oxide layer of silicon oxide or the like, or a nitride layer of silicon nitride or the like. The sidewall insulating layer 23 does not necessarily have to include a stacked structure of an oxide layer and a nitride layer, and therefore can be formed to have a single-layer structure of an insulating layer, such as an oxide layer or a nitride layer. The sidewall insulating layer 23 is provided such that the width (thickness) W2 in the gate length direction of the gate electrode 22 (in the plane direction of the semiconductor substrate 2) is set to be smaller than the width W1 of the sidewall insulating layer 13 of the memory transistor 10.

[0025] The impurity region 24a and impurity region 24b contain an impurity of n-type or p-type conductivity in a predetermined concentration.

[0026] The LDD region 25a and LDD region 25b contain the impurity of the same conductivity type as the conductivity type of the impurity contained in the impurity region 24a and impurity region 24b, in a lower concentration than the impurity region 24a and impurity region 24b.

[0027] In the logic transistor 20, a region between the impurity region 24a and the impurity region 24b (or between the LDD region 25a and the LDD region 25b) under the gate electrode 22 functions as a channel region 26 in which a carrier (electron or hole) moves.

[0028] For example, the logic transistor 20 of the logic region 20a is used to perform programming (writing in) and reading (reading out) operations on the memory transistor 10 of the memory region 10a.

[0029] Each of the programming and reading operations of the memory transistor 10 is performed as follows.

[0030] First, the programming operation is performed by setting each node of the gate electrode 12, impurity region 14a, impurity region 14b, and semiconductor substrate 2 to a predetermined potential to generate hot carriers, and injecting the generated hot carriers into the sidewall insulating layer 13 for accumulation (retention).

[0031] Now, it is assumed that the memory transistor 10 is of an n-channel type, the semiconductor substrate (channel region 16 during non-operation) is of a p-type, and the impurity region 14a and impurity region 14b (the LDD region 15a and LDD region 15b) are of an n-type.

[0032] If electrons are injected into the sidewall insulating layer 13 (13d) on the impurity region 14b side, the impurity region 14a (source) and the semiconductor substrate 2 are grounded, and a positive voltage is applied, for example, to the gate electrode 12 and the impurity region 14b (drain). Alternatively, a negative voltage may be applied to the semiconductor substrate 2. If these potentials are set in this way, an inversion layer (not shown) is formed in the channel region 16 in the n-channel memory transistor 10, and thus electrons flow through the channel region 16 from the impurity region 14a toward the impurity region 14b.The electrons flowing through the channel region 16 toward the impurity region 14b assume a high-energy state near the impurity region 14b due to the electric field caused by the positive voltage applied to the impurity region 14b, thereby generating hot electrons. The hot electrons generated near the impurity region 14b are injected and accumulated in the sidewall insulating layer 14d on the impurity region 14b side by the electric field caused by the positive voltage applied to the gate electrode 12.

[0033] The read operation in the n-channel memory transistor 10 is performed, for example, by grounding the impurity region 14b (source) and the semiconductor substrate 2, and applying a positive voltage to the gate electrode 12 and the impurity region 14a (drain). If electrons are already injected and accumulated in the sidewall insulating layer 13d on the side of the impurity region 14b, positive charges are injected into a region, such as the LDD region 15b, under the sidewall insulating layer 13 to increase the resistance of the LDD region 15b. Therefore, the electric current flowing from the impurity region 14a to the impurity region 14b will decrease.

[0034] If electrons have not yet been injected and accumulated in the sidewall insulating layer 13d on the side of the impurity region 14b, the resistance of a region, such as the LDD region 15b, under the sidewall insulating layer 13 will not increase, and thus the electric current flowing from the impurity region 14a to the impurity region 14b will not decrease. As described above, depending on the electric current flowing from the impurity region 14a to the impurity region 14b, the presence or absence (information of "0" or "1") of electrons in the sidewall insulating layer 13d is read out.

[0035] When the programming operation is performed to inject electrons into the sidewall insulating layer 13 (13c) on the impurity region 14a side, the voltages applied to the impurity region 14a and impurity region 14b (source and drain voltages) can be switched from the voltages applied during the above-described programming operation. Furthermore, when the reading operation is performed to read the presence or absence of electrons from the sidewall insulating layer 13c, the voltages applied to the impurity region 14a and impurity region 14b (source and drain voltages) can be switched from the voltages applied during the above-described reading operation.

[0036] The memory transistor 10 is used as a memory cell for storing 2-bit information depending on the presence or absence of injected electrons from each of the sidewall insulating layer 13c and the sidewall insulating layer 13d.

[0037] When the memory transistor 10 is set to a p-channel type, the semiconductor substrate 2 (channel region 16 during non-operation) is set to an n-type, and the impurity region 14a and impurity region 14b (the LDD region 15a and LDD region 15b) are set to p-types.

[0038] In the p-channel memory transistor 10, holes are injected into the sidewall insulating layer 13 and accumulated, for example, by applying, to each node, a voltage with the opposite sign of the voltage applied during the programming operation described above. In the p-channel memory transistor 10, the presence or absence of holes in the sidewall insulating layer 13 is read, for example, by applying, to each node, a voltage with the opposite sign of the voltage applied during the read operation described above.

[0039] Next, the sidewall insulating layer 13 and the sidewall insulating layer 23 of the memory transistor 10 and logic transistor 20 described above will be described.

[0040] First, for comparison, an example of a semiconductor device according to another embodiment is shown in Fig. 2, in which the width of the sidewall insulating layer of the memory transistor is made equal to the width of the sidewall insulating layer of the logic transistor.

[0041] One in Fig. 2 is different from the semiconductor device 1A according to the embodiment shown in the above Fig. 1 in that the semiconductor device 100 includes a memory transistor 110 provided with a sidewall insulating layer 113 having the same width W2 as the sidewall insulating layer 23 of the logic transistor 20.

[0042] The LDD region 15a and LDD region 15b have an effect of suppressing variation in the generation of hot carriers and the injection of hot carriers into the sidewall insulating layer 13 (13c, 13d) during the programming operation, thereby achieving a small variation in the programming speed. Also in the Fig. In the semiconductor device 100 illustrated in FIG. 2, the provision of the LDD region 15a and LDD region 15b achieves a small variation in the programming speed compared to the case where these LDD region 15a and LDD region 15b are not provided. However, even if such an LDD region 15a and LDD region 15b are provided, a sufficient programming speed required for the semiconductor device 100 is sometimes not obtained. When the storage capacity in a memory region 110a (non-volatile memory) including a plurality of memory transistors 110 is relatively small, the programming time as a whole falls within an acceptable level even if the programming speed of the individual memory transistor 110 (memory cell) is relatively slow. However, when the storage capacity becomes relatively large, the programming time as a whole sometimes falls within the acceptable level.

[0043] One technique for increasing programming speed is to generate more hot carriers. To this end, the electric field under the sidewall insulating layer 13 can be increased, and the impurity concentration of the channel region 16 can be increased. However, if the impurity concentration of the channel region 16 is increased in this way, the threshold voltage of the memory transistor 110 will unnecessarily increase, and the read current will decrease.

[0044] In the above Fig. On the other hand, in the semiconductor device 1A illustrated in FIG. 1, the width W1 of the sidewall insulating layer 13 of the memory transistor 10 is set to be larger than the width W2 of the sidewall insulating layer 23 of the logic transistor 20. Accordingly, when hot carriers are injected into the sidewall insulating layer 13, a variation in resistance in the region under the sidewall insulating layer 13 will easily occur, so that an improvement in programming speed will be achieved.

[0045] Fig. 3A and Fig. 3B are explanatory views of charge injection into the sidewall insulating layer of the memory transistor. Fig. Figure 3A illustrates an example of charge injection into the relatively narrow sidewall insulating layer, while Fig. 3B illustrates an example of charge injection into the relatively wide sidewall insulating layer. This means that Fig. 3A an example of charge injection into the sidewall insulating layer 113 of the device shown in the above Fig. 2 illustrated memory transistor 110. Fig. 3B corresponds to an example of charge injection into the sidewall insulating layer 13 of the device shown in the above Fig. 1 illustrated memory transistor 10.

[0046] In Fig. 3A, impurity regions 14a, 14b and impurity regions 24a, 24b, which are high-concentration source / drain diffusion layers, are formed by impurity ion implantation after forming sidewall insulating layer 113 and sidewall insulating layer 23. Subsequent activation annealing diffuses the impurities laterally beneath sidewall insulating layer 113 and sidewall insulating layer 23. The width W2 of sidewall insulating layer 23 of logic transistor 20 is set so that impurity regions 24a, 24b will diffuse laterally but not extend below gate electrode 22. If the width W2 of sidewall insulating layer 23 is larger than required, parasitic resistance will increase, and performance will decrease.On the other hand, if the width of the sidewall insulating layer 113 of the memory transistor 110 is set to the same as the width W2 of the sidewall insulating layer 23 of the logic transistor 20, the impurity concentration under the sidewall insulating layer 113 will be higher than required due to the lateral diffusion of the impurity regions 14a, 14b, and will thus be hardly affected by charges 13e accumulated in the sidewall insulating layer 113. As a result, more charges 13e must be injected into the sidewall insulating layer 113, and thus, it will take a longer time for programming.

[0047] In contrast, in Fig. 3B, the width of the sidewall insulating layer 13 of the memory transistor 10 is set to the width W1 larger than the width W2 of the sidewall insulating layer 23 of the logic transistor 20. Accordingly, even if impurities of the impurity regions 14a, 14b formed by ion implantation diffuse laterally after the formation of the sidewall insulating layer 23, the LDD regions 15a, 15b having a sufficiently large width will be present under the sidewall insulating layer 13. As a result, a change in resistance when the charge 13e is injected into the sidewall insulating layer 13 will increase even if the amount of charge is the same, so that the programming time will be reduced.

[0048] The same applies to both the injection of electrons and the injection of holes into the sidewall insulating layer 113 and the sidewall insulating layer 13.

[0049] The width W1 of the sidewall insulating layer 13 of the memory transistor 10 is set to be larger than the width W2 of the sidewall insulating layer 23 of the logic transistor 20 which is mixed-mounted in the semiconductor substrate 2 together with the memory transistor 10.

[0050] A wider width of the sidewall insulating layer 13 is better from the above-described point of view, but in fact, the width of the sidewall insulating layer 13 is limited to the width from the sidewall of the gate electrode 12 to a plug (not shown) connected to the impurity region 14a and the impurity region 14b. Note that by increasing the width of the sidewall insulating layer 13, the element region of the memory transistor 10 can be expanded, and the impurity region 14a and the impurity region 14b can be shifted in the direction away from the gate electrode 12. In this case, however, an increase in the size of the memory region 10a including a group of memory transistors 10 and an increase in the size of the semiconductor device 1A including the memory region 10a must be considered.

[0051] To increase the programming speed of the memory transistor 10, the thickness of the oxide film 13a can be thinned in addition to setting the width W1 of the sidewall insulating layer 13 to be larger than the width W2 of the sidewall insulating layer 23 of the logic transistor 20. By thinning the thickness of the oxide film 13a, which is mainly provided between the nitride layer 13b into which charges are injected, and the semiconductor substrate 2, in this way, the injection probability of hot carriers will increase, and therefore, an improvement in the programming speed will be achieved. Note, however, that the thinner the thickness of the oxide film 13a, the easier the injected charges will dissipate, and the data retention property may deteriorate.

[0052] Note that if the width W2 of the sidewall insulating layer 23 on the logic transistor 20 side is increased, the injection probability of hot carriers into the sidewall insulating layer 23 of the logic transistor 20 may be reduced. However, because an increase in the width W2 of the sidewall insulating layer 23 increases the length of the LDD region 25a and LDD region 25b and increases the parasitic resistance, the transistor performance will deteriorate.

[0053] Next, a second embodiment will be described.

[0054] Fig. 4 illustrates an example of a semiconductor device according to the second embodiment. Fig. 4 schematically illustrates an exemplary cross section of a main part of the semiconductor device according to the second embodiment.

[0055] One in Fig. The semiconductor device 1B illustrated in FIG. 4 is an example of the non-volatile memory and includes a transistor (memory transistor) 40 provided in a memory region 40a. The memory transistor 40 is formed on the p-type or n-type semiconductor substrate 2. Various types of semiconductor substrates, such as a silicon substrate, can be used for the semiconductor substrate 2. The region (element region) in which the memory transistor 40 is formed is defined by the element isolation region 3 formed in the semiconductor substrate 2 using STI or the like.

[0056] Although a memory transistor 40 in Fig. 4, note that the memory region 40a of the semiconductor device 1B may include a plurality of memory transistors 40 or at least one memory transistor 40 and another memory transistor.

[0057] As in Fig. As illustrated in Figure 4, the memory transistor 40 includes a gate insulating layer 41 provided over the semiconductor substrate 2, a gate electrode 42 provided over the gate insulating layer 41, and a sidewall insulating layer 43 provided on the sidewall of the gate electrode 42 and above the semiconductor substrate 2. The memory transistor 40 further includes an impurity region 44a and an impurity region 44b provided in the semiconductor substrate 2, respectively, on both sides (both sides in the gate length direction) of the gate electrode 42 and functioning as a source region or a drain region. The memory transistor 40 may include an LDD region 45a and an LDD region 45b on the inside of the impurity region 44a and impurity region 44b in the semiconductor substrate 2 under the sidewall insulating layer 43.The memory transistor 40 further includes a channel region 46 provided in a region between the impurity region 44a and the impurity region 44b (or between the LDD region 45a and the LDD region 45b) under the gate electrode 42, and an impurity region 47 provided under the channel region 46.

[0058] Here, various types of insulating materials, such as silicon oxide, can be used for the gate insulating layer 41. The layer thickness of the gate insulating layer 41 is determined based on, for example, the threshold voltage, programming voltage, and erase voltage specified for the memory transistor 40.

[0059] Various types of conductive materials, such as polysilicon, can be used for the gate electrode 42.

[0060] The sidewall insulating layer 43 includes a stacked structure of an oxide layer 43a of silicon oxide or the like and a nitride layer 43b of silicon nitride or the like. For example, the oxide layer 43a is provided to have an L-shaped cross section on the sidewall of the gate electrode 42 and on the semiconductor substrate 2, and the nitride layer 43b is provided on the oxide layer 43a. The sidewall insulating layer 43 may have a three-layer structure obtained by further providing an oxide layer on the oxide layer having an L-shaped cross section and the nitride layer, or may have a stacked structure of four or more layers of insulating layers. Other than this, the sidewall insulating layer 43 may have a single-layer structure of an oxide layer or nitride layer.

[0061] The impurity region 44a and impurity region 44b contain an impurity of n-type or p-type conductivity in a predetermined concentration.

[0062] The LDD region 45a and LDD region 45b contain the impurity of the same conductivity type as the conductivity type of the impurity contained in the impurity region 44a and impurity region 44b, at a concentration lower than the concentration of the impurity region 44a and impurity region 44b.

[0063] The channel region 46 is an undoped region where no impurity is intentionally added, or a region containing an extremely low concentration of an impurity. The impurity concentration of the channel region 46 is fixed, for example, equal to or less than 1 × 10 17 cm -3 to be.

[0064] The impurity region 47 is a region provided below the channel region 46 and contains a higher concentration of impurities than the channel region 46. The impurity region 47 is also referred to as a screen layer. The impurity region 47 contains, at a predetermined concentration, an impurity of a conductivity type different from the conductivity type of the impurity contained in the impurity region 44a and impurity region 44b, which function as the source region or drain region. The threshold voltage of the memory transistor 40 is controlled by the impurity concentration of the impurity region 47. Furthermore, the impurity region 47 suppresses punch-through between the impurity region 44a and impurity region 44b, which function as the source region or drain region.Because the impurity region 47 is embedded in the semiconductor substrate 2 by the extent of the thickness of the channel region 46 from the interface between the semiconductor substrate 2 and the gate insulating layer 41, and the impurity concentration of the impurity region 47 sets the threshold voltage, the impurity concentration of the impurity region 47 is set to be relatively high, for example, on the order of 1 × 10. 19 cm -3 .

[0065] The memory transistor 40 is a transistor of a non-volatile memory that stores information by accumulating charges (electrons or holes) into the sidewall insulating layer 43.

[0066] Each of the programming operation and reading operation of the memory transistor 40 can be performed as with the memory transistor 10 described in the first embodiment. Namely, each operation is performed by setting each node of the gate electrode 42, impurity region 44a, impurity region 44b, and the semiconductor substrate 2 to a predetermined potential to generate hot carriers, and by injecting and accumulating the generated hot carriers in the sidewall insulating layer 43.

[0067] In the memory transistor 40, the threshold voltage is controlled by the impurity concentration of the impurity region 47 embedded in the semiconductor substrate 2, and the impurity concentration of the channel region 46 above the impurity region 47 is set to be lower. In the memory transistor 40, the impurity concentration of the channel region 46 is not increased, but the impurity concentration of the impurity region 47 below the channel region 46 is increased to increase the generation of hot carriers during the programming operation. Because the impurity region 47 is located away from the interface between the semiconductor substrate 2 and the gate insulating layer 41, the threshold voltage of the memory transistor 40 will not increase significantly even if the impurity concentration of the impurity region 47 is increased.

[0068] That is, in a memory transistor not provided with such an impurity region 47, if the impurity concentration of the channel region is increased to increase hot carrier generation, the threshold voltage may inconveniently increase, and the read current may decrease. In contrast, in the memory transistor 40 with the impurity region 47 with the relatively high concentration provided below the channel region 46 as described above, it is possible to increase hot carrier generation and control the threshold voltage without causing such inconvenience.

[0069] In order to effectively realize the functions such as increasing the generation of hot carriers, controlling the threshold voltage, and suppressing punch-through, the impurity region 47 is provided to contact the impurity region 44a and impurity region 44b, which function as the source region or drain region.

[0070] In the memory transistor 40, an improvement in the programming speed is achieved by adopting the impurity region 47 as described above.

[0071] Fig. 5A to Fig. 5C illustrate the program characteristics of the memory transistor according to the second embodiment. Fig. 5A illustrates a configuration example of the memory transistor according to the second embodiment, while Fig. 5B and Fig. 5C illustrates an example of the relationship between the gate voltage Vg[V] and the read current (drain current) Id[A], respectively. Fig. 6A and Fig. 6B illustrates the program characteristics of a memory transistor according to a comparative example. Fig. 6A schematically illustrates a configuration example of the memory transistor according to the comparative example, while Fig. Figure 6B illustrates an example of the relationship between the gate voltage Vg[V] and the read current (drain current) Id[A].

[0072] In the Fig. In the memory transistor 40 illustrated in Figure 5A, the layer thickness of the gate insulating layer 41 is set to 7 nm, the gate length Lg of the gate electrode is set to 0.1 µm or 0.5 µm, and the width of the sidewall insulating layer 43 is set to 74 nm. The LDD region 45a and LDD region 45b are formed by implanting phosphorus from four directions under the conditions of an acceleration energy of 35 keV and a dose rate of 2.5 × 10 12 cm -2 , while the impurity region 44a and impurity region 44b are formed to have a concentration sufficiently higher than 2.5 × 10 12 cm -2The channel region 46 is formed as a non-doped layer, while the impurity region 47, which is provided in the semiconductor substrate 2 below the channel region 46, is formed by implanting boron under the conditions: the acceleration energy of 20 keV and the dose amount of 2.4 × 10 13 cm -2 .

[0073] The programming operation on the memory transistor 40 is performed under the voltage conditions where the impurity region 44a (source) and the semiconductor substrate 2 are both set to 0 V, and the gate electrode 42 and the impurity region 44b (drain) are both set to 4.5 V. After the programming operation is performed with a programming time Tp set to 1 ms, 100 μs, and 10 μs under these voltage conditions, the reading operation is performed by setting the impurity region 44b (source) and the semiconductor substrate 2 to 0 V and applying a positive voltage to the gate electrode 42 and the impurity region 44a (drain). Here, the voltage of the impurity region 44a is, for example, 0.5 V. The relationship between the gate voltage Vg and the reading current Id flowing from the drain to the source during the reading operation is shown in Fig. 5B (in the case of the gate length of 0.1 µm) and in Fig. 5C (in the case of the gate length of 0.5 µm). The read current Id (initial) before programming is also shown in Fig. 5B and Fig. 5C illustrates.

[0074] In a Fig. In the memory transistor 40A illustrated in Figure 6A, the gate length Lg of the gate electrode 42 is set to 0.35 µm, and a channel region (for convenience, referred to as a "shallow channel region") 46A having a predetermined depth from the surface of the semiconductor substrate 2 is provided. The shallow channel region 46A is formed by implanting boron under the condition of a relatively low dose amount of 3.2 × 10 12 cm -2 . The other configurations are the same as the memory transistor 40 of Fig. 5A.

[0075] The programming operation with respect to the memory transistor 40A is also performed under the same voltage and programming time conditions as the programming operation of the memory transistor 40 of Fig. 5A, and then the read operation is performed. The relationship between the gate voltage Vg and the read current Id flowing from the drain to the source during the read operation is shown in Fig. 6B. The read current (initial) before programming is also shown in Fig. 6B illustrates.

[0076] In the memory transistor 40 of Fig. 5A, which has the impurity region 47 with relatively high concentration provided under the channel region 46, the programming is performed even if the programming time Tp decreases by one digit or more, such as from 1 ms to 100 µs and 10 µs, as in Fig. 5B and Fig. 5C illustrates.

[0077] In the memory transistor 40A of Fig. 6A, which is provided with the flat channel region 46A, the IV characteristic does not change at all even with the programming time Tp of 1 ms, as in Fig. 6B, and thus the programming is not performed. Fig. 6B indicates that all the IV characteristics, initially, after 10 µs, after 100 µs, and after 1 ms, overlap with each other and do not vary, meaning that programming is not performed at all. In the memory transistor 40A provided with the shallow channel region 46A, a higher voltage must be applied for programming, and even if such a higher voltage is applied, the programming speed is slow compared to the memory transistor 40.

[0078] Fig. Fig. 7 is an explanatory view of the evaluation of the programming characteristics of the memory transistor according to the second embodiment. The horizontal axis of Fig. 7 represents a programming voltage Vp[V], while the vertical axis of Fig. 7 represents a ratio (current ratio) R[%] between a read current detected after performing the programming operation for a certain period of time and a read current before programming.

[0079] In the memory transistor 40 ( Fig. 5A), which is provided with the defect region 47, are according to Fig. 7, the current ratios R after performing the programming operation under the conditions: programming voltage Vp = 3.5 V and programming time Tp = 1 ms, Vp = 4.0 V and Tp = 100 µs, or Vp = 4.5 V and Tp = 10 µs, are on the order of 30% and essentially the same. This means that in the memory transistor 40, when the programming voltage Vp increases by 0.5 V, the programming speed increases by one digit.

[0080] In such a memory transistor 40 provided with the impurity region 47 having the relatively high concentration under the channel region 46, a significant improvement in the programming speed can be achieved.

[0081] Next, a third embodiment will be described.

[0082] As the third embodiment, a semiconductor device including the memory transistor 10 and logic transistor 20 described in the above first embodiment and an I / O transistor will be described here.

[0083] Fig. 8 to Fig. 13 illustrate an example of the method for manufacturing the semiconductor device according to the third embodiment. Here, Fig. 8 is an exemplary schematic cross-sectional view of a main portion of the first manufacturing step, Fig. 9 is an exemplary schematic cross-sectional view of the main portion of the second manufacturing step, Fig. 10 is an exemplary schematic cross-sectional view of the main portion of the third manufacturing step, Fig. 11 is an exemplary schematic cross-sectional view of the main portion of the fourth manufacturing step, Fig. 12 is an exemplary schematic cross-sectional view of the main portion of the fifth manufacturing step, and Fig. 13 is an exemplary schematic cross-sectional view of the main part of the sixth manufacturing step. Hereinafter, an example of the manufacturing steps of the semiconductor device according to the third embodiment will be described sequentially with reference to Fig. 8 to Fig. 13 are described.

[0084] As in Fig. 8, first, the element isolation region 3, which is an element region 10b of the memory transistor 10 ( Fig. 13), an element region 20b of the logic transistor 20 ( Fig. 13) and an element region 30b of an I / O transistor 30 ( Fig. 13) is formed in the semiconductor substrate 2 using STI. A well region 6 is formed in the semiconductor substrate 2 before or after the formation of the element isolation region 3. The well region 6 is, for example, a p-type. After the formation of the well region 6 and the element isolation region 3, impurity ion implantation (channel impurity ion implantation) is performed to adjust each threshold voltage of the memory transistor 10, the logic transistor 20, and the I / O transistor 30.

[0085] Subsequently, an oxide layer, for example, with a layer thickness of 7 nm is formed on the semiconductor substrate 2 using thermal oxidation, the oxide layer formed in the element region 20b of the logic transistor 20 is removed, and an oxide layer, for example, with a layer thickness of 1.8 nm is formed on the semiconductor substrate 2 using thermal oxidation again. As shown in Fig. Accordingly, as illustrated in Fig. 8, the gate insulating film 11, the gate insulating film 21, and a gate insulating film 31 each having a predetermined film thickness are formed in the element region 10b of the memory transistor 10, the element region 20b of the logic transistor 20, and the element region 30b of the I / O transistor 30, respectively.

[0086] After the formation of the gate insulating layer 11, gate insulating layer 21 and gate insulating layer 31, a polysilicon 4, which is a gate electrode material, is formed, for example, with a layer thickness of 100 nm, as shown in Fig. 8 illustrates.

[0087] As in Fig. Next, as illustrated in Figure 9, a resist material is formed on the polysilicon 4, and then a region where the gate electrode 12 of the memory transistor 10 is formed and a resist pattern 5a covering the element region 20b and element region 30b are formed by performing exposure and development. With the resist pattern 5a used as a mask, the polysilicon 4 is etched to form the gate electrode 12 of the memory transistor 10.

[0088] After the formation of the gate electrode 12, the resist pattern 5a is removed, and then, with the gate electrode 12 and polysilicon remaining on the semiconductor substrate 2, used as a mask, an impurity implantation is performed on the semiconductor substrate 2 of the element region 10b. With this impurity implantation, the LDD region 15a and LDD region 15b are formed in the semiconductor substrate 2 on both sides of the gate electrode 12, as shown in Fig. 10. The LDD region 15a and LDD region 15b are formed by implanting, for example, arsenic, which is an n-type impurity, under the conditions: the acceleration energy of 10 keV and the dose rate of 1 × 10 13 cm -2 . The channel region 16 of the memory transistor 10 is formed between the LDD region 15a and the LDD region 15b.

[0089] After the formation of the LDD region 15a and LDD region 15b, the oxide layer 13a is first formed to cover the exposed gate electrode 12, polysilicon 4, and gate insulating layer 11, and then the nitride layer 13b is formed on the oxide layer 13a. For example, the oxide layer 13a is formed with a layer thickness of 10 nm, and the nitride layer 13b is formed with a layer thickness of 150 nm on the oxide layer 13a. Then, the formed oxide layer 13a and nitride layer 13b are etched back to form the sidewall insulating layer 13 of the memory transistor 10 with the predetermined width W1 on the sidewall of the gate electrode 12 of the element region 10b and above the semiconductor substrate 2, as shown in Fig. 11. Note that the sidewall insulating layer 13 is similarly formed on the sidewall of the polysilicon 4 except the gate electrode 12 and above the semiconductor substrate 2 (on the element isolation region 3).

[0090] After the formation of the sidewall insulating layer 13, a resist material is formed over the surface, and then exposure and development are performed. As shown in Fig. Accordingly, as illustrated in Figure 12, a resist pattern 5b is formed covering the element region 10b, a region where the gate electrode 22 of the logic transistor 20 is formed, and a region where the gate electrode 32 of the I / O transistor 30 is formed. With the resist pattern 5b used as a mask, the polysilicon is etched to form the gate electrode 22 of the logic transistor 20 and the gate electrode 32 of the I / O transistor 30. Note that Fig. 12 illustrates a shape in which a part (edge) of the polysilicon 4 also remains on the element isolation region 3.

[0091] After forming the gate electrode 22 and the gate electrode 32, the resist pattern 5b is removed, and then an impurity implantation is performed on the semiconductor substrate 2 of the element region 20b and the element region 30b, respectively. Through the above impurity implantation, the LDD region 25a and the LDD region 25b are formed in the semiconductor substrate 2 on both sides of the gate electrode 22, and the LDD region 35a and the LDD region 35b are formed in the semiconductor substrate 2 on both sides of the gate electrode 32, as shown in Fig. 13. The LDD region 25a and LDD region 25b are formed by implanting, for example, arsenic, which is an n-type impurity, under the conditions: the acceleration energy of 1.5 keV and the dose rate of 1 × 10 15 cm -2. The LDD region 35a and LDD region 35b are formed by implanting, for example, phosphorus, which is an n-type impurity, under the conditions: the acceleration energy of 35 keV and the dose level of 1 × 10 13 cm -2 . The channel region 26 of the logic transistor 20 is formed between the LDD region 25a and the LDD region 25b, and the channel region 36 of the I / O transistor 30 is formed between the LDD region 35a and the LDD region 35b.

[0092] Next, an insulating layer, such as a silicon oxide layer, is formed with a thickness of 80 nm, which is then etched back. As shown in Fig. Accordingly, as illustrated in FIG. 13, the sidewall insulating layer 23 of the logic transistor 20 is formed with the predetermined width W2 on the sidewall of the gate electrode 22 of the element region 20b and above the semiconductor substrate 2. At the same time, the sidewall insulating layer 33 of the I / O transistor 30 is formed on the sidewall of the gate electrode 32 of the element region 30b and above the semiconductor substrate 2. The sidewall insulating layer 23 of the logic transistor 20 and the sidewall insulating layer 33 of the I / O transistor 30 are formed to have the predetermined width W2, which is smaller than the width W1 of the sidewall insulating layer 13 of the memory transistor 10.

[0093] Note that the sidewall insulating layer 23 (or 33) is similarly formed also on the sidewall of the polysilicon 4 remaining on the element isolation region 3.

[0094] With the gate electrode 12 and the sidewall insulating layer 13 of the sidewall thereof, the gate electrode 22 and the sidewall insulating layer 23 of the sidewall thereof, and the gate electrode 32 and the sidewall insulating layer 33 of the sidewall thereof used as a mask, an n-type impurity such as phosphorus is implanted on the semiconductor substrate 2. The impurity implantation described above can be performed collectively on the element region 10b, the element region 20b, and the element region 30b, or can be performed separately on the element region 10b, the element region 20b, and the element region 30b.

[0095] At this time, the impurity implantation is performed with respect to the semiconductor substrate 2 of the element region 10b under the conditions that the concentration of the element region 10b becomes higher than the LDD region 15a and LDD region 15b, and that the impurity is implanted in a deeper region than the LDD region 15a and LDD region 15b.Similarly, the impurity implantation of the semiconductor substrate 2 into the element region 20b is performed under the conditions that the concentration of the element region 20b becomes higher than the concentration of the LDD region 25a and the LDD region 25b, and the impurity is implanted into a region deeper than the LDD region 25a and the LDD region 25b. The impurity implantation of the semiconductor substrate 2 into the element region 30b is performed under the conditions that the concentration of the element region 30b becomes higher than the concentration of the LDD region 35a and the LDD region 35b, and the impurity is implanted into a region deeper than the LDD region 35a and the LDD region 35b. For example, phosphorus is implanted under the conditions of an acceleration energy of 8 keV and a dose rate of 1 × 10 . 16 cm -2. Accordingly, the n-type impurity region 14a and impurity region 14b, which function as the source region or drain region of the semiconductor transistor 10, are formed on the outside of the n-type LDD region 15a and LDD region 15b in the semiconductor substrate 2 of the element region 10b. Similarly, the n-type impurity region 24a and impurity region 24b, which function as the source region or drain region of the logic transistor 20, are formed on the outside of the n-type LDD region 25a and LDD region 25b in the semiconductor substrate 2 of the element region 20b, and the n-type impurity region 34a and impurity region 34b, which function as the source region or drain region of the I / O transistor 30, are formed on the outside of the n-type LDD region 35a and LDD region 35b in the semiconductor substrate 2 of the element region 30b.

[0096] With the manufacturing steps described above, a semiconductor device 1C (non-volatile memory) as shown in Fig. 13, which has the memory transistor 10, logic transistor 20, and I / O transistor 30 mixed mounted on the common semiconductor substrate 2. Thereafter, the formation of an interlayer insulating film, the formation of a plug, and the formation of an upper wiring layer including the conductors, such as a wiring and a via, and the like, are performed.

[0097] In the semiconductor device 1C according to the third embodiment, the width W1 of the sidewall insulating layer 13 of the memory transistor 10 is set to be larger than the width W2 of the sidewall insulating layer 23 of the logic transistor 20 (and the sidewall insulating layer 33 of the I / O transistor 30). As described in the above first embodiment, an improvement in the programming speed of the memory transistor 10 is thus achieved. The manufacturing steps described above make it possible to manufacture the memory device 1C provided with the memory transistor 10 having an excellent programming speed.

[0098] Although a memory transistor 10 is illustrated here, note that the semiconductor device 1C may include a plurality of memory transistors 10 or at least one memory transistor 10 and another memory transistor. Furthermore, although a logic transistor 20 is illustrated here, the semiconductor device 1C may include a plurality of logic transistors 20 or at least one logic transistor 20 and another logic transistor. Furthermore, although an I / O transistor 30 is illustrated here, the semiconductor device 1C may include a plurality of I / O transistors 30 or at least one I / O transistor 30 and another I / O transistor.

[0099] Next, a fourth embodiment will be described.

[0100] As the fourth embodiment, a semiconductor device will be described here which includes the memory transistor 40 as described in the above second embodiment and further includes a logic transistor and an I / O transistor.

[0101] Fig. 14 to Fig. 25 illustrate an example of the method for manufacturing the semiconductor device according to the fourth embodiment. Here, Fig. 14 is an exemplary schematic cross-sectional view of a main portion of the first manufacturing step, Fig. 15 is an exemplary schematic cross-sectional view of the main portion of the second manufacturing step, Fig. 16 is an exemplary schematic cross-sectional view of the main portion of the third manufacturing step, Fig. 17 is an exemplary schematic cross-sectional view of the main portion of the fourth manufacturing step, Fig. 18 is an exemplary schematic cross-sectional view of the main portion of the fifth manufacturing step, Fig. 19 is an exemplary schematic cross-sectional view of the main portion of the sixth manufacturing step, Fig. 20 is an exemplary schematic cross-sectional view of the main portion of the seventh manufacturing step, Fig. 21 is an exemplary schematic cross-sectional view of the main portion of the eighth manufacturing step, Fig. 22 is an exemplary schematic cross-sectional view of the main portion of the ninth manufacturing step, Fig. 23 is an exemplary schematic cross-sectional view of the main portion of the tenth manufacturing step, Fig. 24 is an exemplary schematic cross-sectional view of the main portion of the eleventh manufacturing step and is Fig. 25 is an exemplary schematic cross-sectional view of the main part of the twelfth manufacturing step. Hereinafter, an example of the manufacturing steps of the semiconductor device according to the fourth embodiment will be described sequentially with reference to Fig. 14 to Fig. 25 are described.

[0102] As in Fig. 14, first, a resist pattern 5c in which an element region 40b of the memory transistor 40 ( Fig. 25) is opened, and the element region 20b of the logic transistor 20 ( Fig. 25) and the element region 30b of the I / O transistor 30 ( Fig. 25) are formed on the semiconductor substrate 2. With the resist pattern 5c used as a mask, a predetermined impurity implantation is performed on the semiconductor substrate 2 of the element region 40b. With this impurity implantation, a well region 6a and the impurity region 47 with a relatively high concentration are formed under the channel region 46 ( Fig. 25) of the memory transistor 40 is formed in the semiconductor substrate 2 of the element region 40b. The well region 6a and the impurity region 47 are each of a p-type, for example.

[0103] This impurity implantation is performed, for example, under the following conditions. Boron is implanted under the following conditions: acceleration energy of 135 keV or 185 keV and a dose level of 4 × 10 13 cm -2 Germanium (Ge) is implanted under the following conditions: acceleration energy of 30 keV and dose level of 5 × 1014 cm -2 Carbon (C) is implanted under the following conditions: acceleration energy of 5 keV and dose level of 5 × 10 14 cm -2 Boron is implanted under the following conditions: acceleration energy of 20 keV and dose level of 3 × 10 13 cm -2 By implanting each of these impurities under predetermined conditions, the p-type well region 6a and the impurity region 47 are formed in the semiconductor substrate 2 of the element region 40b, respectively. Note that the implantation of germanium and carbon suppresses the diffusion of the p-type impurity contained in the impurity region 47 into lower and / or upper regions.

[0104] After the formation of the well region 6a and the impurity region 47, the resist pattern 5c is removed, and then a semiconductor material is epitaxially grown on the semiconductor substrate. For example, when a silicon substrate is used as the semiconductor substrate 2, silicon, which is the same type of semiconductor material as the semiconductor substrate 2, is epitaxially grown to a layer thickness of 25 nm on the semiconductor substrate 2. With the epitaxial growth of the semiconductor material, a semiconductor layer 8 (non-doped layer) is formed on the impurity region 47 of the element region 40b, as shown in Fig. 15 illustrates. The channel region 46 of the memory transistor 40 is formed in the semiconductor layer 8. Although a semiconductor layer similar to the semiconductor layer 8 of the element region 40b is also formed in the element region 20b and the element region 30b due to epitaxial growth, note that for convenience, the semiconductor layer is described here as the layer integrated into the semiconductor substrate 2. After the formation of the semiconductor layer 8, the element isolation region 3 is formed, which defines the element region 40b, the element region 30b, and the element region 20b, as shown in Fig. 15 illustrates.

[0105] Next, as in Fig. 16, a resist pattern 5d is formed in which the element region 40b is covered, and the element region 20b and the element region 30b are opened. With the resist pattern 5d used as a mask, a predetermined impurity implantation is performed on the semiconductor substrate 2 of the element region 20b and the element region 30b. With this impurity implantation, the well region 6b is formed in the semiconductor substrate 2 of the element region 20b and the element region 30b, as shown in Fig. 16. The well region 6b is, for example, of a p-type. The formation of the well region 6b is carried out, for example, by implanting boron under the conditions: the acceleration energy of 135 keV or 185 keV and the dose rate of 4 × 10 13 cm -2 and by implanting boron fluoride (BF, BF2) under the conditions: the acceleration energy of 15 keV and the dose level of 3 × 10 12 cm -2 .

[0106] After the formation of the well region 6b, the resist pattern 5d is removed, and, as in Fig. As illustrated in Figure 17, a resist pattern 5e is newly formed in which the element region 30b and element region 40b are covered, and the element region 20b is opened. With the resist pattern 5e used as a mask, an impurity implantation for adjusting the threshold voltage of the logic transistor 20 is performed on the semiconductor substrate 2 of the element region 20b. This impurity implantation is performed, for example, by implanting boron fluoride under the conditions of an acceleration energy of 15 keV and a dose rate of 1 × 10 13 cm -2 . Accordingly, the channel region 26 of the logic transistor 20 is formed as shown in Fig. 17 illustrates.

[0107] Subsequently, the resist pattern 5e is removed, and an oxide layer 7 is formed, for example, with a layer thickness of 7 nm using thermal oxidation on the semiconductor substrate 2 of the element region 20b, element region 30b, or element region 40b, as shown in Fig. 18. Then, a resist pattern 5f in which the element region 20b is opened is newly formed, and then the oxide film 7 formed on the semiconductor substrate 2 of the element region 20b is removed.

[0108] Next, the resist pattern 5f is removed, and an oxide layer is formed, for example, with a layer thickness of 1.8 nm on the semiconductor substrate 2 using a renewed thermal oxidation. Accordingly, the gate insulating layer 21, gate insulating layer 31, and gate insulating layer 41 are formed, each with a predetermined layer thickness, in the element region 20b of the logic transistor 20, in the element region 30b of the I / O transistor 30, and in the element region 40b of the memory transistor 40, respectively, as shown in Fig. 19 illustrates.

[0109] After the formation of the gate insulating layer 21, gate insulating layer 31 and gate insulating layer 41, the polysilicon 4, which is a gate electrode material, is formed, for example, with a layer thickness of 100 nm, as shown in Fig. 20, and then the patterning or structuring of the polysilicon 4 is performed. Thus, the gate electrode 22 of the logic transistor 20, the gate electrode 32 of the I / O transistor 30, and the gate electrode 42 of the memory transistor 40 are formed.

[0110] After the formation of the gate electrode 22, gate electrode 32 and gate electrode 42, a resist pattern 5g is formed in which the element region 40b is opened, as shown in Fig. 21, and then, with the resist pattern 5g used as a mask, an impurity implantation is performed on the semiconductor substrate 2 of the element region 40b. With this impurity implantation, the LDD region 45a and LDD region 45b are formed in the semiconductor substrate 2 on both sides of the gate electrode 42, as shown in Fig. 21. The LDD region 45a and LDD region 45b are formed, for example, by implanting arsenic, which is an n-type impurity, under the conditions: the acceleration energy of 10 keV and the dose rate of 1 × 10 13 cm -2 . The channel region 46 of the memory transistor 40 is formed between the LDD region 45a and LDD region 45b above the previously formed impurity region 47 of relatively high concentration.

[0111] Similarly, a resist pattern 5h is formed in which the element region 30b is opened as shown in Fig. 22, and with the resist pattern 5h used as a mask, an impurity implantation is then performed on the semiconductor substrate 2 of the element region 30b to form the LDD region 35a and LDD region 35b of the I / O transistor 30. As shown in Fig. 23, a resist pattern 5i is further formed in which the element region 20b is opened, and with the resist pattern 5i used as a mask, an impurity implantation is then performed on the semiconductor substrate 2 of the element region 20b to form the LDD region 25a and LDD region 25b of the logic transistor 20. The LDD region 35a and LDD region 35b of the I / O transistor 30, in Fig. 22, are formed by implanting, for example, phosphorus, which is an n-type impurity, under the conditions: the acceleration energy of 35 keV and the dose level of 3 × 10 13 cm -2 . The LDD region 25a and LDD region 25b of the logic transistor 20, in Fig. 23, are formed by implanting, for example, arsenic, which is an n-type impurity, under the conditions: the acceleration energy of 1.5 keV and the dose level of 1 × 10 15 cm -2. The channel region 36 of the I / O transistor 30 is formed between the LDD region 35a and the LDD region 35b, while the channel region 26 of the logic transistor 20 is formed between the LDD region 25a and the LDD region 25b.

[0112] Please note that the process of Fig. 21 to Fig. 23 illustrated steps can be swapped and carried out.

[0113] Next, an insulating layer, such as a silicon oxide layer or a silicon nitride layer or a stacked layer thereof, is formed with a layer thickness of 80 nm, which is then etched back. As shown in Fig. Accordingly, as illustrated in Fig. 24, the sidewall insulating layer 23, sidewall insulating layer 33, and sidewall insulating layer 43 are formed on the respective sidewalls of the gate electrode 22, gate electrode 32, and gate electrode 42.

[0114] Note that when only the sidewall insulating layer 43 is formed in a stacked structure of an oxide layer of silicon oxide or the like and a nitride layer of silicon nitride or the like, the following steps may be performed after the formation of the gate insulating layer 21, gate insulating layer 31 and gate insulating layer 41 as in the above Fig. 19.

[0115] After the step of the above Fig. 19, the polysilicon 4 is first formed on the gate insulating layer 21, gate insulating layer 31 and gate insulating layer 41. In accordance with the example of the step of the above Fig. 9 described in the third embodiment, next, the gate electrode 42 (the gate electrode 12 of Fig. 9) is formed in the element region 40b of the memory transistor 40. In accordance with the example of the step of Fig. 10 (or Fig. 21) are next the LDD region 45a and LDD region 45b (elements corresponding to the LDD region 15a and LDD region 15b of Fig. 10) are formed in the element region 40b of the memory transistor 40. In accordance with the example of the step of Fig. 11, an oxide layer and a nitride layer (elements corresponding to the oxide layer 13a and nitride layer 13b of Fig. 11) are stacked and formed with a predetermined layer thickness, and then etched back to form the sidewall insulating layer 43 (the sidewall insulating layer 13 of Fig. 11 corresponding element) of the stacked structure of the oxide layer and nitride layer. In accordance with the example of the step of Fig. 12, the polysilicon 4 of the element region 30b and element region 20b is next patterned to form the gate electrode 32 and gate electrode 22.

[0116] In accordance with the example of the steps of Fig. 22 and Fig. 23, in the fourth embodiment, LDD regions 35a and 35b, and LDD regions 25a and 25b are subsequently formed in element region 30b and element region 20b, respectively. Then, a single layer of a silicon oxide film is formed with a predetermined film thickness as the insulating layer, and then etched back to form sidewall insulating layer 33 and sidewall insulating layer 23, each having a single-layer structure, in element region 30b and element region 20b, respectively.

[0117] It is accordingly possible to form the sidewall insulating layer 43 of the element region 40b in a stacked structure of an oxide layer and a nitride layer, to form the sidewall insulating layer 33 of the element region 30b and the sidewall insulating layer 23 of the element region 20b in a single-layer structure, and to form a structure as shown in Fig. 24. This facilitates the accumulation of charges in the sidewall insulating layer 43 and also makes it possible to suppress the accumulation of charges in the sidewall insulating layer 33 and sidewall insulating layer 23, thereby minimizing the deterioration of the performance of the I / O transistor 30 and the logic transistor 20.

[0118] The steps may be changed as needed according to the structure adopted for the sidewall insulating layer 33, sidewall insulating layer 43, and sidewall insulating layer 23.

[0119] After completing the steps up to step Fig. 24 In the manner described above, the process proceeds to the step of Fig. 25. Here, first, with the gate electrode 22 and the sidewall insulating layer 23 of the sidewall thereof, the gate electrode 32 and the sidewall insulating layer 33 of the sidewall thereof, and the gate electrode 42 and the sidewall insulating layer 43 of the sidewall thereof used as a mask, an n-type impurity such as phosphorus is implanted with respect to the semiconductor substrate 2. Such impurity implantation is performed by implanting phosphorus under the conditions: the acceleration energy of 8 keV and the dose rate of 1 × 10 16 cm -2 . As in Fig. 25, the n-type impurity region 24a and impurity region 24b, which function as the source region or drain region of the logic transistor 20, are formed on the outside of the n-type LDD region 25a and LDD region 25b in the semiconductor substrate 2 of the element region 20b. As shown in Fig. 25, the n-type impurity region 34a and impurity region 34b, which function as the source region or drain region of the I / O transistor 30, are formed on the outside of the n-type LDD region 35a and LDD region 35b in the semiconductor substrate 2 of the element region 30b. As shown in Fig. 25, the n-type impurity region 44a and impurity region 44b, which function as the source region or drain region of the memory transistor 40, are formed on the outside of the n-type LDD region 45a and LDD region 45b in the semiconductor substrate 2 of the element region 40b.

[0120] With the steps described above, a semiconductor device 1D (non-volatile memory) as shown in Fig. 25, which has the logic transistor 20, I / O transistor 30, and memory transistor 40 mixedly mounted on the semiconductor substrate 2. Thereafter, the formation of an interlayer insulating film, the formation of a plug, and the formation of an upper wiring layer including the conductors, such as wiring and via, and the like, are performed.

[0121] In the semiconductor device 1D according to the fourth embodiment, the channel region 46 with a lower impurity concentration is provided in the memory transistor 40, and the impurity region 47 with a relatively high concentration is provided below the channel region 46. As described in the second embodiment, an improvement in the programming speed of the memory transistor 40 is thus achieved. The steps described above make it possible to manufacture the semiconductor device 1D provided with the memory transistor 40 having an excellent programming speed.

[0122] Although a memory transistor 40 is illustrated here, note that the semiconductor device 1D may include a plurality of memory transistors 40 or at least one memory transistor 40 and another memory transistor. Although a logic transistor 20 is illustrated here, the semiconductor device 1D may also include a plurality of logic transistors 20 or at least one logic transistor 20 and another logic transistor. Although an I / O transistor 30 is illustrated here, the semiconductor device 1D may also include a plurality of I / O transistors 30 or at least one I / O transistor 30 and another I / O transistor.

[0123] Next, a fifth embodiment will be described.

[0124] As the fifth embodiment, a semiconductor device will be described herein in which a channel structure having a high impurity concentration region provided under a low impurity concentration channel region as described above is adopted for both a memory transistor and a logic transistor mixed-mounted with the memory transistor.

[0125] Fig. 26 to Fig. 31 illustrate an example of the method for manufacturing the semiconductor device according to the fifth embodiment. Here, Fig. 26 is an exemplary schematic cross-sectional view of the main portion of the first manufacturing step, Fig. 27 is an exemplary schematic cross-sectional view of the main portion of the second manufacturing step, Fig. 28 is an exemplary schematic cross-sectional view of the main portion of the third manufacturing step, Fig. 29 is an exemplary schematic cross-sectional view of the main portion of the fourth manufacturing step, Fig. 30 is an exemplary schematic cross-sectional view of the main portion of the fifth manufacturing step and is Fig. 31 is an exemplary schematic cross-sectional view of the main part of the sixth manufacturing step. Hereinafter, an example of the manufacturing steps of the semiconductor device according to the fifth embodiment will be described sequentially with reference to Fig. 26 to Fig. 31 are described.

[0126] As in Fig. 26, first, a resist pattern 5j in which the element region 40b of the memory transistor 40 ( Fig. 31) and the element region 50b of the logic transistor 50 ( Fig. 31) are opened, and the element region 30b of the I / O transistor 30 ( Fig. 31) is formed on the semiconductor substrate 2. With the resist pattern 5j used as a mask, predetermined impurity implantation is performed on the semiconductor substrate 2 of the element region 40b and element region 50b. With this impurity implantation, the well region 6a, the impurity region 47 with a relatively high concentration of the memory transistor 40, and the impurity region 47 with a relatively high concentration of the logic transistor 50 are formed. The well region 6a, the impurity region 47, and the impurity region 57 are each of a p-type, for example.

[0127] For example, the impurity implantation described above is carried out under the following conditions: Boron is implanted under the conditions: the acceleration energy of 135 keV or 185 keV and the dose level of 4 × 10 13 cm -2. Germanium is implanted under the following conditions: acceleration energy of 30 keV and dose level of 5 × 10 14 cm -2 Carbon is implanted under the following conditions: acceleration energy of 5 keV and dose level of 5 × 10 14 cm -2 Boron is implanted under the following conditions: acceleration energy of 20 keV and dose level of 5 × 10 12 cm -2 Boron fluoride is implanted under the following conditions: acceleration energy of 10 keV and dose level of 1.5 × 10 12 cm -2By implanting each of these impurities under the predetermined conditions, the p-type well region 6a and the impurity region 47 are formed in the semiconductor substrate 2 of the element region 40b, and the p-type well region 6a and the impurity region 47 are formed in the semiconductor substrate 2 of the element region 50b. Note that implanting germanium and carbon suppresses the diffusion of the p-type impurities contained in the impurity region 47 and the impurity region 57 into lower and / or upper regions.

[0128] When the logic transistor 50 to be formed is a super-low leakage transistor, the concentration of the impurity region 57 is set to be low compared with the optimal concentration of the impurity region 47 of the memory transistor 40 in order to minimize a junction leakage current.

[0129] Therefore, when the logic transistor 50 is formed as an ultra-low leakage transistor, an impurity implantation is carried out with respect to the semiconductor substrate 2 of the element region 50b under such conditions to obtain the impurity region 57 having an optimum concentration for the logic transistor 50 in which Fig. 26. As in Fig. 27, an additional impurity implantation is further performed on the semiconductor substrate 2 of the element region 40b of the memory transistor 40 to obtain the impurity region 47 having an optimal concentration for the memory transistor 40. The additional impurity implantation is performed as shown in Fig. 27, with a resist pattern 5k in which the element region 40b is opened, which is used as a mask, by implanting, for example, boron under the conditions: the acceleration energy of 20 keV and the dose amount of 2.5 × 10 13 cm -2 .

[0130] Thereafter, a semiconductor material is epitaxially grown on the semiconductor substrate 2 to form a semiconductor layer 8a (non-doped layer) on the impurity region 47 of the element region 40b and on the impurity region 57 of the element region 50b, as shown in Fig. 28. The channel region 46 of the memory transistor 40 and the channel region 56 of the logic transistor 50 are formed in the semiconductor layer 8a. Although a semiconductor layer similar to the semiconductor layer 8a of the element region 40b and element region 50b is also formed in the element region 30b due to epitaxial growth, note that for convenience, the former semiconductor layer is described here as the layer integrated into the semiconductor substrate 2. After the formation of the semiconductor layer 8a, the element isolation region 3 is formed, which forms the element region 40b, the element region 30b, and the element region 50b, as shown in Fig. 28 illustrates.

[0131] As in Fig. Next, as illustrated in FIG. 29, with a resist pattern 5m in which the element region 30b is opened, used as a mask, impurity implantation is performed to form the well region 6b in the semiconductor substrate 2 of the element region 30b. The well region 6b is, for example, a p-type. Subsequently, impurity implantation for adjusting the threshold voltage of the I / O transistor 30 may be performed on the semiconductor substrate 2 of the element region 30b.

[0132] After that, the steps are similar to the steps in Fig. 18 to Fig. 25, described in the above fourth embodiment, to obtain a Fig. 30 illustrated structure and one as in Fig. 31 to obtain the structure illustrated.

[0133] According to the first example, the steps of Fig. 18 and Fig.19, the gate insulating layer 31, gate insulating layer 41, and gate insulating layer 51, each having a predetermined layer thickness, are formed in the element region 30b, the element region 40b, and the element region 50b, respectively, by thermal oxidation. Next, according to the example of the step of Fig. 20, the gate electrode 32, gate electrode 42, and gate electrode 52 are formed by forming and patterning polysilicon. Then, according to the example of the steps of Fig. 21 to Fig. 23, the LDD region 45a and LDD region 45b, the LDD region 35a and LDD region 35b, and the LDD region 55a and LDD region 55b are each formed by implanting an impurity under predetermined conditions. The LDD region 45a and LDD region 45b, the LDD region 35a and LDD region 35b, and the LDD region 55a and LDD region 55b are each of an n-type, for example. Accordingly, the structure as shown in Fig. 30 is obtained. The channel region 36 of the I / O transistor 30 is formed between the LDD region 35a and the LDD region 35b. The channel region 46 of the memory transistor 40 is formed between the LDD region 45a and the LDD region 45b. The channel region 56 of the logic transistor 50 is formed between the LDD region 55a and the LDD region 55b.

[0134] By forming and etching back an insulating layer according to the example of the step of Fig. 24, furthermore, the sidewall insulating layer 33, sidewall insulating layer 43, and sidewall insulating layer 53 are formed on the respective sidewalls of the gate electrode 32, gate electrode 42, and gate electrode 52. Then, according to the example of the step of Fig. 25 an impurity region which serves as the source region or drain region of the I / O transistor 30,

[0135] The n-type impurity region 34a and 34b, which serve as the source region or drain region of the I / O transistor 30, are formed by implanting an impurity under predetermined conditions. Namely, the n-type impurity region 34a and 34b, which serve as the source region or drain region of the I / O transistor 30, are formed on the outside of the n-type LDD region 35a and 35b in the semiconductor substrate 2 of the element region 30b. Similarly, the n-type impurity region 44a and 44b, which serve as the source region or drain region of the memory transistor 40, are formed on the outside of the n-type LDD region 45a and 45b in the semiconductor substrate 2 of the element region 40b. The n-type impurity region 54a and impurity region 54b, which function as the source region or drain region of the logic transistor 50, are formed on the outside and the outside, respectively.outside the n-type LDD region 55a and LDD region 55b in the semiconductor substrate 2 of the element region 50b. Accordingly, the structure shown in FIG. Fig. 31 illustrated structure is preserved.

[0136] Note that the sidewall insulating layer 33, sidewall insulating layer 43, and sidewall insulating layer 53 may each have a single-layer structure of an oxide layer or a nitride layer, or a stacked structure of an oxide layer and a nitride layer. As described in the above fourth embodiment, the steps may be changed as needed according to a structure adopted for the sidewall insulating layer 33, sidewall insulating layer 43, and sidewall insulating layer 53.

[0137] With the above-described steps, a semiconductor device 1E (non-volatile memory) is obtained having the I / O transistor 30, memory transistor 40, and logic transistor 50 mixedly mounted on the common semiconductor substrate 2. Thereafter, the formation of an interlayer insulating film, the formation of a plug, and the formation of an upper wiring layer including conductors, such as wiring and via, and the like, are performed.

[0138] In the semiconductor device 1E according to the fifth embodiment, the channel region 46 with a lower impurity concentration is provided in the memory transistor 40, and the impurity region 47 with a relatively high concentration is provided below the channel region 46. As described in the above second embodiment, an improvement in the programming speed of the memory transistor 40 is accordingly achieved. Moreover, in the semiconductor device 1E according to the fifth embodiment, the channel region 56 with a lower impurity concentration is also provided in the logic transistor 50, and the impurity region 57 with a relatively high concentration is provided below the channel region 56. Accordingly, a reduction in the variation of the threshold voltage, a reduction in power consumption, and the like of the logic transistor 50 are achieved.The steps described above make it possible to manufacture the semiconductor device 1E provided with the memory transistor 40 having an excellent programming speed and the logic transistor 50 having an excellent operating performance.

[0139] Note that here, a case is illustrated where the logic transistor 50 is assumed to have an ultra-low leakage, and an impurity implantation is first performed under such conditions to form the impurity region 57 with a potential characteristic suitable for the logic transistor 50 ( Fig. 26) optimal concentration, and then an additional impurity implantation is carried out to form the impurity region 47 with a concentration suitable for the memory transistor 40 ( Fig. 27) to maintain optimal concentration.

[0140] On the other hand, if the power consumption requirement of the entire semiconductor device 1E is relaxed, the leakage current requirement of the logic transistor 50 is also relaxed. In this case, the impurity region 57 of the logic transistor 50 can be made to have a higher impurity concentration. The following conditions for impurity implantation in this case can be adopted. Boron is implanted under the following conditions: an acceleration energy of 135 keV or 185 keV and a dose rate of 4 × 10 13 cm -2 . Germanium is implanted under the following conditions: acceleration energy of 30 keV and dose level of 5 × 10 14 cm -2 Carbon is implanted under the following conditions: acceleration energy of 5 keV and dose level of 5 × 10 14 cm -2Boron is implanted under the following conditions: acceleration energy of 20 keV and dose level of 1.8 × 10 13 cm -2 Boron fluoride is implanted under the following conditions: acceleration energy of 25 keV and dose level of 6 × 10 12 cm -2 Boron fluoride is implanted under the following conditions: acceleration energy of 10 keV and dose level of 3.0 × 10 12 cm -2 . In the step of Fig. 26, the p-type well region 6a, impurity region 47, and impurity region 57 are formed in the semiconductor substrate 2 by implanting an impurity each under such conditions. Thereafter, the step of Fig. 28 and the subsequent steps are carried out without going through the step of Fig. 27. When such an approach is adopted, the threshold voltage of the memory transistor 40 becomes slightly high compared to the approach described above ( Fig. 26 and Fig. 27) in which an additional impurity implantation is performed to obtain the impurity region 47. However, because the power consumption requirement of the entire semiconductor device 1E is relaxed, it is possible to overcome such a problem by increasing the read voltage of the memory transistor 40.

[0141] Furthermore, if the constraint on the leakage current is relaxed and the impurity region 57 of the logic transistor 50 can be made to have a higher impurity concentration, the following approach can be used. Namely, in the step of Fig. 26, an impurity implantation is performed simultaneously on the semiconductor substrate 2 of the element region 40b and the element region 50b under such conditions to obtain the impurity region 47 with a concentration optimal for the memory transistor 40. Accordingly, the impurity region 47 with a concentration optimal for the memory transistor 40 is formed in the semiconductor substrate 2 of the element region 40b, and the impurity region 57 with a concentration equal to that of the impurity region 47 is formed in the semiconductor substrate 2 of the element region 50b of the logic transistor 50. Thereafter, the step of Fig. 28 and the subsequent steps are carried out without going through the step of Fig. 27. If the constraint on the leakage current of logic transistor 50 is relaxed, such an approach can be used.

[0142] Furthermore, if the constraint on the leakage current is relaxed and the impurity region 57 of the logic transistor 50 can be made to have a higher impurity concentration, the following approach can be used. Namely, in the step of Fig. 26, an impurity implantation is performed under such conditions to have an impurity region with a concentration higher than the optimum ultra-low leakage concentration for the logic transistor 50, and to obtain an impurity region with a concentration lower than the optimum concentration for the memory transistor 40. Under such conditions, the impurity implantation is performed simultaneously on the semiconductor substrate 2 of the element region 40b and the element region 50b to form the impurity region 47 with a lower concentration and the impurity region 57 with a higher concentration compared with the approach described above ( Fig. 26 and Fig. 27). After that, the step of Fig. 28 and the subsequent steps are carried out without going through the step of Fig. 27. If the constraint on the leakage current of logic transistor 50 is relaxed, such an approach can be used.

[0143] In each of the approaches described above for the impurity region 47 and impurity region 57, the step of additional impurity implantation, as in Fig. 27 can be omitted to reduce the manufacturing steps of the semiconductor device 1E.

[0144] Although a memory transistor 40 is illustrated here, note that the semiconductor device 1E may include a plurality of memory transistors 40 or at least one memory transistor 40 and another memory transistor. Furthermore, although a logic transistor 50 is illustrated here, the semiconductor device 1E may include a plurality of logic transistors 50 or at least one logic transistor 50 and another logic transistor. Furthermore, although an I / O transistor 30 is illustrated here, the semiconductor device 1E may include a plurality of I / O transistors 30 or at least one I / O transistor 30 and another I / O transistor.

[0145] Next, a sixth embodiment will be described.

[0146] Fig. 32 illustrates a first configuration example of a semiconductor device according to the sixth embodiment. Fig. 32 schematically illustrates the cross section of a main part of the first embodiment example of the semiconductor device.

[0147] One in Fig. 32 is different from the semiconductor device 1D described in the above fourth embodiment ( Fig. 25) in that it includes the memory transistor 40 with the sidewall insulating layer 43 having the width W1 greater than the width W2 of the sidewall insulating layer 23 of the logic transistor 20. Note that the sidewall insulating layer 43 is formed with a stacked structure of the oxide layer 43a and nitride layer 43b in Fig. 32 is illustrated.

[0148] The like in Fig. 32 can be obtained by, for example, forming each element according to the example of the steps of Fig. 8 to Fig. 13 described in the above third embodiment, after performing the steps of Fig. 14 to Fig. 17 described in the above fourth embodiment.

[0149] The steps of Fig. 14 to Fig. 17 is first performed to obtain the semiconductor substrate 2 as shown in the above Fig. 17, with the element region 40b of the memory transistor 40, the element region 30b of the I / O transistor 30, and the element region 20b of the logic transistor 20, each element region being defined by the element isolation region 3. The element region 40b of the memory transistor 40 includes the well region 6a, the impurity region 47, and the channel region 46 (semiconductor layer 8). The element region 30b of the I / O transistor 30 includes the well region 6b. The element region 20b of the logic transistor 20 includes the well region 6b and the channel region 26. The well region 6a, the well region 6b, and the impurity region 47 are each of a p-type, for example.

[0150] Then, according to the example of Fig. 8 the gate insulating layer 41 (the gate insulating layer 11 of Fig. 8), gate insulating film 31 and gate insulating film 21, each having a predetermined film thickness, are formed in the element region 40b, the element region 30b and the element region 20b, respectively, and then the polysilicon 4 is formed on these gate insulating films.

[0151] Next, following the example of Fig. 9, the polysilicon 4 is patterned or structured to form the gate electrode 42 (the gate electrode 12 of Fig. 9 corresponding element) of the memory transistor 40.

[0152] According to the example of Fig. 10, the LDD region 45a and LDD region 45b of the memory transistor 40 (elements corresponding to the LDD region 15a and LDD region 15b of Fig. 10) are formed by impurity implantation. The LDD region 45a and LDD region 45b, for example, are of an n-type.

[0153] According to the example of Fig. 11, the oxide layer 43a and the nitride layer 43b (elements added to the oxide layer 13a and the nitride layer 13b of Fig. 11) and etched back. Accordingly, the sidewall insulating layer 43 (corresponding to the sidewall insulating layer 13 of Fig. 11 corresponding element) of the memory transistor 40 with the predetermined width W1.

[0154] According to the example of Fig. 12, the polysilicon 4 of the element region 30b and element region 20b is next patterned to form the gate electrode 32 of the I / O transistor 30 and the gate electrode 22 of the logic transistor 20.

[0155] Next, following the example of Fig. 13, the LDD region 35a and LDD region 35b are formed in the semiconductor substrate 2 of the element region 30b, and the LDD region 25a and LDD region 25b are formed in the semiconductor substrate 2 of the element region 20b. The LDD region 35a and LDD region 35b and the LDD region 25a and LDD region 25b are each of an n-type, for example. In addition, the sidewall insulating layer 33 and sidewall insulating layer 23 are formed on the sidewall of the gate electrode 32 of the element region 30b and on the sidewall of the gate electrode 22 of the element region 20b, respectively, by forming and etching back an insulating layer. Then, the impurity region 44a and impurity region 44b (elements corresponding to the impurity region 14a and impurity region 14b of Fig. 13), which function as the source region or drain region of the memory transistor 40, are formed in the element region 40b by impurity implantation. Similarly, the impurity region 34a and impurity region 34b, which function as the source region or drain region of the I / O transistor 30, are formed in the element region 30b by impurity implantation, and the impurity region 24a and impurity region 24b, which function as the source region or drain region of the logic transistor 20, are formed in the element region 20b. The impurity region 44a and impurity region 44b, the impurity region 34a and impurity region 34b, and the impurity region 24a and impurity region 24b are each of an n-type, for example.

[0156] With such steps, the Fig. 32 is obtained. Thereafter, the formation of an interlayer insulating film, the formation of a plug, and the formation of an upper wiring layer including conductors, such as wiring and via, and the like, are performed.

[0157] In the semiconductor device 1Fa of the first configuration example according to the sixth embodiment, the channel region 46 with a lower impurity concentration is provided in the memory transistor 40, and the impurity region 47 with a relatively high concentration is provided below the channel region 46. Moreover, the width W1 of the sidewall insulating layer 43 of the logic transistor 40 is set to be larger than the width W2 of the sidewall insulating layer 23 of the logic transistor 20 (and the sidewall insulating layer 33 of the I / O transistor 30). These configurations contribute to an improvement in the programming speed of the memory transistor 40, as described in the above first and second embodiments. Adopting these configurations makes it possible to realize the semiconductor device 1Fa provided with the memory transistor 40 having an excellent programming speed.

[0158] Although a memory transistor 40 is illustrated here, note that the semiconductor device 1Fa may include a plurality of memory transistors 40 or at least one memory transistor 40 and another memory transistor. Furthermore, although a logic transistor 20 is illustrated here, the semiconductor device 1Fa may include a plurality of logic transistors 20 or at least one logic transistor 20 and another logic transistor. Further, although an I / O transistor 30 is illustrated here, the semiconductor device 1Fa may include a plurality of I / O transistors 30 or at least one I / O transistor 30 and another I / O transistor.

[0159] Fig. 33 illustrates a second configuration example of the semiconductor device according to the sixth embodiment. Fig. 33 illustrates the cross section of a main part of the second embodiment example of the semiconductor device.

[0160] One in Fig. 33 is different from the semiconductor device 1E ( Fig. 31) described in the above fifth embodiment is that it includes the memory transistor 40 with the sidewall insulating layer 43 having the width W1 greater than the width W2 of the sidewall insulating layer 53 of the logic transistor 50. Note that the sidewall insulating layer 43 is formed with a stacked structure of the oxide layer 43a and nitride layer 43b in Fig. 33 is illustrated.

[0161] The like in Fig. 33 can be obtained, for example, by forming each element according to the example of the steps of Fig. 8 to Fig. 13 described in the above third embodiment, after performing the steps of Fig. 26 to Fig. 29 described in the above fifth embodiment.

[0162] The steps of Fig. 26 to Fig. 29 is first carried out to obtain the semiconductor substrate 2 as shown in Fig. 29 illustrates the element region 40b of the memory transistor 40, the element region 30b of the I / O transistor 30, and the element region 50b of the logic transistor 50, each element region being defined by the element isolation region 3. The element region 40b of the memory transistor 40 includes the well region 6a, the impurity region 47, and the channel region 46 (semiconductor layer 8a). The element region 30b of the I / O transistor 30 includes the well region 6b. The element region 20b of the logic transistor 20 includes the well region 6a, the impurity region 57, and the channel region 56 (semiconductor layer 8a). The well region 6a, the well region 6b, the impurity region 47, and the impurity region 57 are each of a p-type, for example.

[0163] Subsequently, the gate insulating layer 41 (the gate insulating layer 11 of Fig. 8 corresponding element), gate insulating layer 31 and gate insulating layer 51 (the gate insulating layer 21 of Fig. 8 corresponding element), each having a predetermined layer thickness, in the element region 40b, the element region 30b and the element region 50b respectively according to the example of Fig. 8 is formed. In addition, the polysilicon 4 is formed on these gate insulating layers.

[0164] Next, following the example of Fig. 9, the polysilicon 4 is patterned or structured to form the gate electrode 42 (the gate electrode 12 of Fig. 9 corresponding element) of the memory transistor 40.

[0165] Next, following the example of Fig. 10 the LDD region 45a and LDD region 45b (elements corresponding to the LDD region 15a and LDD region 15b of Fig. 10) of the memory transistor 40 are formed by impurity implantation. The LDD region 45a and LDD region 45b are, for example, n-type.

[0166] Next, following the example of Fig. 11 the oxide layer 43a and the nitride layer 43b (elements added to the oxide layer 13a and the nitride layer 13b of Fig. 11) and etched back. Accordingly, the sidewall insulating layer 43 (corresponding to the sidewall insulating layer 13 of Fig. 11 corresponding element) of the memory transistor 40 with the predetermined width W1.

[0167] Next, following the example of Fig. 12, the polysilicon 4 of the element region 30b and element region 20b is patterned to form the gate electrode 32 of the I / O transistor 30 and the gate electrode 52 (the gate electrode 22 of Fig. 12 corresponding element) of the logic transistor 50.

[0168] Next, following the example of Fig. 13, the LDD region 35a and LDD region 35b are formed in the semiconductor substrate 2 of the element region 30b, and the LDD region 55a and LDD region 55b (elements corresponding to the LDD region 25a and LDD region 25b of Fig. 13) are formed in the semiconductor substrate 2 of the element region 50b. The LDD region 35a and LDD region 35b and the LDD region 55a and LDD region 55b are each of an n-type, for example. In addition, the sidewall insulating layer 33 and sidewall insulating layer 53 (the sidewall insulating layer 23 of Fig. 13) on the sidewall of the gate electrode 32 of the element region 30b and on the sidewall of the gate electrode 52 of the element region 50b, respectively, by forming and etching back an insulating layer. Then, the impurity region 44a and impurity region 44b (elements corresponding to the impurity region 14a and impurity region 14b of Fig. 13), which function as the source region or drain region of the memory transistor 40, are formed in the element region 40b by impurity implantation. Similarly, the impurity region 34a and impurity region 34b, which function as the source region or drain region of the I / O transistor 30, are formed in the element region 30b by impurity implantation. The impurity region 54a and impurity region 54b (elements corresponding to the impurity region 24a and impurity region 24b of Fig. 13), which function as the source region or drain region of the logic transistor 50, are formed in the element region 50b. The impurity region 44a and impurity region 44b, the impurity region 34a and impurity region 34b, and the impurity region 54a and impurity region 54b are each of an n-type, for example.

[0169] With these steps, the Fig. 33 is obtained. Thereafter, the formation of an interlayer insulating film, the formation of a plug, and the formation of an upper wiring layer including conductors, such as wiring and via, and the like, are performed.

[0170] In the semiconductor device 1Fb of the second configuration example according to the sixth embodiment, the channel region 46 with a lower impurity concentration is provided in the memory transistor 40, and the impurity region 47 with a relatively high concentration is provided below the channel region 46. Moreover, the width W1 of the sidewall insulating layer 43 of the memory transistor 40 is set to be larger than the width W2 of the sidewall insulating layer 23 of the logic transistor 20 (and the sidewall insulating layer 33 of the I / O transistor 30). These configurations contribute to an improvement in the programming speed of the memory transistor 40, as described above in the above first and second embodiments.Furthermore, in the logic transistor 50, as with the memory transistor 40, the channel region 56 with a lower impurity concentration is provided, and the impurity region 57 with a relatively high concentration is provided below the channel region 56, thereby achieving a reduction in the variation of the threshold voltage, a reduction in power consumption, and the like. Adopting these configurations makes it possible to realize the semiconductor device 1Fb provided with the memory transistor 40 having excellent programming speed and the logic transistor 50 having excellent operating performance.

[0171] Although one memory transistor 40 is illustrated here, note that the semiconductor device 1Fb may include a plurality of memory transistors 40 or at least one memory transistor 40 and another memory transistor. Furthermore, although one logic transistor 50 is illustrated here, the semiconductor device 1Fb may include a plurality of logic transistors 50 or at least one logic transistor 50 and another logic transistor. Furthermore, although one I / O transistor 30 is illustrated here, the semiconductor device 1Fb may include a plurality of I / O transistors 30 or at least one I / O transistor 30 and another I / O transistor.

[0172] Next, a seventh embodiment will be described.

[0173] In order to increase the generation of hot carriers in the memory transistor 40 provided with the impurity region 47 having a relatively high concentration under the channel region 46 having a low impurity concentration, for example, the following approach can be adopted: that is, an approach to steepen the concentration distribution of the impurity region 44a and impurity region 44b functioning as the source region or drain region of the memory transistor 40. In order to steepen the concentration distribution of the impurity region 44a and impurity region 44b of the memory transistor 40, for example, the Fig. 34 and Fig. 35 illustrated steps are carried out.

[0174] Fig. 34 and Fig. 35 illustrate an example of the method for manufacturing a semiconductor device according to the seventh embodiment. Here, Fig. 34 is an exemplary schematic cross-sectional view of a main portion of the first manufacturing step, while Fig. 35 is an exemplary schematic cross-sectional view of the main portion of the second manufacturing step. Hereinafter, an example of the manufacturing steps of the semiconductor device according to the seventh embodiment will be described sequentially with reference to Fig. 34 and Fig. 35 are described.

[0175] Here, a case is taken as an example where the concentration distribution of the impurity region 44a and impurity region 44b of the memory transistor 40 of the semiconductor device 1Fb ( Fig. 33), which was taken as the second configuration example in the above sixth embodiment, is made steeper. In this case, impurity implantation with respect to the element region 40b of the memory transistor 40 and impurity implantation with respect to the element region 30b of the I / O transistor 30 and with respect to the element region 50b of the logic transistor 50 are performed in separate steps, not simultaneously (collectively).

[0176] For example, after forming the sidewall insulating layer 33, sidewall insulating layer 43 and sidewall insulating layer 53, a resist pattern 5p covering the element region 40b of the memory transistor 40 is first formed as shown in Fig. 34. With the resist pattern 5p used as a mask, impurity implantation is performed to form the impurity region 34a and impurity region 34b of the I / O transistor 30 and the impurity region 54a and impurity region 54b of the logic transistor 50. This impurity implantation is performed by, for example, implanting phosphorus under the conditions: the acceleration energy of 8 keV and the dose amount of 1 × 10 16 cm -2 .

[0177] Next, the resist pattern 5p is removed and, as shown in Fig. As illustrated in Figure 35, a resist pattern 5q is formed covering the element region 30b of the I / O transistor 30 and the element region 50b of the logic transistor 50. With the resist pattern 5q used as a mask, impurity implantation is performed to form the impurity region 44a and impurity region 44b of the memory transistor 40. This impurity implantation is performed by, for example, implanting arsenic under the conditions of an acceleration energy of 5 keV and a dose rate of 5 × 10 15 cm -2 . Using such conditions makes it possible to obtain the impurity region 44a and impurity region 44b, each having a steeper concentration distribution than that of the impurity region 34a and impurity region 34b of the I / O transistor 30 and that of the impurity region 54a and impurity region 54b of the logic transistor 50. The resist pattern 5q is removed after the impurity implantation.

[0178] Performing such steps makes it possible to realize a semiconductor device (non-volatile memory) provided with the memory transistor 40 including the impurity region 44a and impurity region 44b with a steeper concentration distribution and capable of increasing the generation of hot carriers.

[0179] Although a memory transistor 40 is illustrated here, it should be noted that the semiconductor device described above may include a plurality of memory transistors 40 or at least one memory transistor 40 and another memory transistor. Furthermore, although a logic transistor 50 is illustrated here, the semiconductor device described above may include a plurality of logic transistors 50 or at least one logic transistor 50 and another logic transistor. Furthermore, although an I / O transistor 30 is illustrated here, the semiconductor device described above may include a plurality of I / O transistors 30 or at least one I / O transistor 30 and another I / O transistor.

[0180] Here, a case has been taken and described as an example where the concentration distribution of the impurity region 44a and impurity region 44b of the memory transistor 40 of the semiconductor device 1Fb ( Fig. 33), which was taken as the second configuration example in the sixth embodiment, is steepened. The approach of steepening the concentration distribution of an impurity region in this way is also easily applicable to the memory transistor 10 described in the third embodiment and to the memory transistor 40 described in the fourth and fifth embodiments and described in the first configuration example of the sixth embodiment, to obtain the same effect as the above-described effect.

[0181] Next, an eighth embodiment will be described.

[0182] Further, a relatively high-concentration impurity region (embedded high-concentration layer) may be provided under the channel region of the above-described memory transistor or under the relatively high-concentration impurity region provided under the channel region. As the eighth embodiment, a semiconductor device having a memory transistor provided with such an embedded high-concentration layer will be described.

[0183] Fig. 36 to Fig. 39 illustrate an example of the method for manufacturing the semiconductor device according to the eighth embodiment. Here, Fig. 36 is an exemplary schematic cross-sectional view of a main portion of the first manufacturing step, Fig. 37 is an exemplary schematic cross-sectional view of the main portion of the second manufacturing step, Fig. 38 is an exemplary schematic cross-sectional view of the main portion of the third manufacturing step and is Fig. 39 is an exemplary schematic cross-sectional view of the main part of the fourth manufacturing step. Hereinafter, an example of the manufacturing steps of the semiconductor device according to the eighth embodiment will be described sequentially with reference to Fig. 36 to Fig. 39 are described.

[0184] Here, a case is taken as an example where the embedded high concentration layer under the impurity region 47 of the memory transistor 40 of the semiconductor device 1Fb ( Fig. 33) which is taken as the second configuration example in the sixth embodiment.

[0185] In this case, the first step is Fig. 26 is performed to form the well region 6a, the impurity region 47 having a relatively high concentration of the memory transistor 40, and the impurity region 57 having a relatively high concentration of the logic transistor 50 in the semiconductor substrate 2. The well region 6a, the impurity region 47, and the impurity region 57 are each of a p-type, for example.

[0186] Then, as in Fig. 36 illustrates, a resist pattern 5r in which the element region 40b of the memory transistor 40 is opened is formed on the semiconductor substrate 2. With the resist pattern 5r used as a mask, impurity implantation is performed on the semiconductor substrate 2 of the element region 40b. In this impurity implantation, an impurity of the same conductivity type as the impurity region 47 and well region 6a, for example, a p-type impurity, is implanted if the impurity region 47 and the well region 6a are p-type. For the impurity implantation, for example, boron is implanted under the conditions: the acceleration energy of 20 keV and the dose amount of 2.5 × 10 11 cm -2 , and is implanted under the conditions: the acceleration energy of 200 keV and the dose level of 1 × 10 14 cm -2. With this impurity implantation, the embedded high concentration layer 48 is formed under the impurity region 47.

[0187] After forming the embedded high concentration layer 48 in this way, a semiconductor material is epitaxially grown on the semiconductor substrate 2 to form a semiconductor layer 8b (non-doped layer) on the impurity region 47 of the element region 40b and on the impurity region 57 of the element region 50b, as shown in Fig. 37. The channel region 46 of the memory transistor 40 and the channel region 56 of the logic transistor 50 are formed in the semiconductor layer 8b. Although a semiconductor layer similar to the semiconductor layer 8b of the element region 40b and element region 50b is also formed in the element region 30b due to epitaxial growth, note that for convenience, the former semiconductor layer is described here as the layer integrated into the semiconductor substrate 2. After the formation of the semiconductor layer 8b, the element isolation region 3 is formed, which defines the element region 40b, the element region 30b, and the element region 50b, as shown in Fig. 37 illustrates.

[0188] Next, as in Fig. 38 illustrates, with a resist pattern 5u in which the element region 30b is opened, which is used as a mask, an impurity implantation is performed to form the well region 6b in the semiconductor substrate 2 of the element region 30b. The well region 6b is, for example, of a p-type. Subsequently, an impurity implantation for adjusting the threshold voltage of the I / O transistor 30 may be performed on the semiconductor substrate 2 of the element region 30b.

[0189] Thereafter, as described in the second embodiment example according to the above sixth embodiment, each element is processed according to the example of the steps of Fig. 8 to Fig. 13 described in the third embodiment to obtain a semiconductor device 1G (non-volatile memory) as shown in Fig. 39. Thereafter, the formation of an interlayer insulating layer, the formation of a plug, and the formation of an upper wiring layer including the conductors, such as a wiring and a via, and the like, are performed.

[0190] Although one memory transistor 40 is illustrated here, note that the semiconductor device 1G may include a plurality of memory transistors 40 or at least one memory transistor 40 and another memory transistor. Furthermore, although one logic transistor 50 is illustrated here, the semiconductor device 1G may include a plurality of logic transistors 50 or at least one logic transistor 50 and another logic transistor. Furthermore, although one I / O transistor 30 is illustrated here, the semiconductor device 1G may include a plurality of I / O transistors 30 or at least one I / O transistor 30 and another I / O transistor.

[0191] In the semiconductor device 1G according to the eighth embodiment, the embedded high-concentration layer 48 is further provided under the impurity region 47 having a relatively high concentration provided under the channel region 46 of the memory transistor 40. In the semiconductor device 1G, the provision of the embedded high-concentration layer 48 makes it possible to achieve a reduction in the resistance (well resistance) when applying a bias (substrate bias) to the semiconductor substrate 2. Reducing the well resistance makes it possible to achieve a reduction in the substrate bias for application.

[0192] Furthermore, reducing the well resistance makes it possible to reduce the area of ​​the memory region of the semiconductor device 1G and reduce the size of the semiconductor device 1G. This is due to the following reason.

[0193] Namely, in the memory region of the semiconductor device 1G, a well tap region electrically connected to the well region in the semiconductor substrate 2 is provided on the semiconductor substrate, and a substrate bias is applied from the well tap region on the semiconductor substrate 2 to the well region in the semiconductor substrate 2. The memory region typically includes memory transistors 40 in a number corresponding to the memory capacity. The well region is shared by a certain number of memory transistors 40, and the substrate bias is applied from a well tap region to the well region shared by the certain number of memory transistors 40. Accordingly, well tap regions are arranged on the semiconductor substrate 2 in a number corresponding to a total number of memory transistors 40 included in the memory region.

[0194] If the well resistance is reduced by providing the well region 6a and the embedded high concentration layer 48 in the semiconductor substrate 2 as described above, a certain substrate bias can be applied from a well drain region to a wider area of ​​a well region 6a and embedded high concentration layer 48. If the area in which a certain substrate bias can be applied from a well drain region expands, the number of memory transistors 40 to which a certain substrate bias can be applied from a well drain region can be increased. If the number of memory transistors 40 to which a certain substrate bias can be applied from a well drain region can be increased, a total number of well drain regions arranged on the semiconductor substrate 2 can be reduced.If the total number of well drain regions can be reduced, the area occupied by the well drain region on the semiconductor substrate 2 can be reduced, and accordingly, the area of ​​a memory region can be reduced. Furthermore, reducing the area of ​​a memory region makes it possible to achieve a reduction in the size of the semiconductor device 1G provided with the memory region.

[0195] Here, a case has been described where the embedded high concentration layer 48 under the impurity region 47 of the memory transistor 40 of the semiconductor device 1Fb ( Fig. 33) taken as the second configuration example in the above sixth embodiment. The approach of providing the embedded high concentration layer 48 can be similarly applied to the memory transistor 40 described in the fourth and fifth embodiments, the first configuration example of the sixth embodiment, and the seventh embodiment, and the same effect as the above-described effect is obtained. Moreover, the approach of providing the embedded high concentration layer can also be applied to the above-described memory transistor 10, logic transistor 20, logic transistor 50, and I / O transistor 30, and accordingly, a reduction in the size of the semiconductor device can be achieved.

[0196] When a transistor not provided with the impurity regions 47 (shield (SCR) layer) as described above is used as the memory transistor of a non-volatile memory, the layout of the memory cell array may be limited.

[0197] Here illustrated Fig. 40 a memory transistor of a comparative example. Fig. 40 schematically illustrates an exemplary cross-section of a main portion of the memory transistor.

[0198] One in Fig. The memory transistor 40B illustrated in FIG. 40 includes a gate insulating layer 41 provided over the semiconductor substrate 2, a gate electrode 42 provided over the gate insulating layer 41, and a sidewall insulating layer 43 provided on the sidewall of the gate electrode 42 and over the semiconductor substrate 2. The sidewall insulating layer 43 has a stacked structure of an oxide layer 43a of silicon oxide or the like and a nitride layer 43b of silicon nitride or the like. The memory transistor 40B further includes impurity regions 44a and 44b provided in the semiconductor substrate 2 on both sides of the gate electrode 42, respectively, and functioning as a source region or a drain region (SD region). The memory transistor 40B also includes LDD regions 45a and 45b within the impurity regions 44a and 44b, which function as the SD region, in the semiconductor substrate 2 under the sidewall insulating layer 43.The region between the LDD regions 45a and 45b serves as a channel region 46B in which a charge carrier moves.

[0199] For example, in the case of the n-channel memory transistor 40B, information is written by injecting and accumulating the hot electrons (hot carriers 49) generated in the vicinity of the impurity region 44b (drain region) into the sidewall insulating layer 43. In addition, information is erased by neutralizing the electrons injected and accumulated in the sidewall insulating layer 43 with the hot holes (hot carriers 49) generated in the vicinity of the impurity region 44b.

[0200] In the memory transistor 40B, in order to efficiently generate the hot carriers 49 near the impurity region 44b, a p-type impurity is implanted into the surface of the semiconductor substrate, in which the channel region 46B is formed. In the semiconductor substrate 2 under the sidewall insulating layer 43, an n-type impurity is implanted together with the p-type impurity, so that the p-type impurity is canceled by a part of the n-type impurity, and the n-type impurity regions 45a and 45b are formed. To stably form the n-type impurity regions 45a and 45b in the semiconductor substrate 2 under the sidewall insulating layer 43, the concentration of the n-type impurity must be set sufficiently high relative to the concentration of the p-type impurity. Therefore, the concentration of the n-type impurity must not be too low.As a result, only a characteristic difference of an on-current ratio, which differs on the order of one digit, is obtained between the memory transistor 40B with the information written therein and the memory transistor 40B without any information written therein. The on-current ratio converted into a threshold voltage is very small, i.e., on the order of 0.1 V.

[0201] In addition, an evaluated variation value AVT of the threshold voltage of the memory transistor 40B is on the order of 10 mVµm or more. Note that the evaluated variation value AVT of the threshold voltage is the gradient (mVµm) of a Pelgrom plot (which is the standard deviation σ(mV) of the threshold voltage plotted against the inverse number (µm -1) of the square root of the gate area (channel length L × channel width W)). Assuming that W / L of the memory transistor 40B is 0.1 µm / 0.1 µm, the variation of the threshold voltage is 0.1 V as one σ and is thus 5σ = 0.5 V in a 1M-bit memory cell array, which significantly exceeds a shift in the threshold voltage before and after programming. When attempting to create a non-volatile memory using the memory transistor 40B as shown in Fig. 40, it is therefore difficult to adopt a NOR type layout for the memory cell array.

[0202] As a layout that makes it possible to stably read information even in a memory cell array using the memory transistor 40B, a twin-bit cell type layout as shown in Fig. 41 illustrates, should be considered.

[0203] Fig. 41 illustrates an example of the twin-bit cell type non-volatile memory. Fig. 41 schematically illustrates an exemplary planar layout of the main portion of the twin-bit cell type non-volatile memory.

[0204] One in Fig. 41 illustrated non-volatile memory 60 (semiconductor device) includes as the element region (element region of the semiconductor substrate 2 of Fig. 40) a plurality of (for example, four) active regions 61a, 61b, 61c and 61d extending in a direction S and arranged in parallel in a direction T perpendicular to the direction S. Word lines WL1 and WL2 (corresponding to the gate electrode 42 of Fig. 40) extend, via a non-illustrated gate insulating layer (corresponding to the gate insulating layer 41 of Fig. 40), in the direction T, to span these active regions 61a, 61b, 61c and 61d. A sidewall insulating layer 63 (corresponding to the sidewall insulating layer 43 of Fig. 40) is formed on the sidewall of the word lines WL1 and WL2. Impurity regions 64 (corresponding to the impurity regions 44a and 44b of Fig. 40) functioning as the SD region are formed on both sides of the word lines WL1 and WL2 of each of these active regions 61a, 61b, 61c, and 61d, respectively. Non-illustrated LDD regions (corresponding to the impurity regions 45a and 45b of Fig. 40) are formed under the sidewall insulating layer 63 and on the inside of the impurity region 64, and a non-illustrated channel region is formed between the LDD regions. The non-volatile memory 60 includes a plurality of (for example, eight) memory transistors 70a, 70b, 70c, 70d, 70e, 70f, 70g, and 70h (corresponding to the memory transistor 40B of Fig. 40), which is formed from these elements.

[0205] A plug 71 (contact) extending toward the upper layer is formed on each impurity region 64. Each impurity region 64 is connected via the plug 71 to wirings 72a, 72b, and 72c included in the first conductive layer.

[0206] The wiring 72a has a planar cross-sectional shape including a region 72aa extending in the S direction and a region 72ab extending in the T direction. The region 72aa extends in the S direction between the adjacent active regions 61a and 61b. The region 72ab extends in the T direction to connect the impurity region 64 shared by the memory transistors 70a and 70b of the active region 61a and the impurity region 64 shared by the memory transistors 70c and 70d of the active region 61b.

[0207] The wiring 72b has a planar crisscross shape, including a region 72ba extending in the S direction and a region 72bb extending in the T direction. The region 72ba extends in the S direction between the adjacent active regions 61c and 61d. The region 72bb extends in the T direction to connect the impurity region 64 shared by the memory transistors 70e and 70f of the active region 61c and the impurity region 64 shared by the memory transistors 70g and 70h of the active region 61d. The wiring 72c is connected via the connector 71 to the impurity region 64 on the opposite side of the impurity region 64, which is connected to the wirings 72a and 72b of each of the memory transistors 70a, 70b, 70c, 70d, 70e, 70f, 70g and 70h.

[0208] A via 73 extending to the upper layer is formed on each of the wirings 72a, 72b, and 72c. The wiring 72a is connected to a source line SL1 extending in the direction S via the via 73. The wiring 72b is connected to a source line SL2 extending in the direction S via the via 73. The wiring 72c, which is connected to the impurity region 64 of the transistors 70a and 70b of the active region 61a, is connected to a bit line BL1 extending in the direction S via the via 73. The wiring 72c, which is connected to the impurity region 64 of the transistors 70c and 70d of the active region 61b, is connected to a bit line / BL1 extending in the direction S via the via 73.The wiring 72c, which is connected to the impurity region 64 of the transistors 70e and 70f of the active region 61c, is connected via the via 73 to a bit line BL2 extending in the direction S. The wiring 72c, which is connected to the impurity region 64 of the transistors 70g and 70h of the active region 61d, is connected via the via 73 to a bit line / BL2 extending in the direction S. The source lines SL1 and SL2 and the bit lines BL1, / BL1, BL2, and / BL2 are included in the second conductive layer of the non-volatile memory 60.

[0209] In the non-volatile memory 60 of the twin-bit cell type, a pair of memory transistors 70a and 70c functions, for example, through a frame 74 of Fig. 41, as one memory cell. In the memory cell within the frame 74, mutually opposite pieces of information are written into the memory transistors 70a and 70c connected to the bit lines BL1 and / BL1, and then the information of one memory cell is read by differentially driving the memory transistors 70a and 70c. Similarly, in the non-volatile memory 60, a pair of memory transistors 70b and 70d, a pair of memory transistors 70e and 70g, and a pair of memory transistors 70f and 70h each function as a memory cell.

[0210] An example of each of the programming (writing), reading and erasing operations of information in the non-volatile memory 60 will be specifically described with reference to Fig. 42, Fig. 43 and Fig. 44. Note here that the non-volatile memory 60 provided with the n-channel memory transistors 70a, 70b, 70c, 70d, 70e, 70f, 70g, and 70h is taken as an example.

[0211] Fig. Fig. 42 is an explanatory view of the programming operation of the twin-bit cell type non-volatile memory.

[0212] During the programming operation, for example, with respect to the memory cell (within frame 74) having the pair of memory transistors 70a and 70c, the potential of word line WL1 is set to a high level, the potential of bit line BL1 is set to a low level, the potential of bit line / BL1 is set to a high level, and the potential of a source line SL1 is set to a high level. The potential of word line WL2 is set to a low level, the potential of each of bit lines BL2 and / BL2 is set to a low level, and the potential of a source line SL2 is set to a low level. Accordingly, hot electrons (hot carriers 49, electric charges 49a) are injected and accumulated in the sidewall insulating layer 63 of the memory transistor 70a, thereby performing information programming.

[0213] Fig. 43 is an explanatory view of the read operation of the twin-bit cell type non-volatile memory.

[0214] During the read operation with respect to the memory cell (within frame 74) with the memory transistors 70a and 70c, the potential of the word line WL1 is set to a high level, the potential of each of the bit lines BL1 and / BL1 is set to a high level, and the potential of the source line SL1 is set to a low level. The potential of the word line WL2 is set to a low level, the potential of each of the bit lines BL2 and / BL2 is set to a low level, and the potential of the source line SL2 is set to a low level. In the memory cell with the memory transistor 70a, where programming has been performed as in the above Fig. 42, when such potentials are set, the currents flowing through bit lines BL1 and / BL1, which are connected to memory transistors 70a and 70c, respectively, will differ in magnitude from each other. By detecting a difference in magnitude between the currents, the information of memory transistor 70a is read.

[0215] Fig. 44 is an explanatory view of the erase operation of the twin-bit cell type non-volatile memory.

[0216] During the erase operation on the memory cell (within frame 74) having memory transistors 70a and 70c, the programming operation described above is first performed on memory transistors 70a and 70c (not illustrated). After both memory transistors 70a and 70c of the memory cell are set to a programmed state, the potential of word line WL1 is set to be negative, the potential of each of bit lines BL1 and / BL1 is set to a low level, and the potential of source line SL1 is set to a high level. The potential of word line WL2 is set to a low level, the potential of each of bit lines BL2 and / BL2 is set to a low level, and the potential of source line SL2 is set to a low level.Thus, the information programmed into the two memory transistors 70a and 70c of the memory cell is erased.

[0217] Such a non-volatile memory 60 of the twin-bit cell type is designed to store, for example, the data as shown in the next Fig. 45 illustrated area.

[0218] Fig. 45 is an explanatory view of the area of ​​the twin-bit cell type non-volatile memory.

[0219] We now focus on a memory cell with, for example, the memory transistors 70a and 70c.

[0220] In the S direction of this memory cell, assume that the size (gate length Lg) of word line WL1 is 0.06 µm, half the size of each of the wirings 72a (region 72ab) and 72c connected to the connector 71 is 0.04 µm, and the size between word line WL1 and each of the wirings 72a (region 72ab) and 72c is 0.07 µm. In this case, a size U in the S direction of the memory cell with the memory transistors 70a and 70c results in 0.28 µm (=0.06 µm + 0.04 µm × 2 + 0.07 µm × 2).

[0221] In the T direction of the memory cell, it is assumed that the width and pitch, or height, of each of the interconnections 72a (region 72aa) and 72c total 0.18 µm. In this case, a size V in the T direction of the memory cell with the memory transistors 70a and 70c results in 0.54 µm (=0.18 µm × 3).

[0222] Accordingly, the area of ​​a memory cell with the memory transistors 70a and 70c of the non-volatile memory 60 results in 0.1512 µm 2 (=0.28 µm × 0.54 µm). The same applies to the other memory cells. In the case of the non-volatile 1M-bit memory 60, for example, the total area of ​​the memory region is 1.21 mm 2 , the area of ​​an entire memory macro (including a memory region, an I / O region, and the like in addition to the memory region) results in 3 mm 2 , and thus the occupancy ratio of the storage region is 40%.

[0223] A memory transistor without the SCR layer and a twin-bit cell type non-volatile memory using this memory transistor are described, but in contrast, if a memory transistor with the SCR layer is used, the following advantages are obtained.

[0224] Fig. 46 illustrates an example of a memory transistor according to an embodiment. Fig. 46 schematically illustrates an exemplary cross-section of a main portion of the memory transistor.

[0225] One in Fig. The memory transistor 40C illustrated in FIG. 46 includes the gate insulating layer 41 provided over the semiconductor substrate 2, the gate electrode 42 provided over the gate insulating layer 41, and the sidewall insulating layer 43 provided on the sidewall of the gate electrode 42 and over the semiconductor substrate 2. The sidewall insulating layer 43 has a stacked structure of the oxide layer 43a of silicon oxide or the like and the nitride layer 43b of silicon nitride or the like. The memory transistor 40C further includes the impurity regions 44a and 44b provided in the semiconductor substrate 2 on both sides of the gate electrode 42, respectively, and which function as the SD region. The memory transistor 40C also includes the LDD regions 45a and 45b within the impurity regions 44a and 44b, which function as the SD region, in the semiconductor substrate 2 under the sidewall insulating layer 43.The region between the LDD regions 45a and 45b serves as the channel region 46, in which a charge carrier moves. The memory transistor 40C contains the impurity region 47, as the SCR layer, beneath the channel region 46.

[0226] The channel region 46 of the memory transistor 40C is a non-doped region where any impurity is intentionally not added, or a region where a very low concentration of an impurity is contained. The impurity region 47 under the channel region 46 is a region, for example, a high-concentration p-type region, which has a different conductivity type from the LDD regions 45a and 45b and contains a higher concentration of an impurity than the channel region 46. The dose amount during impurity implantation of the LDD regions 45a and 45b is set to a value lower than the dose amount during impurity implantation of the impurity region 47, which is the SCR layer.

[0227] In the memory transistor 40C, the non-doped or very low concentration channel region 46 achieves a lower threshold voltage and also reduces the threshold voltage variation. The evaluated threshold voltage variation value AVT of the memory transistor 40C is on the order of 4 mVµm, and over the entire 1M-bit memory region, the threshold voltage variation is on the order of 5σ = 0.2 V, which is very small compared to the case where the above-described memory transistor 40B ( Fig. 40) is used.

[0228] In the memory transistor 40C, the relatively high concentration impurity region 47 efficiently generates the hot carriers 49. The LDD regions 45a and 45b under the sidewall insulating layer 43 are formed in the semiconductor layer in which the non-doped or very low concentration channel region 46 is formed ( Fig. 63 and Fig. 64). The semiconductor layer in which the undoped or very low concentration channel region 46 is formed suppresses the diffusion of the impurity, for example, a p-type impurity, from the impurity region 47. Therefore, even if the impurity implantation of the LDD regions 45a and 45b, for example, an implantation of an n-type impurity, is performed under the condition of a lower dose level, the conductivity type of the LDD regions 45a and 45b always results in the conductivity type of the impurity, for example, an n-type, thus not causing any offset. Accordingly, in the memory transistor 40C, a higher on-current can be stably achieved in a state where the electric charge 49a is not trapped in the sidewall insulating layer 43, and a larger variation in the threshold voltage can be caused in a state where the electric charge 49a is trapped in the sidewall insulating layer 43.

[0229] Here is an example of the concentration profile in Fig. 47A to Fig. Figure 47D illustrates when phosphorus is used for the impurity of the LDD region.

[0230] Fig. 47A to Fig. 47D each illustrates the concentration profile obtained by TCAD (Technology Computer Aided Design) when phosphorus for the LDD region was implanted into a semiconductor substrate that formed the SCR layer by impurity implantation ( Fig. 61), which formed the semiconductor layer by epitaxial growth ( Fig. 63) and the gate electrode has been formed via the gate insulating layer ( Fig. 64).

[0231] The following impurity implantation conditions are used in the formation of the SCR layer. Germanium is implanted under the following conditions: acceleration energy of 30 keV and dose level of 5 × 10 14 cm -2Carbon is implanted under the following conditions: acceleration energy of 5 keV and dose level of 5 × 10 14 cm -2 Boron is implanted under the following conditions: acceleration energy of 20 keV and dose level of 4 × 10 13 cm -2 .

[0232] Fig. Figure 47A illustrates the concentration profile when implanting phosphorus under the conditions: acceleration energy of 35 keV and dose level of 2.5 × 10 12 cm -2 is carried out from four directions with an inclination angle of 28° to form the LDD region. Fig. Figure 47B illustrates the concentration profile when implanting phosphorus under the conditions: acceleration energy of 35 keV and dose level of 1.0 × 10 12 cm -2 is carried out from four directions with the inclination angle of 28° to form the LDD region. Fig. Figure 47C illustrates the concentration profile when implanting phosphorus under the conditions: acceleration energy of 35 keV and dose level of 5.0 × 10 11 cm -2 is carried out from four directions with the inclination angle of 28° to form the LDD region. Fig. Figure 47D illustrates the concentration profile when implanting phosphorus under the conditions: acceleration energy of 35 keV and dose level of 2.5 × 10 11 cm -2 is carried out from four directions with the inclination angle of 28° to form the LDD region.

[0233] In Fig. 47A to 47D, the horizontal axis represents the depth (µm) from the surface of the semiconductor substrate, while the vertical axis represents the concentration (cm -3 ) of the p-type and n-type impurities. Note that in Fig. 47A to Fig. 47D the concentration profile of the p-type impurity is drawn with a thick chain line, the concentration profile of the n-type impurity is drawn with a thick solid line, and the cancelled concentration profile of the p-type and n-type impurities is drawn with a thin dotted line.

[0234] As in Fig. For example, as illustrated in Figure 47A, an n-type impurity (phosphorus) implanted to form the LDD region is closer to the front side of the semiconductor substrate than the p-type impurity (boron) implanted to form the SCR layer. Under the implantation conditions of the n-type impurity as shown in Fig. 47A, the n-type LDD region is stably formed near the surface of the semiconductor substrate with the p-type SCR layer formed therein. Even under the implantation conditions of the n-type impurity as in Fig. 47B and Fig. Similarly, in Figure 47C, the n-type impurity is located closer to the front of the semiconductor substrate than the p-type impurity, and the n-type LDD region is stably formed near the surface of the semiconductor substrate with the p-type SCR layer formed therein. Even under the n-type impurity implantation conditions as in Fig. 47D, the n-type LDD region is also formed near the surface of the semiconductor substrate with the p-type SCR layer formed therein. Even at a very low concentration, for example, 1 × 10 17 cm -3 or less, may be Fig. 47A to Fig. 47D, the n-type LDD region may be formed near the surface of the semiconductor substrate with the p-type SCR layer formed therein.

[0235] In addition, Fig. 48A to Fig. Figure 48D illustrates an example of the concentration profile when arsenic is used for the impurity of the LDD region.

[0236] Fig. 48A to Fig. 48D each illustrates the concentration profile obtained by TCAD when arsenic for the LDD region was implanted into a semiconductor substrate that formed the SCR layer by impurity implantation ( Fig. 61), which formed the semiconductor layer by epitaxial growth ( Fig. 63) and which has formed the gate electrode via the gate insulating layer ( Fig. 64).

[0237] The following impurity implantation conditions are used in the formation of the SCR layer. Germanium is implanted under the following conditions: acceleration energy of 30 keV and a dose level of 5 × 10 14 cm -2 Carbon is implanted under the following conditions: acceleration energy of 5 keV and dose level of 5 × 10 14 cm -2 Boron is implanted under the following conditions: acceleration energy of 20 keV and dose level of 4 × 1013 cm -2 .

[0238] Fig. Figure 48A illustrates the concentration profile when implanting arsenic under the conditions: acceleration energy of 10 keV and dose level of 2.5 × 10 12 cm -2 four times with the inclination angle of 0° to form the LDD region. Fig. Figure 48B illustrates the concentration profile when implanting arsenic under the conditions: acceleration energy of 10 keV and dose level of 1.0 × 10 12 cm -2 four times with the inclination angle of 0° to form the LDD region. Fig. Figure 48C illustrates the concentration profile when implanting arsenic under the conditions: acceleration energy of 10 keV and dose level of 5.0 × 10 11 cm -2 four times with the inclination angle of 0° to form the LDD region. Fig. Figure 48D illustrates the concentration profile when implanting arsenic under the conditions: acceleration energy of 10 keV and dose level of 2.5 × 10 11 cm -2 four times with the tilt angle of 0° to form the LDD region.

[0239] In Fig. 48A to 48D, the horizontal axis represents the depth (µm) from the surface of the semiconductor substrate, while the vertical axis represents the concentration (cm -3 ) of the p-type and n-type impurities. Note that in Fig. 48A to Fig. 48D the concentration profile of the p-type impurity is drawn with a thick chain line, the concentration profile of the n-type impurity is drawn with a thick solid line, and the cancelled concentration profile of the p-type and n-type impurities is drawn with a thin dotted line.

[0240] As in Fig. For example, as illustrated in Figure 48A, the n-type impurity (arsenic) implanted to form the LDD region is closer to the front side of the semiconductor substrate than the p-type impurity (boron) implanted to form the SCR layer. Under the implantation conditions of the n-type impurity as shown in Fig. 48A, the n-type LDD region is stably formed near the surface of the semiconductor substrate with the p-type SCR layer formed therein. Even under the implantation conditions of the n-type impurity as in Fig. 48B to Fig. 48D, similarly, the n-type impurity is present closer to the front surface of the semiconductor substrate than the p-type impurity, and the n-type LDD region is stably formed near the surface of the semiconductor substrate with the p-type SCR layer formed therein.

[0241] Fig. Figure 49 illustrates an example of the programming characteristics of the memory transistor with the SCR layer.

[0242] Fig. Fig. 49 illustrates a relationship between the gate voltage Vg(V) and the read current (drain current) Id(A / µm), the relationship being obtained by the read operation before and after programming, of the memory transistor 40C having the impurity region 47 having the voltages shown in the above Fig. 46 is the SCR layer illustrated.

[0243] The programming operation with respect to the memory transistor 40C is performed under the voltage conditions where the impurity region 44a and the semiconductor substrate 2 are both set to 0 V, and the gate electrode 42 and the impurity region 44b are both set to 4 V (programming voltage Vp = 4 V). After the programming operation is performed with a program time Tp = 1 µs under the voltage conditions described above, the reading operation is performed by setting the impurity region 44b and the semiconductor substrate 2 to 0 V and applying a predetermined voltage to the gate electrode 42 and applying 0.5 V (drain voltage Vd = 0.5 V) to the impurity region 44a. The relationship between the gate voltage Vg and the reading current Id during the reading operation is shown in Fig. 49 illustrates.

[0244] The threshold voltage before programming (the initial threshold voltage) of the memory transistor 40C is on the order of 0.5 V. Fig. 49 reveals that in the memory transistor 40C, a sufficient on-current of 0.5 µA or more is obtained even with the gate voltage Vg = 1.0 V. If the programming operation is performed with a relatively low voltage and short time, such as the voltage Vp = 4 V and programming time Tp = 1 µs as described above, with respect to the memory transistor 40C, the threshold voltage after programming will shift to a higher Vg side by about the order of 1 V. The on-current ratio between before programming and after programming is significantly large by about four digits compared with the above-described memory transistor 40B without the SCR layer (impurity region 47).This shift in the threshold voltage in memory transistor 40C before and after programming is significantly greater than the variation in the threshold voltage across the entire memory region in the case of, for example, a 1M-bit memory. Accordingly, memory transistor 40C does not need to adopt the twin-bit cell type design.

[0245] The memory transistor 40C will be described further.

[0246] Fig. 50 illustrates an example of the erase characteristics of the memory transistor with the SCR layer.

[0247] Fig. Fig. 50 illustrates a relationship between the gate voltage Vg(V) and the read current Id(A / µm), the relationship being obtained in the read operation before and after the program operation and after the erase operation, of the memory transistor 40C used in the above Fig. 46, with the impurity region 47 being the SCR layer.

[0248] The programming operation on the memory transistor 40C is performed with the program time Tp set to 1 µs under the voltage conditions where the impurity region 44a and the semiconductor substrate 2 are both set to 0 V, and the gate electrode 42 and the impurity region 44b are both set to 4 V (programming voltage Vp = 4 V). The erase operation after the programming operation is performed with the erase time Te set to 1 ms, 10 ms, 100 ms, and 1 s, respectively, under the voltage conditions where the impurity region 44a and the semiconductor substrate 2 are both set to 0 V, the gate electrode 42 is set to -5 V, and the impurity region 44b is set to 5 V (erase voltage Ve = 5 V).The read operation before and after programming and after erasing is performed by setting the impurity region 44b and the semiconductor substrate 2 to 0 V and applying a predetermined voltage to the gate electrode 42 and applying 0.5 V (drain voltage Vd = 0.5 V) to the impurity region 44a. The relationship between the gate voltage Vg and the read current Id during the read operation is shown in FIG. Fig. 50 illustrates.

[0249] If the programming operation is performed under the conditions: the programming voltage Vp = 4 V and the program time Tp = 1 µs, as in the above Fig. 49, the threshold voltage after programming will shift to a higher Vg side, by the order of 1 V, than before programming (as the initial value).

[0250] Regarding the memory transistor 40C, if the erase operation is performed after programming under the conditions: the erase voltage Ve = 5 V and the erase time of 1 ms, the threshold voltage after the erase operation shifts back, by the order of 0.4 V, to a lower Vg side, as shown in Fig. 50. With respect to the memory transistor 40C, if the erase operation is performed with a longer erase time of 10 ms after programming, the threshold voltage after erasing will return to the value before programming (to the initial value). In the memory transistor 40C, even if the erase operation is performed with an even longer erase time of 100 ms or 1 s after programming, the threshold voltage hardly shifts after erasing, as shown in Fig. 50, and thus the memory transistor 40C will not be in an over-erased state. As described above, in the memory transistor 40C having the SCR layer (impurity region 47), an excellent erase operation can be performed under the conditions: the erase voltage Ve = 5 V, the erase time 10 ms or more.

[0251] Fig. 51A and Fig. 51B to Fig. 53A and Fig. 53B each illustrates the LDD region concentration dependence of the programming characteristics of the memory transistor with the SCR layer.

[0252] Fig. Figure 51A illustrates the programming characteristics of memory transistor 40C in the case where boron is implanted into the impurity region 47, which is the SCR layer, phosphorus is implanted into the LDD regions 45a and 45b, and then arsenic is implanted into the impurity regions 44a and 44b, which are the SD regions. Here, the boron of the SCR layer is implanted under the conditions of an acceleration energy of 20 keV and a dose rate of 2.5 × 10 13 cm -2 . The phosphorus of the LDD regions 45a and 45b is implanted from four directions under the conditions: the acceleration energy of 35 keV, the dose rate of 2.5 × 10 12 cm -2 and the inclination angle of 28°.

[0253] The programming operation is performed with the program time Tp set to 10 µs under the voltage conditions where the impurity region 44a and the semiconductor substrate 2 are both set to 0 V, and the gate electrode 42 and the impurity region 44b are both set to 4 V (programming voltage Vp = 4 V). The reading operation is performed by setting the impurity region 44b and the semiconductor substrate 2 to 0 V, applying a predetermined gate voltage Vg to the gate electrode 42, and applying the drain voltage Vd = 0.5 V to the impurity region 44a. Fig. 51A illustrates a relationship between the gate voltage Vg(V) and the read current Id(A / µm), the relationship being obtained in the read operation before and after programming. Fig. 51B illustrates the concentration profiles of the p-type and n-type impurities of the impurity region 47 and LDD regions 45a and 45b in the memory transistor 40C obtained by TCAD with the Id-Vg characteristics of Fig. 51A.

[0254] Fig. 52A illustrates the programming characteristics of the memory transistor 40C in the case where boron is implanted into the impurity region 47, which is the SCR layer, arsenic is implanted into the LDD regions 45a and 45b, and then arsenic is implanted into the impurity regions 44a and 44b, which are the SD regions. Here, the boron of the SCR layer is implanted under the conditions of an acceleration energy of 20 keV and a dose rate of 2.5 × 10 13 cm -2 The arsenic of the LDD regions 45a and 45b is implanted four times under the conditions: acceleration energy of 10 keV, dose level of 5 × 10 11 cm -2and the inclination angle of 0°.

[0255] The programming operation is performed with the program time Tp set to 10 µs under the voltage conditions where the impurity region 44a and the semiconductor substrate 2 are both set to 0 V, and the gate electrode 42 and the impurity region 44b are both set to 4 V (programming voltage Vp = 4 V). The reading operation is performed by setting the impurity region 44b and the semiconductor substrate 2 to 0 V, applying a predetermined gate voltage Vg to the gate electrode 42, and applying the drain voltage Vd = 0.5 V to the impurity region 44a. Fig. 52A illustrates a relationship between the gate voltage Vg(V) and the read current Id(A / µm), the relationship being obtained in the read operation before and after programming. Fig. 52B illustrates the concentration profile of the p-type and n-type impurities of the impurity region 47 and LDD regions 45a and 45b in the memory transistor 40C obtained by TCAD with the Id-Vg characteristics of Fig. 52A.

[0256] Fig. 53A illustrates the programming characteristics of memory transistor 40C in the case where boron is implanted into the impurity region 47, which is the SCR layer, arsenic is implanted into the LDD regions 45a and 45b, and arsenic is implanted into the impurity regions 44a and 44b, which are the SD regions. Here, the boron of the SCR layer is implanted under the conditions: the acceleration energy of 20 keV and the dose rate of 2.5 × 10 13 cm -2 . The arsenic of the LDD regions 45a and 45b is implanted four times under the conditions: acceleration energy of 10 keV, dose level of 1 × 10 13 cm -2 and the inclination angle of 0°.

[0257] The programming operation is performed with the program time Tp set to 10 µs under the voltage conditions where the impurity region 44a and the semiconductor substrate 2 are both set to 0 V, and the gate electrode 42 and the impurity region 44b are both set to 4 V (programming voltage Vp = 4 V). The reading operation is performed by setting the impurity region 44b and the semiconductor substrate 2 to 0 V, applying the predetermined gate voltage Vg to the gate electrode 42, and applying the drain voltage Vd = 0.5 V to the impurity region 44a. Fig. 53A illustrates a relationship between the gate voltage Vg(V) and the read current Id(A / µm), the relationship being obtained in the read operation before and after programming. Fig. 53B illustrates the concentration profiles of the p-type and n-type impurities of the impurity region 47 and LDD regions 45a and 45b in the memory transistor 40C obtained by TCAD with the Id-Vg characteristics of Fig. 53A.

[0258] Fig. 51A reveals that in the memory transistor 40C having the LDD regions 45a and 45b formed by implanting phosphorus under the conditions described above, after programming with Vp = 4 V and Tp = 10 µs, the threshold voltage shifts relatively large from the value before programming (the initial value). Furthermore, Fig. 52A that even in the memory transistor 40C having the LDD regions 45a and 45b formed by implanting arsenic under the conditions described above, after programming with Vp = 4 V and Tp = 10 µs, the threshold voltage shifts relatively large from the value before programming (the initial value). In contrast, Fig. 53A that in the case where the LDD regions 45a and 45b were formed by implanting arsenic in a higher concentration than the case of Fig. 52A have been formed, after programming with Vp = 4 V and Tp = 10 µs the threshold voltage hardly shifts from the value before programming (the initial value).

[0259] In the memory transistor 40C, whose threshold voltage shifts relatively large, as in Fig. 51A and Fig. 52A, there is a relatively low concentration n-type impurity (LDD region) near the surface of the semiconductor substrate 2 with the p-type impurity (SCR layer) therein, as shown in Fig. 51B and Fig. 52B. In contrast, in the memory transistor 40C, whose threshold voltage hardly shifts, as in Fig. 53A, an n-type impurity with relatively high concentration (LDD region) near the surface of the semiconductor substrate 2 with the p-type impurity (SCR layer) therein, as in Fig. 53B.

[0260] Fig. 51A and Fig. 51B to Fig. 53A and Fig. 53B reveals that in the memory transistor 40C, if the LDD regions 45a and 45b are of a relatively low concentration, a relatively high programming speed is obtained, whereas if the LDD regions 45a and 45b are of an excessively high concentration, the programming speed will decrease. From the viewpoint of suppressing a significant reduction in the programming speed, the concentration of the LDD regions 45a and 45b is set to 5 × 10 18 cm -3 or less, preferably 5 × 10 17 cm -3 or less, more preferably 3 × 10 17 cm -3 or less, and furthermore 1 × 10 17 cm-3 or less set.

[0261] Fig. 54 and Fig. 55 illustrate the SCR layer concentration dependence and SD region impurity type dependence of the programming characteristics of the memory transistor with the SCR layer, respectively.

[0262] In Fig. 54 is the Id-Vg characteristic before programming (the initial Id-Vg characteristic), illustrated in the above Fig. 51A, is drawn with a solid line X1i, while the Id-Vg characteristic after programming is drawn with a chain line X1p. In addition, Fig. 54 shows the Id-Vg characteristic before programming (the initial Id-Vg characteristic) of the memory transistor 40C having the impurity region 47 of the SCR layer with a higher concentration than in the case of the above Fig. Figure 51A is plotted with a thick solid line X2i, while the Id-Vg characteristic after programming is plotted with a thick chain line X2p. Boron is implanted into the high-concentration SCR layer under the following conditions: acceleration energy of 20 keV and dose rate of 4.0 × 10 13 cm -2 . In which the Id-Vg characteristics of Fig. 54, arsenic is implanted into the impurity regions 44a and 44b of the SD region. Note that the programming operation and reading operation are carried out under the same conditions as in the case of the above Fig. 51A.

[0263] Fig. Fig. 55 illustrates the Id-Vg characteristics of the memory transistor 40C when the impurity implantation conditions (impurity concentration) of the impurity region 47 of the SCR layer and the LDD regions 45a and 45b are the same as in the case of Fig. 54, and not arsenic, but phosphorus has been implanted into the impurity regions 44a and 44b of the SD region.

[0264] Namely, the first memory transistor 40C contains the SCR layer of a relatively low concentration, and boron is implanted into the SCR layer under the conditions: the acceleration energy of 20 keV and the dose level of 2.5 × 10 13 cm -2 . Phosphorus is implanted into the LDD regions 45a and 45b of the first memory transistor 40C four times under the conditions: the acceleration energy of 35 keV, the dose rate of 2.5 × 10 12 cm -2 and the tilt angle of 28°, and phosphorus is implanted into the SD region. In Fig. In Fig. 55, the Id-Vg characteristic before programming (the initial Id-Vg characteristic) of the first memory transistor 40C is drawn with a solid line Y1i, while the Id-Vg characteristic after programming is drawn with a chain line Y1p. Note that the programming operation and read operation are performed under the same conditions as in the case of the above. Fig. 54 be carried out.

[0265] In addition, the second memory transistor 40C contains the SCR layer of a relatively high concentration, and boron is implanted into the SCR layer under the conditions: the acceleration energy of 20 keV and the dose amount of 4.0 × 10 13 cm -2 . Phosphorus is implanted into the LDD regions 45a and 45b of the second memory transistor 40C four times under the conditions: the acceleration energy of 35 keV, the dose rate of 2.5 × 10 12 cm -2and the tilt angle of 28°, and phosphorus is implanted into the SD region. In Fig. In Fig. 55, the Id-Vg characteristic before programming (the initial Id-Vg characteristic) of the second memory transistor 40C is drawn with a thick solid line Y2i, while the Id-Vg characteristic after programming is drawn with a thick chain line Y2p. Note that the programming operation and read operation are performed under the same conditions as in the case of the above. Fig. 54 be carried out.

[0266] Fig. 54 and Fig. 55 reveal that in either the case where the impurity implanted in the SD region is arsenic or the case where it is phosphorus, a shift in the threshold voltage before and after programming under the same conditions increases more in the case where the dose extent of the SCR layer is increased to increase the impurity concentration. In addition, Fig. 54 and Fig. 55 that in the case where the impurity implanted in the SD region is phosphorus ( Fig. 55), the junction leakage can be further reduced to reduce an off-current Ioff than the case where the impurity implanted in the SD region is arsenic ( Fig. 54).

[0267] Fig. 56 illustrates another example of the programming characteristics of the memory transistor with the SCR layer.

[0268] Fig. Figure 56 illustrates the Id-Vg characteristics associated with the solid line Y1i and chain line Y1p in the above Fig. 55 are drawn. In fact, Fig. 56 the Id-Vg characteristics before and after programming the first memory transistor 40C, in the above Fig. 55, with the solid line Y1i or chain line Y1p. In addition, Fig. 56, the Id-Vg characteristic when a back-bias Vbb of -3.0 V is applied to the semiconductor substrate 2 during the programming operation of the first memory transistor 40C is drawn with a thick chain line Z1p. Note that the programming operation and reading operation are carried out under the same conditions as in the case of the above Fig. 55 can be carried out.

[0269] Fig. Figure 56 reveals that in the case where the substrate bias voltage Vbb is applied during the programming operation (thick chain line Z1p), the threshold voltage after programming shifts to a significantly higher Vg side relative to the threshold voltage before programming than in the case where the substrate bias voltage Vbb is not applied (chain line Y1p). Applying the substrate bias voltage Vbb during the programming operation makes it possible to achieve a significant improvement in programming speed.

[0270] As described above, in the memory transistor 40C having the impurity region 47 as the SCR layer, the impurity implanted into the LDD regions 45a and 45b, for example, an n-type impurity such as phosphorus or arsenic, can be set at a very low concentration. Furthermore, adjusting the type and concentration of an impurity implanted into each of the LDD regions 45a and 45b, the impurity region 47 (SCR layer), and the impurity regions 44a and 44b (SD regions), or further applying the substrate bias voltage Vbb, makes it possible to achieve an improvement in the characteristics of the memory transistor 40C. For example, an increase in the variation of the threshold voltage before and after programming the memory transistor 40C, that is, an increase in the programming speed, can be achieved. Furthermore, overerasing can be suppressed in the memory transistor 40C.Therefore, in the non-volatile memory using the memory transistor 40C, a relatively complicated processing operation such as erase verification does not need to be performed after the erase operation.

[0271] Subsequently, a non-volatile memory will be formed using the memory transistor 40C with the SCR layer as described above.

[0272] Fig. 57 illustrates an example of the non-volatile memory using the memory transistor with the SCR layer. Fig. 57 schematically illustrates an exemplary planar layout of a main portion of the non-volatile memory using the memory transistor with the SCR layer.

[0273] One in Fig. 57 illustrated non-volatile memory 80 (semiconductor device) includes as an element region (element region of the semiconductor substrate 2 of Fig. 46) a plurality of (for example, four) active regions 81, 81b, 81c and 81d extending in the direction S and arranged in parallel in the direction T perpendicular to the direction S. The word lines WL1, WL2 (the gate electrode 42 of Fig. 46) extend via a non-illustrated gate insulating layer (the gate insulating layer 41 of Fig. 46) in the direction T to traverse these active regions 81a, 81b, 81c and 81d. A sidewall insulating layer 83 (the sidewall insulating layer 43 of Fig. 46) is formed on the sidewall of the word lines WL1 and WL2. An impurity region 84 (corresponding to the impurity regions 44a and 44b of Fig. 46), which functions as the SD region, is formed on both sides of the word lines WL1 and WL2 of each of the active regions 81a, 81b, 81c, and 81d. A non-illustrated LDD region (corresponding to the impurity regions 45a and 45b of Fig. 46) is formed under the sidewall insulating layer 83 and on the inside of the impurity region 84, and a non-illustrated channel region is formed between the LDD regions. Furthermore, a non-illustrated impurity region serving as the SCR layer is formed under the channel region. The non-volatile memory 80 includes a plurality of (for example, eight) memory transistors 90a, 90b, 90c, 90d, 90e, 90f, 90g, and 90h (the memory transistor 40C of Fig. 46 accordingly), which is formed from these elements.

[0274] A plug 91 (contact) extending to the upper layer is formed on each impurity region 84. Each impurity region 84 is connected via the plug 91 to the wirings 92a and 92b included in the first conductive layer.

[0275] The wiring 92a extends in the direction T. The wiring 92a is connected via the connector 91 to the impurity region 84 shared by the memory transistors 90a and 90b of the active region 81a. The wiring 92a is connected via the connector 91 to the impurity region 84 shared by the memory transistors 90c and 90d of the active region 81b. The wiring 92a is connected via the connector 91 to the impurity region 84 shared by the memory transistors 90e and 90f of the active region 81c. The wiring 92a is connected via the connector 91 to the impurity region 84 shared by the memory transistors 90g and 90h of the active region 81d. The wiring 92a is used as the source line (SL1).

[0276] The wiring 92b is connected via the connector 91 to the impurity region 84 on the opposite side of the impurity region 84, which is connected to the source line SL1 of each of the memory transistors 90a, 90b, 90c, 90d, 90e, 90f, 90g and 90h.

[0277] A via 93 extending to the upper layer is formed on each wiring 92b. The wiring 92b, which is connected to the impurity region 84 of the transistors 90a and 90b of the active region 81a, is connected via the via 93 to the bit line BL1 extending in the S direction. The wiring 92b, which is connected to the impurity region 84 of the transistors 90c and 90d of the active region 81b, is connected via the via 93 to the bit line BL2 extending in the S direction. The wiring 92b, which is connected to the impurity region 84 of the transistors 90e and 90f of the active region 81c, is connected via the via 93 to the bit line BL3 extending in the S direction.The wiring 92b, which is connected to the impurity region 84 of the transistors 90g and 90h of the active region 81d, is connected via the via 93 to the bit line BL4 extending in the direction S. The bit lines BL1, BL2, BL3, and BL4 are included in the second conductive layer of the non-volatile memory 80.

[0278] In the non-volatile memory 80, the individual memory transistors 90a, 90b, 90c, 90d, 90e, 90f, 90g, and 90h function as a memory cell. An example of each of the programming, reading, and erasing operations of information in the non-volatile memory 80 will be specifically described with reference to Fig. 58A and Fig. 58B, Fig. 59A and Fig. 59B and Fig. 60A and Fig. 60B. Note that the non-volatile memory 80 provided with the n-channel memory transistors 90a, 90b, 90c, 90d, 90e, 90f, 90g, and 90h is taken as an example here.

[0279] Fig. 58A and Fig. 58B are explanatory views of the programming operation of the non-volatile memory using the memory transistor with the SCR layer. Fig. 58A schematically illustrates a planar layout of a main portion of the non-volatile memory during the programming operation, while Fig. 58B schematically illustrates a cross-section of the main portion of the non-volatile memory during the programming operation. Note that Fig. 58B is a schematic cross-sectional view taken along a line L1-L1 of Fig. 58A is.

[0280] For example, during the programming operation with respect to the memory transistor 90a (memory cell) having the impurity region 87 serving as the SCR layer, the potential of the word line WL1 on the gate insulating layer 81 is set to a high level (4 V to 5 V), the potential of the bit line BL1 is set to a low level (0 V), and the potential of the source line SL1 is set to a high level (4 V to 5 V). The potential of the unselected word line WL2 is set to a low level (0 V), and the potential of the unselected bit lines BL2 to BL4 is set to a high level (4 V to 5 V). Thus, the hot electrons (hot carriers 49, electric charges 49a) are injected and accumulated in the sidewall insulating layer 83 above the LDD region 85 on the source line SL1 side of the memory transistor 90a, thereby performing the programming of the information.

[0281] Because the LDD region 85 of the memory transistor 90a is in a very low concentration, the electric field of the LDD region 85 is relatively small. On the other hand, because the impurity region 84, which is the SD region adjacent to the outside of the LDD region 85, is in a high concentration, the electric field abruptly increases at an edge of the impurity region 84. As a result, hot electrons are efficiently generated near the impurity region 84 (drain) on the source line SL1 side, and the generated hot electrons are efficiently injected into the sidewall insulating layer 83 above the LDD region 85 on the source line SL1 side.

[0282] Fig. 59A and Fig. 59B are explanatory views of the read operation of the non-volatile memory using the memory transistor with the SCR layer. Fig. 59A schematically illustrates a planar layout of a main portion of the non-volatile memory during the read operation, while Fig. 59B schematically illustrates a cross-section of the main portion of the non-volatile memory during the read operation. Note that Fig. 59B is a schematic cross-sectional view along a line L2-L2 of Fig. 59A is.

[0283] During the read operation with respect to memory transistor 90a, the potential of word line WL1 is set to a high level (0.5 V), the potential of bit line BL1 is set to a high level (0.5 V), and the potential of source line SL1 is set to a low level (0 V). The potential of unselected word line WL2 is set to a low level (0 V), and the potential of unselected bit lines BL2 to BL4 is set to a low level (0 V). Note that Fig. 59A and Fig. 59B illustrates the memory transistor 90a in which the electric charges 49a are injected and accumulated in the sidewall insulating layer 83. Reading the information of the memory transistor 90a is performed by detecting a current flowing from the bit line BL1 side to the source line SL1 side when such potentials are set.

[0284] Fig. 60A and Fig. 60B are explanatory views of the erase operation of the non-volatile memory using the memory transistor with the SCR layer. Fig. 60A schematically illustrates a planar layout of a main portion of the non-volatile memory during the erase operation, while Fig. 60B schematically illustrates a cross-section of the main portion of the non-volatile memory during the erase operation. Note that Fig. 60B is a schematic cross-sectional view along a line L3-L3 of Fig. 60A is.

[0285] During the erase operation with respect to memory transistor 90a, the programming operation as described above is first performed on memory transistors 90a, 90c, 90e, and 90g connected to word line WL1 (not illustrated). After memory transistors 90a, 90c, 90e, and 90g are set to a programmed state, the potential of word line WL1 is set to negative (-5 V to -6 V), the potential of bit lines BL1 to BL4 is set to a low level (0 V), and the potential of source line SL1 is set to a high level (5 V to 6 V). The potential of the non-selected word line WL2 is set to a low level (0 V). Thus, erasure of the information programmed into memory transistors 90a, 90c, 90e, and 90g connected to word line WL1 is performed.

[0286] During the erase operation, hot holes (hot carriers 49) are generated near the impurity region 84 on the source line SL1 side to neutralize the electrons (electric charges 49a) accumulated in the sidewall insulating layer 83 above the LDD region 85 on the source line SL1 side. Because the hot holes are generated near the impurity region 84 on the source line SL1 side, the influence on the threshold voltage in regions away from the impurity region 84 is reduced. Accordingly, unless a gate length Lg of the word line WL1 is excessively reduced, the threshold voltage as a whole is positive, that is, the off-current of the memory transistor 90a will not significantly exceed the initial value.

[0287] Note that in a floating-gate type memory transistor, if the erase time is extended, an over-erase problem will occur in which the threshold voltage becomes negative, but in a memory transistor having the SCR layer as described above, such a problem can be prevented unless the gate length Lg is set excessively small.

[0288] In the non-volatile memory 80, in which each of the programming, reading, and erasing operations can be performed in a manner described above, a reduction in the area of ​​the memory region can be achieved compared to the above-described twin-bit cell type non-volatile memory 60. Here, we will focus on a memory cell, for example, the memory cell 90a, in the Fig. 57 illustrated non-volatile memory 80.

[0289] In the S direction of the memory transistor 90a, assume that the size (gate length Lg) of the word line WL1 is 0.06 µm, a half size of each of the source line SL1 and the wiring 92b connected to the connector 91 is 0.04 µm, and the size between the word line WL1 and each of the source line SL1 and the wiring 92b is 0.07 µm. In this case, the size U in the S direction of the memory transistor 90a results in 0.28 µm (=0.06 µm + 0.04 µm × 2 + 0.07 µm × 2).

[0290] If it is assumed that the width and pitch of the wiring 92b is 0.18 µm in total, a size V in the direction T of the memory transistor 90a results in 0.18 µm.

[0291] Accordingly, the area of ​​a memory cell of the non-volatile memory 80 results in 0.0504 µm 2(=0.28 µm × 0.18 µm). The same applies to the other memory cells. In the exemplary case of the 1M-bit non-volatile memory 80, the total area of ​​the memory region is 0.402 mm 2 , the area of ​​the entire memory macro (including a logic region, an I / O region, and the like in addition to the memory region) is 1.34 mm 2 , and thus the occupancy ratio of the memory region is 30%. In the non-volatile memory 80, the area of ​​the memory region can be reduced to one-third compared to the twin-bit cell type non-volatile memory 60.

[0292] An example of the configuration of a non-volatile memory using the memory transistor 40C (90a or the like) and a method of manufacturing the same will be further described with reference to Fig. 61 to Fig. 65 described.

[0293] Fig. 61 to Fig. 65 illustrate an example of the method for manufacturing the non-volatile memory. Here, Fig. 61 is an exemplary schematic cross-sectional view of a main part in the first manufacturing step, Fig. 62 is an exemplary schematic cross-sectional view of the main portion in the second manufacturing step, Fig. 63 is an exemplary schematic cross-sectional view of the main part in the third manufacturing step, Fig. 64 is an exemplary schematic cross-sectional view of the main portion in the fourth manufacturing step and is Fig. 65 is an exemplary schematic cross-sectional view of the main part in the fifth manufacturing step. Hereinafter, an example of the steps for manufacturing the non-volatile memory will be described sequentially with reference to Fig. 61 to Fig. 65 are described.

[0294] As in Fig. 61, first, a resist pattern 5v in which an element region 40b of the memory transistor 40C ( Fig. 65) is opened, and an element region 50b of the logic transistor 50 ( Fig. 65) and the element region 30b of the I / O transistor 30 ( Fig. 65) are formed on the semiconductor substrate 2. With the resist pattern 5v used as a mask, a predetermined impurity implantation is performed on the semiconductor substrate 2 of the element region 40b. For example, germanium is implanted under the conditions: the acceleration energy of 30 keV and the dose rate of 5 × 10 14 cm -2 Carbon is implanted under the following conditions: acceleration energy of 5 keV and dose level of 5 × 10 14 cm -2 Boron is implanted under the following conditions: acceleration energy of 20 keV and dose level of 4 × 10 11 cm -2. With these impurity implantations, the relatively high concentration impurity region 47 (SCR layer) of the memory transistor 40C is formed.

[0295] As in Fig. Next, as illustrated in Fig. 62, a resist pattern 5w in which the element region 50b of the logic transistor 50 is opened and the element region 40b of the memory transistor 40C and the element region 30b of the I / O transistor 30 are covered is formed on the semiconductor substrate 2. With the resist pattern 5w used as a mask, a predetermined impurity implantation is performed on the semiconductor substrate 2 of the element region 50b. For example, germanium is implanted under the conditions: the acceleration energy of 30 keV and the dose amount of 5 × 10 14 cm -2 Carbon is implanted under the following conditions: acceleration energy of 5 keV and dose level of 5 × 10 14 cm -2Boron is implanted under the following conditions: acceleration energy of 20 keV and dose level of 5 × 10 12 cm -2 Boron fluoride is implanted under the following conditions: acceleration energy of 10 keV and dose level of 1.5 × 10 12 cm -2 . With the impurity implantation, the impurity region 57 with a relatively high concentration (SCR layer) of the logic transistor 50 is formed.

[0296] As in Fig. 63, a semiconductor material is next epitaxially grown on the semiconductor substrate 2 to form a semiconductor layer 8c (non-doped layer) on the impurity region 47 of the element region 40b and on the impurity region 57 of the element region 50b. The channel region 46 of the memory transistor 40c and a channel region 56 of the logic transistor 50 are formed in the semiconductor layer 8c. Although a semiconductor layer similar to the semiconductor layer 8c of the element region 40b and element region 50b is also formed in the element region 30b due to the epitaxial growth, note that for convenience, the semiconductor layer will be described here as the layer integrated with the semiconductor substrate 2. After the formation of the semiconductor layer 8c, an element isolation region 3 is formed, which defines the element region 40b, the element region 30b, and the element region 50b, as shown in Fig. 63 illustrates.

[0297] Next, impurity implantation for adjusting each threshold voltage of the I / O transistor 30 and the logic transistor 50 is performed on the semiconductor substrate 2 of the element region 30b and the element region 50b. Subsequently, by thermal oxidation as shown in Fig. 64 illustrates that the gate insulating layer 31, the gate insulating layer 41, and the gate insulating layer 51 are formed with a predetermined thickness in the element region 30b, the element region 40b, and the element region 50b, respectively. For example, the gate insulating layer 31 and the gate insulating layer 41 are formed with a thickness of 7 nm, and the gate insulating layer 51 is formed with a thickness of 1.5 nm. Next, the gate electrode 32, the gate electrode 42, and the gate electrode 52 are formed by forming and patterning polysilicon.

[0298] By impurity implantation under a predetermined condition, as in Fig. As illustrated in Figure 64, LDD regions 45a and 45b, LDD regions 35a and 35b, and LDD regions 55a and 55b are formed next. For example, phosphorus is implanted from four directions under the conditions: acceleration energy of 35 keV, dose rate of 2.5 × 10 12 cm -2 , and the tilt angle of 28° to form LDD regions 45a and 45b and LDD regions 35a and 35b. Arsenic is implanted twice under the conditions: the acceleration energy of 1.5 keV, the dose rate of 2.5 × 10 14 cm -2 , and the inclination angle of 0° to form the LDD regions 55a and 55b. Thus, the Fig. 64 is obtained. The channel region 36 of the I / O transistor 30 is formed between the LDD regions 35a and 35b. The channel region 46 of the memory transistor 40C is formed between the LDD regions 45a and 45b. The channel region 56 of the logic transistor 50 is formed between the LDD regions 55a and 55b.

[0299] By forming and etching back an insulating layer, as in Fig. Next, as illustrated in FIG. 65, the sidewall insulating layer 33, the sidewall insulating layer 43, and the sidewall insulating layer 53 are formed on each sidewall of the gate electrode 32, the gate electrode 42, and the gate electrode 52. For example, an oxide layer 101 of silicon oxide or the like with a film thickness of 5 nm and a nitride layer 102 of silicon nitride or the like with a film thickness of 70 nm are sequentially formed and etched back, thereby forming the sidewall insulating layer 33, the sidewall insulating layer 43, and the sidewall insulating layer 53. Note that the oxide layer 101 having a different film thickness may be adopted for the sidewall insulating layer 43 of the memory transistor 40C and the sidewall insulating layer 53 of the logic transistor 50.For example, the oxide layer 101 of the sidewall insulating layer 43 of the memory transistor 40C is made thinner than the oxide layer 101 of the sidewall insulating layer 53 of the logic transistor 50. Thus, in the memory transistor 40C, the injection efficiency of hot carriers into the nitride layer 102 is improved, and the programming speed is improved.

[0300] Next, by impurity implantation under a predetermined condition as shown in Fig. As illustrated in Figure 65, impurity regions 34a and 34b, impurity regions 44a and 44b, and impurity regions 54a and 54b, each serving as the SD region of each of the I / O transistor 30, memory transistor 40C, and logic transistor 50, are formed. For example, phosphorus is implanted under the conditions of an acceleration energy of 8 keV and a dose rate of 1.2 × 10 16 cm -2to form impurity regions 34a and 34b, impurity regions 44a and 44b, and impurity regions 54a and 54b.

[0301] With the manufacturing steps described above, a non-volatile memory 80a is obtained having the I / O transistor 30, memory transistor 40C, and logic transistor 50 mixedly mounted on the common semiconductor substrate 2. Thereafter, the formation of an interlayer insulating film, the formation of a plug, and the formation of an upper wiring layer including conductors, such as wiring and via, and the like, are performed.

[0302] Another example of the configuration of a non-volatile memory using the memory transistor 40C (90a or the like) and a method for manufacturing the same will be further described with reference to Fig. 66 to Fig. 71 described.

[0303] Fig. 66 to Fig. 71 illustrate another example of the method for manufacturing the non-volatile memory. Here, Fig. 66 is an exemplary schematic cross-sectional view of a main portion in the first manufacturing step, Fig. 67 is an exemplary schematic cross-sectional view of the main portion in the second manufacturing step, Fig. 68 is an exemplary schematic cross-sectional view of the main portion in the third manufacturing step, Fig. 69 is an exemplary schematic cross-sectional view of the main portion in the fourth manufacturing step, Fig. 70 is an exemplary schematic cross-sectional view of the main portion in the fifth manufacturing step and is Fig. 71 is an exemplary schematic cross-sectional view of the main part in the sixth manufacturing step. Hereinafter, an example of the steps for manufacturing the non-volatile memory will be described sequentially with reference to Fig. 66 to Fig. 71 described.

[0304] After the formation of the gate insulating layer 31, gate insulating layer 41 and gate insulating layer 51, in the steps of the above Fig. 61 to Fig. 63 and the steps of the above Fig. 64, in this example a polysilicon 4 is first formed as in Fig. 66 illustrates.

[0305] Next, as in Fig. 67, a predetermined resist pattern 5x is formed on the polysilicon 4, and with the resist pattern 5x used as a mask, the polysilicon 4 is etched to form the gate electrode 42 of the memory transistor 40C.

[0306] Next, the resist pattern 5x is removed, and with the gate electrode 42 and polysilicon 4 remaining on the semiconductor substrate 2 used as a mask, a predetermined impurity implantation is next performed on the semiconductor substrate 2 of the element region 40b to form the LDD regions 45a and 45b, as shown in Fig. 68. For example, phosphorus is implanted from four directions under the conditions: acceleration energy of 35 keV, dose rate of 2.5 × 10 12 cm -2 , and the tilt angle of 28° to form the LDD regions 45a and 45b. The channel region 46 of the memory transistor 40C is formed between the LDD regions 45a and 45b.

[0307] Next, by forming and etching back an insulating layer, as in Fig. 69, the sidewall insulating layer 43 is formed on the sidewall of the gate electrode 42. For example, an oxide layer 101 of silicon oxide or the like with a film thickness of 5 nm and a nitride layer 102 of silicon nitride or the like with a film thickness of 70 nm are sequentially formed and etched back, thereby forming the sidewall insulating layer 43. Note that the sidewall insulating layer 43 is similarly also formed on the sidewall of the polysilicon 4 other than the gate electrode 42 and above the semiconductor substrate 2 (above the element isolation region 3).

[0308] As in Fig. 70, a predetermined resist pattern 5y is formed, and with the resist pattern 5y used as a mask, the polysilicon 4 is etched to form the gate electrode 32 of the I / O transistor 30 and the gate electrode 52 of the logic transistor 50. Note that Fig. 70 illustrates a shape in which a part (edge) of the polysilicon 4 also remains on the element isolation region 3.

[0309] By impurity implantation under a predetermined condition, as in Fig. Next, as illustrated in Figure 71, LDD regions 35a and 35b are formed in element region 30b, and LDD regions 55a and 55b are formed in element region 50b. Channel region 36 of I / O transistor 30 is formed between LDD regions 35a and 35b, and channel region 56 of logic transistor 50 is formed between LDD regions 55a and 55b.

[0310] By forming and etching back an insulating layer, as in Fig. 71, next, the sidewall insulating layer 33 and sidewall insulating layer 53 are formed on each sidewall of the gate electrode 32 and gate electrode 52. The sidewall insulating layer 33 and sidewall insulating layer 53 are formed to have a width smaller than the width of the sidewall insulating layer 43 of the memory transistor 40C. Note that the sidewall insulating layer 53 (or 33) is similarly also formed on the sidewall of the polysilicon 4 remaining on the element isolation region 3. Next, by the impurity implantation under a predetermined condition, as shown in Fig. 71, the impurity regions 34a and 34b, impurity regions 44a and 44b, and impurity regions 54a and 54b, each serving as the SD region of each of the I / O transistor 30, memory transistor 40C, and logic transistor 50, are formed.

[0311] With the manufacturing steps described above, a non-volatile memory 80b is obtained that has the I / O transistor 30, memory transistor 40C, and logic transistor 50 mixedly mounted on the common semiconductor substrate 2. Thereafter, the formation of an interlayer insulating film, the formation of a plug, and the formation of an upper wiring layer including conductors, such as wiring and via, and the like, are performed.

[0312] The width of the sidewall insulating layer 43 of the memory transistor 40C is an important parameter that affects the transistor characteristics of the memory transistor 40C, as described above. Fig. 66 to Fig. 71, the width of the sidewall insulating layer 43 of the memory transistor 40C can be adjusted independently of the width of the sidewall insulating layer 53 of the logic transistor 50.

[0313] Fig. 72 is an explanatory view of the memory transistor with the SCR layer.

[0314] As described above, in the memory transistor 40C (90a or the like), the LDD regions 45a and 45b are formed by impurity implantation into a non-doped layer or a very low concentration layer (semiconductor layer 8c to be epitaxially grown) under the sidewall insulating layer 43. Therefore, the LDD regions 45a and 45b are stably formed with a very low concentration. For example, if the LDD regions 45a and 45b are formed to have a concentration equal to or less than 5 × 10 17 cm -3To have, the LDD regions 45a and 45b hardly contribute to causing ionization. Therefore, at an edge of the impurity region 44b (SD region) with a concentration higher than the LDD region 45b, for example, the hot carriers 49 are generated and injected into the sidewall insulating layer 43 above the impurity region 44b. If there is the electric charge 49a in the sidewall insulating layer 43, the LDD region 45b with the very low concentration below the sidewall insulating layer 43 will be easily modulated, and thus the threshold voltage of the memory transistor 40C will vary. Moreover, because the conductivity type of the LDD regions 45a and 45b is determined, displacement of the memory transistor 40C can also be suppressed.Furthermore, improvement of the programming characteristics is achieved by adjusting the configuration (material, width and the material, thickness and the like of each layer of the stacked structure) of the sidewall insulating layer 43.

[0315] The memory transistor 40C may have a configuration in which a transistor 40Cb having a SONOS (semiconductor substrate 2 - oxide film 43a - nitride film 43b - oxide film 43a - gate electrode 42) structure is added to the side surface of a main body transistor 40Ca.

[0316] With the disclosed technique, a transistor having excellent programming speed as a memory transistor and a semiconductor device including such a transistor can be realized.

Claims

[1] A semiconductor device (1A, 1C, 1D, 1Fa, 1Fb, 80a) comprising: a storage region (10a, 10b, 40b); a logic region (20a, 20b, 50b); and an element region (30b) of an I / O transistor (30), wherein the memory region (10a, 10b, 40b) contains a first transistor (10, 40, 40c) with: a first gate insulating layer (11, 41) provided over a semiconductor substrate (2, 6a, 6b); a first gate electrode (12, 42) provided over the first gate insulating layer (11, 41); a first sidewall insulating layer (13, 43) provided on a sidewall of the first gate electrode (12, 42) and above the semiconductor substrate (2, 6, 6a); and a first source region (14a, 44a) and a first drain region (14b, 44b) provided in the semiconductor substrate (2, 6a, 6b) on both sides of the first gate electrode (12, 42), wherein the first transistor (10, 40, 40c) stores information by accumulating charge in the first sidewall insulating layer (13, 43), where the logic region (20a, 20b, 50b) contains a second transistor (20, 50) with: a second gate insulating layer (21, 51) provided over the semiconductor substrate (2, 6a, 6b), a second gate electrode (22, 52) provided over the second gate insulating layer (21, 51), a second sidewall insulating layer (23, 53) provided on a sidewall of the second gate electrode (22, 52) and above the semiconductor substrate (2, 6a, 6b); and a second source region (24a, 54a) and a second drain region (24b, 54b) provided in the semiconductor substrate (2, 6a, 6b) on both sides of the second gate electrode (22, 52), wherein a width of the first sidewall insulating layer (13, 43) is greater than a width of the second sidewall insulating layer (23, 53), wherein the I / O transistor has a third gate insulating layer (31) which is equal to the first gate insulating layer (11) of the first transistor (10, 40, 40c), and wherein a thickness of the first gate insulating layer (11, 41) and the third gate insulating layer (31) is greater than a thickness of the second gate insulating layer (21, 51). [2] A semiconductor device according to claim 1, wherein the first source region and the first drain region contain an impurity of a first conductivity type, and wherein the first transistor (10, 40, 40c) further includes a first impurity region provided on an inner side of the first source region and the first drain region in the semiconductor substrate under the first sidewall insulating layer, and including the impurity of the first conductivity type at a lower concentration than the first source region and the first drain region. [3] A semiconductor device according to claim 2, wherein the first source region and the first drain region contain an impurity of a first conductivity type, and wherein the first transistor further includes a first channel region provided in the semiconductor substrate between the first source region and the first drain region, and a second impurity region provided in the semiconductor substrate below the first channel region and containing an impurity of a second conductivity type different from the first conductivity type, the impurity having a higher concentration than an impurity of the first channel region. [4] The semiconductor device according to claim 3, wherein the second impurity region contacts the first source region and the first drain region. [5] A semiconductor device according to any one of claims 1 to 4, wherein the second source region and the second drain region contain an impurity of a first conductivity type, and wherein the second transistor further comprises: a second channel region provided in the semiconductor substrate between the second source region and the second drain region; and a fourth impurity region provided in the semiconductor substrate below the second channel region and containing an impurity of a second conductivity type different from the first conductivity type, the impurity having a higher concentration than the second channel region. [6] The semiconductor device according to claim 5, wherein the fourth impurity region contacts the second source region and the second drain region. [7] The semiconductor device according to any one of claims 1 to 6, wherein a concentration distribution of impurities included in the first source region and the first drain region in the semiconductor substrate is steeper than a concentration distribution of impurities included in the second source region and the second drain region. [8] A semiconductor device (1D) comprising: a storage region (40b); a logic region (20b); and an element region (30b) of an I / O transistor (30), wherein the memory region (40b) contains a first transistor (40) with: a first gate insulating layer (41) provided over a semiconductor substrate (2, 6a, 6b); a first gate electrode (42) provided over the first gate insulating layer (42); a first sidewall insulating layer (43) provided on a sidewall of the first gate electrode (42) and over the semiconductor substrate (2, 6a, 6b); a first source region (44a) and a first drain region (44b) each provided in the semiconductor substrate (2, 6a, 6b) on both sides of the first gate electrode (42) and containing an impurity of a first conductivity type, a first channel region (46) provided in the semiconductor substrate (2, 6a, 6b) between the first source region (44a) and the first drain region (44b), and a second impurity region (47) provided in the semiconductor substrate (2, 6a, 6b) under the first channel region (46) and containing an impurity of a second conductivity type different from the first conductivity type, the impurity having a higher concentration than an impurity of the first channel region, wherein the first transistor (40) stores information by accumulating charge in the first sidewall insulating layer (43), where the logic region (20b) contains: a second transistor (20, 50) with: a second gate insulating layer (21, 51) provided over the semiconductor substrate (2, 6a, 6b), a second gate electrode (22, 52) provided over the second gate insulating layer (21, 51), a second sidewall insulating layer (23, 53) provided on a sidewall of the second gate electrode (22, 52) and over the semiconductor substrate (2, 6a, 6b); a second source region (24a, 54a) and a second drain region (24b, 54b) each provided in the semiconductor substrate (2, 6a, 6b) on both sides of the second gate electrode (22, 52), wherein a width of the first sidewall insulating layer (13, 43) is greater than a width of the second sidewall insulating layer (23, 53), wherein the I / O transistor has a third gate insulating layer (31) which is equal to the first gate insulating layer (11) of the first transistor (10, 40, 40c), and wherein a thickness of the first gate insulating layer (11, 41) and the third gate insulating layer (31) is greater than a thickness of the second gate insulating layer (21, 51). [9] The semiconductor device according to claim 8, wherein the first transistor (40) further includes a first impurity region provided on an inside of the first source region and the first drain region in the semiconductor substrate under the first sidewall insulating layer, and including the impurity of the first conductivity type at a lower concentration than the first source region and the first drain region, wherein the impurity concentration of the first impurity region is equal to or less than 5×10 17 cm -3 is. [10] A semiconductor device according to claim 9, further comprising: a word management group; a bit line group; a ground wire group; and the first transistor provided in a plurality, wherein each of the plurality of first transistors the first gate electrode is connected to a word line of the word line group, and one of the first source region and the first drain region is connected to a bit line of the bit line group and the other is connected to a ground line of the ground line group, and wherein each of the plurality of first transistors forms a memory cell. [11] A semiconductor device according to any one of claims 8 to 10, wherein the first conductivity type impurity included in the first source region and the first drain region is phosphorus. [12] A semiconductor device according to any one of claims 8 to 11, wherein the second impurity region contacts the first source region and the first drain region. [13] A semiconductor device according to claim 8, wherein the second source region and the second drain region contain the impurity of the first conductivity type, and wherein the second transistor further includes a fourth impurity region provided in the semiconductor substrate below the second channel region and containing the impurity of the second conductivity type at a higher concentration than the second channel region. [14] The semiconductor device according to claim 8, wherein a concentration distribution of impurities included in the first source region and the first drain region in the semiconductor substrate is steeper than a concentration distribution of impurities included in the second source region and the second drain region.

Images