SEMICONDUCTOR DEVICE

Abstract

Semiconductor device, comprising: a plurality of semiconductor chips (104) arranged on a circuit pattern within a housing defined in a top view by an outer frame (102); Bond wires (103) for electrically connecting the plurality of semiconductor chips (104) and the circuit pattern to one another; and a main electrode (106, 106a) which is located inside the housing, wherein the plurality of semiconductor chips (104) is arranged along a longer side direction of the housing, wherein the bond wires (103) are arranged along the longer side direction of the housing, wherein the main electrode (106, 106a) is located near one of the sides extending in the longer lateral direction of the housing, and wherein the main electrode (106, 106a) and the circuit pattern are connected to each other by ultrasonic bonding, soldering or brazing, wherein the circuit pattern is made of a copper foil with a thickness of 0.4 mm or more, and the semiconductor device has two first complex elements (33, 93, 34, 94) in which two of the multitude of semiconductor chips (104) are connected in antiparallel, wherein one (33, 93) of the two first complex elements is configured such that two from the plurality of semiconductor chips (104) are connected antiparallel via a first transition circuit pattern (35, 95) which is located at a position which in a top view is situated between the two from the plurality of semiconductor chips (104), and wherein another (34, 94) of the first two complex elements is configured such that two of the plurality of semiconductor chips (104) are not directly connected antiparallel via a first transition circuit pattern (35, 95).

Description

BACKGROUND OF THE INVENTION Area of ​​the invention

[0001] A technique disclosed in the description relates to a semiconductor device and a method for manufacturing the semiconductor device, and relates, for example, to a semiconductor device used for different power electronics and a method for manufacturing the semiconductor device. Description of the state of the art

[0002] A semiconductor device essentially comprises a plurality of semiconductor chips within a rectangular housing in plan view. The semiconductor device also includes a heat-dissipating surface for the exchange of heat generated by the semiconductor chips via an external heat-dissipating device. The heat-dissipating surface is insulating. The semiconductor device further includes a terminal located approximately opposite the heat-dissipating surface and electrically connected to an external circuit.

[0003] The exposed terminal for the electrical connection to the external circuit is routed to the inside of the housing as an electrode and contains a conductor. The radiating surface inside the housing has a conductive plate nearby, bonded to an insulating substrate made of an insulating material such as ceramic. The conductive plate is partially separated to form a circuit pattern.

[0004] The semiconductor chips are bonded to the circuit pattern by a bonding agent that combines electrical and thermal conductivity. Furthermore, an opposing surface of a bonding pad on each semiconductor chip is electrically connected to the circuit pattern or electrode via bond wires.

[0005] The circuit pattern on the substrate is made of a thin conductive film, as disclosed, for example, in published Japanese patent application No. 2003-243610. In this case, the width of the pattern is approximately half the total effective width of the pattern in a narrow direction (i.e., a shorter side direction) of the package to carry a main current through the pattern. Approximately two circuit patterns, through which the main current flows, are arranged on a longer side direction of the package. Furthermore, bond wires are arranged in the narrow direction (i.e., the shorter side direction) to connect the semiconductor chips and the circuit pattern. A main electrode and the circuit pattern are connected in a complex manner using gaps between the wires.

[0006] In a wire bonding setup, the arm that performs the wire bonding has a limited length due to its mechanical rigidity. Furthermore, the arm is geometrically thicker in a section higher (wider) than the bonding point. This thicker section of the arm negatively impacts an area, such as the periphery of the object being bonded. Therefore, wire bonding in deep and narrow enclosures, for example, presents many limitations. In particular, a module with a width of approximately 50 mm or less exhibits these limitations quite noticeably.

[0007] One method to avoid such a situation involves completing the wire bonding as far as possible before fitting the housing into the substrate. Unfortunately, such a method cannot necessarily be used for an electrode located within the housing.

[0008] This means the electrode in the package can be bonded to the circuit pattern before the package is fitted into the substrate. In this case, a force is exerted on a bonding area between the electrode and the circuit pattern when the package is fitted into the substrate, increasing the risk of malfunctions. Therefore, it is difficult to choose a vulnerable bonding method, such as soldering.

[0009] However, if ultrasonic (US) bonding is chosen, increasing the frequency is difficult due to limitations in the shape of the electrode bonding area. US bonding, which still requires a large tool (horn), restricts bonding inside deep and narrow housings in terms of the arrangement.

[0010] From US 2012 / 0119256A1, a semiconductor module is known in which a U-terminal and an M-terminal overlap in a certain manner. In this module, a P-terminal, an M-terminal, an N-terminal, and a U-terminal are arranged such that the U-terminal, through which currents flow in and out, is located furthest from the control electrodes.

[0011] From DE 11 2013 003 161 T5, a power semiconductor module is known which comprises a base plate as a metallic heat sink, a first insulating layer on the base plate, and a first wiring pattern on the first insulating layer. On a predetermined area, which is part of the first wiring pattern, a second wiring pattern for a second layer is laminated only by means of a second insulating layer formed from resin, thus forming a laminated pattern area. A power semiconductor element is placed in an area that differs from the laminated pattern area on the first wiring pattern. The base plate, the first insulating layer, the first wiring pattern, the second insulating layer, the second wiring pattern, and the power semiconductor element are integrally enclosed by a transfer-formed resin, thus obtaining the power semiconductor module.

[0012] A low-inductance power semiconductor assembly is known from DE 10 2010 002 627 A1. In this assembly, the semiconductor switches used are arranged one after the other in a main current direction.

[0013] The object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that minimizes limitations in wire bonding activities. This object is achieved by the features of claim 1. The dependent claims disclose preferred embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Further details, features and advantages of the invention will become apparent from the following description of exemplary embodiments with reference to the drawings. These show: Fig. 1 a top view illustrating schematically a configuration for enabling a semiconductor device according to a preferred embodiment; Fig. 2 a top view illustrating schematically a configuration for enabling a semiconductor device according to a preferred embodiment; Fig. 3 a top view illustrating schematically a structure of a semiconductor chip and its periphery inside a housing in a configuration to enable a semiconductor device according to a preferred embodiment; Fig. 4 a top view illustrating schematically a configuration for enabling a semiconductor device according to a preferred embodiment; Fig. 5 a top view illustrating schematically a configuration for enabling a semiconductor device according to a preferred embodiment; Fig. 6 a top view illustrating schematically a configuration for enabling a semiconductor device according to a preferred embodiment; Fig. 7 a cross-sectional view which schematically illustrates a structure near a bending area of ​​a main electrode according to a preferred embodiment; Fig. 8 a top view illustrating schematically a configuration for enabling a semiconductor device according to a preferred embodiment; Fig. 9 a top view schematically illustrating the structure of a semiconductor chip and its periphery inside a package in a configuration to enable a semiconductor device according to a preferred embodiment; and Fig. 10 a top view illustrating schematically a configuration to enable a semiconductor device according to a preferred embodiment. DESCRIPTION OF PREFERRED EXAMPLES

[0015] Preferred embodiments are described with reference to the accompanying drawings. It should be noted that the drawings are merely schematic representations of the invention, and the relationships between sizes and positions of individual images in the various drawings are not necessarily accurate and may therefore be subject to change. Furthermore, it should be noted that in the following descriptions, identical components are consistently identified by the same symbols and also have the same names and functions. Detailed descriptions of the identical components are therefore unnecessary.

[0016] Furthermore, in the following descriptions, the use of terms such as "top," "bottom," "side," "bottom," "front," and "back," which denote specific positions and directions, serves solely for the sake of simplicity and to facilitate understanding of the exemplary embodiments. These terms have no bearing on actual directions when the exemplary embodiments are implemented. <Erstes bevorzugtes Ausführungsbeispiel>

[0017] A semiconductor device and a method for manufacturing the semiconductor device according to a first preferred embodiment are described below. For the sake of simplicity, the description begins with bond wires arranged along a shorter side of an outer frame of a housing, as disclosed in published Japanese patent application No. 2003-243610.

[0018] Fig. Figure 10 shows a top view illustrating a schematic configuration for enabling the semiconductor device according to the present preferred embodiment.

[0019] As in Fig. As illustrated in Figure 10, a semiconductor chip 200, a semiconductor chip 201, a semiconductor chip 202, and a semiconductor chip 203 are arranged inside the housing, which is defined by an outer frame 102. Bond wires 103 for connecting individual semiconductor chips and circuit patterns are arranged along a shorter side of the outer frame 102 of the housing. Furthermore, a main electrode 204, a main electrode 205, and a main electrode 206 are encapsulated on the circuit patterns. The circuit patterns are formed on an insulating substrate 105. The outer frame 102 of the housing is provided with electrodes 100 and signal terminals 101. <Konfiguration einer Halbleitervorrichtung>

[0020] Fig. Figure 2 shows a top view illustrating a configuration for enabling the semiconductor device according to the present preferred embodiment.

[0021] As in Fig. As illustrated in Figure 2, a plurality of semiconductor chips 104 are arranged on a circuit pattern inside the housing, which is defined in a top view by the outer frame 102. The semiconductor chips 104 are arranged along a longer side of the outer frame 102 of the housing. Furthermore, bond wires 103 for connecting the semiconductor chips 104 to the circuit pattern are arranged along the longer side of the outer frame 102 of the housing. It should be noted that the angle between the direction in which the bond wires 103 are arranged and the longer side of the outer frame 102 of the housing is preferably within approximately 20 degrees. In addition, the outer frame 102 of the housing is provided with the electrodes 100 and the signal terminals 101.

[0022] The length of the housing in its longer side direction is greater than or equal to twice the length of the housing in its shorter side direction. Furthermore, the length of the housing in its shorter side direction is approximately 50 mm or less.

[0023] All bond wires 103 are arranged along the longer side of the outer frame 102 of the package in the structure described above. This structure allows bonding activities to take place only in one longer side, which is the most freely movable in a narrow and deep package. This facilitates bonding the semiconductor chips and the circuit pattern inside the package to each other after the package has been fitted into a substrate. Furthermore, this facilitates bonding the electrodes in the outer frame 102 of the package to the circuit pattern inside the package.

[0024] To enable the above configuration, the circuit pattern must be formed from the semiconductor chips 104 through the electrodes in the outer frame 102 of the housing. Unfortunately, supplying a large current requires a certain width relative to the large current. However, a large pattern width proportionally increases the gaps between the semiconductor chips 104. Consequently, a module is long in its longer side direction in order to limit current values.

[0025] Accordingly, a "thick copper" substrate can be used to form the circuit pattern. The thick copper substrate is made from a conductive film containing a copper foil approximately 0.4 mm thick or more.

[0026] The use of the thick copper substrate increases the cross-sectional area of ​​the pattern per unit width. Consequently, a large current would flow through a narrowly wide pattern, if present, and a current would flow freely in a narrow direction of the pattern, if present.

[0027] Such a configuration allows the wires to be attached to a narrow pattern in the vertical direction, i.e., on a side face of the circuit pattern with respect to wire bonding for electrically connecting the semiconductor chips 104 and the circuit pattern to each other. Consequently, the wires are short, or the gaps for wire bonding are short. This reduces the limitations in implementing wire bonding for the semiconductor chips 104 in an approximately linear fashion. <Zweites bevorzugtes Ausführungsbeispiel>

[0028] A semiconductor device and a method for manufacturing the semiconductor device according to a second preferred embodiment are described below. All components similar to those in the preceding preferred embodiment are identified by the same symbols, and detailed descriptions of the same components are omitted where necessary. <Konfiguration einer Halbleitervorrichtung>

[0029] Fig. Figure 3 shows a top view illustrating a schematic configuration for enabling the semiconductor device according to the present preferred embodiment.

[0030] As in Fig. Figure 3 illustrates a large number of semiconductor chips arranged on a circuit pattern inside a package.

[0031] As in Fig. As illustrated in Figure 3, bond wires 103 from an emitter of an insulated-gate bipolar transistor (IGBT) semiconductor chip and bond wires 103 from an anode of a diode chip are connected to a common circuit pattern. However, separate connections of the individual wires consume a large area of ​​the pattern, i.e., increase the footprint of the pattern. This is disadvantageous with regard to miniaturization and the manufacturing costs of the devices.

[0032] Here, the use of the previously described thick copper substrate allows the free flow of current in a narrow direction of the pattern. Accordingly, a narrow transition circuit pattern 35 is provided, which is arranged in a top view between these two semiconductor chips, in order to connect the bond wires 103 from the emitter of the IGBT semiconductor chip and the bond wires 103 from the anode of the diode chip to each other at bond points 32.

[0033] Meanwhile, two complex elements, each containing the IGBT semiconductor chip and the diode chip, can be arranged inside the package. Such a case (e.g., a series connection, a common collector, a common emitter, or an AC switch) can introduce waste in providing the circuit pattern for connecting these two complex elements. To eliminate this waste, one of the elements, i.e., complex element 33, is configured such that the two semiconductor chips are connected with an antiparallel diode via the narrow junction circuit pattern 35. The other, i.e., complex element 34, is configured such that the two semiconductor chips are connected with the antiparallel diode via the narrow junction circuit pattern 35.

[0034] This method is used for the following reason. The paths in the circuit pattern are long, for example, because the gaps between the two IGBT semiconductor chips increase, or the emitters of the two IGBT semiconductor chips are opposite each other when both complex elements are connected antiparallel via the transition circuit pattern or not via the transition circuit pattern. <Drittes bevorzugtes Ausführungsbeispiel>

[0035] A semiconductor device and a method for manufacturing the semiconductor device according to a third preferred embodiment are described below. All components similar to those in the previous preferred embodiments are identified by the same symbols, and detailed descriptions of the same components are omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0036] Fig. Figure 4 shows a top view illustrating a schematic configuration for enabling the semiconductor device according to the present preferred embodiment.

[0037] As in Fig. As shown in Figure 4, an insulating substrate 105 is arranged inside a housing defined by an outer frame 102. Furthermore, a plurality of main electrodes 106 are arranged on the insulating substrate 105. It should be noted that the semiconductor chips 104 have been omitted from the drawing for simplification.

[0038] In a typical narrow-width module, bonding areas between individual terminals of the main electrodes 106 and a circuit pattern on the insulating substrate 105 were positioned sporadically or on both sides of the module to improve the pattern area efficiency of the bonding areas between the individual main electrodes 106 and the circuit or to improve heat dissipation. Unfortunately, such positioning leads to increased inductance, higher electrode costs, and further complicates designs aimed at eliminating problems, including mutual induction with signal lines.

[0039] Accordingly, thermal diffusion can be expected using the circuit pattern by employing the previously described thick copper substrate. Thus, the heat dissipation property is improved by allocating a sufficient pattern area.

[0040] Furthermore, a relatively small, card-sized thick copper substrate (e.g., 85.60 mm × 53.98 mm) does not offer many options regarding substrate size, which reduces manufacturing costs. Such a card-sized substrate therefore does not offer many advantages in the typical positioning described above. Consequently, a thermal diffusion medium is considered to be the area of ​​the pattern obtained by bonding the terminals of the main electrodes 106 and the circuit pattern together, not by wire bonding but by another method, such as ultrasonic bonding, soldering, or brazing. The thermal diffusion medium is also considered to be an ineffective area obtained by clustering the bonding areas between the terminals of the main electrodes 106 and the circuit pattern near one side extending in a longer lateral direction of the package.Consequently, the inductance is reduced by intentionally clustering the bonding areas between the terminals of the main electrodes 106 and the circuit pattern near the side extending along the longer side of the case, and furthermore by concentrating the electrodes that are magnetic flux sources to exhibit high magnetic resistance. In addition, mutual induction is reduced by increasing the distance from the signal line. Here, the proximity of the side extending along the longer side of the case lies within a region approximately one-third of the distance of the side extending along the shorter side of the case.

[0041] As many semiconductor chips as possible must be arranged along the bonding areas between the terminals of the main electrodes 106 and the circuit pattern so that the wall areas effectively serve as heat dissipation elements. Therefore, the package is preferably slim. <Viertes bevorzugtes Ausführungsbeispiel>

[0042] A semiconductor device and a method for manufacturing the semiconductor device according to a fourth preferred embodiment are described below. All components similar to those in the previous preferred embodiments are identified by the same symbols, and detailed descriptions of the same components are omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0043] Fig. Figure 5 shows a top view illustrating a schematic configuration for enabling the semiconductor device according to the present preferred embodiment.

[0044] As in Fig. Figure 5 shows an insulating substrate 105 arranged inside a housing defined by an outer frame 102.

[0045] Furthermore, a plurality of semiconductor chips 104 are arranged on the insulating substrate 105. Additionally, a plurality of signal electrodes 107 are arranged on the insulating substrate 105. Each of the semiconductor chips 104 is bonded to the corresponding signal electrode 107. Moreover, each of the signal electrodes 107 is individually arranged near sides extending in a shorter direction of the outer frame 102 of the housing and is electrically connected to a corresponding signal terminal 101 by a signal line 108. The signal terminals 101 are located on a side of the outer frame 102 extending in the shorter direction of the housing. The area surrounding the side extending in the shorter direction of the housing is, for example, a region within approximately one-third of the side extending in a longer direction of the housing.

[0046] If the signal lines 108 receive mutual induction from a main circuit, a problem such as feedback or coupling may occur. To avoid such a problem, the signal electrodes 107 were typically electrically connected to the circuit pattern at a position as close as possible to the signal terminals 101. If the package is rectangular in a top view, one of the IGBT semiconductor chips is located away from the signal terminals 101. Consequently, one of the signal lines 108 runs between the IGBT semiconductor chip located away from the signal terminals 101 and the signal terminals 101 through a region with dense circuit structures. This has resulted in a complicated design and prevented the achievement of an ideal positioning.

[0047] Another method involves positioning the signal connections at a distance. However, this method merely shifts the problems to external lines. Fundamental solutions to the problems were therefore often neglected.

[0048] The structure according to the present preferred embodiment is configured such that the terminals of the main electrodes 106 are concentrated on only one side of the longer sides of the housing. Therefore, the other side, opposite the side where the terminals of the main electrodes 106 are located, will hardly receive the mutual induction. Accordingly, one of the signal lines 108 is arranged near the other side, opposite the side where the terminals of the main electrodes 106 are located. It should be noted that one of the signal lines 108 is arranged between the signal electrodes 107, which are furthest from the signal terminals 101, and the signal terminals 101.Such a positioning of the signal line 108 makes it difficult to receive the mutual induction from the terminals of the main electrodes 106, and the positioning further achieves a wiring to avoid the region with the dense circuit structures.

[0049] It should be noted that individual connections can be made directly on the semiconductor chips 104 and can be made via the circuit pattern or another semiconductor chip.

[0050] Furthermore, the structure according to the present preferred embodiment is, when combined with the one in Fig. 2 or Fig. 3 is combined and configured such that the signal electrodes of the two complex elements are arranged opposite each other on the shorter sides of the housing. This positioning results in linearity of the wire bonding, including the wire bonding between the complex elements and the signal electrodes. Furthermore, the endpoints of the wire bonding are positioned close to the center along the longer side of the housing. This positioning reduces the mutual induction on the signal line 108 between the complex element and the signal terminal. <Fünftes bevorzugtes Ausführungsbeispiel>

[0051] A semiconductor device and a method for manufacturing the semiconductor device according to a fifth preferred embodiment are described below. All components similar to those in the previous preferred embodiments are identified by the same symbols, and detailed descriptions of the same components are omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0052] Fig. Figure 6 shows a top view illustrating a configuration to enable the semiconductor device according to the present preferred embodiment.

[0053] As in Fig. As illustrated in Figure 6, an insulating substrate 105 is arranged inside a housing defined by an outer frame 102. Furthermore, a plurality of main electrodes 106 are arranged on the insulating substrate 105.

[0054] In addition, a complex element 65 and a complex element 66 are arranged on the insulating substrate 105.

[0055] An IGBT semiconductor chip in an IGBT module and an antiparallel diode chip are not powered simultaneously. However, these chips are powered simultaneously when the IGBT semiconductor chip is replaced by the diode chip, thus forming two parallel chips of a single diode.

[0056] If, in this case, wire bonding can be achieved across another semiconductor chip, twice the current flows through a junction area. Consequently, a significant amount of wire bonding is required, and some diode chip sizes can prevent the formation of a sufficient number of bond wires. Unfortunately, connecting each diode chip to a circuit pattern consumes a considerable area of ​​the pattern. This is therefore disadvantageous in terms of package size and manufacturing costs.

[0057] Here, the use of the previously described thick copper substrate allows current to flow freely in a narrow pattern direction. Accordingly, a narrow transition circuit pattern 67 is provided, in which the transition circuit pattern is arranged in a top view between two semiconductor chips. This establishes a connection between bond wires 103 from an emitter of the IGBT semiconductor chip and bond wires 103 from an anode of the diode chip at bond points 62 via the transition circuit pattern 67.

[0058] Unfortunately, placing two complex elements can introduce waste in providing the circuit pattern to connect them. To eliminate this waste, one of the complex elements, i.e., complex element 65, is configured so that the two semiconductor chips are connected to the parallel diode via a narrow junction circuit pattern 67. The other, i.e., complex element 66, is configured so that the two semiconductor chips are not connected to the parallel diode via the narrow junction circuit pattern 67. <Sechstes bevorzugtes Ausführungsbeispiel>

[0059] A semiconductor device and a method for manufacturing the semiconductor device according to a sixth preferred embodiment are described below. All components similar to those in the previous preferred embodiments are identified by the same symbols, and detailed descriptions of the same components are omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0060] Fig. Figure 7 shows a cross-sectional view schematically illustrating a structure near a bending region of a main electrode. A dashed area in Fig. Figure 7 illustrates the main electrode before it was subjected to bending.

[0061] As in Fig. As illustrated in Figure 7, a rim of a main electrode 106a extends from a recessed area 71 in the top of a housing 73. Furthermore, the main electrode 106a has a terminal that is bent in a direction away from the outer frame of the housing 73 in the recessed area 71 of the top of the housing 73, i.e., in a top view, in an inward direction of the housing 73. The recessed area 71 has a C-plane in the inward direction in which the main electrode 106a is bent. The recessed area 71 also has a gap in an outward direction opposite the inward direction in which the main electrode 106a is bent when the main electrode 106a is positioned for bending.

[0062] The main electrode 106a can be bent to form a circuit pattern after bonding. In an effort to maximize the internal space of a module in such a structure, the main electrode 106a, before being bent, should ideally have its terminal positioned as close as possible to the outer frame. Unfortunately, if the terminal of the main electrode 106a is located close to the outer frame, the creepage distance may be insufficient.

[0063] Accordingly, in the present preferred embodiment, a relatively large curvature R of the terminal of the main electrode 106a is specified, and the terminal of the main electrode 106a is bent in a recessed position on the top of the housing. Such a structure would provide sufficient creepage distance between an outer frame 102 and the terminal of the bent main electrode 106a if the terminal of the main electrode 106a is arranged close to the outer frame 102 before it is bent.

[0064] It should be noted that if the number of main electrodes is, for example, as in Fig. Figure 6 shows that the distances between the curved areas of the main electrodes and the outer frame of the housing adjacent to the curved areas are approximately equal, without taking into account variations in processing accuracy. <Siebtes Ausführungsbeispiel>

[0065] A semiconductor device and a method for manufacturing the semiconductor device according to a seventh preferred embodiment are described below. All components similar to those in the previous preferred embodiments are identified by the same symbols, and detailed descriptions of the same components are omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0066] Fig. Figure 8 shows a top view schematically illustrating a configuration to enable the semiconductor device according to the present preferred embodiment.

[0067] As in Fig. As shown in Figure 8, the semiconductor chips 81 and the semiconductor chips 82 are arranged inside a housing defined by an outer frame 102.

[0068] A wire bonding time within a cycle time of a step is considerably long in terms of depreciation costs of wire bonding equipment.

[0069] Furthermore, products with different wire bond configurations can be manufactured in parallel at multiple plants. In such a case, complex wiring of bond wires increases fixture downtime during a wire bonding program, impacting initial costs. Additionally, complex wire bonding complicates initial inspections, quickly leading to extra costs due to returns of missing designs.

[0070] According to the present preferred embodiment, the angle between the direction in which the semiconductor chips 81 of the same type are arranged and the direction in which the bond wires 103 are arranged in the semiconductor chips 81 is within 20 degrees. Furthermore, the angle between the direction in which the semiconductor chips 82 of the same type are arranged and the direction in which the bond wires 103 are arranged in the semiconductor chips 82 is within 20 degrees. This configuration provides wire bonding with high symmetry, continuity, and periodicity, thereby solving the problems described above. <Achtes bevorzugtes Ausführungsbeispiel>

[0071] A semiconductor device and a method for manufacturing the semiconductor device according to an eighth preferred embodiment are described below. All components similar to those in the previous preferred embodiments are identified by the same symbols, and detailed descriptions of the same components are omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0072] Fig. Figure 9 shows a top view schematically illustrating the structure of a semiconductor chip and its periphery inside a housing in a configuration to enable the semiconductor device according to the present preferred embodiment. Fig. Figure 9 shows only one signal line 108 for a complex element 94 and omits one signal line 108 for a complex element 93.

[0073] Bond wires 103 from the emitter of an IGBT semiconductor chip are long when connected to a circuit pattern via a diode chip. Consequently, the number of bond wires must increase to address heat generation. This is detrimental in terms of processing time and manufacturing costs. Unfortunately, the wire connections of a drive emitter are short when the bond wires 103 from the emitter of the IGBT semiconductor chip are not connected to the circuit pattern via the diode chip.

[0074] Accordingly, in the present preferred embodiment, a complex element 93 and a complex element 94 each comprise the IGBT semiconductor chip and the diode chip, respectively. The complex element 94 is not provided via a transition circuit pattern 95. In the complex element 94, an emitter drive line, which is a driver potential reference 91 of the IGBT semiconductor chip, is connected to the circuit pattern or a signal electrode via the diode chip. <Neuntes bevorzugtes Ausführungsbeispiel>

[0075] A semiconductor device and a method for manufacturing the semiconductor device according to a ninth preferred embodiment are described below.

[0076] In a general method, as much wire bonding as possible is used in the absence of a physical obstacle, such as a housing or electrode. A main electrode is then bonded by ultrasonic bonding, followed by a common electrical connection between a signal electrode of the housing and a circuit pattern on an insulating substrate.

[0077] This method requires wire bonding before and after ultrasonic bonding, thus necessitating two wire bonding steps. However, the tools used in ultrasonic bonding are large. It is therefore difficult to bond the signal electrode to the circuit pattern via ultrasonic bonding for a module with a narrow interior. Consequently, eliminating the wire bonding step the second time around by connecting the signal electrode during the ultrasonic bonding step creates a significant design obstacle.

[0078] Accordingly, all electrodes are bonded by ultrasonic bonding without performing wire bonding to connect the semiconductor chips and the circuit pattern. Wire bonding is then performed to connect the semiconductor chips and the circuit pattern. <Zehntes bevorzugtes Ausführungsbeispiel>

[0079] A semiconductor device and a method for manufacturing the semiconductor device according to a tenth preferred embodiment are described below.

[0080] The use of a thick copper substrate results in a very high probability of current excitation. A typical silicon semiconductor chip device cannot therefore fully exploit its advantages due to limitations imposed by heat loss and heat dissipation. Consequently, a semiconductor chip incorporating a wide-bandgap semiconductor is used.

[0081] Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), diamond (C), Ga₂O₃, AlN, C₃N₄, Si₃N₄, Ge₃N₄, Sn₃N₄, Al₄C₃, Ga₄C₃, and GeC. A wide-bandgap semiconductor is typically one with a bandgap of approximately 2 eV or higher. Examples of wide-bandgap semiconductors include a group III nitride, such as gallium nitride (GaN), a group II oxide, such as zinc oxide (ZnO), a group II chalcogenide, such as zinc selenide (ZnSe), diamond, and silicon carbide.

[0082] A switching device comprising a wide-bandgap semiconductor typically exhibits a lower amount of heat loss per unit area than a switching device comprising an SI semiconductor. Consequently, the limitations imposed by heat loss and heat dissipation would be eased by using the thick copper substrate. <Elftes bevorzugtes Ausführungsbeispiel>

[0083] A semiconductor device and a method for manufacturing the semiconductor device according to an eleventh preferred embodiment are described below. All components similar to those in the previous preferred embodiments are identified by the same symbols, and detailed descriptions of the same components are omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0084] Fig. Figure 1 shows a top view schematically illustrating a configuration for enabling the semiconductor device according to the present preferred embodiment. Fig. Figure 1 illustrates the previously described components of the individual preferred embodiment in a combination.

[0085] As in Fig.As illustrated in Figure 1, an insulating substrate 105 is arranged inside a housing defined by an outer frame 102. Furthermore, a complex element 113 and a complex element 114 are arranged on the insulating substrate 105. Bond wires 103 are also arranged along a longer side of the outer frame 102 of the housing to connect each of the complex elements to the circuit pattern.

[0086] In addition, the outer frame 102 of the housing is provided with electrodes 100 and signal connections 101.

[0087] Furthermore, the use of the thick copper substrate allows current to flow freely in a narrow pattern direction. Accordingly, a narrow junction circuit pattern 115 is provided between individual semiconductor chips of the complex element 113. This establishes a connection between bond wires 103 from an emitter of the IGBT semiconductor chip and bond wires 103 from a diode of a diode chip via the junction circuit pattern 115.

[0088] Furthermore, a large number of main electrodes 106 are arranged on the insulating substrate 105. The main electrodes 106 are concentrated near a side extending in the longer lateral direction of the outer frame 102 of the housing.

[0089] Furthermore, a plurality of signal electrodes 107 are arranged on the insulating substrate 105. The signal electrodes 107 are each individually arranged near sides extending in a shorter lateral direction of the outer frame 102 of the housing and are each electrically connected to the individual signal terminals 101 by signal lines 108. One of the signal lines 108 is arranged near a side opposite the side on which the terminals of the main electrodes 106 are arranged, with the signal line 108 extending between some of the signal electrodes 107 that are positioned away from the signal terminals 101 and the signal terminals 101. <Effekte der bevorzugten Ausführungsbeispiele>

[0090] The following illustrates the effects of the preferred embodiments described above. These effects are based on specific configurations illustrated in the preferred embodiments described above. Furthermore, these effects can be replaced, to the extent that similar effects are achieved, by different specific embodiments illustrated in the description. This replacement can also be achieved using several preferred embodiments. That is, combinations of the individual configurations illustrated in the various preferred embodiments can produce similar effects.

[0091] According to the preferred embodiments described above, the semiconductor device comprises the plurality of semiconductor chips 104 and the bond wires 103. Furthermore, the semiconductor chips 104 are arranged on the circuit pattern inside the housing, which is defined in plan view by the outer frame 102. The bond wires 103 are used to electrically connect the semiconductor chips 104 and the circuit pattern. The semiconductor chips 104 are arranged along the longer side of the housing. The bond wires 103 are also arranged along the longer side of the housing.

[0092] Such configurations minimize limitations on wire bonding activities inside the narrow and deep enclosure.

[0093] Several configurations illustrated in the description can be omitted if necessary, with the exception of the configurations listed above. That is, the configurations listed above alone produce the effect described above. However, the configurations listed above can additionally include at least one of the various configurations illustrated in the description, if necessary. That is, the configurations listed above can additionally include the various configurations illustrated in the description that are excluded from these configurations. Such an additionally included configuration still produces the effect described above.

[0094] Furthermore, according to the preferred embodiments described above, the circuit pattern is made from a copper foil with a thickness of 0.4 mm or greater. Such a configuration increases the cross-sectional area of ​​the pattern per unit pattern width. Consequently, a large current would flow in the narrow pattern width, and the current would flow freely in the narrow pattern direction.

[0095] According to the preferred embodiments described above, the semiconductor device further comprises two first complex elements in which the two semiconductor chips are connected antiparallel. Here, complex element 33 and complex element 34 correspond to the two first complex elements. Furthermore, one of the first complex elements, i.e., complex element 33, is configured such that the two semiconductor chips are connected in parallel via the first transition circuit pattern, which is arranged between the two semiconductor chips in the top view. Here, transition circuit pattern 35 corresponds to the first transition circuit pattern. The other first complex element, i.e., complex element 34, is configured such that the two semiconductor chips are directly connected antiparallel, not via transition circuit pattern 35. Such a configuration reduces waste and / or...unused areas when providing the circuit pattern to connect the two complex elements, and minimizes the size and manufacturing costs of the enclosures.

[0096] Furthermore, the semiconductor device according to the preferred embodiment described above comprises the signal electrodes, which are arranged inside the housing and electrically connected to the individual semiconductor chips 104. In addition, one of the two first complex elements comprises the IGBT semiconductor chip and the diode chip. Here, complex element 93 and complex element 94 correspond to the first complex elements. Furthermore, complex element 94 corresponds to the other first complex element. The driver potential reference 91 of the IGBT semiconductor chip is also connected to the circuit pattern or the signal electrodes via the diode chip. In such a configuration, the bond wires 103 from the emitter of the IGBT semiconductor chip are not excessively long. This eliminates the need to increase the number of bond wires to address heat generation. Consequently, machining times and manufacturing costs are reduced.

[0097] Furthermore, the semiconductor device according to the preferred embodiments described above comprises two second complex elements in which the two semiconductor chips, which are the diode chips, are connected in parallel. Here, complex element 65 and complex element 66 correspond to the second complex elements. Moreover, one of the two second complex elements, i.e., complex element 65, is configured such that the two semiconductor chips are connected in parallel via the second transition circuit pattern. Here, transition circuit pattern 67 corresponds to the second transition circuit pattern.

[0098] Furthermore, the other of the two second complex elements, i.e., complex element 66, is configured such that the two semiconductor chips are not directly connected in parallel via the second transition circuit pattern. This configuration reduces the waste or unused area in providing the circuit pattern for connecting the two complex elements and minimizes the size and manufacturing costs of the packages.

[0099] According to the preferred embodiments described above, the plurality of semiconductor chips 104 further comprises a wide-bandgap semiconductor. A switching device that typically comprises a wide-bandgap semiconductor exhibits a lower amount of heat loss per unit area than a switching device that comprises a silicon semiconductor. Consequently, the limitations imposed by heat loss and heat dissipation would be eased when the thick copper substrate is used.

[0100] Furthermore, the semiconductor device according to the preferred embodiments described above comprises the main electrodes 106 inside the housing. The main electrodes 106 are arranged near the side extending along the longer side of the housing. In addition, the main electrodes 106 and the circuit pattern are connected to each other by ultrasonic bonding, soldering, or brazing. Such a configuration allows for a reduction in inductance by concentrating the electrodes, which are magnetic flux sources, near one side, thus exhibiting high magnetic resistance. Moreover, the configuration reduces the manufacturing costs of the electrodes. Furthermore, the configuration simplifies the design process for eliminating problems related to mutual inductance with the signal lines 108.

[0101] Furthermore, the semiconductor device according to the preferred embodiments described above comprises the plurality of signal electrodes 107 and the signal terminals 101, which are electrically connected to the signal electrodes 107. In addition, the plurality of signal electrodes 107 are arranged inside the housing and are electrically connected to the individual semiconductor chips 104. The signal electrodes 107 are also individually arranged near one side extending in the shorter direction of the housing. Furthermore, the signal terminals 101 are arranged on one side of the outer frame 102 extending in the shorter direction of the housing. Finally, the signal line 108 for connecting the signal electrodes 107 and the signal terminals 101 runs near the other side extending in the longer direction of the housing.It should be noted that the signal electrodes 107 are arranged near the side extending in the shorter direction of the housing, with this side opposite one side of the outer frame 102 where the signal terminals 101 are located. It should further be noted that the other side is opposite the one side extending in the longer direction of the housing where the main electrodes 106 are located. In such a configuration, the signal line 108 is unlikely to be affected by mutual induction of the main electrodes 106. Furthermore, such a configuration allows the signal lines to be arranged away from the other circuits in the circuit diagram.

[0102] According to the preferred embodiments described above, the housing further comprises a recessed area 71 on the top surface of the housing. In addition, the edge of the main electrode 106a is exposed within the recessed area 71 and is bent inwards towards the housing in a top view. Such a structure would provide sufficient creepage distance between the outer frame 102 and the terminal of the bent main electrode 106a if the terminal of the main electrode 106a is located close to the outer frame 102 before being bent.

[0103] Furthermore, according to the preferred embodiments described above, the plurality of semiconductor chips, each of the same type, are arranged along the longer side of the package. Moreover, the angle between the direction in which the plurality of semiconductor chips are arranged and the direction in which the bond wires 103 are arranged in the semiconductor chips is within 20 degrees. Such a structure provides wire bonding with high symmetry, continuity, and periodicity, thereby reducing manufacturing costs.

[0104] Furthermore, according to the preferred embodiments described above, a method for manufacturing the semiconductor device comprises bonding the main electrodes 106 to the circuit pattern inside the housing, which is defined in plan view by the outer frame, by ultrasonic bonding near one of the sides extending in the longer side direction of the housing. The method also comprises electrically connecting the plurality of semiconductor chips 104 to the circuit pattern with the bond wires 103 after bonding the main electrode 106. It should be noted that the plurality of semiconductor chips 104 are arranged on the circuit pattern inside the housing along the longer side direction of the housing. It should also be noted that the bond wires 103 are arranged in a row along the longer side direction of the housing.

[0105] This configuration minimizes the limitations of wire bonding activities inside the narrow and deep housing. Furthermore, the bonding step is performed only once in this configuration. This reduces manufacturing costs and shortens cycle time.

[0106] Various configurations illustrated in the description can be omitted if necessary, with the exception of the configurations above. That is, the configurations above alone produce the effect described above. However, the configurations above can additionally include, if necessary, at least one of the other configurations illustrated in the description. That is, the configurations above can also include the other configurations that are excluded from those illustrated in the description. Such additionally included configurations likewise produce the effect described above. <Variationen der bevorzugten Ausführungsbeispiele>

[0107] The material quality, size, or shape of each component, the positions of the components relative to one another, or any condition for an implementation described in each of the preferred embodiments are in all aspects illustrative and do not limit the present invention. Therefore, it can be assumed that various variations not shown are within the scope of the technology disclosed in the description. Examples of such variations include a modification, an addition, and an omission of at least one component. Another example includes omitting at least one component from at least one of the preferred embodiments and combining the omitted component with another component from a different preferred embodiment.

[0108] Furthermore, unless otherwise stated, "a" component as described in any of the preferred embodiments may comprise "one or more" components. Individual components are also conceptual units. A component may comprise multiple structures, a component may correspond to a part of a structure, and multiple components may be contained within a structure. Each component comprises a structure of a different configuration or shape, provided that the structure of the different configuration or shape achieves the same function.

[0109] Furthermore, the explanations in the description are used for all purposes of the present technique. This is therefore not an admission that each of the descriptions provided herein represents a conventional technique.

[0110] If the preferred embodiments described above further contain descriptions of materials without being specifically specified, it is quite understandable that an example of these materials, unless otherwise stated, includes alloys with further additives in these materials.

[0111] In summary, it can be stated that: One technique disclosed in the description relates to a semiconductor device that enables a minimization of limitations in wire bonding activities, and to a method for producing the

[0112] Semiconductor device. The semiconductor device of the present technology comprises: a plurality of semiconductor chips 104 arranged on a circuit pattern inside a housing defined in a top view by an outer frame 102; and bond wires 103 for electrically connecting the semiconductor chips 104 and the circuit pattern to one another. The semiconductor chips 104 are arranged along a longer side of the housing. The bond wires 103 are arranged along the longer side of the housing. REFERENCE MARK LIST 32 bonding points 33, 34 complex element 35 transition circuit patterns 62 bonding points 65, 66 complex element 67 Transition Circuit Patterns 71 recessed area 73a Housing 81, 82 semiconductor chips 91 Driver Potential Reference 93, 94 complex element 95 transition circuit patterns 100 electrodes 101 Signal connection 102 outer frame 103 bond wires 104 Semiconductor chips 105 Insulating substrate 106a Main electrode 107 Signal electrode 108 Signal line 200, 201, 203 Semiconductor chip 204, 205 Main electrode 32 bonding points 33, 34 complex element 35 transition circuit patterns 62 bonding points 65, 66 complex element 67 Transition Circuit Patterns 71 recessed area 73a Housing 81, 82 semiconductor chips 91 Driver Potential Reference 93, 94 complex element 95 transition circuit patterns

Claims

[1] Semiconductor device comprising: a plurality of semiconductor chips (104) arranged on a circuit pattern within a housing defined in a top view by an outer frame (102); Bond wires (103) for electrically connecting the plurality of semiconductor chips (104) and the circuit pattern to one another; and a main electrode (106, 106a) which is located inside the housing, wherein the plurality of semiconductor chips (104) is arranged along a longer side direction of the housing, wherein the bond wires (103) are arranged along the longer side direction of the housing, wherein the main electrode (106, 106a) is located near one of the sides extending in the longer lateral direction of the housing, and wherein the main electrode (106, 106a) and the circuit pattern are connected to each other by ultrasonic bonding, soldering or brazing, wherein the circuit pattern is made of a copper foil with a thickness of 0.4 mm or more, and the semiconductor device has two first complex elements (33, 93, 34, 94) in which two of the multitude of semiconductor chips (104) are connected in antiparallel, wherein one (33, 93) of the two first complex elements is configured such that two from the plurality of semiconductor chips (104) are connected antiparallel via a first transition circuit pattern (35, 95) which is located at a position which in a top view is situated between the two from the plurality of semiconductor chips (104), and wherein another (34, 94) of the first two complex elements is configured such that two of the plurality of semiconductor chips (104) are not directly connected antiparallel via a first transition circuit pattern (35, 95). [2] Semiconductor device according to claim 1, comprising a signal electrode arranged inside the housing, wherein the signal electrode is connected to each of the plurality of semiconductor chips (104), wherein the other (94) of the first two complex elements (93, 94) comprises an IGBT semiconductor chip and a diode chip, and wherein the IGBT semiconductor chip has a driver potential reference which is connected to the circuit pattern or signal electrode via the diode chip. [3] Semiconductor device according to one of claims 1 or 2, wherein the plurality of semiconductor chips (104) comprise large bandgap semiconductors. [4] Semiconductor device according to any one of claims 1 to 3, further comprising: a plurality of signal electrodes (107) arranged inside the housing, wherein the plurality of signal electrodes (107) are electrically connected to the plurality of semiconductor chips (104); and a signal terminal (101) which is electrically connected to each of the signal electrodes (107), wherein the signal electrodes (107) are each arranged near a side that extends in a shorter lateral direction of the housing, wherein the signal terminal (101) is located on a side of the outer frame (102) which extends in the shorter lateral direction of the housing, and wherein a signal line (108) for connecting each of the signal electrodes (107) and the signal terminal (101) to each other runs near a first longer side, wherein each of the individual electrodes (107) is arranged near a first shorter side, which is the side extending in the shorter lateral direction of the housing, wherein the first shorter side is opposite one side of the outer frame (102) where the signal terminal (101) is arranged, wherein the first longer side is another of the sides extending in the longer lateral direction of the housing, wherein the first longer side is opposite a second longer side, which is one of the sides extending in the longer lateral direction of the housing where the main electrode (106, 106a) is arranged. [5] Semiconductor device according to any one of claims 1 to 4, wherein the housing has a recessed area (71) on a top surface of the housing, and wherein the main electrode (106a) has an end region which is exposed from the recessed area (71) and is bent inwards towards the housing in a top view of the recessed area (71). [6] Semiconductor device according to any one of claims 1 to 5, wherein the plurality of semiconductor chips are arranged along the longer side direction of the housing, wherein the plurality of semiconductor chips are all of the same type, and wherein an angle between a direction in which the plurality of semiconductor chips are arranged and a direction in which the bond wires (103) of the semiconductor chips are arranged is within 20 degrees.

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