Semiconductor device, method for manufacturing a semiconductor device and method

Abstract

Semiconductor device (100, 300) comprising: a substrate (102) with a fin (104, 302, 307) extending from it, the fin (104, 302, 307) having a channel region (304) and a source and a drain region (306) adjacent to and on either side of the channel region (304); a gate structure (108, 308) arranged over the channel region (304), the gate structure (108, 308) having a metal layer (114, 308) arranged over a dielectric layer (112, 308); a first epitaxial layer (306A, 306B) embedded at least partially in the source and drain regions (306); a second epitaxial layer (702) arranged over the first epitaxial layer (306A, 306B) is arranged, wherein an upper surface of the second epitaxial layer (702) is higher than an upper surface of the metal layer (114, 308) along a direction perpendicular to the substrate (102);and a silicide layer (802) arranged above and in contact with the second epitaxial layer (702); wherein the first epitaxial layer (306A, 306B) is symmetric about a plane which intersects the fin (104, 302, 307) along a longitudinal direction of the fin (104, 302, 307) in the middle, and wherein the second epitaxial layer (702) is asymmetric about the plane in the source region (306B) and symmetric about the plane in the drain region (306A).

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US patent application No. 62 / 343,644, filed on May 31, 2016, which is hereby incorporated by reference in its entirety. BACKGROUND

[0002] The electronics industry is experiencing a constantly increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting a greater number of increasingly complex and demanding functions. Accordingly, the semiconductor industry continues its trend toward producing cost-effective, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by scaling down the dimensions of semiconductor ICs (e.g., minimum feature size), thereby improving production efficiency and reducing associated costs. However, this scaling has also led to increased complexity in the semiconductor manufacturing process.Therefore, achieving further progress in semiconductor ICs and semiconductor devices requires similar progress in semiconductor manufacturing processes and technology.

[0003] Recently, in an effort to improve gate control by increasing gate-to-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs), multi-gate devices have been introduced. One such multi-gate device is the Fin field-effect transistor (FinFET). The FinFET derives its name from the fin-like structure (fin = fin) that extends from the substrate on which it is formed and is used to create the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs.In at least some examples, FinFET fabrication can involve epitaxial growth of source and drain regions in both p-type and n-type FinFETs, for example, through a dual-epi process. However, conventional dual-epi processes are limited in that contact resistances and contact area (e.g., silicide contact area) cannot be improved (e.g., increased) without compromising capacitance due to pitch scaling, and the choice of materials is restricted by the high thermal budget of front-end-of-line (FEOL) processes. The ability to improve source / drain stressors (e.g., stress applied to a device channel) is also limited for similar reasons. Furthermore, stress reduction is achieved through the conventional pre-amorphization implant (PAI) process (e.g., by using a stylus to reduce the surface area of ​​the source).(used in connection with silicide formation). Thus, the existing methods have not yet proven to be completely satisfactory in every respect. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity.

[0005] Fig. 1 is a perspective view of an embodiment of a FinFET device according to one or more aspects of the present disclosure;

[0006] Fig. 2 is a flowchart of a process for manufacturing a FinFET device according to one or more aspects of the present disclosure;

[0007] Fig. 3– Fig. Figure 10 shows sectional views of an embodiment of a FinFET device, which includes one or more steps of the method of Fig. 2 correspond;

[0008] Fig. 3A– Fig. 6A, Fig. 9A and Fig. 10A are provided along a sectional view, which is essentially similar to section AA' of Fig. 1 is;

[0009] Fig. 3B– Fig. 6B, Fig. 9B and Fig. 10B are provided along a sectional view, which is essentially similar to section BB' of Fig. 1 is; and

[0010] Fig. Figure 11 provides a top view of an embodiment of several FinFET devices according to one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing various features of the intended subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not to be considered limiting. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which further features may be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself establish a connection between the various designs and / or configurations discussed.

[0012] Furthermore, terms denoting spatial relationships, such as "below," "under," "lower," "above," "upper," and the like, may be used here to simplify the description and describe the relationship of one element or feature to another, as illustrated in the figures. These terms denoting spatial relationships are intended to include other orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or moved to a different orientation), and the terms used here to describe spatial relationships may be interpreted accordingly.

[0013] It should also be noted that the present disclosure introduces embodiments in the form of multi-gate transistors or multi-gate fin transistors, referred to herein as FinFET devices. Such a device may be a p-type metal-oxide-semiconductor FinFET device or an n-type metal-oxide-semiconductor FinFET device. The FinFET device may be a dual-gate device, a triple-gate device, a bulk device, a silicon-on-insulator (SOI) device, and / or have another configuration. A person skilled in the art may be aware of other embodiments of semiconductor devices that may benefit from aspects of the present disclosure. For example, some embodiments described here can also be applied to Gate-All-Around (GAA) devices, Omega-Gate (Ω-Gate) devices, or Pi-Gate (H-Gate) devices.

[0014] In Fig. 1 is a FinFET device 100 The FinFET device is shown. 100 The FinFET device features one or more fin-based multi-gate field-effect transistors (FETs). 100 a substrate 102 , at least one that is distinct from the substrate 102 extending fin element (fin element) 104 , isolation areas 106 and one on the fin element 104 and the gate structure arranged around it 108 on. The substrate 102The substrate can be a semiconductor, such as a silicon substrate. The substrate can have various layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate can have various doping configurations, depending on design requirements, as is known in the art. The substrate can also have other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate can have a semiconducting compound and / or a semiconducting alloy. Furthermore, in some embodiments, the substrate can have an epitaxial layer (epi-layer), the substrate can be strained to improve performance, the substrate can have a silicon-on-insulator (SOI) structure, and / or the substrate can have other suitable features that enhance performance.

[0015] The fin element 104 can, like the substrate 102 , silicon or another elemental semiconductor such as germanium; a semiconducting compound, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; a semiconducting alloy, including SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP; or combinations thereof. The Finns 104These elements can be manufactured using suitable processes, including photolithography and etching. The photolithography process may involve: forming a photoresist layer overlaid on the substrate (e.g., on a silicon layer), exposing the resist to a structure, performing a post-exposure bake process, and developing the resist to form a masking element containing the resist. In some embodiments, the structuring of the resist to form the masking element can be performed using an electron beam (E-beam) lithography process. The masking element can then be used to protect areas of the substrate, while an etching process forms pits in the silicon layer, creating an elongated fin. 104leaves behind. The depressions can be etched using a dry etching process (e.g., chemical oxide removal), a wet etching process, and / or other suitable processes. Numerous other embodiments of methods can also be used to etch the fins. 104 on the substrate 102 to be trained, applied.

[0016] Each of the several fins 104 It also has a source area. 105 and a drain area 107 on, with the source and drain areas 105 , 107 in or on the fin 104 and / or are designed to surround them. The source and drain areas. 105 , 107 can via the Finn 104 to have grown epitaxially. A channel area of ​​a transistor is located within the fin. 104 arranged, with it under the gate structure 108lays, along a plane that is essentially parallel to one defined by the intersection AA' of Fig. 1 defined plane. In some examples, the channel region of the fins features a high-mobility material, such as germanium, as well as any of the semiconducting compounds or semiconducting alloys discussed above, and / or combinations thereof. High-mobility materials include those with an electron mobility greater than that of silicon. For example, higher than that of Si, which has an intrinsic electron mobility at room temperature (300 K) of approximately 1350 cm⁻¹. 2 / V – s and a hole mobility of approximately 480 cm 2 / V – s exhibits.

[0017] The isolation areas 106These could be shallow trench insulation (STI) features. Alternatively, a field oxide, a LOCOS feature, and / or other suitable insulation features on and / or within the substrate could be present. 102 be implemented. The isolation areas 106 They can consist of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a dielectric with a low k-value, combinations thereof, and / or another suitable material known in the art. In one embodiment, the insulating structures are STI features and are formed by creating grooves in the substrate. 102 The grooves can be etched. They can then be filled with insulating material, followed by a chemical-mechanical polishing (CMP) process. However, other embodiments are also possible. In some embodiments, the insulating areas can be... 106have a multi-layered structure, for example with one or more liner layers.

[0018] The gate structure 108 features a gate stack with an interface layer 110 , which are above the channel area of ​​the Finn 104 is formed, a gate dielectric layer 112 , which are above the interface layer 110 is formed, and a metal layer 114 , which are above the gate dielectric layer 112 is formed, on. The interface layer 110 It can have a dielectric material such as a silicon oxide layer (SiO2) or silicon oxynitride (SiON). The interface layer 110 The gate dielectric layer can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or another suitable method. 112The gate dielectric layer can include a high k-value dielectric layer, such as hafnium oxide (HfO2). Alternatively, the high k-value dielectric layer can include other high k-value dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, combinations thereof, or another suitable material. In still other embodiments, the gate dielectric layer can include silicon dioxide or another suitable dielectric. The gate dielectric layer can be formed by ALD, physical vapor deposition (PVD), oxidation, and / or other suitable methods. The metal layer 114 may include a conductive layer, such as W, TiN, TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, Ni, combinations thereof, and / or other suitable compositions. In some embodiments, the metal layer may 114The FinFET device can feature a first metal material for n-type FinFETs and a second metal material for p-type FinFETs. Thus, the FinFET device can... 100 exhibit a metal-gate configuration with a dual working function. For example, the first metal material (e.g., for n-type devices) may include metals with a working function that is essentially consistent with a working function of the substrate conduction band or at least essentially consistent with a working function of the conduction band of the fin channel region. 104 is consistent. Similarly, for example, the second metal material (e.g., for p-type devices) can include metals with a work function that is essentially consistent with a work function of the substrate valence band or at least essentially consistent with a work function of the valence band of the fin's channel region. 104 is in harmony. Thus, the metal layer can114 a gate electrode for the FinFET device 100 provide, specifically for both n-type and p-type FinFET devices. 100 In some embodiments, the metal layer 114 Alternatively, it may contain a polysilicon layer. The metal layer 114 It can be formed using PVD, CVD, electron beam evaporation (E-beam evaporation) and / or other suitable processes. In some embodiments, the sidewalls of the gate structure have [features / structures - context needed]. 108 Sidewall spacers are formed. The sidewall spacers can contain a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof.

[0019] As explained above, the fabrication of a FinFET device (e.g., the FinFET device) can 100) in both a p-type FinFET and an n-type FinFET, epitaxial growth of source and drain regions (e.g., the source / drain regions) occurs. 105 , 107These include, for example, a dual-epitactic process. However, conventional dual-epi processes are limited in that contact resistances and contact area (e.g., silicide contact area) cannot be improved (e.g., increased) without compromising capacity due to pitch scaling, and the choice of materials is limited by the high thermal budget of front-end-of-line (FEOL) processes. The ability to improve source / drain stressors (e.g., stress applied to a device channel) is also limited for similar reasons. Furthermore, stress reduction is achieved through the conventional pre-amorphization implant (PAI) process (e.g., used in conjunction with silicide formation). Thus, existing methods have not yet proven entirely satisfactory in every respect.

[0020] Embodiments of the present disclosure offer advantages over existing technology; however, it is understood that other embodiments may offer other advantages, not all advantages are necessarily discussed here, and no particular advantage is required for all embodiments. For example, embodiments described here include methods and structures for providing a unique structure for source and drain (S / D) features of FinFETs, which ensure reduced S / D contact resistance, improved FinFET channel stress, and lower capacitance. For example, such S / D features include stacked epitaxial (EPI) layers in each of the S / D regions. In some embodiments, the stacked EPI layers in each of the S / D regions may be referred to as cascaded EPI features.In some examples, the cascaded EPI features include a first EPI layer, partially embedded in a fin over a semiconductor substrate, and a second EPI layer on top of the first. For example, the two stacked EPI layers may be lattice-connected and may consist of the same or different semiconductor material(s). In some embodiments involving an n-type FinFET, the second EPI layer may have a lattice constant smaller than that of silicon (Si). In some embodiments involving a p-type FinFET, the second EPI layer may have a lattice constant larger than that of silicon germanium (SiGe).In various examples, the second EPI layer can be partially self-aligning with the first EPI layer, and the shape of the second EPI layer can be at least partially defined by an opening in an inter-layer dielectric (ILD) layer arranged above the semiconductor substrate. In some cases, the FinFET device can further include a silicide feature over a top surface of the second EPI layer, the silicide feature having an extended surface area to reduce the S / D contact resistance. Further embodiments and advantages are explained below or will be obvious to those skilled in the art who are in possession of this disclosure.

[0021] It will now be on Fig. 2. Reference is made to it; it shows a procedure 200 for the fabrication of a semiconductor device which includes a FinFET device. The process 200This method can be applied to implement a fin-based semiconductor device, comprising a method to provide cascaded EPI features in both a source and a drain region of a FinFET. In some embodiments, the method can 200 to be used to operate the device 100 to produce the above with reference to Fig. 1 was described. Therefore, one or more aspects described above with reference to the device may not apply. 100 as explained, also regarding the procedure 200 be applied. Furthermore, they Fig. 3– Fig. 10 sectional views of an exemplary device 300 ready to proceed according to one or more steps of the procedure 200 from Fig. 2 was manufactured.

[0022] It goes without saying that parts of the procedure 200 and / or the semiconductor device 300They can be manufactured using a well-known process sequence of complementary metal-oxide-semiconductor (CMOS) technology, and therefore some processes are only briefly described here. Furthermore, as described above, the device can be 300 exhibit aspects that are also present in the device 100 are present; therefore, some aspects and / or processes of the device are 300 This is only briefly discussed for the sake of clarity of understanding. Furthermore, the semiconductor device 300 Various other devices and features are included, such as additional transistors, bipolar transistors, resistors, capacitors, diodes, fuses, etc. However, it is simplified here for a better understanding of the inventive concepts of the present disclosure. Furthermore, in some embodiments, the semiconductor device includes 300several semiconductor devices (e.g. transistors) which can be interconnected.

[0023] In various embodiments, the device can 300 an intermediate device that is manufactured during the processing of an integrated circuit or part thereof and which may include a static random access memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors and inductors, and active components such as P-channel field-effect transistors (PFETs), N-channel FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells and / or combinations thereof.

[0024] The focus will now shift to the procedure. 200 Reference is made to; the procedure 200 begins with block 202 , where a substrate is provided that has one or more devices having a first epitaxial (EPI) source / drain layer. In some embodiments, the one or more devices may include one or more FinFET devices with fin elements extending from the substrate, isolation regions to separate the one or more FinFET devices, and a gate structure formed over a channel region of the fin elements. The substrate may be substantially similar to the substrate 102 to be, which above with reference to Fig. As explained in section 1. The fins and insulation areas can also be essentially similar to the fin elements. 104 and isolation areas 106 be, which above with reference to the device 100 from Fig. 1. Furthermore, the gate structure can be essentially similar to the gate structure. 108 be, which above with reference to the device 100 from Fig. 1 was described. We will now turn to the example of Fig. 3A / Fig. Reference is made to 3B; a semiconductor device is shown. 300 , which has a semiconductor substrate from which a fin element extends 302 The device extends 300 also shows canal areas 304 within the fin element 302 from adjacent FinFET devices and a source / drain structure 306 , which are between the canal areas 304 is arranged. In various devices, the device has 300 furthermore, a gate structure 308 on, which above each of the canal areas 304 is arranged, and a nitride layer 310 , which are above each of the gate structures 308is arranged. In some examples, the nitride layer can 310 This can be described as a sacrificial layer. In some embodiments, the nitride layer can be 310 It can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or another suitable process. In some embodiments, part of the gate structure can be 308 (e.g., a metal layer) can be etched back, for example to form a depression within which the nitride layer 310 is being trained. Side wall spacers 312 , which are essentially similar to those mentioned above with reference to the device 100 from Fig. As described in section 1, they can also be found on the side walls of the gate structures. 308 be trained.

[0025] Fig. 3B, which provides a section view that is essentially similar to section BB' of Fig. 1 indicates adjacent source / drain structures. 306A , 306B In various examples, the source / drain structure can be 306 each of the source / drain structures 306A , 306B This includes, for example, the source / drain structures. 306A , 306B by epitaxial growth of a semiconductor material layer (e.g. over fin sections) 307 ) can be formed. In various embodiments, the semiconductor material layer used to form the source / drain structures can be 306A , 306B to form, including Ge, Si, SiGeB, GaAs, AlGaAs, SiGe, GaAsP, SiP or another suitable material. The source / drain structures 306A , 306Bcan be formed through one or more epitaxial (epi)processes. However, for the purposes of this disclosure, the source / drain structures can be considered. 306A / 306B This can be referred to as a "first epitaxial source / drain layer." As described in more detail below, a "second epitaxial source / drain layer" subsequently forms over the first epitaxial source / drain layer, thereby creating the cascaded EPI features described above. Furthermore, the source / drain structures can 306 , 306A , 306B due to their position in the fin 302 The embedded position can be referred to as "embedded epitaxial source / drain layers". In some embodiments, the source / drain structures can 306A , 306Bdoping occurs in place during the epi-process. For example, in some embodiments, epitaxially grown source / drain structures can be created. 306A , 306B SiGe is doped with boron to form SiGeB. In some embodiments, epitaxially grown epi-source / drain structures can be formed. 306A , 306B Si can be doped with carbon to form Si:C source / drain structures, with phosphorus to form Si:P source / drain structures, or with both carbon and phosphorus to form SiCP source / drain structures. In some embodiments, the source / drain structures are 306A , 306B The nutrient is not placed in place; instead, an implantation process is performed to secure the source / drain structures. 306A , 306B to dope. In some embodiments, the formation of the source / drain structures can 306A , 306Bfor n-conducting and p-conducting source / drain structures 306A , 306B Each step is performed in separate processing sequences. In some embodiments, after the formation of the source / drain structures, 306A , 306B An epi-tempering process can be carried out. Furthermore, in some embodiments, after the formation of the source / drain structures, 306A , 306B Side wall spacers 316 can be formed. This can be done in various configurations, and for example depending on the distance between the source / drain structures. 306A , 306B , the source / drain structures can 306A , 306B unite (e.g., by physically touching each other) to form a single, unified source / drain structure. Furthermore, in some examples, a gap area may be present. 320 (e.g. a cavity) in a space between the source / drain structures 306A , 306B be trained, as in Fig. 3B is shown.

[0026] As explained above and for example in Fig. The source / drain structure is shown in 3A. 306 (or 306A , 306B ) a canal area (e.g. the canal areas) 304 ) arranged adjacently. This can lead to the formation of source / drain structures. 306 , 306A , 306B The selected material is chosen so that a stress of a desired magnitude (e.g., tensile or compressive stress) is exerted on the adjacent channel area. In other words, a material suitable for the source / drain structures. 306 , 306A , 306BThe material used can differ from that used for the channel region, thereby generating the desired stress. In at least some conventional processes, after the desired channel stress has been established (e.g., by means of an adjacent source / drain structure), subsequent processing steps, such as pre-amorphization implant (PAI) of silicide or subsequent source / drain ion implantation, can adversely affect the previously established channel stress (e.g., undesired stress relaxation may occur). In embodiments of the present disclosure, these and other possible causes of stress relaxation are advantageously avoided by using the cascaded source / drain structures, as described in more detail below.

[0027] It will be reopened Fig. 3A / Fig. 3B referred to; a dielectric interlayer (ILD) 314 is above the device 300 In some embodiments, a contact etch stop layer (CESL) is also formed. 322 trained before the ILD layer 314 is trained. In some examples, the CESL includes 322 a silicon nitride layer, silicon oxide layer, silicon oxynitride layer and / or other materials known in engineering. The CESL 322 can be formed by a plasma-enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer exhibits 314Materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon dioxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 314 can be deposited by a PECVD process or another suitable deposition method. In some embodiments, the semiconductor device can 300 after formation of the ILD layer 314 to undergo a tempering process, for example to temper the ILD layer 314 to temper. In some examples, a planarization process (e.g., a CMP process) can be performed to create a top surface for the semiconductor device. 300 to planarize.

[0028] In some embodiments, the process 200 then with block 204continued, where a "pull-back" process is performed. In some embodiments, the "pull-back" process can also be referred to synonymously as a "re-etching process." Reference is made to the example of Fig. 4A / Fig. 4B referred to; an upper section of each of the nitride layers 310 (e.g. a sacrificial layer) and the side wall spacer 312 is sunk through the “pull-back” process, resulting in sunk nitride layers 310A and recessed side wall spacers 312A This results in various outcomes. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and / or a combination thereof.

[0029] In various embodiments, the process 200 then with block 206continued, where a sacrificial helmet layer is deposited. For example, referring to the example of Fig. 5A / Fig. 5B, a victim helmet layer 502 above the nitride layers 310A and the side wall spacers 312A separated. In some embodiments, the sacrificial helmet layer can 502 a polysilicon layer, a nitride layer (e.g., TiN, TaN), a metal oxide layer such as HfO2, or another dielectric layer with a high k-value (e.g., like those mentioned above in connection with the gate dielectric layer). 112 (as explained) exhibit, or another suitable dielectric material. In various embodiments, the sacrificial helmet layer can 502 deposited by CVD, ALD, PVD, or another suitable process. In some examples, a sacrificial helmet layer material may be used. 502be different from a material used for the nitride layer 310 is used, and / or from a material that is used for the side wall spacers 312 is used. In various examples, the victim helmet layer is used. 502 used to create the nitride layers 310A to protect, and thus the gate structure 308 and the side wall spacers 312A In some cases, the victim's helmet layer 502 optional and therefore not separated.

[0030] For example, the procedure 200 then with block 208 continued, where openings are formed. It refers to the example of Fig. 6A / Fig. Reference is made to 6B; source / drain openings are described. 602 , 604 trained to gain access to the source / drain structures 306 , 306A , 306B to ensure this. For example, the openings can 602 , 604through a suitable combination of lithographic structuring and etching processes (e.g. wet or dry etching) of the ILD layer 314 to be formed. In some embodiments, sections of the CESL can be formed. 322 , which result from the formation of the openings 602 , 604 exposed areas can be removed (e.g., by wet or dry etching). It should also be noted that the size of the openings... 602 , 604 (e.g. length and width in a plane that is substantially parallel to a surface of the substrate) 102 is) for the source and for the drain of a given device, such as the device 300, each independently and as required. For example, a larger opening can be used for either the source or the drain of the device to provide lower resistance at the source or drain with the larger opening, as explained in more detail below. Alternatively, in some embodiments, a similarly sized opening can be used for both the source and the drain of a device. Further details regarding the size of the openings 602 , 604 will be discussed below with reference to Fig. 11 explains. The example of is used again. Fig. 6A / Fig. Reference is made to 6B; in at least some conventional processes, at this stage a pre-amorphization implant (PAI) of silicide, silicide formation and contact layer metal deposition can occur over the now exposed source / drain structures. 306 , 306A ,306B as well as possible source / drain temperature control. However, as explained above, this can lead to undesirable stress relaxation in an adjacent channel of the device (e.g., the channel regions). 304 ). Therefore, embodiments of the present disclosure, as described in more detail below, instead involve the formation of a second epitaxial source / drain layer over the source / drain structures. 306 , 306A , 306B before, for example, potential PAI, silicide formation, or contact layer metal deposition. Furthermore, in various embodiments, the sacrificial helmet layer can be... 502 , if present, after the openings have formed 602 , 604 be removed. For example, the removal of the sacrificial helmet layer. 502 using a dry etching process, a wet etching process and / or a combination thereof.

[0031] In some embodiments, the process 200 then with block 210 The process continues, where a second epitaxial (EPI) source / drain layer is formed over the first source / drain EPI layer. In some embodiments, the formation of the second source / drain EPI layer can be performed in separate processing sequences for an n-type device and a p-type device, respectively. For the sake of clarity, the process for the exemplary device will be described below. 300 It describes a device that can include either an n-type or a p-type device. The example of... Fig. 6B and Fig. 7. Referenced; a second epitaxial layer 702 is placed above the first epitaxial layer (e.g., above the source / drain structures). 306A / 306B ) within the opening 604 (as well as inside the opening 602). In some embodiments, if the first epitaxial layer did not grow sufficiently (e.g., to a desired height), for example due to a merging of the source / drain structures, 306A / 306B The first epitaxial layer can be described as an “underfilled first epitaxial layer.” In such cases, the second epitaxial layer 702 This also serves to fill the underfilled first epitaxial layer. For example, the second epitaxial layer 702 The second epitaxial layer may be lattice-connected to the first epitaxial layer and may comprise the same semiconductor material(s) as the first epitaxial layer, or a different one. In some embodiments incorporating an n-type FinFET, the second epitaxial layer may be... 702The material must have a lattice constant smaller than that of silicon (Si) (e.g., such as SiCP, a Ga compound, an In compound, an As compound, or another suitable material). In some embodiments incorporating a p-type FinFET, the second epitaxial layer may be 702 a material with a lattice constant greater than that of silicon germanium (SiGe) (e.g., such as SiGeB with a Ge concentration greater than about 60%, GeB, SnGeB, or another suitable material). Of course, in some embodiments, the second epitaxial layer may 702 also or instead include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, GaP, Si-doped GaP or another suitable material. As in Fig. As shown in Figure 7, the openings (e.g. the openings) can be 602 , 604 ), as described above, be formed in such a way that the second epitaxial layer702 at least partially self-adjusting with respect to the source / drain structures 306A / 306B Furthermore, in some embodiments, the shape of the second epitaxial layer can be 702 at least partially through the openings 602 , 604 be defined as below with reference to Fig. 11 is described in more detail. For example, in some cases the second epitaxial layer 702 exhibit an extensive surface area (e.g. along a plane that is substantially parallel to a surface of the substrate) 102 is), on which a silicide layer is formed, as explained below. In some embodiments, after the formation of the second epitaxial layer, 702 An epi-temper process will be performed.

[0032] Subsequently, in some embodiments, the process 200 with block 212continued, where a silide layer forms above the second source / drain Epi layer. It refers to the example of Fig. 7 and Fig. 8. Referenced; a silicide layer 802 is above the second epitaxial layer 702 formed. For example, the silicide layer 802 The n-type and p-type devices each have the same or different material(s). In some embodiments, the silicide layer may be... 802 They feature a dual silicide process and a dual silicide structure, with a first material used for an n-type device and a second material used for a p-type device. For example, in some cases, the silicide layer can 802TiSi, Yb-doped TiSi, Zn-doped TiSi and / or Yb / Zn-doped TiSi for an n-conducting device. Furthermore, in some embodiments, the silicide layer may be 802 NiSi and / or Pt-doped NiSi for a p-type conductive device. In some cases, TiSi can be used as the silicide layer. 802 It can be used for both n-type and p-type devices. In some embodiments, the silicide layer can be 802 may also include multiple metal layers of the same or different material(s).

[0033] In some cases, the silicide layer exhibits 802 an extensive surface area (e.g. along a plane that is essentially parallel to a surface of the substrate) 102 (is), which serves to reduce the S / D contact resistance. Furthermore, in some embodiments, an InGaAs layer can be placed between the second epitaxial layer. 702and the silicide layer 802 be designed to further reduce the S / D contact resistance. In some examples, after the formation of the second epitaxial layer, 702 , and as part of the formation of the silicide layer 802 A pre-amorphization implant (PAI), metal layer deposition, and / or tempering may be performed. According to embodiments of the present disclosure, the formation of the silicide layer serves 802 after the formation of the second epitaxial layer 702 to prevent unwanted voltage relaxation in an adjacent channel of the device (e.g., the channel regions). 304 to avoid the above-mentioned issue. It is recalled that, as explained above, in at least some conventional processes a silicide layer forms directly over the exposed source / drain structures. 306 , 306A , 306BThis process can lead to stress relaxation (e.g., in a channel area of ​​the device). The formation of the silicide layer... 802 at a higher level, for example above the second epitaxial layer 702 and at a distance from an adjacent channel area, any previously induced channel voltage (e.g., which is at least partially due to the source / drain structures) is eliminated. 306 , 306A , 306B (which can be ensured) and maintained (e.g., stress relaxation is avoided). More precisely, a PAI process of silicide (for example, carried out as part of the formation of the silicide layer). 802 ), a supplementary source / drain ion implantation, silicification tempering or any other such process will then not adversely affect the voltage (e.g. channel voltage).

[0034] It refers to the example of Fig. 9A and Fig. Reference is made to 9B; therein are views of the device 300 along section AA' of Fig. 1 ( Fig. 9A) and along section BB' of Fig. 1 ( Fig. 9B) after the formation of the silicide layer 802 , which was explained above. In particular, it should be noted that in some embodiments, as in Fig. Figure 9A shows that the upper surface of the second semiconductor layer is higher than the upper surface of the metal gate along a direction 'N' perpendicular to the semiconductor substrate. The position of the upper surface of the second semiconductor layer ensures the formation of the silicide layer. 802 at a higher level, as explained above, thereby avoiding adverse stress relaxation.

[0035] In some embodiments, the process 200 then with block 214 continued where a contact metal is placed over the block 212a silicide layer is formed. In some embodiments, as in the examples of Fig. 10A and Fig. 10B shows a contact metal 1002 over and in contact with the silicide layer 802 formed. In some embodiments, the contact metal includes 1002 Ti, W, Co, Cu, Al, Mo, MoW, W, TiN, TaN, WN, silicide, combinations thereof, or another suitable conductive material. Thus, in some cases, the contact metal can be 1002 They may have multiple layers. In some examples, the contact metal may be... 1002 in the openings (e.g. the openings) 602 , 604 ) are deposited to form the silicide layer 802 to contact. Alternatively, after the silicide layer has formed, 802 in some examples an ILD layer 1003 (e.g. the ILD layer) 314 (similar) over the device 300are deposited and structured (e.g. by a suitable combination of lithographic structuring and wet and / or dry etching) to form openings which the silicide layer 802 expose and within which the contact metal 1002 is deposited. In some examples, after the formation of the contact metal, 1002 A CMP process is performed to remove excess material (e.g., excess contact metal) and to clean the top surface of the device. 300 to planarize. Then, in some embodiments, and after formation of the silicide layer contact metal, 1002 , an ILD layer 1004 (e.g. the ILD layer) 314 and 1003 (similar) over the device 300are deposited and structured (e.g. by a suitable combination of lithographic structuring and wet and / or dry etching) to form openings which allow the contact metal to 1002 expose and within which is a metal layer intended for through-hole plating (VIA metal layer) 1006 is deposited. In some embodiments, the VIA metal layer includes 1006 Ti, W, Co, Cu, Al, Mo, MoW, W, TiN, TaN, WN, silicide, combinations thereof, or any other suitable conductive material. In some examples, after formation of the VIA 1006 A CMP process is performed to remove excess material (e.g., excess material from the VIA metal layer). 1006 ) and an upper surface of the device 300 to planarize.

[0036] The semiconductor device 300It can be subjected to further processing to create various features and areas known in engineering. For example, subsequent processing can create various contacts / vias / conductors and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate. 102are designed to combine the various features to form a functional circuit, which may include one or more FinFET devices. Extending the example, a multilayer interconnect can have vertical conductor connections, such as vias or contacts, and horizontal conductor connections, such as metal traces. Various conductive materials can be used for the different conductor connection features, including copper, tungsten, and / or silicide. In one example, a Damascene and / or dual-Damascene process is used to form a copper-based multilayer interconnect structure. Furthermore, additional process steps can be incorporated before, during, and after the process. 200 can be implemented, and some of the process steps described above can be adapted according to different embodiments of the method. 200 be replaced by others or omitted.

[0037] We will now turn to the example of Fig. 11 Reference is made to this; it shows a top view of an embodiment of several FinFET devices according to one or more aspects of the present disclosure. In particular, it shows Fig. 11 a fin element 1108 , which is the fin element 302 It can be a gate structure 1104 , which defines the gate structure 308 It can be a gate contact, VG, source areas 1102 and drain areas 1106 In some embodiments, the source / drain areas can be 1102 , 1106 be trained in essentially the same way as above with reference to the procedure 200 was described (e.g., formation of source / drain structures). 306 , 306A , 306B , Formation of source / drain openings 602 , 604 , Formation of the second epitaxial layer 702 and the silicide layer802 , and formation of the contact metal 1002 and the VIA 1006 As shown, the source areas exhibit 1102 a source area width 'Ws' and a source area length 'Ls', and the drain areas 1006 They have a drain area width, 'Wd', and a drain area length, 'Ld'. Then the dimensions of each of the source / drain areas can be determined. 1102 , 1106 through the openings 602 , 604 be defined as Fig. 6A / 6B The dimensions of each source / drain area are shown. 1102 , 1106 also a form of the second epitaxial layer 702 and / or the silicic acid layer 802 , which are above the second epitaxial layer 702 is trained, define. Furthermore, illustrates Fig. 11 a way in which the second epitaxial layer 702 and / or the silicic layer 802It can have an extensive surface area, which serves to reduce contact resistance. As described above, a similarly sized opening can be used for both a source and a drain of a device, so that each of the source / drain areas 1102 , 1106 similar dimensions. Alternatively, a larger opening can be used for either the source or the drain of the device to provide lower resistance at the source or drain with the larger opening. For example, as shown in Fig. 11 shown, openings (e.g. openings) 602 , 604 ) in the source region be larger than in the drain region, and as a result, the second epitaxial layer can 702 and the silicide layer 802 also be larger in the source region than in the drain region. In the example of Fig. 11 is the source area 1102longer than the drain area 1106 along a direction perpendicular to a longitudinal direction of the fin. In other words, there is an asymmetry about a plane that intersects the fin along its longitudinal direction at its midpoint. Fig. Figure 11 also illustrates a method according to the present embodiment, wherein a first and a second opening (e.g. openings) 602 , 604 ) for each of the source / drain areas 1102 , 1106 They can be formed separately, so that the sizes of each of the source / drain areas can be determined. 1102 , 1106 They can be controlled separately.

[0038] The various embodiments described here offer several advantages over the prior art. It is understood that not all advantages have necessarily been explained here, no particular advantage is required for all embodiments, and other embodiments may offer different advantages. For example, embodiments described here include methods and structures for providing a special structure for FinFET S / D features that ensure reduced S / D contact resistance, improved FinFET channel voltage, and lower capacitance. For example, such S / D features include stacked epitaxial (EPI) layers in each of the S / D regions.In some examples, the cascaded EPI features provided here include a first EPI layer partially embedded in a fin over a semiconductor substrate and a second EPI layer on top of the first. For example, the two stacked EPI layers may be lattice-connected and may have the same or different semiconductor material(s). In several examples, the second EPI layer may be partially self-aligning with the first EPI layer, and the shape of the second EPI layer may be defined, at least partially, by an opening in an inter-layer dielectric (ILD) layer placed over the semiconductor substrate. In some cases, the FinFET device may further include a silicide feature over a top surface of the second EPI layer, with the silicide feature having an extended surface area to reduce the S / D contact resistance.

[0039] One embodiment of the present disclosure describes a semiconductor device comprising a substrate with a fin extending from it, the fin having a channel region as well as a source and a drain region adjacent to and on either side of the channel region. In various embodiments, a gate structure is arranged over the channel region, and the gate structure comprises a metal layer arranged over a dielectric layer. In some examples, a first epitaxial layer is at least partially embedded in the source and drain regions. Furthermore, a second epitaxial layer is arranged over the first epitaxial layer, wherein an upper surface of the second epitaxial layer is higher than an upper surface of the metal layer along a direction perpendicular to the substrate.In several examples, a silicide layer is also arranged above and in contact with the second epitaxial layer.

[0040] In another embodiment, a method is described in which a substrate is provided having a fin extending from it, wherein the fin has a channel region as well as a source and a drain region adjacent to and on either side of the channel region, and wherein a gate structure is arranged over the channel region. For example, a first epitaxial layer is formed which is at least partially embedded in the source and drain regions, and a dielectric layer is arranged over the first epitaxial layer. In various embodiments, the dielectric layer is etched to form a first and a second opening which at least partially expose an upper surface of the first epitaxial layer in the source region and in the drain region, respectively.Subsequently, in various examples, a second epitaxial layer is deposited over and in contact with the upper surface of the first epitaxial layer. In some embodiments, the first and second epitaxial layers provide cascaded epitaxial source and drain features in both the source and drain regions. Additionally, a silicide layer can be formed over and in contact with the second epitaxial layer.

[0041] In yet another embodiment, a method is described in which a substrate is provided that has a fin extending from it. In various cases, the fin has a channel region, a source region, and a drain region, which are adjacent to and arranged on either side of the channel region, and a gate structure arranged above the channel region. The gate structure has a metal layer over a gate dielectric layer. In various embodiments, a first epitaxial layer is formed, which is at least partially embedded in the source and drain regions, and the first epitaxial layer generates voltages in the channel region. In various embodiments, a second epitaxial layer is formed above and in contact with the first epitaxial layer, and the second epitaxial layer has a larger surface area in the source region than in the drain region.Furthermore, in some embodiments, an upper surface of the second epitaxial layer is higher than an upper surface of the metal layer along a direction perpendicular to the substrate. For example, a silicide layer can also be formed above and in contact with the second epitaxial layer.

[0042] The above outlines features of various embodiments to enable those skilled in the field to better understand aspects of the present disclosure. It should be clear to those skilled in the art that they can easily use the present disclosure as a basis for developing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments presented herein. It should also be clear to those skilled in the art that such equivalent designs do not deviate from the basic idea and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to them without deviating from the basic idea and scope of protection of the present disclosure.

Claims

[1] Semiconductor device comprising: a substrate with a fin extending from it, the fin having a channel area and a source and a drain area adjacent to the channel area and arranged on both sides of it; a gate structure arranged over the channel area, wherein the gate structure has a metal layer arranged over a dielectric layer; a first epitaxial layer that is at least partially embedded in the source and drain regions; a second epitaxial layer arranged above the first epitaxial layer, wherein an upper surface of the second epitaxial layer is higher than an upper surface of the metal layer along a direction perpendicular to the substrate; and a silicide layer that is arranged above and in contact with the second epitaxial layer. [2] Semiconductor device according to claim 1, wherein the second epitaxial layer has a larger surface area in the source region than in the drain region. [3] Semiconductor device according to claim 2, wherein the silicide layer has a larger surface area in the source region than in the drain region. [4] Semiconductor device according to one of the preceding claims, wherein the first epitaxial layer comprises a material different from a material used for the channel region. [5] Semiconductor device according to one of the preceding claims, which further comprises a structured dielectric layer which at least partially exposes the first dielectric layer, so that the second epitaxial layer and the first epitaxial layer are at least partially self-aligning. [6] Semiconductor device according to any of the preceding claims, wherein the semiconductor device includes an n-type FinFET, and wherein the second epitaxial layer has a material having a lattice constant that is smaller than that of silicon (Si). [7] Semiconductor device according to one of the preceding claims, wherein the semiconductor device includes a p-type FinFET, and wherein the second epitaxial layer has a material having a lattice constant greater than that of silicon germanium (SiGe). [8] Semiconductor device according to any of the preceding claims, wherein the semiconductor device includes an n-type FinFET, and wherein the silicide layer includes at least one of TiSi, Yb-doped TiSi, Zn-doped TiSi and Yb / Zn-doped TiSi. [9] Semiconductor device according to one of the preceding claims, wherein the semiconductor device includes a p-type FinFET, and wherein the silicide layer includes at least one NiSi and Pt-doped NiSi. [10] Semiconductor device according to one of the preceding claims, wherein the first epitaxial layer is symmetric about a plane which intersects the fin along a longitudinal direction of the fin in the middle, and wherein the second epitaxial layer is asymmetric about the plane in the source region and symmetric about the plane in the drain region. [11] Method for manufacturing a semiconductor device comprising: Providing a substrate having a fin extending from it, the fin having a channel area and a source and a drain area adjacent to and on either side of the channel area, and wherein a gate structure is arranged over the channel area; Formation of a first epitaxial layer that is at least partially embedded in the source and drain regions; Formation of a dielectric layer occurs above the first epitaxial layer; Etching the dielectric layer to form a first and a second opening which at least partially expose an upper surface of the first epitaxial layer in the source region and in the drain region, respectively; depositing a second epitaxial layer over and in contact with the upper surface of the first epitaxial layer, wherein the first and the second epitaxial layers provide cascaded epitaxial source and drain features in both the source and drain regions; and Formation of a silicide layer above and in contact with the second epitaxial layer. [12] Method according to claim 11, wherein the first opening is larger than the second opening. [13] The method of claim 11 or 12, which further comprises: Before etching the dielectric layer, a protective sacrificial layer is formed over the gate structure. [14] Method according to any one of the preceding claims 11 to 13, wherein the etching of the dielectric layer exposes the upper surface of the first epitaxial layer in at least two physically separate and adjacent fins, and wherein the deposition of the second epitaxial layer serves to form a single, unified epitaxial area in the source and / or drain region. [15] Method according to any one of the preceding claims 12 to 14, wherein the second epitaxial layer has a larger surface area in the source region than in the drain region. [16] Method according to claim 15, wherein the silicide layer has a larger surface area in the source region than in the drain region. [17] Method according to any one of the preceding claims 11 to 16, wherein the gate structure comprises a metal layer, and wherein an upper surface of the second epitaxial layer is higher than an upper surface of the metal layer along a direction perpendicular to the substrate. [18] Procedure which includes: Providing a substrate having a fin extending from it, the fin having a channel area and a source and a drain area adjacent to and on either side of the channel area, and a gate structure being arranged over the channel area, the gate structure having a metal layer; Forming a first epitaxial layer that is at least partially embedded in the source and drain regions, wherein the first epitaxial layer generates stresses in the channel region; Deposition of a second epitaxial layer over and in contact with the first epitaxial layer, wherein the second epitaxial layer has a larger surface area in the source region than in the drain region, and wherein an upper surface of the second epitaxial layer is higher than an upper surface of the metal layer along a direction perpendicular to the substrate; and Formation of a silicide layer above and in contact with the second epitaxial layer. [19] The method of claim 18, which further comprises: Before the formation of the second epitaxial layer, a first dielectric layer forms over the first epitaxial layer; and Etching of the first dielectric layer to form a first and a second opening which at least partially expose an upper surface of the first epitaxial layer in the source region and in the drain region, respectively. [20] The method of claim 19, which further comprises: After the formation of the silicide layer, a second dielectric layer forms over the silicide layer; Structuring the second dielectric layer to form contact openings that expose the silicide layer, and depositing a contact metal within the contact openings and in contact with the silicide layer; Formation of a third dielectric layer above the contact metal; and Structuring the third dielectric layer to form via openings that expose the contact metal, and depositing a via metal within the via openings and in contact with the contact metal.