Arrangement for operating optoelectronic semiconductor chips and display device
The digital control unit with memory and counters in the semiconductor chip arrangement stabilizes color output and improves image quality by managing current and pulse width, addressing leakage current issues in active matrix displays.
DE102017122014B4Active Publication Date: 2026-05-28OSRAM OPTO SEMICON GMBH & CO OHG
Patent Information
- Application Number
- DE102017122014
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2017-09-22
- Publication Date
- 2026-05-28
- Estimated Expiration
- 2037-09-22
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Abstract
Arrangement (201, 202, 203) for operating optoelectronic semiconductor chips, comprising - a first semiconductor chip (10) with a first and second electrode (11, 12) which is configured to emit electromagnetic radiation during operation, - a control unit (100) for setting a current to operate the first semiconductor chip (10), - a first LED voltage input (101) coupled to the first electrode (11) of the first semiconductor chip (10), and a reference voltage input (103) coupled via the control unit (100) to the second electrode (12) of the first semiconductor chip (10), - an LED data input (105) which is coupled to the control unit (100) and via which a data characteristic (D) can be provided which is representative of a current for operating the first semiconductor chip (10), and - a cycle input (106) which is coupled to the control unit (100) and via which an external reference cycle signal (R) with respect to the arrangement (201, 202, 203) can be provided, which is representative of an operating phase of the arrangement (201, 202, 203), wherein - the control unit (100) includes a memory (110) which has a storage capacity > 3 bits and is configured to store the data identifier (D) as a memory value (S) depending on the reference cycle signal (R), and - the control unit (100) is set up to adjust the current for operating the first semiconductor chip (10) depending on the memory value (S), wherein - the control unit (100) comprises a shift register (161, 162, 163) for each semiconductor chip (10, 20, 30), having a clock input via which a PWM clock signal (B) can be provided, a data input which is coupled to the memory, and a data output, wherein the shift register (161, 162, 163) is configured to store an initial shift value depending on the memory value (S), to shift the respective shift value bitwise depending on the PWM clock signal (B), and to output it as a control value (W1, W2, W3) via the data output, and - the control unit (100) is set up to adjust the current for operating the respective semiconductor chip (10, 20, 30) depending on the corresponding control value (W1, W2, W3), wherein the shift register (160) is designed as a circular shift register.
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Citation Information
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