Optoelectronic semiconductor chip

Abstract

Optoelectronic semiconductor chip (1) comprising: - a semiconductor body (2) having a first semiconductor region (20) and a second semiconductor region (22); - a first and second contact element (4, 5) for electrical contacting the semiconductor body (2); - a chip carrier (3) on which the semiconductor body (2) and the first and second contact elements (4, 5) are arranged side by side, the first and second contact elements (4, 5) being arranged on a first side (I) of the semiconductor body (2); - an electrically conductive contact layer (6) arranged on a first main surface (2A) of the semiconductor body (2) facing the chip carrier (3); - an electrically conductive lead layer (7) arranged on a side of the contact layer (6) facing away from the semiconductor body (2) and connected to the first contact element (4); - an insulating layer (8).which is arranged between the contact layer (6) and the supply layer (7), wherein the insulating layer (8) electrically insulates the electrically conductive contact layer (6) from the electrically conductive supply layer (7), and several electrically conductive feedthrough elements (9) embedded in the insulating layer (8) and electrically connecting the supply layer (7) to the contact layer (6), wherein a number or size (a1, a2) of the feedthrough elements (9) on a second side (II) of the semiconductor body (2) opposite the first side (I) is larger than on the first side (I).

Description

[0001] An optoelectronic semiconductor chip is described, comprising a semiconductor body and contact elements for electrical contacting the semiconductor body, which are preferably arranged laterally to the side of the semiconductor body, particularly on the same side of the semiconductor body. Preferably, the semiconductor chip is a high-current semiconductor chip that, in normal operation, exhibits a current density of at least 4 A / mm². 2 and has a forward voltage of 4.5 V + / - 2 V.

[0002] In such a semiconductor chip, particularly when current is injected into the semiconductor body via a relatively thin contact layer, the problem of so-called "current crowding" can occur. This means that an inhomogeneous current density distribution exists near the contact elements, especially in the region of a p-contact element. The current density is relatively high near the p-contact element. In a radiation-emitting semiconductor chip, this inhomogeneous current density distribution leads to fluctuations in the intensity of the emitted radiation across the chip. The temperature can also fluctuate across the chip. The resulting current density and temperature spikes can lead to disproportionately severe degradation of the semiconductor body.

[0003] The problem to be solved in this case is to specify an optoelectronic semiconductor chip with a comparatively homogeneous current density distribution. This problem is solved, among other things, by an optoelectronic semiconductor chip with the features of the independent claim.

[0004] Advantageous further developments of the optoelectronic semiconductor chip are the subject of the dependent claims.

[0005] According to at least one embodiment, the optoelectronic semiconductor chip comprises a semiconductor body with a first semiconductor region and a second semiconductor region. Furthermore, the semiconductor body has a first principal surface and a second principal surface opposite the first principal surface, wherein, in particular, the first principal surface is formed by a surface of the first semiconductor region and the second principal surface by a surface of the second semiconductor region. In particular, the first principal surface and the second principal surface delimit the semiconductor body in a vertical direction.

[0006] Furthermore, the semiconductor body preferably has at least one side surface that connects the first main surface to the second main surface. The number of side surfaces is determined by the geometry of the semiconductor body. For example, the semiconductor body can have a geometric shape approximating a truncated pyramid. In this case, the semiconductor body has multiple side surfaces. The at least one side surface is preferably arranged largely transversely to the first and second main surfaces. "Transversely" means that a normal vector of the side surface is not parallel to a normal vector of the first and / or second main surface. Preferably, the at least one side surface bounds the semiconductor body in one or more lateral directions. The lateral directions are arranged in a plane whose normal vector is parallel to a vertical direction.In particular, the direction in which the second semiconductor region follows the first semiconductor region is called the vertical direction.

[0007] Furthermore, at least one of the sides can be a surface composed of at least two sub-surfaces. For example, the sub-surfaces can be planar surfaces whose surface normals run perpendicular to each other, i.e., not parallel to each other.

[0008] The first semiconductor region can have a first conductivity and the second semiconductor region a second conductivity. Preferably, the first semiconductor region is a p-type semiconductor region. Furthermore, the second semiconductor region is preferably an n-type semiconductor region. The first and second semiconductor regions can each have a sequence of layers. It is possible that the first semiconductor region and the second semiconductor region contain one or more undoped layers in addition to doped layers.

[0009] The first and second semiconductor regions can be fabricated layer by layer on a growth substrate using an epitaxial process, preferably by first depositing the second semiconductor region onto the growth substrate and then depositing the first semiconductor region onto the second semiconductor region. Suitable materials for the growth substrate include, for example, sapphire, SiC, and / or GaN. After fabrication of the semiconductor body, the growth substrate can be at least partially removed, thus exposing at least part of the second main surface or a surface of the second semiconductor region.

[0010] The semiconductor body advantageously has an active zone suitable for radiation generation or detection. In particular, the active zone is a pn junction zone. The active zone can be configured as a single layer or as a sequence of multiple layers. For example, during operation of the semiconductor chip, the active zone emits electromagnetic radiation, such as in the visible, ultraviolet, or infrared spectral range. Alternatively, during operation of the semiconductor chip, the active zone can absorb electromagnetic radiation and convert it into electrical signals or electrical energy. The active zone is preferably located between the first and second semiconductor regions. A significant portion of the radiation generated or absorbed by the active zone preferably passes through the second main surface of the semiconductor body.Advantageously, the second main surface is not covered by the contact elements arranged laterally on the semiconductor body, so that these cannot cause any radiation losses on the second main surface.

[0011] The layers of the semiconductor body preferably contain at least one III / V semiconductor material, for example a material from the material systems InxGayAl1-x-yP, InxGayAl1-x-yN or InxGayAl1-x-yAs, each with 0 ≤ x, y ≤ 1 and x + y ≤ 1. III / V semiconductor materials are particularly suitable for generating radiation in the ultraviolet (InxGayAl1-x-yN), through the visible (InxGayAl1-x-yN, especially for blue to green radiation, or InxGayAl1-x-yP, especially for yellow to red radiation) to the infrared (InxGayAl1-x-yAs) spectral range.

[0012] Furthermore, according to at least one embodiment, the semiconductor chip has a first and second contact element, which are provided for electrical contacting the semiconductor body. The contact elements are, in particular, electrically conductive layers arranged outside the semiconductor body, which can be electrically contacted from the outside, for example by means of bond wires. The first contact element can form a p-contact and the second contact element an n-contact.

[0013] Furthermore, according to a preferred embodiment, the semiconductor chip comprises a chip carrier. The chip carrier can be a substrate that differs from the growth substrate used to manufacture the semiconductor body. Advantageously, the chip carrier contains a material with high thermal conductivity, for example, a metal, a semiconductor material, or a ceramic material. The chip carrier can be electrically conductive or electrically insulating. Suitable materials for the chip carrier include, for example, Si3N4 and AlN.

[0014] The semiconductor body and the first and second contact elements are preferably arranged side by side on the chip carrier. In other words, the three elements are arranged with at most partial lateral overlap. Furthermore, the first and second contact elements are preferably arranged on a first side of the semiconductor body. This allows several such semiconductor chips to be arranged side by side and easily electrically contacted at their edges. The different sides of the semiconductor body are defined in particular by the different facets of the semiconductor body.

[0015] Furthermore, in a preferred embodiment, the semiconductor chip has an electrically conductive contact layer arranged on the first main surface of the semiconductor body facing the chip substrate. Preferably, the contact layer is formed from an electrically conductive and, in particular, highly reflective material, such as a metal like silver or aluminum, or an electrically conductive oxide, such as ZnO. The contact layer can be formed from a sequence of metal layers and conductive oxide layers. The thickness of the contact layer is preferably between 100 nm and 500 nm. Here, "thickness" refers in particular to the maximum vertical extent of the layer.

[0016] In a preferred embodiment, the contact layer is a continuous layer. This means that all areas of the contact layer are interconnected. This is particularly advantageous with regard to current being supplied to the semiconductor body via the contact layer. Furthermore, the contact layer preferably has a homogeneous thickness. "Homogeneous" here means that thickness variations in the contact layer are at most 20% of a mean value.

[0017] Furthermore, in a preferred embodiment, the semiconductor chip has an electrically conductive lead layer arranged on a side of the contact layer facing away from the semiconductor body and connected to the first contact element. In particular, the lead layer is electrically conductively connected to the first contact element and directly adjacent to it. The lead layer can be made of an electrically conductive material, such as a metal like gold. The thickness of the lead layer is preferably between 200 nm and 1 µm. In particular, the lead layer is thicker than the contact layer.

[0018] In a preferred embodiment, the lead-in layer is a continuous layer. This means that all regions of the lead-in layer are interconnected. Furthermore, the lead-in layer can have a largely homogeneous thickness. For example, the lead-in layer can be thicker near the first contact element than in regions covered by the semiconductor body.

[0019] According to a preferred embodiment, the semiconductor chip has an insulating layer arranged between the contact layer and the lead layer. The insulating layer provides partial electrical isolation between the contact layer and the lead layer. Suitable materials for the insulating layer are electrically weakly conductive or non-conductive materials, in particular silicon oxides or silicon nitrides. The thickness of the insulating layer is preferably between 200 nm and 2 µm. The insulating layer can be single-layered or multi-layered. In the case of a multi-layered insulating layer, it has at least two different sublayers, which are formed, for example, from different materials such as SiO₂ and SiN. The thickness of a sublayer is preferably 10 nm, with thickness deviations preferably not exceeding 20% ​​of a mean value.

[0020] According to at least one embodiment, the semiconductor chip has at least one electrically conductive feedthrough element embedded in the insulating layer, which electrically connects the lead layer to the contact layer. The at least one feedthrough element is made of an electrically conductive material, such as a metal like gold (Au). In particular, the feedthrough element can be made of the same material as the lead layer. The feedthrough element can have the geometric shape of a cylinder or prism. In the case of multiple feedthrough elements, these are specifically not connected but formed separately.

[0021] According to a preferred embodiment, the number and / or size of the feedthrough elements on a second side of the semiconductor body, opposite the first side, is greater than on the first side. "Size" refers in particular to the area of ​​a cross-section of a feedthrough element running parallel to the first main surface. In the case of a single feedthrough element, it is located on the second side of the semiconductor body. Therefore, there is no feedthrough element on the first side, and consequently, the number of feedthrough elements on the second side is greater than on the first side. In the case of multiple feedthrough elements, their size increases from the first to the second side. The current density distribution in the semiconductor body can be specifically influenced by the arrangement and / or structure, that is, in particular, the size and shape, of the feedthrough element.

[0022] In particular, the at least one electrically conductive feedthrough element is arranged and designed such that, during operation, a plurality of current paths exist between the first and second contact elements, each with a total series resistance, and the current paths largely exhibit the same total series resistance. This advantageously results in a relatively constant intensity of the emitted radiation across the semiconductor chip. In contrast, in a semiconductor chip where the contact layer is energized directly and not indirectly via at least one feedthrough element, current paths exist with highly variable total series resistances, leading to the aforementioned problems of inhomogeneous current injection and inhomogeneous current density distribution.

[0023] The criterion that the current paths largely exhibit the same total series resistance is fulfilled, in particular, if at least 50% of the current paths have a total series resistance that deviates from an ideal value by no more than 10%. Specifically, the semiconductor chip described herein is a high-current semiconductor chip that, in normal operation, exhibits a current density of at least 4 A / mm². 2 , in particular of at least 5 A / mm 2 , exhibits such characteristics. A semiconductor chip like this can have a forward voltage of 4.5 V + / - 2 V and a total current of 10 A. The ideal total series resistance is therefore between 0.1 and 0.65 Ω.

[0024] In this configuration, a current path runs from the first contact element through the lead-in layer, through at least one feedthrough element, through the contact layer, and through the semiconductor body to the second contact element. The total series resistance along a current path is fundamentally composed of the various series resistances of the layers or elements through which the current flows. In this case, the total series resistance is primarily determined by the various series resistances of the lead-in layer, the at least one feedthrough element, the contact layer, the semiconductor body, a terminal layer of the second semiconductor region, and the second contact element. While the series resistances of the contact layer and the semiconductor body are essentially constant for the various current paths, the series resistances of the lead-in layer and the feedthrough elements vary.

[0025] During operation, the series resistance of the lead layer increases from the first to the second side of the semiconductor body. This phenomenon occurs, for example, in a continuous lead layer of largely homogeneous thickness between 200 nm and 3 µm.

[0026] Furthermore, when multiple feedthrough elements are used, the series resistance of the feedthrough elements preferably decreases from the first to the second side of the semiconductor body. This is achieved, for example, when the size of the feedthrough elements increases from the first to the second side. For instance, the feedthrough elements near the first contact element can have a diameter, i.e., a lateral extent, of 0.2 µm to 0.5 µm inclusive, and a diameter of approximately 3 µm further away from the first contact element, particularly on the second side of the semiconductor body. The diameter can thus increase tenfold from the first to the second side. Preferably, the feedthrough elements are smaller overall with a thinner lead layer than with a thicker lead layer.

[0027] In an advantageous embodiment, the semiconductor chip has several feedthrough elements arranged in rows, offset from one another. In other words, the feedthrough elements are arranged in a matrix. Preferably, the size of the feedthrough elements in a row increases from the first to the second side of the semiconductor body. Furthermore, the size of the feedthrough elements in a row can be constant from a third side to a fourth side of the semiconductor body opposite the third.

[0028] According to at least one embodiment, the semiconductor chip has a single, planar feedthrough element located on the second side of the semiconductor body and extending along a side edge of the semiconductor body that bounds the first main surface. In this embodiment as well, the series resistance between the feedthrough layer and the contact layer decreases during operation from the first to the second side of the semiconductor body. For example, the feedthrough element can be strip-shaped. The width of the feedthrough element is preferably between 70 µm and 90 µm inclusive.

[0029] According to a further embodiment, the optoelectronic semiconductor chip can have several strip-shaped feedthrough elements extending from the third to the fourth side of the semiconductor body. In other words, the strip-shaped feedthrough elements are arranged in a grid-like pattern. The width of the feedthrough elements preferably increases from the first to the second side of the semiconductor body.

[0030] According to at least one embodiment, the semiconductor chip has several vias, each extending from the chip substrate through the lead layer, the insulating layer, the contact layer, and the first semiconductor region into the second semiconductor region. The vias are arranged in openings that extend through the lead layer, the insulating layer, the contact layer, and the first semiconductor region into the second semiconductor region. The vias can be made of an electrically conductive material, such as a metal like silver. Preferably, the feedthrough elements are arranged in spaces between the vias.

[0031] Furthermore, the semiconductor chip can have a connection layer that electrically connects the second contact element to the vias. The connection layer is preferably arranged on a side of the lead layer facing away from the semiconductor body. The thickness of the connection layer is preferably between 500 nm and 3 µm. Preferably, the connection layer is thicker than the lead layer. This applies particularly to areas covered by the semiconductor body. As a result, the fluctuations in current density occurring on the n-side are negligibly small compared to the fluctuations occurring on the p-side. The connection layer is mechanically bonded to the chip substrate, particularly on its surface facing away from the lead layer.

[0032] According to at least one embodiment, the semiconductor chip has a current-expansion layer arranged between the contact layer and the insulating layer, wherein the current-expansion layer is in electrical contact with the contact layer and, in particular, completely covers it. The contact layer and the current-expansion layer can differ in their material composition. The current-expansion layer can be made of a metal, such as titanium, copper, nickel, gold, platinum, aluminum, or silver.

[0033] In an advantageous embodiment, the current expansion layer has a non-homogeneous thickness. In particular, in areas where the current expansion layer is connected to a feedthrough element, it has a smaller thickness than in areas without a feedthrough element. This prevents the vertical extent or height of the semiconductor chip from being increased by the additional feedthrough element.

[0034] Furthermore, the semiconductor chip can have a first and / or second coating layer applied to the second main surface and preferably also to at least one side surface of the semiconductor body. The first coating layer is located between the semiconductor body and the second coating layer. For example, the first coating layer can contain or consist of Al₂O₃. The second coating layer can be an insulating layer, for example, made of silicon oxide, silicon nitride, or aluminum oxide such as Al₂O₃. It is possible that the second coating layer contains scattering particles and / or phosphor particles. The contact elements are not covered by the coating layers at their contact surface.

[0035] Further advantages, preferred embodiments and further developments of the optoelectronic semiconductor chip will be explained in the accompanying notes. Figs. 1 to Figs. 8.

[0036] They show: Figs. 1 a schematic sectional view and Figs. 2 a schematic top view of an optoelectronic semiconductor chip according to a first embodiment, Figs. 3 and Figs. 4 schematic top views of an optoelectronic semiconductor chip according to a second and third embodiment, Figs. 5 a schematic sectional view and Figs. 6 A schematic top view of an optoelectronic semiconductor chip according to a comparative example, Figs. 7 a diagram of the current density distribution in an optoelectronic semiconductor chip according to the comparative example and Figs. 8 A diagram of the temperature distribution in an optoelectronic semiconductor chip according to the comparative example.

[0037] Figs. Figure 1 shows a schematic sectional view of an optoelectronic semiconductor chip. 1along one in the Figs. 2 shown cross-sectional area SECOND' The semiconductor chip 1 includes a semiconductor body 2 and a chip carrier 3 , on which the semiconductor body 2 is arranged. Furthermore, the semiconductor chip comprises 1 a first contact element 4 and a second contact element 5 , which are used for electrical contacting the semiconductor body 2 are provided. The semiconductor body is involved. 2 as well as the first and second contact element 4 , 5 side by side on the chip carrier 3 arranged, wherein the first and second contact elements 4 , 5 on a first page I of the semiconductor body 2 are arranged (compare Figs. 2) Furthermore, the semiconductor chip includes 1 an electrically conductive contact layer 6 , which are on a first, the chip carrier 3facing main surface 2A of the semiconductor body 2 is arranged, as well as an electrically conductive supply layer. 7 , which are located on a semiconductor body 2 far side of the contact layer 6 arranged and with the first contact element 4 is connected. Furthermore, the semiconductor chip includes 2 an insulating layer 8 , which are between the contact layer 6 and the supply layer 7 is arranged. Furthermore, the semiconductor chip comprises 1 several electrically conductive feedthrough elements 9 , which are in the insulation layer 8 are embedded and the supply layer 7 with the contact layer 6 Connect electrically. The total number of feedthrough elements 9 is 1mm 2 large semiconductor chip 1 preferably between 50 and 70 , in particular60 .

[0038] In the first embodiment, the feedthrough elements 9 Arranged in staggered rows. The size of the connecting elements increases. 9 , that is, a first lateral expansion a1 and / or a second lateral extension a2 , in a series from the first page I to one of the first opposite second sides II of the semiconductor body 2 to. However, the size of the implementation elements changes. 9 in a series from a third page III to one of the third pages III opposite fourth page IV of the semiconductor body 2 hardly at all or remains constant. For example, the implementation elements can 9 near the first contact element 4 a first and second lateral extension a1 and a2from and including 0.2 µm to and including 0.5 µm from the first contact element 4 on the second page II of the semiconductor body 2 a first and second lateral extension a1 and a2 of approximately 3 µm. In the first embodiment, the feedthrough elements have 9 each has the geometric shape of a cylinder, such that the first and second lateral extensions a1 and a2 are of the same size. The implementation elements 9 are specifically trained separately.

[0039] During operation, the series resistance of the feedthrough elements increases. 9 from the first page I to the second page II of the semiconductor body 2 off, while the series resistance of the supply layer 9 from the first page I to the second page II of the semiconductor body 2increases. This allows the semiconductor chip to be used. 1 A relatively constant overall series resistance, and thus a homogeneous current density distribution, is achieved. In other words, during operation, there is no resistance between the first and second contact elements. 4 , 5 A multitude of current paths, most of which have the same total series resistance, preferably between 0.1 and 0.65 Ω. One current path originates from the first contact element. 4 through the supply layer 7 , through the implementation element 9 , through the contact layer 6 and through the semiconductor body 2 through to the second contact element 5 The total series resistance along a current path is basically composed of the various series resistances of the layers or elements through which the current flows.

[0040] In particular, the semiconductor chip 1 a high-current semiconductor chip that, in normal operation, has a current density of at least 4 A / mm² 2 , in particular of at least 5 A / mm 2 , exhibits. The semiconductor chip can be 1 exhibit a forward voltage of 4.5 V + / - 2 V and a total current of 10 A.

[0041] The semiconductor body 2 exhibits a first semiconductor area 20 , a second semiconductor area 22 and one between the first and second semiconductor regions 20 , 22 arranged active zone 21 Furthermore, the semiconductor body exhibits 2 a first main area 2A and one of the first main areas 2A opposite second main area 2B on, which the semiconductor body 2 in a vertical direction V limit the semiconductor body 2It has a geometric shape approximating a truncated pyramid. The semiconductor body exhibits 2 multiple side surfaces 2C , 2D , 2E , 2F on, each of which is the first main area 2A with the second main area 2F connect the side surfaces 2C , 2D , 2E , 2F are largely perpendicular to the first and second main areas 2A , 2B arranged and limit the semiconductor body 2 in several lateral directions L1 , - L1 , L2 , - L2 Furthermore, the side surfaces can 2C , 2D , 2E , 2F Each must be a surface composed of at least two flat sub-surfaces, whose surface normals do not run parallel to each other.

[0042] Preferably, the first semiconductor area is 20around a p-type semiconductor region and at the second semiconductor region 22 around an n-conducting semiconductor region, each of which can have a sequence of layers. The semiconductor regions 20 , 21 , 22 or layers of the semiconductor body 2 preferably contain at least one III / V semiconductor material, such as a material from the material systems InxGayAl1-x-yP, InxGayAl1-x-yN or InxGayAl1-x-yAs, each with 0 ≤ x, y ≤ 1 and x + y ≤ 1. The growth substrate used for fabrication is at least partially removed, so that the chip carrier 3 preferably a replacement carrier.

[0043] The chip carrier 3 It contains, for example, a metal, a semiconductor material, or a ceramic material. The chip carrier 3 It can be electrically conductive or electrically insulating. For the chip carrier 3Suitable materials include Si3N4 and AlN.

[0044] Preferably, the optoelectronic semiconductor chip 1 around a radiation-emitting semiconductor chip, wherein in the active zone 21 Radiation is generated. In particular, the active zone emits 21 during the operation of the semiconductor chip 1 Electromagnetic radiation, for example in the visible, ultraviolet, or infrared spectral range. A significant portion of the radiation emitted by the active zone 21 The generated radiation passes through the second main surface 2B of the semiconductor body 2B through the semiconductor body 2 It points advantageously to the second main surface 2B A roughened surface is applied, which improves radiation extraction compared to a flat radiation extraction surface. Furthermore, the second main surface... 2B advantageously from the sides of the semiconductor body 2arranged contact elements 4 , 5 uncovered, so that these are on the second main surface 2B cannot cause any radiation losses.

[0045] In the contact elements 4 , 5 These are electrically conductive layers, especially metallizations, applied from the outside, for example by means of bond wires. 10 , can be electrically contacted. The first contact element can be 4 a p-contact and the second contact element 5 form an n-contact.

[0046] The contact layer 6 It is formed from a particularly highly reflective material, such as a metal like silver or aluminum, or an electrically conductive oxide, such as ZnO. The contact layer 6 It can be formed from a sequence of layers consisting of metal layers and conductive oxide layers. A thickness D1 the contact layer 6The diameter is preferably between 100 nm and 500 nm. In particular, the contact layer has a diameter of 100 nm and 500 nm. 6 a uniform thickness D1 and is coherently formed. The first semiconductor area 20 is achieved by means of the contact layer 6 powered up.

[0047] Furthermore, the semiconductor chip 1 a current expansion layer 11 on, which between the contact layer 6 and the insulation layer 8 is arranged, wherein the current expansion layer 11 in electrical contact with the contact layer 6 stands and completely covers it. The current widening layer 11 It is formed, for example, from a metal such as titanium, copper, nickel, gold, platinum, aluminum, or silver. The current expansion layer 11 can result in an inhomogeneous thickness D2 exhibiting, in areas where they are connected to an implementation element9 is connected, in particular is thinner than in areas without a feedthrough element 9 .

[0048] For the insulation layer 8 Suitable materials include electrically weak or non-conductive materials, especially silicon oxides or silicon nitrides. The thickness D3 the insulation layer 8 The thickness is preferably between 200 nm and 2 µm. 3 the insulation layer 8 is thereby in the contact layer 6 covered areas with feedthrough elements 9 larger than in areas without penetrations 9 . By means of the insulating layer 8 is the contact layer 6 in some areas from the supply layer 7 electrically insulated.

[0049] In addition to the implementation elements 9 is also the supply layer 7 into the insulation layer 8embedded. The insulation layer extends here. 8 in lateral directions L1 , - L1 , L2 , - L2 about the semiconductor body 2 beyond. For the production of the feedthrough elements. 9 or supply layer 7 can the insulating layer 8 They are provided with openings in which an electrically conductive material, such as a metal like gold, is placed. The feedthrough elements can be... 9 in one manufacturing step together with the supply layer 7 and therefore, in particular, made of the same material as the supply layer 7 be formed.

[0050] The supply layer 7 is with the first contact element 4 electrically conductive and directly adjacent to it. The thickness D4 the supply layer 7preferably between 200 nm and 1 µm, wherein the lead layer 7 near the first contact element 4 is thicker than in the semiconductor body 2 covered areas.

[0051] Furthermore, the semiconductor chip 1 multiple vias 12 each originating from the chip carrier 3 through the supply layer 7 , through the insulating layer 8 , through the contact layer 6 and the first semiconductor area 20 through to the second semiconductor area 22 extend. This includes the vias. 12 each arranged in openings that extend through the supply layer 7 , through the insulating layer 8 , through the contact layer 6 and the first semiconductor area 20 through to the second semiconductor area 22extend. A passivation layer can be applied to each of the side surfaces bordering the openings. 13 be arranged which the through-hole connection 12 laterally enclosed. The vias 12 They can be made of an electrically conductive material, such as a metal like silver. Preferably, the feedthrough elements are 9 in the spaces between the vias 12 arranged (compare Figs. 2).

[0052] Furthermore, the semiconductor chip 1 a connection layer 14 on, which the second contact element 5 with the vias 12 electrically connects. The connection layer 14 is on a semiconductor body 2 far side of the supply layer 7 arranged. The thickness D5 the connection layer 14The diameter is particularly between 500 nm and 3 µm. Preferably, the connection layer is 14 in many areas thicker than the supply layer 7 . As a result, the fluctuations in current density occurring on the n-side are negligibly small compared to the fluctuations occurring on the p-side.

[0053] The semiconductor chip 1 points to one of the semiconductor body 2 far side of the connection layer 14 a bonding layer 15 on, through which the semiconductor body 2 indirectly with the chip carrier 3 mechanically connected. In the bonding layer 15 For example, it could be an adhesive layer or a solder layer.

[0054] Between the connection layer 14 and the bonding layer 15 can a further current expansion layer 16be arranged. The further current widening layer 16 is an n-sided current expansion layer that connects to the terminal layer 14 is in electrical contact. The further current expansion layer 16 extends, like the connecting layer 14 into the openings in which the vias 12 are arranged.

[0055] The chip carrier 3 can be on a semiconductor body 2 opposite side with a metallization 17 be provided with it. By means of metallization. 17 can the semiconductor chip 1 It can be connected to a mounting bracket, such as a circuit board, on its rear side.

[0056] The semiconductor chip has a front side 1 a first covering layer 18 and a second covering layer 19 on, whereby the second covering layer 19 on one of the chip carrier3 far side of the first covering layer 18 is arranged. The covering layers 18 , 19 are on the second main area 2B and the side surfaces 2C , 2D , 2E , 2F of the semiconductor body 2 applied and extend to the semiconductor body 2 uncovered areas of the chip carrier 3 . In the first covering layer 18 This is preferably a layer containing or consisting of Al2O3. The second covering layer 19 This is, in particular, an insulating layer made of, for example, silicon oxide, silicon nitride, or aluminum oxide such as Al₂O₃. It is possible that the second covering layer 19 The semiconductor chip contains scattering particles and / or phosphor particles. 2 is formed at the front by the second covering layer 19limited, wherein a front outer surface of the second covering layer 19 a predominant part of the front outer surface of the semiconductor chip 1 forms. Furthermore, the exposed contact surfaces of the contact elements form 4 , 5 a part of the front outer surface of the semiconductor chip 1 .

[0057] The in Figs. 3 semiconductor chips shown 1 It has a similar structural design to the semiconductor chip 1 as in the first embodiment. Differences exist with regard to the number and design of the feedthrough elements. 9 The semiconductor chip 1 according to the in Figs. The second embodiment shown in Figure 3 has a single, flat feedthrough element. 9 up, which is on the second page II of the semiconductor body 2is arranged and extends along a side edge that borders the first main surface 23 of the semiconductor body 2 extends. In this embodiment as well, the series resistance between the supply layer decreases. 7 and the contact layer 6 during operation from the first to the second side of the semiconductor body 2 off. The implementation element 9 It is formed in a stripe shape. A width or initial lateral extension. a1 of the implementation element 9 The second lateral dimension is preferably between 70 µm and 90 µm inclusive. a2 This corresponds in particular to the length of the side edge 23 .

[0058] Also the one in Figs. 4 semiconductor chips shown 1 According to the third embodiment, it has a similar structural design to the semiconductor chip. 1as in the first embodiment. Differences exist with regard to the number and design of the feedthrough elements. 9 The semiconductor chip 1 features several strip-shaped feedthrough elements 9 each of which extends from the third side III to the fourth page IV of the semiconductor body 2 extend. In other words, the strip-shaped feedthrough elements are 9 grid-like and especially parallel to the side edge 23 arranged. The implementing elements are 9 in the spaces between the vias 12 arranged. The width or first lateral dimension a1 the implementation elements 9 It starts from the first page I to the second page II of the semiconductor body 2 to.

[0059] The Figs. 5 and Figs.Figure 6 shows a comparative example of a semiconductor chip. 1 , where the semiconductor chip 1 in Figs. 5 along the in Figs. 6 shown cross-sectional area SECOND' shown in a sectional view. The semiconductor chip 1 It has a similar structural design to semiconductor chips. 1 according to the first, second, and third embodiments. However, differences exist with regard to the p-side contacting of the semiconductor body. 2 The semiconductor chip 1 has no implementation elements 9 on. Rather, the current is impressed into the contact layer. 6 through the connection between the first contact element 4 and the contact layer 6 arranged current expansion layer 11 instead, which is via the semiconductor chip 1 across most of the way it has a homogeneous thickness.

[0060] The in Figs.Figure 7 shows the current density distribution in the optoelectronic semiconductor chip. 1 according to the comparison example, where an edge length is specified on the L1 axis. K of the semiconductor chip 1 plotted in meters. The current density J is indicated by hatching, where the current density J increases with hatching density (compare bar graph). The current density J is given in A / m2.

[0061] As can be seen from the diagram, the area indicated by the arrow is near the first contact element. 4 the current density J higher than in the first contact element 4 remote areas of the semiconductor chip 1, that is, that an inhomogeneous current density distribution exists in the vicinity of the p-contact element 4 (so-called “current crowding”), which, for example, leads to the intensity of the emitted radiation across the semiconductor chip 1 fluctuates. This effect can be prevented in the semiconductor chips according to the first, second and third embodiments.

[0062] The in Figs. Figure 8 shows the temperature distribution in the optoelectronic semiconductor chip. 1 according to the comparison example, where the edge length is on the L1 axis K of the semiconductor chip 1 The temperature is plotted in meters. The temperature is indicated by hatching, where the temperature T with increasing hatching density (compare bar graph). The temperature T is given in Kelvin.

[0063] As can be seen from the diagram, the area indicated by the arrow is near the first contact element. 4 the temperature T higher than in the first contact element 4 remote areas of the semiconductor chip 1 This means that an inhomogeneous temperature distribution exists near the p-contact element 4. This can lead to a disproportionately strong degradation of the semiconductor body. 2 This effect can occur in semiconductor chips. 1 as described in the first, second and third embodiments.

[0064] The invention is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes every combination of features in the patent claims, even if this feature or combination itself is not explicitly specified in the patent claims or exemplary embodiments. Reference symbol list 1 optoelectronic semiconductor chip 2 Semiconductor bodies 2A first main surface of the semiconductor body 2B second main surface of the semiconductor body 2C, 2D, 2E, 2F Side surface 3 chip carriers 4 first contact element 5 second contact element 6 Contact layer 7 Supply layer 8 Insulation layer 9 Implementation element 10 Bond wire 11 Current expansion layer 12 Through-hole plating 13 Passivation layer 14 Connection layer 15 Compound layer 16 Current expansion layer 17 Metallization 18 first covering layer 19 second covering layer 20 first semiconductor area 21 active zones 22 second semiconductor area 23 Side edge I first page II second page III third page IV fourth page AA' Intersection a1 first lateral extension a2 second lateral extension D1, D2, D3, D4, D5 Thickness J Current density K edge length L1, L2 Lateral direction Temperature V vertical direction

Claims

[1] Optoelectronic semiconductor chip (1) comprising - a semiconductor body (2) comprising a first semiconductor region (20) and a second semiconductor region (22), - a first and second contact element (4, 5) which are provided for electrical contacting the semiconductor body (2), - a chip carrier (3) on which the semiconductor body (2) and the first and second contact elements (4, 5) are arranged side by side, wherein the first and second contact elements (4, 5) are arranged on a first side (I) of the semiconductor body (2), - an electrically conductive contact layer (6) arranged on a first main surface (2A) of the semiconductor body (2) facing the chip carrier (3), - an electrically conductive lead-in layer (7) which is arranged on a side of the contact layer (6) facing away from the semiconductor body (2) and is connected to the first contact element (4), - an insulating layer (8) arranged between the contact layer (6) and the supply layer (7), and - at least one electrically conductive feedthrough element (9) embedded in the insulating layer (8) and electrically connecting the supply layer (7) to the contact layer (6), wherein a number and / or size (a1, a2) of the feedthrough elements (9) on a second side (II) of the semiconductor body (2) opposite the first side (I) is larger than on the first side (I). [2] Optoelectronic semiconductor chip (1) according to the preceding claim, wherein the lead-in layer (7) is a continuous layer with a largely homogeneous thickness (D4). [3] Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the contact layer (6) is a continuous layer of homogeneous thickness (D1). [4] Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the at least one feedthrough element (9) has the geometric shape of a cylinder or prism. [5] Optoelectronic semiconductor chip (1) according to one of the preceding claims, comprising several feedthrough elements (9) arranged offset from one another in rows, wherein the size (a1, a2) of the feedthrough elements (9) increases in a row from the first to the second side (I, II) of the semiconductor body (2). [6] Optoelectronic semiconductor chip (1) according to one of the preceding claims, comprising several feedthrough elements (9) arranged offset from one another in rows, wherein the size (a1, a2) of the feedthrough elements (9) in a row is constant from a third side (III) to a fourth side (IV) opposite the third side of the semiconductor body (2). [7] Optoelectronic semiconductor chip (1) according to any one of claims 1 to 4, comprising a single planar feedthrough element (9) arranged on the second side (II) of the semiconductor body (2) and extending along a side edge (23) of the semiconductor body (2) bounding the first main area (2A). [8] Optoelectronic semiconductor chip (1) according to the preceding claim, wherein the feedthrough element (9) is strip-shaped. [9] Optoelectronic semiconductor chip (1) according to any one of claims 1 to 4, comprising several strip-shaped feedthrough elements (9) extending from a third side (III) to a fourth side (IV) opposite the third side of the semiconductor body (2), wherein a width (a1) of the feedthrough elements (9) increases from the first to the second side (I, II) of the semiconductor body (2). [10] Optoelectronic semiconductor chip (1) according to one of the preceding claims, comprising several vias (12) which extend from the chip carrier (3) through the lead-in layer (7), through the insulating layer (8), through the contact layer (6) and the first semiconductor region (20) to the second semiconductor region (22). [11] Optoelectronic semiconductor chip (1) according to the preceding claim, comprising a connection layer (14) which electrically connects the second contact element (5) to the vias (9). [12] Optoelectronic semiconductor chip (1) according to the preceding claim, wherein the connection layer (14) is thicker than the lead layer (7). [13] Optoelectronic semiconductor chip (1) according to one of claims 10 to 12, wherein the feedthrough elements (9) are arranged in spaces between the vias (12). [14] Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the at least one feedthrough element (9) is formed from the same material as the lead-in layer (7). [15] Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the insulating layer (8) is multilayered and has at least two different sublayers.

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