Method for manufacturing an integrated circuit device with a source / drain barrier

Abstract

A method comprising: receiving a workpiece (100) containing: a substrate (102); and a device fin (104) extending above the substrate (102), the device fin (104) including a channel region (110); Etching a portion of the device fin (104) adjacent to the channel region (110), wherein the etching creates a source / drain recess (702) and forms a dielectric barrier (118) within the source / drain recess (702); Cleaning the workpiece (100) such that a lowermost portion of the dielectric barrier (118) remains within a lowermost portion of the source / drain recess (702); and Forming a source / drain structure element (108) within the source / drain recess (702) such that the lowermost portion of the dielectric barrier (118) is disposed between the source / drain structure element (108) and a remainder of the device fin (104).

Description

BACKGROUND

[0001] The semiconductor industry has evolved into nanometer-scale processing nodes in an effort to achieve higher device density, higher performance, and lower cost. Beyond simply shrinking devices, circuit designers are currently seeking novel structures to further increase performance. One research direction is the development of three-dimensional designs, such as a fin-like field-effect transistor (FinFET). A FinFET can be thought of as a typical planar device extruded from a substrate and into the gate. An exemplary FinFET is fabricated with a thin "fin" (or fin structure) extending upward from a substrate. The FET's channel region is formed in this vertical fin, and a gate is formed over (e.g., wrapped around) the fin's channel region.Wrapping the gate around the fin increases the contact area between the channel region and the gate and allows the gate to control the channel from multiple sides. This can be exploited synergistically in various ways, and in some applications, FinFETs enable reduced short-channel effects, reduced leakage currents, and higher current flow. In other words, they can be faster, smaller, and more efficient than planar devices.

[0002] Due to the complexity inherent in FinFETs and other non-planar devices, manufacturing techniques continue to be developed to reduce size, improve efficiency, and increase speed.

[0003] US 2017 / 0278962 A1 discloses a semiconductor device comprising an oxide layer arranged beneath a gate stack, wherein the oxide layer lies horizontally on a semiconductor layer without extending onto a vertical portion of the gate stack. A sufficient thickness of the oxide layer prevents the oxide layer from being removed during a cleaning process. SUMMARY OF THE INVENTION

[0004] The present invention relates to a method according to claim 1 and a method according to claim 11. Preferred embodiments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention is best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale and are used for illustrative purposes only. The dimensions of the various structural elements may be exaggerated or reduced as needed for clarity of discussion. Fig. 1 is a perspective view of a portion of a workpiece that may be manufactured by a method according to various aspects of the present invention. Fig. 2 is a flow diagram of a method for fabricating a FinFET device on a workpiece according to various aspects of the present invention. Fig. 3 is a perspective view of a portion of a workpiece manufactured according to the invention. Fig. 4-9 are cross-sectional views of a portion of a workpiece made according to the invention along a component fin. Fig. 10 is a cross-sectional view of the portion of the workpiece fabricated according to the invention along a source / drain region. Fig. 11 is a cross-sectional view of a portion of a workpiece made according to the invention along a component fin. Fig. 12 is a cross-sectional view of a portion of a workpiece made according to the invention along a device fin. DETAILED DESCRIPTION

[0006] The following invention provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, only examples. For example, the formation of a first structural element over or on a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements are not necessarily in direct contact. Furthermore, the present invention may repeat reference numerals and / or letters in the various examples.This repetition is for simplicity and clarity and does not automatically create a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, the formation of a structural element on, in connection with, and / or in coupling with another structural element in the following present invention may include embodiments in which the structural elements are formed in direct contact, but may also include embodiments in which further structural elements may be formed that lie between the structural elements, such that the structural elements may not be in direct contact. Furthermore, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "over," "below," "beneath," "upward," "downward," "top," "bottom," etc., as well as their derivatives (for example, "horizontally," "downwardly," "upwardly," etc.), are used to simplify the present invention with respect to the relationship of one structural element to another structural element.The spatially relative terms are intended to cover different orientations of the building element containing the structural elements.

[0008] Advances in integrated circuit design and manufacturing have led to improvements in the speed and efficiency of circuits. However, despite new structures and new manufacturing techniques, losses and efficiency inefficiencies still exist in transistors and other circuit elements. In many cases, parasitic effects, such as leakage currents, hot carrier injection, tunneling, drain-induced barrier depression, and others, have a greater impact with each generation of improvements because the new technologies produce smaller devices operating at lower voltages. These parasitic effects can waste power, generate excess heat, reduce the maximum operating frequency, and / or increase the minimum operating voltage. In extreme cases, they can lead to premature device failure.

[0009] One example is leakage current, the unwanted flow of carriers (such as when the device is in the off state), which includes source-to-drain leakage current, pn junction leakage current, and source (or drain)-to-bulk breakdown. Because some types of leakage current increase as the channel length decreases, leakage current can thwart attempts to reduce device size.

[0010] To solve the problem of leakage current and other parasitic effects, some examples of the present invention provide a transistor, such as a fin-type field-effect transistor (FinFET), with dielectric barriers at the base of the transistor's source / drain features. The dielectric barriers electrically isolate the lowest portions of the source / drain features to prevent leakage current from flowing around the channel region or into the bulk of the substrate. The sides of the source / drain features may be free of the dielectric barrier to allow the flow of carriers through the channel region. Unlike a buried dielectric layer, the dielectric barriers may be physically separated from each other and may be formed exclusively in the source / drain regions.

[0011] The dielectric barriers can reduce several types of leakage current, and many examples enable improved efficiency, reduced heat, and / or higher switching frequency. In some examples, the dielectric barriers allow the formation of transistors with smaller channel lengths, thereby improving device density. However, unless otherwise stated, no embodiment may provide any particular advantage.

[0012] Fig. 1 is a perspective view of a portion of a workpiece 100 according to various aspects of the present invention. The perspective view of Fig. 1 was cut along the longitudinal length of a fin. Fig. 1 has been simplified for clarity and to better illustrate the concepts of the present invention. Additional structural elements may be incorporated into the workpiece 100, and some of the structural elements described below may be replaced or omitted to obtain other embodiments of the workpiece 100.

[0013] The workpiece 100 includes a substrate 102 with one or more device fins 104 formed thereon and separated by isolation features 106. The device fins 104 are representative of any raised features. While the illustrated embodiments include FinFET device fins 104, other embodiments also include other raised active and passive devices formed on the substrate 102. Each FinFET device fin 104 may include any number of FinFETs, each of which may include a pair of opposing source / drain features 108 separated by a channel region 110. As shown in Fig. 1, the source / drain features 108 and the channel region 110 rise above the plane of the substrate 102 on which they are formed and above the isolation features 106. Accordingly, the circuit devices formed from the device fins 104 may be referred to as "non-planar" devices.

[0014] The flow of carriers (electrons for an n-channel FinFET and holes for a p-channel FinFET) through the channel region 110 of a FinFET is controlled by a voltage applied to a gate stack 112 adjacent to and enveloping the channel region 110. The gate stack 112 is shown as translucent to better illustrate the underlying channel region 110. The raised channel region 110 provides a larger surface area near the gate stack 112 than comparable planar devices. This enhances the electromagnetic field interactions between the gate stack 112 and the channel region 110, which can reduce leakage currents and short-channel effects associated with smaller devices. Thus, in many embodiments, FinFETs and other non-planar devices offer better performance with a smaller footprint than their planar counterparts.

[0015] Despite the better control that a FinFET has over the channel, it was found that a leakage current can still flow from the source / drain features 108. One path for the flow of carriers is out through the base of a first source / drain feature 108, through the substrate 102 below the channel region, and in through the base of a second source / drain feature 108. This potential leakage current path is indicated by arrow 114 in Fig. 1. Because the gate stack 112 does not extend down to the leakage current path, the gate stack 112 may not be able to prevent this unwanted flow of carriers, even when the device is in an off state. Another path for the flow of carriers is out of the base of a source / drain structure 108 and through the bulk of the substrate 102, as indicated by arrow 116.

[0016] To reduce potential leakage current through the base of the source / drain features 108, in some examples, the workpiece 100 includes a dielectric barrier 118 disposed between the base of each source / drain feature 108 and the remainder of the fin 104, inhibiting the flow of carriers. To allow normal transistor function, the vertical surfaces of the source / drain features 108 (such as surface 120) adjacent to the channel region 110 are free of the dielectric barrier 118, so that the vertical surfaces of the source / drain features 108 physically touch the channel region 110. This allows carriers to flow through the portions of the channel region 110 under the control of the gate stack 112, while inhibiting the flow of carriers through the substrate 102, the device fin 104, and / or the portions of the channel region 110 that are not sufficiently under the control of the gate stack 112.

[0017] It should be noted that the dielectric barriers 118 may be physically separated from each other. In some examples described below, this is because the dielectric barriers 118 are formed during the formation of the source / drain features 108. The process forms each dielectric barrier 118 in the region between the respective source / drain feature 108 and the portion of the fin 104 or substrate 102 directly below the source / drain feature 108. In other words, in some examples, the dielectric barriers 118 do not extend below the channel region 110.

[0018] Exemplary methods for forming FinFETs with a dielectric barrier 118 will now be described with reference to the Fig. 2-10. In particular, Fig. 2 is a flowchart of a method 200 for fabricating a FinFET device on a workpiece according to various aspects of the present invention. It should be understood that additional steps may be performed before, during, and after method 200, and that some of the described steps may be replaced or omitted to obtain other embodiments of the method. Fig. 3 is a perspective view of a portion of the workpiece 300 according to various aspects of the present invention. Fig. 3 is cut along the longitudinal length of a fin 104. The Fig. 4-9 are cross-sectional views of a portion of the workpiece 300 along a component fin (along plane 302 of Fig. 3) according to various aspects of the present invention. Fig. 10 is a cross-sectional view of the portion of the workpiece along a source / drain region (along plane 304 of Fig. 3) according to various aspects of the present invention. Fig. 3-10, the concepts of the present invention have been simplified for clarity and clarity. Unless otherwise stated, the elements of the Fig. 3-10 essentially those of Fig. 1 resemble.

[0019] We first turn to Block 202 of Fig. 2 and Fig. 3, where a workpiece 300 is received that includes a substrate 102 having fins 104 disposed thereon. In various examples, the substrate 102 includes an elemental (single-element) semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; a non-semiconductor material, such as soda-lime glass, fused silica, fused silica, and / or calcium fluoride (CaF2); and / or combinations thereof.

[0020] The substrate 1002 may be of uniform composition or may include various layers. The layers may have similar or different compositions. For example, a silicon-on-insulator (SOI) substrate 102 includes an insulator layer, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and / or other suitable insulator materials for electrical isolation. In further examples, the substrate 102 includes layers with different semiconductor lattice arrangements to induce strain in the device and thereby tune device performance.

[0021] The fins 104 are disposed on the substrate 102 and may be formed by etching portions of the substrate 102, by depositing various layers on the substrate 102 and etching the layers, and / or by other suitable techniques. The fins 104 may be of a similar composition to the substrate 102 or may be different. For example, in some embodiments, the substrate 102 may include primarily silicon, while the fins 104 include one or more layers that are primarily germanium or a SiGe compound semiconductor. In some embodiments, the substrate 102 includes a SiGe compound semiconductor, and the fins 104 include one or more layers that include a SiGe compound semiconductor with a different ratio of silicon to germanium.

[0022] The workpiece 300 may include gate stacks 112 disposed over channel regions 110 of the fins 104. The gate stacks 112 are disposed on top of the fins 104 and may also extend along the side surfaces of the fins 104. Because the gate stacks 112 surround the fins 104, more of the channel region 110 is located near the gate stack 112 than in a conventional planar device.

[0023] The gate stacks 112 are in Fig. 4 in greater detail. The gate stacks 112 are arranged on the channel regions 110 of the fins 104 and extend along the vertical sidewalls of the channel regions 110 of the fins 104. In the context of Fig. 4, the outline 402 represents the relative position of the portion of a gate stack 112 that extends out of the cross-sectional plane along a side surface of the fin 104.

[0024] A finished gate stack 112 may include: an interface layer disposed on the channel region 110, a gate dielectric disposed on the interface layer, a gate electrode disposed on the gate dielectric, and / or other suitable elements. However, at this point in the method 200, the gate stack 112 may include placeholder elements. For example, in a gate-last process, the gate stack 112 includes a temporary gate electrode 404 used as a placeholder during some of the manufacturing processes. The temporary / placeholder gate electrode 404 is subsequently removed and replaced with an interface layer, a gate dielectric, a functional gate electrode, and / or other gate elements. A gate-last process may be used when the functional gate materials are sensitive to some manufacturing processes, such as annealing.Accordingly, in some examples, when receiving the workpiece 300, the gate stacks 112 include dummy gate electrodes 404. A dummy gate electrode 404 may include polysilicon, dielectric material, and / or other suitable materials. In contrast, a functional gate electrode replacing the dummy gate electrode 404 may include tungsten, aluminum, copper, titanium, tantalum, molybdenum, ruthenium, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN (TAC), TaSiN, metal alloy, other suitable materials, and / or combinations thereof.

[0025] Each gate stack 112 may include a cap layer 406 disposed on top of the gate electrode 404. The cap layer 406 protects the gate electrode 404 during manufacturing processes such as etching. In various examples, the cap layer 406 includes a dielectric material (e.g., semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor oxycarbonitrides, etc.) and / or other suitable materials. In one embodiment, the cap layer 406 includes silicon carbide.

[0026] The gate stacks 112 may also include gate spacers 408 or sidewall spacers disposed on the side surfaces of the gate electrode 404. Similar to the cap layer 406, the gate spacers 408 may protect the gate electrode 404 and may be used to offset subsequently formed source / drain features and control the source / drain structure (junction) profile. In various examples, the gate spacers 408 include dielectric materials (e.g., semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor oxycarbonitrides, etc.) and / or other suitable materials and have a different composition and etchant sensitivity than the cap layers 406. In one embodiment, the gate spacers 408 each include one or more layers of silicon nitride and / or silicon oxide.

[0027] To form the source / drain features 108 on opposite sides of the channel region 110, portions of the fins 104 may be etched, and the source / drain features 108 may be epitaxially grown in the resulting recesses. Referring to block 204 of Fig. 2 and on Fig. 5, a photoresist layer 502 is deposited on the workpiece 300. An exemplary photoresist layer 502 includes a light-sensitive material that causes the layer to undergo a property change when exposed to light. This property change can be used to remove exposed or unexposed portions of the photoresist layer in a process referred to as lithographic patterning.

[0028] With reference to Block 206 of Fig. 2 and on Fig. 6, the photoresist layer is patterned to expose source / drain portions of fins 104. In one such embodiment, a photolithographic system exposes photoresist layer 502 to radiation in a particular pattern determined by a mask. Light passing through or reflecting off the mask impinges on photoresist layer 502, thereby transferring a pattern formed on the mask to photoresist 502. In other such embodiments, photoresist layer 502 is exposed using a direct-write or maskless lithographic technique, such as laser patterning, e-beam patterning, and / or ion beam patterning. After exposure, photoresist layer 502 is developed, leaving behind the exposed portions of the resist or, in alternative examples, the unexposed portions of the resist.An exemplary patterning process includes soft firing of the photoresist layer 502, mask alignment, exposure, post-exposure firing, developing the photoresist layer 502, rinsing, and drying (e.g., hard firing). The patterned photoresist layer 502 exposes portions of the fins 104 to be etched.

[0029] With reference to Block 208 of Fig. 2 and on Fig. 7, an etching process is performed on the workpiece 300 to form source / drain recesses 702. The etching processes may include any suitable etching technique, such as wet etching, dry etching, reactive ion etching (RIE), ashing, and / or other etching methods. In some embodiments, the etching process includes dry etching using an oxygen-based etchant, a fluorine-based etchant (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-based etchant (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-based etchant (e.g., HBr and / or CHBR3), an iodine-based etchant, other suitable etchant gases or plasmas, and / or combinations thereof.In some embodiments, the etching process includes wet etching using dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH), and / or other suitable wet etchants. In some examples, the etchant is selected to etches the fins 104 without significantly etching the surrounding structures, such as the outer materials of the gate stack 112 (e.g., the cap layer 406 or the gate spacers 408) or the isolation features 106. This may allow the etching to be performed even if the patterned photoresist layer 502 is not perfectly aligned.

[0030] The etch process may recess the fins 104 to any suitable depth, measured from the top of the channel region 110 of the fin 104 to the lowest point on the surface of the fin 104 within the source / drain recesses 702 (as indicated by marker 704). In some examples, the etch process is controlled such that the etching stops when the source / drain recesses 702 (except for the dielectric barriers 118, which will be discussed in more detail below) are below the topmost surface of the isolation features 106 (indicated by a dashed line 706 because the isolation features 106 may be outside the cross-sectional plane) and, accordingly, the bottommost surface of the gate stack 112 (also indicated by the dashed line 706).In some examples, the etching process is controlled such that etching stops when the source / drain recesses 702 (except for the dielectric barriers 118) are substantially coplanar with the top surface of the isolation features 106. In further examples, the etching process is controlled such that etching stops when the source / drain recesses 702 (except for the dielectric barriers 118) are above the top surface of the isolation features 106.

[0031] In some such examples, where a fin 104 extends between about 45 nm and about 60 nm above the isolation features 106, the etch process may be controlled to etch to a depth (indicated by marker 704) of between about 50 nm and about 65 nm from the top surface of the first fin 104. Accordingly, in various examples, the lowest point on the surface of the fin 104 within the source / drain recesses 702 is between about 5 nm and about 10 nm below the top surface of the isolation features 106 and, accordingly, the bottom surface of the gate stack 112. In further examples, the lowest point on the surface of the fin 104 within the source / drain recesses 702 is substantially coplanar with the top surface of the isolation features 106.In further examples, the lowest point on the surface of the fin 104 within the source / drain recesses 702 is between about 5 nm and about 10 nm above the top surface of the isolation features 106.

[0032] As in Fig. 7, the etching process may form dielectric barriers 118 within the source / drain recesses 702. The dielectric barriers 118 include a native oxide and / or other dielectric material (e.g., semiconductor oxides, semiconductor hydroxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, semiconductor oxycarbonitrides, etc.) that are formed when the etchant and ambient chemicals react with the semiconductor of the fin 104. For example, the dielectric barrier 118 may include: carbon, hydrogen, or oxygen from an etchant; nitrogen from an ambient gas; and / or carbon, hydrogen, oxygen, or nitrogen from photoresist residues. In some examples, the dielectric barriers 118 primarily include a semiconductor oxide, such as silicon oxide, silicon carbon oxide, germanium oxide, germanium carbon oxide, SiGe oxide, SiGe carbon oxide, and / or combinations thereof.In various examples, the dielectric barrier 118 is a material comprising between about 0 and about 1 atomic percent of one or more semiconductors (e.g., Si and / or Ge), between about 30 and about 40 atomic percent of carbon, between about 10 and about 20 atomic percent of oxygen, and between about 20 and about 30 atomic percent of hydrogen. Accordingly, in some such examples, the material of the dielectric barrier 118 is free of semiconductors.

[0033] By using the material formed by etching fin 104 as a dielectric barrier 118, a barrier deposition step in a subsequent process is eliminated. Each manufacturing process (e.g., deposition, annealing, etc.) can contribute to the thermal budget: an upper limit on how much the workpiece can be heated without sustaining damage. Eliminating a deposition step can leave more room in the budget for other processes. Furthermore, by forming dielectric barrier 118 by etching fin 104, the semiconductor composition of dielectric barrier 118 (e.g., the semiconductor species and / or the ratio of semiconductors) can be substantially similar to that of fin 104.

[0034] With reference to Block 210 of Fig. 2 and on Fig. 8, any portion of the photoresist layer 502 remaining on the workpiece 300 is removed in a photoresist stripping process. The stripping process may use wet etching, dry etching, RIE, and / or ashing to remove the photoresist layer 502. The stripping of the photoresist, as well as the transport of the workpiece 300 between blocks 208 and 210, may further contribute to the formation of the dielectric barrier 118 within the source / drain recesses 702.

[0035] Because the dielectric barrier 118 may inhibit the flow of carriers through an interface between the source / drain feature 108 and the channel region 110, a portion of the dielectric barrier 118 may be removed from the interface of the channel region 110 by a cleaning process or other suitable technique. The cleaning process may include any suitable number of steps, some of which may form the dielectric barrier 118 by removing a portion from the sides of the source / drain recesses 702, and some of which may leave the dielectric barrier 118 substantially unchanged.

[0036] In an example of the latter case, as shown in block 212 of Fig. 2, the source / drain recesses 702 and the remainder of the workpiece 300 may be cleaned in a first cleaning process. Unlike an etching process, the first cleaning process may be configured to remove loosely bound films, particles, and material debris. The first cleaning process may use any suitable wet cleaning or dry cleaning process, and in some examples, the first cleaning process includes a wet cleaning where deionized water (DI), SC1 (deionized water (D1), NH4OH and / or H2O2), SC2 (D1, HCl and / or H2O2), ozonized deionized water (DIWO3), SPM (H2SO4 and / or H2O2), SOM (H2SO4 and / or O3), SPOM, H3PO4, dilute hydrofluoric acid (DHF), HF, HF / ethylene glycol (EG), HF / HNO3, NH4OH, tetramethylammonium hydroxide (TMAH), etc., are applied to the workpiece 300 in which the source / drain recesses 702 are located.The workpiece 300 and / or the wet cleaning solution may be agitated using ultrasonic energy or some other technique to facilitate the cleaning process. Heat may also be applied to enhance cleaning.

[0037] In some embodiments, the first cleaning process is configured to leave at least a portion of the dielectric barrier 118 in place while removing other films, particles, and / or debris. In one example where the wet cleaning uses an RF-based solution, the HF within the solution is diluted to a maximum of 500:1 (D1:HF), as larger concentrations of HF have been found to remove the dielectric barrier 118. In further examples, agitation and heating are reduced to avoid removing the dielectric barrier 118. These process conditions (e.g., the particular concentration of the cleaning solution, whether and how much agitation should be applied, whether and how much heating should be applied, etc.) can be specifically chosen to reduce the cleaning rate and make the cleaning process less time-sensitive.In some examples, this effect is used synergistically to maintain the dielectric barrier 118 within the source / drain recesses 702. In one such example, a wet cleaning using diluted RF is performed for about 10 seconds to clean the workpiece 300 while maintaining the dielectric barrier 118.

[0038] With reference to Block 214 of Fig. 2 and on Fig. 8, the source / drain recesses 702 and the remainder of the workpiece 300 may be cleaned in a second cleaning process. As with the first cleaning process, the second cleaning process may use any suitable wet cleaning or dry cleaning process, and in some examples, the second cleaning process includes a dry cleaning process where O2, ozone, H2, NF3, noble gas(es), and / or other suitable cleaning chemicals are applied in a gas or plasma phase. In one such example, the second cleaning process includes a plasma cleaning process where NF3 and NH3 precursors are used to form NH4F and NF4FHF, which are deposited onto the workpiece 300. The plasma cleaning process is followed by a firing process.During the plasma process, NH4F may react with native semiconductor oxides (e.g., SiO2) on the workpiece 300 to form a compound that transitions to a gaseous form during the firing process and separates from the workpiece 300. The second cleaning process may repeat the plasma cleaning and firing for any number of cycles, and in one such embodiment, the second cleaning process includes three cycles of plasma cleaning and firing.

[0039] In contrast to the first cleaning process, in some embodiments, the second cleaning process is configured to remove a first portion of the dielectric barrier 118 from the sidewalls of the source / drain recesses 702, while leaving the lowermost portion of the dielectric barrier 118 at the base of the source / drain recess 702. Accordingly, when the corresponding source / drain feature is formed, the remaining dielectric barrier 118 isolates the base of the source / drain feature from the rest of the fin 104 and / or the substrate 102. The first cleaning process of block 212 and the second cleaning process of blocks 214 may thin the dielectric barrier 118, and after the cleaning processes are completed, the remaining dielectric barrier 118 may have any suitable thickness.In various examples, the final dielectric barrier 118 has a thickness at its thickest point (e.g., the thickness indicated by marker 708) between about 5 nm and about 10 nm.

[0040] With reference to Block 216 of Fig. 2 and on Fig. 9, an epitaxial process is performed on the workpiece 300 to grow source / drain features 108 within the source / drain recesses 702. The epitaxial process may include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes for applying gaseous and / or liquid precursors to deposit a semiconductor in a crystalline form within the source / drain features 108. The semiconductor of the source / drain features 108 may be the same as that of the device fin 104 and / or the surrounding substrate 102, or may have a different composition or structure. For example, the source / drain features 108 may contain a different ratio of silicon to germanium than the device fin 104 to induce strain on the channel region 110 and thereby tune the carrier mobility in the channel region 110.

[0041] The source / drain structures 108 may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. In various examples, SiGe-containing source / drain structures 108 are doped with boron to a concentration between about 4 × 10 20 atoms / cm 3 and about 9 × 10 20 atoms / cm 3 implanted. In further examples, S1-containing source / drain structural elements 108 are implanted with phosphorus to a concentration between about 3 × 10 21 atoms / cm 3 and about 7 × 10 21 atoms / cm 3implanted. The dopants can be incorporated during the epitaxial process and / or in a subsequent implantation process (i.e., a junction implantation process). An annealing process can be performed on the workpiece 300 to activate the dopants, such as rapid thermal annealing (RTA) and / or laser annealing.

[0042] As in Fig. As can be seen in Figure 9, the bases of the source / drain features 108 are separated from the substrate 102 and the remainder of the device fin 104 by the dielectric barrier 118. The dielectric barrier 118 may prevent the flow of carriers through the base and out through the portion of the fin 104 and / or the substrate 102 not under the control of the gate stack 112. In this way, the dielectric barrier 118 may reduce leakage currents and thereby improve the efficiency of the device. The dielectric barrier 118 may have a curvilinear (curved) bottom surface, with the lowest point of the dielectric barrier 118 extending any distance below the top surface of the isolation features 106 and, accordingly, the bottom surface of the gate stack 112. In various examples, the dielectric barrier 118 extends between about 5 nm and about 10 nm below the top surface of the isolation features 106.In such examples, the thickness of the dielectric barrier 118 may be such that the top surface of the dielectric barrier extends above the top surface of the isolation features 106 and the bottom surface of the gate stack 112.

[0043] It should further be noted that the remainder of the source / drain features 108 (e.g., along the vertical sidewalls 902) is free of the dielectric barrier 118 and is in direct physical contact with the channel region 110 of the device fin 104. In this way, carriers can freely flow through the channel region 110 from the source to the drain when the gate stack 112 drives the device to the on state.

[0044] A corresponding cross section through the source / drain structure elements 108 is shown in Fig. 10. As can be seen, the lowermost surfaces of the source / drain features 108 are separated from the rest of the fins 104 and the substrate 102 by the dielectric barriers 118. For each source / drain feature 108 and the corresponding fin 104, the respective dielectric barrier 118 extends from an isolation feature 106 on one side of the source / drain feature 108 and the fin 104 to an isolation feature 106 on the other sides of the source / drain feature 108 and the fin 104. Thus, between the dielectric barrier 118 and the isolation feature 106, there is no vertical carrier path from the source / drain feature 108 to the rest of the fin 104 and the substrate 102.

[0045] With reference to Block 218 of Fig. 2, the workpiece is prepared for further manufacturing. This may include replacing placeholder elements of the gate stack 112 (e.g., placeholder gate electrode 404, cap layer 406, etc.) with functional elements, forming an interconnect structure that electrically couples the FinFETs, and other suitable manufacturing processes.

[0046] As explained above, the orientation of the source / drain recesses 702, the dielectric barriers 118 and the isolation features 106 and the gate stack 112 may be different in other examples. In some examples described with reference to Fig. 11, the etching causes the bottom of the source / drain recesses 702 to be substantially coplanar with the top of the isolation features. In this regard, Fig. 11 is a cross-sectional view of a portion of a workpiece 1100 along a device fin according to various aspects of the present invention. The workpiece 1100 includes a substrate 102, fins 104, channel regions 110, gate stacks 112 (e.g., gate electrode 404, cap layer 406, gate spacers 408, etc.), and source / drain features 108 substantially similar to those described above.

[0047] The etching of block 208 may remove any suitable amount of the fin 104 to form the source / drain features 108, and in some examples, the etch is controlled to etch to a depth such that the bottom of the dielectric barrier 118 is substantially coplanar with the top of the isolation features 106 (indicated by marker 706) and, accordingly, substantially coplanar with the bottom surface of the gate stack 112 (also indicated by marker 706).

[0048] It should also be noted that the top surface of the dielectric barrier 118 may have any suitable shape. In contrast to the examples of Fig. 9, where the top of the dielectric barrier 118 is curvilinear and concave, is shown in the examples of Fig. 11, the top surface of the dielectric barrier 118 is substantially planar. In various examples, the top and bottom surfaces are such that the dielectric barrier 118 has a thickness (e.g., the thickness indicated by marker 1102) between about 5 nm and about 10 nm at its thickest point.

[0049] In some examples related to Fig. 12, the etching causes the bottom of the source / drain recesses 702 to lie above the top of the isolation features. In this regard, Fig. 12 illustrates a cross-sectional view of a portion of a workpiece 1200 along a device fin according to various aspects of the present invention. The workpiece 1200 includes a substrate 102, fins 104, channel regions 110, gate stacks 112 (e.g., gate electrode 404, cap layer 406, gate spacers 408, etc.), and source / drain features 108 substantially similar to those described above.

[0050] The etching of block 208 may remove any suitable amount of fin 104 to form source / drain features 108, and in some examples, the etch is controlled to etch to a depth such that the bottom of dielectric barrier 118 is above the top surface of isolation features 106 (indicated by marker 706) and, accordingly, is substantially coplanar with the bottom surface of gate stack 112 (also indicated by marker 706). The bottom of dielectric barrier 118 may be any distance above the plane defined by the top surface of isolation features 106 and the bottom surface of gate stack 112, and in various examples, the bottom of dielectric barrier 118 is between about 5 nm and about 10 nm above the plane.

[0051] The top of the dielectric barrier 118 may have any suitable shape. In contrast to the examples of Fig. 9, where the top of the dielectric barrier 118 is curvilinear and concave, and the examples of Fig. 11, where the top of the dielectric barrier 118 is substantially planar, is shown in the examples of Fig. 12, the top surface of the dielectric barrier 118 is curvilinear and convex. In various examples, the top and bottom surfaces are such that the dielectric barrier 118 has a thickness (e.g., the thickness indicated by marker 1202) between about 5 nm and about 10 nm at its thickest point.

Claims

[1] Method comprising: Receiving a workpiece (100) containing: a substrate (102); and a component fin (104) extending over the substrate (102), wherein the component fin (104) contains a channel region (110); Etching a section of the component fin (104) next to the channel region (110), wherein the etching creates a source / drain recess (702) and forms a dielectric barrier (118) within the source / drain recess (702); Cleaning the workpiece (100) such that a lowest section of the dielectric barrier (118) remains within a lowest section of the source / drain recess (702); and Forming a source / drain structural element (108) within the source / drain recess (702) such that the lowest section of the dielectric barrier (118) is arranged between the source / drain structural element (108) and a remainder of the component fin (104). [2] Method according to claim 1, wherein the cleaning of the workpiece (100) includes a dry cleaning process configured to remove a lateral section of the dielectric barrier (118) arranged along a side surface of the source / drain recess (702) and leaving the bottommost section of the dielectric barrier (118). [3] Method according to claim 2, wherein the cleaning of the workpiece (100) further includes a wet cleaning process configured such that the dielectric barrier (118) remains after the wet cleaning process. [4] Method according to claim 2, wherein the dry cleaning process removes the lateral section of the dielectric barrier (118) such that a side surface of the source / drain structural element (108) is free of the dielectric barrier (118) and physically touches the channel region (110). [5] Method according to any one of the preceding claims, wherein: the received workpiece (100) further contains a gate stack (112) which is arranged on and around the channel region (110); and the etching of the section of the component fin (104) is carried out to such a depth that a bottom surface of the dielectric barrier (118) extends to a depth below a bottom surface of the gate stack (112). [6] Method according to claim 5, wherein a top surface of the dielectric barrier (118) is arranged above the bottom surface of the gate stack (112). [7] Method according to any one of claims 1 to 4, wherein: the received workpiece (100) further contains a gate stack (112) which is arranged on and around the channel region (110); and the etching of the section of the component fin (104) is carried out to such a depth that a bottom surface of the dielectric barrier (118) extends to a depth that is essentially coplanar with a bottom surface of the gate stack (112). [8] Method according to any one of claims 1 to 4, wherein: the received workpiece (100) further contains a gate stack (112) which is arranged on and around the channel region (110); and the etching of the section of the component fin (104) is carried out to such a depth that a bottom surface of the dielectric barrier (118) extends to a depth above a bottom surface of the gate stack (112). [9] Method according to any one of the preceding claims, wherein: the received workpiece (100) further contains an insulating structural element (106) arranged along the component fin (104); and the etching of the section of the component fin (104) is carried out to such a depth that the dielectric barrier (118) extends under a top surface of the insulating structure element (106). [10] Method according to any one of the preceding claims, wherein: the component fin (104) is arranged between a first insulation structure element (106) and a second insulation structure element (106) and extends over it; and the dielectric barrier (118) extends from the first insulation structure element (106) to the second insulation structure element (106). [11] Method comprising the following: Receiving a substrate (102) and a fin formed on the substrate (102) and containing a channel region (110); Etching of the fin (104) to define a first source / drain recess (702) on a first side of the channel region (110) and a second source / drain recess (702) on a second side of the channel region (110) opposite the first side, wherein by etching the fin (104) a first insulating barrier (118) is formed within a lowest section of the first source / drain recess (702) and a second insulating barrier (118) is formed within a lowest section of the second source / drain recess (702); and epitaxial growth of a first source / drain structural element (108) within the first source / drain recess (702) on the first insulating barrier (118) and a second source / drain structural element (108) within the second source / drain recess (702) on the second insulating barrier (118). [12] The method of claim 11, wherein the method further comprises: a first cleaning process in which the first source / drain recess (702) and the second source / drain recess (702) are cleaned by a wet cleaning process after etching the fin and before epitaxial growth of the first source / drain structural element (108) and the second source / drain structural element (108), wherein the first cleaning process is configured to leave the first insulating barrier (118) within the bottom section of the first source / drain recess (702) and the second insulating barrier (118) within the bottom section of the second source / drain recess (702), where the wet cleaning uses an HF-based solution where the concentration of HF corresponds to a dilution of the HF in the solution of 1 to 500 or less. [13] Method according to claim 11 or 12, wherein the first insulating barrier (118) and the second insulating barrier (118) are physically separated by the channel region (110). [14] Method according to any one of the preceding claims 11 to 13, wherein the first insulating barrier (118) and the second insulating barrier (118) do not extend below the channel region (110). [15] Method according to any one of the preceding claims 11 to 14, wherein the first insulating barrier (118) and the second insulating barrier (118) are formed by etching the fin to define the first source / drain recess (702) and the second source / drain recess (702). [16] Method according to claim 12, further comprising a second cleaning process configured to remove a first section of the first insulating barrier (118) along a side surface of the first source / drain recess (702) and to leave a second section of the first insulating barrier (118) along a bottom surface of the first source / drain recess (702).

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