Semiconductor component and method for its manufacture

Abstract

Method for producing a structure with negative capacitance comprising the following steps: producing a dielectric layer (30) over a substrate (10); producing a first metal layer (40) over the dielectric layer (30); after the first metal layer (40) has been produced, performing an annealing step followed by a cooling step; producing a second metal layer (52) over the first metal layer (40), wherein the second metal layer (52) is produced after the cooling step;and forming a work function setting layer (54) over the second metal layer (52), wherein after the cooling step the dielectric layer (30) has become a ferroelectric dielectric layer (30) with an orthorhombic crystal phase, wherein the dielectric layer (30) comprises HfO2 doped with Si in an amount of 2 to 6 mol%, wherein after the formation of the structure with negative capacitance the ferroelectric dielectric layer (30) continues to have Ti in an amount of 2 to 5 mol% and / or Al in an amount of 5 to 7 mol%.

Description

Technical FieldThe present invention relates to semiconductor integrated circuits and, more particularly, to semiconductor devices having negative capacitance field effect transistors (NC-FETs).BackgroundThe prethreshold swing is a characteristic of a current-voltage characteristic of a transistor. In the prethreshold region, the drain current response is similar to the exponentially increasing current of a forward biased diode. A plot of drain logarithmic current vs. gate voltage at fixed drain, source and bulk voltages shows an approximately logarithmic linear response in this metal oxide semiconductor (MOS) FET operating region. In order to improve the threshold characteristics, a negative capacitance field effect transistor (NC-FET) for which a ferroelectric material is used has been proposed.Methods for producing ferroelectric dielectric layers are known, for example, from U.S. Pat. No. 9,793,397 B1, DE 10 2017,110,434 A1, DE 10 2014 221 371 A1, U.S. Pat. No. 2016 / 0 359 109 A1, U.S. Pat. No. 2016 / 0 308 070 A1 and U.S. Pat. No. 2015 / 0 076 437 A1.Brief Description of the DrawingsAspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1A and 1B show cross-sectional views of metal-insulator-semiconductor (MIS) FET NC FETs, and FIG. 1C shows a cross-sectional view of a metal-insulator-metal-insulator-semiconductor (MIMIS) FET NC FET.FIGS. 2A to 2D show various stages of manufacturing a negative capacitance structure according to an embodiment of the present invention.FIGS. 3A to 3D show various atomic structures of HfO 2. FIG. 4 shows measurement results of x-ray diffraction (XRD).FIGS. 5 and 6 show measurement results of electron energy loss spectroscopy (EELS).FIGS. 7A to 7D show various stages of manufacturing an NC-FET according to an embodiment of the present invention.FIGS. 8A to 8D show various stages of manufacturing an NC-FET according to an embodiment of the present invention.FIGS. 9A to 9C show various stages of manufacturing an NC-FET according to an embodiment of the present invention.FIGS. 10A to 10C show various stages of manufacturing an NC-FET according to an embodiment of the present invention.FIGS. 11A to 11C show various stages of manufacturing an NC-FET according to an embodiment of the present invention.FIGS. 12A to 12C show various stages of manufacturing an NC-FET according to an embodiment of the present invention.FIGS. 13A to 13C show various stages of manufacturing an NC-FET according to an embodiment of the present invention.FIGS. 14A to 14D show various stages of manufacturing an NC-FET according to another embodiment of the present invention.FIGS. 15A to 15D show various stages of manufacturing an NC-FET according to an embodiment of the present invention.Detailed DescriptionThe present invention provides a method of manufacturing a negative capacitance structure according to claim 1, a method of manufacturing a negative capacitance field effect transistor according to claim 7, and a negative capacitance field effect transistor according to claim 15. Exemplary embodiments are given in the dependent claims. It is to be understood that the following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements will be described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the specified range of values, but may be dependent on process conditions and / or desired characteristics of the device. Moreover, the formation of a first element over or on a second element in the description below may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. For simplicity and clarity, different elements may be arbitrarily drawn at different scales. In the accompanying drawings, some layers or structural elements may be omitted for simplicity.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein may also be interpreted accordingly. Moreover, the term "made of" may mean either "comprises" or "consisting of". In addition, in the manufacturing process below, there may be one or more other steps between the described steps, and the order of the steps may be changed.To reduce the subthreshold swing (SS) of a field effect transistor (FET), negative capacitance (NC) technology, such as integrating ferroelectric (FE) materials, provides a possible solution to substantially reduce the V DD( supply voltage). With this technology, a FET with a steep SS for low power consumption operation is achieved.In an NC-FET, a capacitor (e.g., a ferroelectric capacitor) having a negative capacitance is connected in series with a gate of a MOSFET. The negative ferroelectric capacitor may be a single capacitor connected to the gate of the MOSFET through a conductive layer (e.g., a wire or a contact), in some embodiments. In other embodiments, one of the electrodes of the negative capacitor is a gate electrode of the MOSFET. In this case, the negative capacitor is formed in sidewall spacers of the MOSFET.In conventional devices, high-k gate materials, such as HfO 2, typically form an amorphous layer. However, the undoped HfO 2 is amorphous and paraelectric and does not exhibit a negative capacitance effect. Ferroelectric materials having a perovskite structure such as PZT and BaTiO 3, have very good ferroelectric properties. However, these materials are still problematic in that their production is not fully compatible with silicon-based semiconductors and their ferroelectric properties deteriorate with the reduction of their thickness by a size effect.In the present invention, a doped HfO 2- layer having an orthorhombic crystal phase and exhibiting good ferroelectric properties and its production methods are provided.FIGS. 1A and 1B show cross-sectional views of metal-insulator-semiconductor (MIS) FET NC FETs, and FIG. 1C shows a cross-sectional view of a metal-insulator-metal-insulator-semiconductor (MIMIS) FET NC FET. Although FIGS. 1A to 1C show NC-FETs having a planar MOS transistor structure, FinFETs and / or gate-all-around FETs may also be used.As shown in FIG. 1A, the MIS NC-FET includes a substrate 100, a channel 101, and a source and a drain 102. The source and drain 102 are appropriately doped with dopants. In addition, the source and drain and channel (active regions) are surrounded by a dielectric separation layer (not shown), such as shallow trench isolation (STI), made of, for example, silicon oxide.An intermediate layer 103 is formed over the channel layer 101 in some embodiments. The intermediate layer 103 is made of silicon oxide having a thickness in the range of about 0.5 nm to about 1.5 nm in some embodiments.A ferroelectric dielectric layer 105 is arranged above the intermediate layer 103. The ferroelectric dielectric layer 105 comprises HfO 2 doped with one or more elements selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr. In some embodiments, the ferroelectric dielectric layer 105 includes HfO 2 doped with Si and / or Zr. In certain embodiments, the ferroelectric dielectric layer 105 includes HfO 2 doped with Si in an amount of 2 to 6 mol %, or HfZrO 2( Hf:Zr=1:1). In the present invention, the ferroelectric dielectric layer 105 has an orthorhombic crystal phase. The orthorhombic crystal of the ferroelectric dielectric layer 105 is polycrystalline in some embodiments. The ferroelectric dielectric layer 105 has a thickness of about 1.0 nm to about 5 nm in some embodiments, and may be formed by a suitable method, such as ALD or CVD.A gate electrode layer 106 is arranged over the ferroelectric dielectric layer 105. The gate electrode layer 106 includes one or more metal layers. In some embodiments, the gate electrode layer 106 includes: a first conductive layer (a capping layer) disposed on the ferroelectric dielectric layer 105; a second layer (a barrier layer) disposed on the first conductive layer; a third conductive layer (a work function adjustment layer) disposed on the second conductive layer; a fourth conductive layer (an adhesive layer) disposed on the third conductive layer; and / or a fifth conductive layer (a main gate metal layer) disposed on the fourth conductive layer.The capping layer comprises a TiN-based material, such as TiN and TiN, doped with one or more other elements. In some embodiments, the TiN layer is doped with Si. The barrier layer comprises TaN in some embodiments.The work function adjustment layer includes one or more layers of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For an n-channel FinFET, one or more of the compounds / elements TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for a p-channel FinFET, one or more of the compounds / elements TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer.The adhesive layer includes Ti, TiN, and / or TaN in some embodiments. The main gate metal layer includes a metal selected from the group consisting of W, Cu, Ti, Al and Co.In addition, sidewall spacers 109 are formed on opposite side surfaces of the gate structure, as shown in FIG. 1A. The sidewall spacers 109 include one or more layers of an insulating material, such as silicon oxide, silicon nitride, and silicon oxynitride.FIG. 1B is a sectional view of a MIS-FET NC-FET according to another embodiment. In FIG. 1B, the intermediate layer 103 has a planar shape, and the ferroelectric dielectric layer 105 is conformally formed in the gate space and has a height substantially equal to the height of the gate electrode layer 106.In FIG. 1C, similar to FIGS. 1A and / or 1B, a channel 101 and a source and a drain 102 are formed on a substrate 100. A first gate dielectric layer 113 is disposed over the channel 101. The first gate dielectric layer 113 includes one or more high-k dielectric layers (e.g., having a dielectric constant greater than 3.9) in some embodiments. The one or more gate dielectric layers may be, for example, one or more layers of a metal oxide or a silicate of Hf, Al Zr, combinations thereof, and multilayers thereof. Other suitable materials are La, Mg, Ba, Ti, Pb and Zr in the form of metal oxides, metal alloy oxides and combinations thereof. Exemplary materials are MgO x, SiN (Si 3 N 4), Al 2 O 3, La 2 O 3, Ta 2 O 3, Y 2 O3, HfO2, ZrO2, GeO2, HfxZr1-xO2, Ga2O3, Gd 2 O 3, TaSiO 2, TiO 2, HfSiON, YGe x O y, YSi x O y, LaAlO 3 and the like. In certain embodiments, HfO 2, ZrO 2 and / or Hf x Zr 1-x O 2 are used. The manufacturing methods for the first gate dielectric layer 113 include molecular beam deposition (MBD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like. In some embodiments, the first gate dielectric layer 113 has a thickness of about 1.0 nm to about 5.0 nm.In some embodiments, an intermediate layer (not shown) may be formed over the channel 101 before forming the first gate dielectric layer 113, wherein the first gate dielectric layer 113 is formed over the intermediate layer.On the first gate layer 113, a first gate electrode 114 is disposed as an inner electrode. The first gate electrode 114 may include one or more metals, such as W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. In some embodiments, the first gate electrode 114 includes one or more of the compounds / elements TiN, WN, TaN, and Ru. Metal alloys such as Ti-Al, Ru-Ta, Ru-Zr, Pt-Ti, Co-Ni and Ni-Ta, and / or metal nitrides such as WN x, TiN x, MoN x, TaN x and TaSi x N y, may also be used. In some embodiments, at least one of the compounds / elements W, Ti, Ta, TaN, and TiN is used as the first gate electrode 114. In some embodiments, the first gate electrode 114 includes a work function adjustment layer.A ferroelectric dielectric layer 115 is produced on the first gate electrode 114. The ferroelectric dielectric layer 115 comprises HfO 2 doped with one or more elements selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr. In some embodiments, the ferroelectric dielectric layer 115 includes HfO 2 doped with Si and / or Zr. In certain embodiments, the ferroelectric dielectric layer 115 includes HfO 2 doped with Si in an amount of 2 to 6 mol %, or HfZrO 2( Hf:Zr=1:1). In the present invention, the ferroelectric dielectric layer 115 has an orthorhombic crystal phase. The orthorhombic crystal of the ferroelectric dielectric layer 115 is polycrystalline in some embodiments. The ferroelectric dielectric layer 115 has a thickness of about 1.0 nm to about 5 nm in some embodiments, and may be formed by a suitable method such as ALD or CVD.Further, on the ferroelectric dielectric layer 115, a second gate electrode 116 as an outer gate is disposed. The second gate electrode 116 may be made of one or more metals selected from the group consisting of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. The second gate electrode 116 is made of the same material as the first gate electrode 114 or of a different material. In addition, sidewall spacers 119 are formed on opposite side surfaces of the gate structure as shown in FIG. 1C. The sidewall spacers 119 include one or more layers of an insulating material such as silicon oxide, silicon nitride, and silicon oxynitride.As shown in Figs. 1A to 1C, the ferroelectric dielectric layers 105 and 115 and the first gate dielectric layer 113 have a U-shape in cross section with a thin central part and thick side parts in the vertical direction.FIGS. 2A to 2D show various stages of manufacturing a negative capacitance structure according to an embodiment of the present invention. It will be appreciated that additional steps may be provided before, during, and after the processes shown in FIGS. 2A-2D, and some of the steps described below may be replaced or omitted in additional embodiments of the method. The order of the steps / processes is interchangeable. Moreover, materials, configurations, dimensions, and / or processes similar or similar to those of the above embodiments described with reference to FIGS. 1A to 1C may be used in the following embodiments, and their detailed explanation may be omitted.As shown in FIG. 2A, an intermediate layer 20 is formed on a substrate 10. In some embodiments, the substrate 10 is comprised of: a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as group IV compound semiconductors, e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, and SiGeSn, or group III-V compound semiconductors, e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenic phosphide (GaAsP), or gallium indium phosphide (GaInP); or the like. In addition, the substrate 10 may include an epitaxial layer that may be strained to improve performance and / or may have a silicon-on-insulator (SOI) structure.In some embodiments, the intermediate layer 20 is made of a chemical silicon oxide that can be formed by chemical reactions. A chemical silica can be prepared, for example, by demineralized water+ozen (DIO 3), NH 4 OH+H 2 O 2+ H 2 O (APM), or by other methods. In other embodiments, a different material or processes may be used for the intermediate layer. In some embodiments, the intermediate layer has a thickness of about 0.5 nm to about 1.5 nm.A dielectric layer 30 is then formed over the intermediate layer 20. The dielectric layer 30 comprises HfO 2 doped with one or more elements selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr.The manufacturing methods for the dielectric layer 30 include molecular beam deposition (MBD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like. In some embodiments, HfO 2, which is doped with Zr, may be produced by ALD using HfCl 4 and H 2 O as a first precursor and ZrCl 4 and H 2 O as a second precursor at a temperature in the range of about 200° C. to 400° C. For HfO 2, which is doped with Si, SiH 4, Si 2 H 6 and / or SiH 2 Cl 2 or another suitable silicon gas source may be used. The deposited dielectric layer 30 is amorphous and paraelectric. The thickness of the dielectric layer 30 is in the range of about 1 nm to about 5 nm in some embodiments.After the dielectric layer 30 is formed, a capping layer 40 is formed on the dielectric layer 30, as shown in FIG. 2B. Capping layer 40 includes a TiN-based material, such as TiN or TiN, doped with one or more other elements, in some embodiments. In some embodiments, the TiN layer is doped with Si. Capping layer 40 may be formed by ALD, CVD, or physical vapor deposition, such as sputtering, or other suitable methods. When the ALD is used, in some embodiments, it is performed at a temperature in the range of about 400° C. to about 500° C. The thickness of the capping layer 40 is in the range of about 1 nm to about 5 nm in some embodiments.After the capping layer 40 is formed, an annealing process is performed as shown in FIG. 2C. The annealing process is performed at a temperature in the range of about 700° C. to about 1000° C. in an inert gas environment such as N 2, Ar, and / or He. The annealing time is about 10 seconds to 1 minute in some embodiments. After the annealing, cooling is carried out. In some embodiments, the substrate is cooled to less than 100° C. or to room temperature (about 25° C.). The annealing process after the formation of the capping layer 40 provides a driving force for the transition of the doped HfO 2- structure from the amorphous phase to a tetragonal high-temperature phase, and the capping layer 40 provides, by cooling, the mechanical stress required for the crystal transition from the tetragonal high-temperature phase to the ferroelectric orthorhombic high-pressure phase.In some embodiments, after the capping layer 40 is formed, an amorphous silicon layer is formed on the capping layer 40, and then an annealing process is performed. After the annealing process, cooling is performed and the amorphous silicon layer is removed.After cooling, a barrier layer 52 made of, for example, TaN is formed over the capping layer 40, as shown in FIG. 2D. The barrier layer 52 may be formed by ALD, CVD, or physical vapor deposition, such as sputtering, or other suitable methods. When the ALD is used, in some embodiments, it is performed at a temperature in the range of about 300° C. to about 400° C. The thickness of the barrier layer 52 is in the range of about 1 nm to about 5 nm in some embodiments. In some embodiments, an annealing process for converting the amorphous structure to the orthorhombic structure may be performed after the barrier layer 52 is formed.A work function adjustment layer 54 is then formed on the barrier layer 52. In some embodiments, work function adjustment layer 54 includes TiN for a p-type transistor and TiAl for an n-type transistor. However, another suitable metallic material may be used for the work function adjustment layer 54. In some embodiments, a TiAl layer is also formed on a TiN work function adjustment layer for a p-type transistor. The work function adjustment layer 54 may be formed by ALD, CVD, or physical vapor deposition such as sputtering, or other suitable methods. When the ALD is used, in some embodiments, it is performed at a temperature in the range of about 300° C. to about 400° C. The thickness of the work function adjustment layer 54 is in the range of about 1 nm to about 5 nm in some embodiments.Further, a metal gate main layer 58 is formed over the work function adjustment layer 54. The main gate metal layer 58 includes one or more metals, such as W, Cu, Ti, Al, and Co, or another suitable material. When the metal gate main layer 58 is made of W, an adhesive layer 56 is formed on the work function adjustment layer 54 in some embodiments. In some embodiments, the adhesive layer 56 is made of Ti. As shown in FIG. 2D, a gate electrode 50 may include: a barrier layer 52 disposed on the capping layer 40; a work function adjustment layer 54 disposed on the barrier layer 52; an adhesive layer 56 disposed on the work function adjustment layer 54; and a metal gate main layer 58.FIGS. 3A to 3D show various atomic structures of HfO 2. FIG. 3A shows the amorphous structure of the deposited doped HfO 2. By applying heat, the amorphous structure changes to a tetragonal crystal structure (phase) as shown in FIG. 3B. When the heated HfO 2, which has a tetragonal crystal structure, is cooled with a capping metal thereon, the HfO 2 assumes an orthorhombic crystal structure (phase), as shown in FIG. 3C. When the heated HfO 2, which has a tetragonal crystal structure, is cooled without the capping metal thereon, the HfO 2 assumes a mixed structure of a monolithic crystal structure (left) and a tetragonal crystal structure (right), as shown in FIG. 3D. The orthorhombic HfO 2 has a non-centrosymmetric structure, and therefore, spontaneous polarization occurs by replacement of four oxygen ions. This enables better ferroelectric properties to be achieved with the orthorhombic HfO 2.FIG. 4 shows measurement results of x-ray diffraction (XRD). As samples, deposited doped HfO 2 with a thickness of 3 nm and doped HfO 2 with a thickness of 3 nm were used after the annealing process with a capping layer. The deposited doped HfO 2 exhibits a broad spectrum indicative of an amorphous structure. In contrast, after annealing with a capping layer, the doped HfO 2 exhibits peaks corresponding to the orthorhombic phase.FIGS. 5 and 6 show measurement results of electron energy loss spectroscopy (EELS). As stated above, after the dielectric layer 30 is converted to an orthorhombic phase, further layers are formed using multiple thermal processes. The doping elements in HfO 2, such as semiconductor materials (Si) and metallic elements (Zr, Al, La, Y, Gd and / or Sr) introduced by in situ doping during growth by ALD, are substantially uniformly distributed in the doped HfO 2- layer. As shown in FIGS. 5 and 6, Ti derived from the capping layer 40 (a TiN-based material) diffuses into the HfNbO 2- layer. When a TiAl layer is used as the work function adjustment layer 54 for an n-type transistor, Al may also diffuse into the HfZrO 2- layer as shown in FIG. 5. In some embodiments, the HfMnO 2- layer includes Al in an amount of 5 to 7 mol %. When a TiN layer is used as the work function adjustment layer 54 for a p-type transistor, Ti derived from the TiN work function adjustment layer may also diffuse into the HfNbO 2- layer, as shown in FIG. 6. In a p-type transistor, Al may not diffuse into the HfMnO 2- layer (below a detection limit) even when a TiAl layer is formed on the TiN work function adjustment layer. In some embodiments, the HfMnO 2- layer includes Ti in an amount of 2 to 5 mol %.In some embodiments, the ferroelectric HfO 2- layer is comprised of an orthorhombic crystal phase. In other embodiments, the ferroelectric HfO 2- layer is substantially formed by an orthorhombic crystal phase. In this case, the orthorhombic crystal phase constitutes about 80% or more of the ferroelectric HfO 2- layer, and the remaining phases may be an amorphous phase, a monolithic phase and / or a tetragonal phase.FIGS. 7A to 13C show various stages of manufacturing an NC-FET according to an embodiment of the present invention. It will be appreciated that additional steps may be provided before, during, and after the processes shown in FIGS. 7A-13C, and some of the steps described below may be replaced or omitted in additional embodiments of the method. The order of the steps / processes is interchangeable. Moreover, materials, configurations, dimensions, and / or processes similar or similar to those of the above embodiments described with reference to FIGS. 1A to 2D may be used in the following embodiments, and their detailed explanation may be omitted.FIG. 7A is a perspective view, and FIG. 7B is a sectional view along the x direction, showing one of a plurality of stages of manufacturing according to an embodiment of the present invention. As shown in FIGS. 7A and 7B, a substrate 200 is provided. In some embodiments, the substrate 200 is comprised of: a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as group IV compound semiconductors, e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, and SiGeSn, or group III-V compound semiconductors, e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenic phosphide (GaAsP), or gallium indium phosphide (GaInP); or the like. In addition, the substrate 200 may include an epitaxial layer that may be strained to improve performance and / or may have a silicon-on-insulator (SOI) structure. The upper portion of the substrate 200 may include multilayers of Si and SiGe.FIG. 7C is a perspective view, and FIG. 7D is a sectional view along the x direction, showing one of a plurality of stages of manufacturing according to an embodiment of the present invention. As shown in FIGS. 7C and 7D, fin structures 210 are formed by etching the substrate 200 and forming a dielectric isolation layer 220. The fin structures 210 may be patterned using any suitable method. For example, the fin structures 210 may be patterned using one or more photolithography processes, such as dual-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes that can produce patterns having, for example, pitch spacings that are less than those that can otherwise be achieved with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers, or mandrels, may then be used to pattern the fin structures 210. In some embodiments, the width of the fin structures 210 is in the range of about 4 nm to about 10 nm, and the pitch of the fin structures 210 is in the range of about 10 nm to about 50 nm.An insulating material layer 220 is then formed over the fin structures, thereby embedding the fin structures. The insulating material layer 220 may be comprised of suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or fluorosilicate glass (FSG); low-k dielectrics such as carbon doped oxides; extreme low-k dielectrics such as porous carbon doped silicon dioxide; polymers such as polyimide; combinations thereof, or the like. In some embodiments, the insulating material layer 220 is formed by a method such as CVD, flowable CVD (FCVD), or spinon glass process, but another suitable method may be used. Subsequently, portions of the insulating material layer 220 that pass over the top surfaces of the fin structures 210 are removed, for example, with an etching process, a chemical mechanical polishing (CMP), or the like, as shown in FIGS. 7C and 7DFIG. 8A is a perspective view, and FIG. 8B is a sectional view along the x direction, showing one of a plurality of stages of manufacturing according to an embodiment of the present invention. As shown in FIGS. 8A and 8B, the insulating material layer 220 is recessed to expose the top portions of the fin structures 210. The recessed insulating material layer 220 is referred to as a dielectric isolation layer or a shallow trench isolation (STI). The height of the exposed fin structures 210 measured from the top surface of the dielectric separation layer 220 is in the range of about 30 nm to about 100 nm in some embodiments.FIG. 8C is a perspective view, and FIG. 8D is a sectional view along the x direction, showing one of a plurality of stages of manufacturing according to an embodiment of the present invention. As shown in FIGS. 8C and 8D, a dummy gate dielectric layer 215 is subsequently formed over the top portions of the fin structure 210. The dummy gate dielectric layer 215 is a silicon oxide layer formed by CVD or ALD in some embodiments, and the thickness of the dummy gate dielectric layer 215 is in the range of about 1 nm to about 3 nm in some embodiments.A polysilicon layer 230 is then formed over the dummy gate dielectric layer 215, and a hard mask is also formed on the polysilicon layer. The hard mask layer is patterned into a hard mask pattern 235 using appropriate lithography and etching steps, as shown in FIGS. 9A to 9C. The hard mask pattern 235 includes one or more layers of an insulating material, such as silicon oxide and silicon nitride, in some embodiments.FIG. 9A is a perspective view, FIG. 9B is a sectional view along the y direction, and FIG. 9C is a sectional view along the x direction, and illustrate one of a plurality of stages of manufacturing according to an embodiment of the present invention. Using the hard mask pattern 235 as an etching mask, the polysilicon layer is patterned into dummy gate electrodes 230 as shown in FIGS. 9A to 9C. In some embodiments, the width of the dummy gate electrode 230 is in the range of about 8 nm to about 20 nm.FIG. 10A is a perspective view, FIG. 10B is a sectional view along the y direction, and FIG. 10C is a sectional view along the x direction, and show one of a plurality of stages of manufacturing according to an embodiment of the present invention. Sidewall spacers 240 are formed on opposite side surfaces of the dummy gate electrodes 230. The sidewall spacers 240 include one or more layers of an insulating material, such as silicon oxide, silicon nitride, and silicon oxynitride. Additionally, source / drain epitaxial layers 250 are formed over source / drain regions of the fin structures 210. The source / drain epitaxial layers 250 include SiP, SiAs, SiGeP, SiGeAs, GeP, GeAs, and / or SiGeSn, or other suitable material for an n-type FET, and SiB, SiGa, SiGeB, SiGeGa, GeB, GeGa, and / or SiGeSn, or other suitable material for a p-type FET. The thickness of the source / drain epitaxial layers 250 is in the range of about 3 nm to about 8 nm in some embodiments. In some embodiments, an alloy layer, such as a silicide layer, is formed over the source / drain epitaxial layers 250.FIG. 11A is a perspective view, FIG. 11B is a sectional view along the y direction, and FIG. 11C is a sectional view along the x direction, and it shows one of a plurality of stages of manufacturing according to an embodiment of the present invention. Subsequently, a contact etch stop layer (CESL) 245 and an interlayer dielectric layer 260 are formed, and a planarization process such as CMP is performed to expose top surfaces of the dummy gate electrodes 230, as shown in FIGS. 11A to 11C.In some embodiments, the CESL layer 245 is made of a silicon nitride-based material, such as SiN and SiON, and the interlayer dielectric layer 260 is made of a silicon oxide-based material, such as SiO 2, or a low-k material. In some embodiments, an anneal is performed after the formation of the interlayer dielectric layer.FIG. 12A is a perspective view, FIG. 12B is a sectional view along the y direction, and FIG. 12C is a sectional view along the x direction, and show one of a plurality of stages of manufacturing according to an embodiment of the present invention. Then, the dummy gate electrodes 230 and the dummy gate dielectric layer 215 are removed by dry and / or wet etching to form gate spaces 265, as shown in FIGS. 12A to 12C. In the gate spaces 265, an intermediate layer 271 and a dielectric layer 270 are formed again, as shown in FIGS. 12A to 12C. As set forth above, the intermediate layer 271 is made of silicon oxide, and the dielectric layer 270 is a doped HfO 2- layer.FIG. 13A is a perspective view, FIG. 13B is a sectional view along the y direction, and FIG. 13C is a sectional view along the x direction, and show one of a plurality of stages of manufacturing according to an embodiment of the present invention. Then, similarly to the steps described with reference to FIGS. 2A to 2D, a capping layer (not shown) may be optionally formed, and an annealing process is performed to convert the amorphous HfO 2- layer into an orthorhombic HfO 2- layer. In addition, a gate electrode 280 is formed as shown in Figs. 13A to 13C. The capping layer and the gate electrode may be formed by a suitable method, such as ALD, CVD, PVD, or plating, or combinations thereof. After the gate electrode conductive materials are deposited, a planarization process, such as a CMP, is performed to remove excess materials over the interlayer dielectric layer 260.After the formation of the gate structures, further CMOS processes are performed to form various features, such as further interlayer dielectric layers, contacts / vias, metal interconnect layers, and passivation layers.FIGS. 14A to 14D show other manufacturing steps for an NC-FET according to some embodiments of the present invention. In all illustrations and illustrative embodiments, similar reference symbols are used to designate similar elements. It will be appreciated that additional steps may be provided before, during, and after the processes shown in FIGS. 14A-14D, and some of the steps described below may be replaced or omitted in additional embodiments of the method. The order of the steps / processes is interchangeable. Moreover, materials, configurations, dimensions, and / or processes similar or similar to those of the above embodiments described with reference to FIGS. 1A, 2A to 2D, and 7A to 13C may be used in the following embodiments, and their detailed explanation may be omitted.As shown in FIG. 14A, fin structures 320 are patterned using a hard mask pattern 312, and a dielectric isolation layer 325 is formed. Then, a dummy gate dielectric layer (not shown) and a polysilicon layer 332 are formed over the fin structures 320, and further, a hard mask pattern 334 is formed on the polysilicon layer 332, as shown in FIG. 14B. The hard mask pattern 334 includes one or more layers of an insulating material, such as silicon oxide and silicon nitride.Using the hard mask pattern 334 as an etch mask, the polysilicon layer 332 is patterned into a dummy gate electrode 332. Then, sidewall spacers 336 are formed on opposite side surfaces of the dummy gate electrode 332, and an interlayer dielectric layer 342 is formed as shown in FIG. 14C. The sidewall spacers 336 include one or more layers of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the interlayer dielectric layer 342 includes one or more layers of an insulating material such as a silicon oxide-based material such as silicon oxide (SiO 2) and SiON. The material for the sidewall spacers 336 and the material for the interlayer dielectric layer 342 are different from each other, so that these layers can be selectively etched. In an embodiment, sidewall spacer 336 is made of SiOCN, SiCN, or SiON, and interlayer dielectric layer 342 is made of SiO 2.Then, the dummy gate electrode 332 and the dummy gate dielectric layer 342 are removed by dry and / or wet etching, so that a gate gap 333 is formed, as shown in FIG. 14D.In the gate space 333, a first gate dielectric layer 303 and a first gate electrode 304 are formed as shown in FIGS. 15A and 15B. After a conductive material is deposited over the first gate dielectric layer 303, a planarization process, such as a CMP, is performed to form the first gate electrode 304. The first gate dielectric layer 303 is made of, for example, a high-k dielectric material, and the first gate electrode 304 is made of, for example, a conductive material such as TiN or another metallic material. Then, an etch back process is performed to reduce the height of the first gate dielectric layer 303 and the first gate electrode 304. The conductive material may be deposited by a suitable method, such as ALD, CVD, PVD, or plating, or combinations thereof.Then, a ferroelectric dielectric layer 305 and a second gate electrode 306 are formed in the gate space 333 as shown in Figs. 15C and 15D. The ferroelectric dielectric layer 305 is formed by the steps described with reference to Figs. 2A to 2D. A conductive material is deposited over the ferroelectric dielectric layer 303. After the conductive material is deposited over the ferroelectric dielectric layer 305, a planarization process such as CMP is performed to form the second gate electrode 306 as shown in FIGS. 15C and 15DAfter the formation of the gate structures, further CMOS processes are performed to form various features, such as further interlayer dielectric layers, contacts / vias, metal interconnect layers, passivation layers, etc.Other methods and structures for making MIMIS NC-FETs are described in U.S. Patent Application Serial Nos. 15 / 476,221 and 15 / 447,479, which are incorporated by reference.It should be appreciated that not necessarily all of the benefits have been discussed herein, no particular benefit is required for all embodiments or examples, and other embodiments or examples may provide other benefits.For example, in the present invention, doped HfO 2 having an orthorhombic crystal phase is used for an NC-FET. By using a metallic capping layer during an annealing process, an amorphous structure of the deposited HfO 2- layer can be effectively converted into an orthorhombic crystal structure. In contrast to other ferroelectric perovskite layers (such as PZT or BaTiO 3) the ferroelectric HfO 2 disclosed herein can maintain polarization without degradation up to 3 nm.

Claims

A method of manufacturing a negative capacitance structure comprising the steps of: forming a dielectric layer (30) over a substrate (10); forming a first metal layer (40) over the dielectric layer (30); after the first metal layer (40) is formed, performing an annealing step followed by a cooling step; forming a second metal layer (52) over the first metal layer (40), the second metal layer (52) being formed after the cooling step; and forming a work function adjustment layer (54) over the second metal layer (52), wherein after the cooling step, the dielectric layer (30) has become a ferroelectric dielectric layer (30) having an orthorhombic crystal phase, the dielectric layer (30) comprising HfO2 doped with Si in an amount of 2 to 6 mol %, wherein after forming the negative capacitance structure, the ferroelectric dielectric layer (30) further comprises Ti in an amount of 2 to 5 mol % and / or Al in an amount of 5 to 7 mol %.The method of claim 1, wherein the annealing step is performed at a temperature in the range of 700°C to 1000°C in an inert gas environment.Method according to one of the preceding claims, wherein the first metal layer (40) comprises TiN or TiN doped with Si.The method of any preceding claim, wherein the second metal layer is TaN.The method of any preceding claim, wherein the orthorhombic crystal phase is polycrystalline.The method according to any of the preceding claims, wherein the produced dielectric layer (30) is amorphous.A method of manufacturing a negative capacitance field effect transistor, comprising the steps of: forming a dielectric layer (30) over a channel layer (101); forming a metallic capping layer (40) over the dielectric layer; after the metallic capping layer (40) is formed, performing an annealing step followed by a cooling step; forming a barrier layer (52) over the capping layer (40), wherein the barrier layer (52) is formed after the cooling step; and forming a work function adjustment layer (54) over the barrier layer (52), wherein after the cooling step, the dielectric layer (30) has become a ferroelectric dielectric layer (30) having an orthorhombic crystal phase, the dielectric layer (30) comprising HfO2doped with Si in an amount of 2 to 6 mol %, wherein after forming the negative capacitance field effect transistor, the ferroelectric dielectric layer (30) further comprises Ti in an amount of 2 to 5 mol % and / or Al in an amount of 5 to 7 mol %.The method of claim 7, wherein the annealing step is performed at a temperature in a range of 700°C to 1000°C in an inert gas environment.The method of claim 7 or 8, wherein the metallic capping layer (40) comprises TiN or Si-doped TiN.The method of any one of claims 7 to 9, wherein the orthorhombic crystal phase is polycrystalline.The method of any of claims 7 to 10, wherein the barrier layer (52) is TaN.The method of any of claims 7 to 11, further comprising forming a metal gate layer (58) over the work function adjustment layer.The method of claim 12, further comprising forming an adhesive layer (56) over the work function adjustment layer prior to forming the metal gate layer.The method of any of claims 7 to 13, further comprising forming an intermediate oxide layer (103) over the channel layer (101) prior to forming the dielectric layer (30).A negative capacitance field effect transistor comprising: a channel layer made of a semiconductor; a ferroelectric dielectric layer (105, 115, 270, 305) disposed over the channel layer; and a gate electrode layer (106, 116, 280, 306) disposed over the ferroelectric dielectric layer (105, 115, 270, 305), the gate electrode layer comprising: a metallic capping layer disposed on the ferroelectric dielectric layer (105, 115, 270, 305); a barrier layer (52) disposed on the metallic capping layer; and a work function adjustment layer (54) disposed on the barrier layer (52), the ferroelectric dielectric layer (105, 115, 270, 305) having an orthorhombic crystal phase, the ferroelectric dielectric layer (105, 115, 270, 305) having HfO2 doped with Si in an amount of 2 to 6 mol %, the ferroelectric dielectric layer (30) further having Ti in an amount of 2 to 5 mol % and / or Al in an amount of 5 to 7 mol %.

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