MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE BY METAL-INTERMEDIATE DOTENATION FILM WITH DIFFUSION IN SOURCE / DRAIN AND ASSOCIATED SEMICONDUCTOR DEVICE

Abstract

Procedure, comprehensive: Etching a substrate (50) to form a first semiconductor strip (52); Forming a first dummy gate structure (70) over a first channel region of the first semiconductor strip (52), wherein the first dummy gate structure (70) is perpendicular to the first semiconductor strip (52); Etching a first depression (124, 226) in the first semiconductor strip (52) on a first side of the first dummy gate structure (70); Etching a second depression (124, 226) in the first semiconductor strip (52) on a second side of the first dummy gate structure (70); Formation of a first intermetal doping film (220) in the first well (124, 226) and the second well (124, 226); Diffusion of a first dopant of the first intermetal doping film (220) into the first semiconductor strip (52) near the first well (124, 226) and into the first semiconductor strip (52) near the second well (124, 226); epitaxial cultivation of a source / drain region (82) in the first well (124, 226); and epitaxial cultivation of a source / drain region (82) in the second well (124, 226), where: the epitaxial growth of the source / drain regions (82) in the first well (124, 226) and in the second well (124, 226) each comprises a first growth of a first layer (82A) of epitaxial material and a subsequent growth of a second layer (82B) of epitaxial material, the second layer (82B) has an upper width W4 at the top of the corresponding depression (124, 226), a middle width W5 at 50% of the depth of the second layer (82B) and a lower width W6 at 90% of the depth of the second layer (82B), and The middle width W5 is 80% to 90% of the upper width W4, and the lower width W6 is 2% to 61% wider than the upper width W4.

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by depositing insulating or dielectric layers, conductive layers, and semiconductor layers of various materials one after the other over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, reducing the minimum feature size creates additional problems that need to be addressed.

[0003] Methods for forming a doped region in a semiconductor device by means of diffusion from a doping film are known, for example, from US 2017 / 0 069 543 A1, US 2013 / 0 122 676 A1, US 2012 / 0 135 575 A1, US 2017 / 0 125 591 A1 and US 2016 / 0 087 104 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present invention are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of description. Fig. 1 is a perspective view of a fin field effect transistor ("FinFET") device according to some embodiments. The Fig. 2A to 26A, 26B, and 26C are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. The Fig. 27C, Fig. 28C and Fig. 29C are cross-sectional views of a FinFET device according to some embodiments. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0005] The present invention provides methods for manufacturing a semiconductor device having the features of claim 1 and 9, respectively, and a semiconductor device having the features of claim 17. Exemplary embodiments are specified in the dependent claims.

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0007] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to other element(s) or feature(s) as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0008] Embodiments are described with respect to a specific context, namely a FinFET device and a method of forming the same. Various embodiments described herein enable the formation of source / drain regions of a FinFET device such that the dopant concentration in a well interface of the source / drain region is increased to reduce sheet resistance and increase carrier mobility. Various embodiments presented herein are described in the context of FinFETs formed using a gate-last process. In further embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices, such as planar FETs.

[0009] Fig. 1 shows an example of a fin field-effect transistor (FinFET) 30 in a three-dimensional view. The FinFET 30 includes a fin 36 on a substrate 32. The substrate 32 has isolation regions 34, and the fin 36 protrudes above and lies between adjacent isolation regions 34. A gate dielectric 38 is disposed along sidewalls and above a top surface of the fin 36, and a gate electrode 40 is disposed above the gate dielectric 38. Source / drain regions 42 and 44 are disposed on opposite sides of the fin 36 with respect to the gate dielectric 38 and the gate electrode 40. Fig. 1 further shows reference cross-sections used in the subsequent figures. Cross-section AA passes through a channel, the gate dielectric 38, and the gate electrode 40 of the FinFET 30. Cross-section CC lies in a plane parallel to cross-section AA and arranged outside the channel through the fin 36. Cross-section BB is perpendicular to cross-section AA and lies along a longitudinal axis of the fin 36 and in the direction, for example, of a current flow between the source / drain regions 42 and 44. The subsequent figures refer to these reference cross-sections for clarity.

[0010] The Fig. 2A to 26A-C are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 2A to 26A-C are figures ending with an “A” label, along the Fig. 1, except that there are multiple FinFETs and multiple fins per FinFET; figures ending with a “B” label are along the Fig. 1 shown reference cross-section BB; and figures ending with a “C” label are shown along the Fig. 1. In some cases, cross-sectional views are omitted in certain steps, for example, when the omitted cross-section is not specifically described.

[0011] Fig. 2A shows a substrate 50. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulator layer. The insulator layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor, for example, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, for example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0012] Substrate 50 may further include integrated circuit devices (not shown). As one of ordinary skill in the art will appreciate, a wide variety of integrated circuit devices, such as transistors, diodes, capacitors, resistors, or the like, or combinations thereof, may be formed in and / or on substrate 50 to meet the structural and / or functional design requirements for the resulting FinFETs. The integrated circuit devices may be formed using any suitable method.

[0013] In some embodiments, the substrate 50 may include a first region 100A and a second region 100B. The first region 100A may be used to form n-type devices, such as n-type metal oxide semiconductor (NMOS) transistors, such as n-type FinFETs. The second region 100B may be used to form p-type devices, such as p-type metal oxide semiconductor (PMOS) transistors, such as p-type FinFETs. Accordingly, the first region 100A may also be referred to as NMOS region 100A, and the second region 100B may also be referred to as PMOS region 100B.

[0014] Fig. 2A further illustrates the formation of a mask 53 over the substrate 50. In some embodiments, the mask 53 may be used in a subsequent etching step to pattern the substrate 50 (see Fig. 3A). As in Fig. 2A, the mask 53 may include a first mask layer 53A and a second mask layer 53B. The first mask layer 53A may be a hard mask layer. In some embodiments, the first mask layer 53A may include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a combination thereof, or the like, and may be formed using any suitable method, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), a combination thereof, or the like. The first mask layer 53A may be used to prevent or minimize etching of the substrate 50 underlying the first mask layer 53A in the subsequent etching step (see Fig. 3A). The second mask layer 53B may comprise a photoresist and, in some embodiments, may be used to pattern the first mask layer 53A for use in the subsequent etching step described above. The second mask layer 53B may be formed using a spin-coating technique and may be patterned using suitable photolithography techniques. In some embodiments, the mask 53 may comprise three or more mask layers.

[0015] Fig. 3A shows the formation of semiconductor stripes 52 in the substrate 50. First, the mask layers 53A and 53B may be patterned, wherein openings in the mask layers 53A and 53B expose regions of the substrate 50 where trenches 55 are formed. Next, an etching process is performed, wherein the etching process creates the trenches 55 in the substrate 50 through the openings in the mask 53. The remaining portions of the substrate 50 underlying a patterned mask 53 form a plurality of semiconductor stripes 52. The etching may be any suitable etching process, such as a reactive ion etch (RIE), a neutral beam etch (NBE), the like, or a combination thereof. The etching process may be anisotropic. In some embodiments, the semiconductor stripes 52 may have a height H o between about 50 nm and about 60 nm and a width W o between about 6 nm and about 8 nm.

[0016] Fig. 4A shows the formation of an insulating material in the trenches 55 (see Fig. 3A) between adjacent semiconductor strips 52 to form isolation regions 54. The isolation material may be an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it to another material, such as an oxide), the like, or a combination thereof. Other isolation materials formed by any suitable methods may also be used.

[0017] Furthermore, in some embodiments, the isolation regions 54 may include a liner (not shown) that is attached to sidewalls and a bottom surface of the trenches 55 (see Fig. 3A) is formed before the trenches 55 are filled with an insulating material of the isolation regions 54. In some embodiments, the liner may comprise a semiconductor nitride (e.g., a silicon nitride), a semiconductor oxide (e.g., a silicon oxide), a thermal semiconductor oxide (e.g., a thermal silicon oxide), a semiconductor oxynitride (e.g., a silicon oxynitride), a polymer dielectric, combinations thereof, and the like. Forming the liner may comprise any suitable method, for example, ALD, CVD, HDP-CVD, PVD, a combination thereof, or the like.In some embodiments, forming the liner may result in a conformally deposited layer having horizontal portions and vertical (or non-horizontal) portions that have substantially the same thickness, for example, where the vertical thickness of the vertical portions of the liner and the horizontal thickness of the horizontal portions of the liner have a difference of less than 20 percent. In such embodiments, the liner may prevent (or at least reduce) the diffusion of semiconductor material from the semiconductor stripes 52 (e.g., Si and / or Ge) into the surrounding isolation regions 54 during subsequent annealing of the isolation regions 54. For example, after the isolation material of the isolation regions 54 has been deposited, an annealing process may be applied to the isolation material of the isolation regions 54.

[0018] Further referring to Fig. 4A, a planarization process, such as chemical mechanical polishing (CMP), may remove any excess insulation material of the isolation regions 54 such that the top surfaces of the isolation regions 54 and the top surfaces of the semiconductor stripes 52 are coplanar (within process variances). In some embodiments, the CMP may also remove the mask 53. In further embodiments, the mask 53 may be removed using a wet cleaning process separately from the CMP.

[0019] Fig. 5A illustrates the deepening of isolation regions 54 to form shallow trench isolation (STI) regions 54. Isolation regions 54 are deepened such that fins 56 protrude between adjacent isolation regions 54 in first region 100A and second region 100B. Furthermore, the upper surfaces of isolation regions 54 may have a flat surface as shown, a convex surface, a concave surface (such as concaves), or a combination thereof. The upper surfaces of isolation regions 54 may be formed flat, convex, and / or concave by a suitable etch. Isolation regions 54 may be deepened using a suitable etching process that is, for example, selective to the material of isolation regions 54. For example, chemical removal of the oxide can be used using a CERTAS® etch or a SICONI tool from Applied Materials or dilute hydrofluoric (dHF) acid.

[0020] This in relation to the Fig. The method described in Figures 2A to 5A is only one example of how the fins 56 may be formed. In further embodiments, a dielectric layer may be formed over a top surface of the substrate 50; trenches may be etched through the dielectric layer; homoepitaxial structures may be grown epitaxially in the trenches; and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. In still further embodiments, heteroepitaxial structures may be used for the fins. For example, the semiconductor stripes 52 may be Fig. 4, and a material different from the semiconductor stripes 52 may be epitaxially grown in their place. In yet another embodiment, a dielectric layer may be formed over a top surface of the substrate 50; trenches may be etched through the dielectric layer; heteroepitaxial structures may be epitaxially grown in the trenches using a material different from the substrate 50; and the dielectric layer may be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins 56. In some embodiments where homoepitaxial or heteroepitaxial structures are grown epitaxially, the grown materials may be doped in situ during growth.In further embodiments, homoepitaxial or heteroepitaxial structures may be doped, for example, using ion implantation after the homoepitaxial or heteroepitaxial structures have been epitaxially grown. Even further, it may be advantageous to epitaxially grow a material in the NMOS region 100A that is different from the material in the PMOS region 100B. In various embodiments, the fins 56 may comprise silicon germanium (Si). x Ge 1-x , where x can be between about 0 and 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, available materials for forming III-V compound semiconductors include, without limitation, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0021] In the Fig. 6A and Fig. 6B, a dummy dielectric layer 58 is formed on the fins 56. The dummy dielectric layer 58 may be made of, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown (for example, using thermal oxidation or the like) according to suitable techniques. A dummy gate layer 60 is formed over the dummy dielectric layer 58, and a mask 62 is formed over the dummy gate layer 60. In some embodiments, the dummy gate layer 60 may be deposited over the dummy dielectric layer 58 and then planarized, for example, using a CMP process. The mask 62 may be deposited over the dummy gate layer 60.The dummy gate layer 60 may, for example, be made of polysilicon, although other materials having high etch selectivity with respect to the material of the isolation regions 54 may also be used. The mask 62 may comprise one or more layers, for example, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof. In one embodiment, the mask 62 comprises a first mask layer 62A made of silicon nitride and a second mask layer 62B made of silicon oxide. In some embodiments, the first mask layer 62A may have a thickness between about 18 nm and about 22 nm, and the second mask layer 62B may have a thickness between about 50 nm and about 90 nm. In some embodiments, the dummy dielectric layer 58 may have a thickness between about 11 nm and about 15 nm, and the dummy gate layer 60 may have a thickness between about 50 nm and about 80 nm.In some embodiments, the dummy dielectric layer 58 may be omitted.

[0022] Referring to the Fig. 6A and Fig. 6B, in the embodiment shown, a single dummy dielectric layer 58, a single dummy gate layer 60, and a single mask 62 are formed over the first region 100A and the second region 100B. In further embodiments, separate dummy dielectric layers, separate dummy gate layers, and separate masks may be formed in the first region 100A and the second region 100B.

[0023] Referring to the Fig. 6A and Fig. 6B, suitable doped wells (not shown) may be formed in the fins 56, the semiconductor stripes 52, and / or the substrate 50. Recesses may be formed before or after the dummy gates 70 and 76 (hereinafter referred to as Fig. 7A, Fig. 7B and Fig. 7C). In embodiments where wells are formed prior to forming the dummy gates 70 and 76, the wells may, for example, be formed prior to forming the dummy dielectric layer 58. For example, a p-well may be formed in the first region 100A and an n-well may be formed in the second region 100B. The various implantation steps for the various regions 100A and 100B may be performed using a photoresist or further masks (not shown). For example, a photoresist is formed over the fins 56 and the isolation regions 54 in the first region 100A and the second region 100B. The photoresist is patterned to expose the second region 100B of the substrate 50, such as a PMOS region, while protecting the first region 100A, such as an NMOS region.The photoresist may be formed using a spin-coating technique and may be patterned using suitable photolithography techniques. Once the photoresist is patterned, n-type impurities are implanted into the second region 100B, and the photoresist may serve as a mask to substantially prevent n-type impurities from being implanted into the first region 100A. The n-type impurities may be phosphorus, arsenic, or the like and may be deposited in the second region 100B to a concentration of 10. 18 cm -3 or less, such as in a range of about 10 17 cm -3 up to about 10 18 cm -3 , implanted. After the implantation process, the photoresist is removed using, for example, a suitable ashing process followed by a wet cleaning process.

[0024] After implanting the second region 100B, a second photoresist (not shown) is formed over the fins 56 and the isolation regions 54 in the first region 100A and the second region 100B. The second photoresist is patterned to expose the first region 100A of the substrate 50 while protecting the second region 100B. The second photoresist may be formed using a spin-coating technique and patterned using suitable photolithography techniques. Once the second photoresist is patterned, p-type impurities are implanted into the first region 100A, and the second photoresist may serve as a mask to substantially prevent p-type impurities from being implanted into the second region 100B. The p-type impurities may be boron, BF2, or the like and may be concentrated in the first region 100A to a concentration of 10 18 cm -3or less, such as in a range of about 10 17 cm -3 up to about 10 18 cm -3 implanted. After the implantation process, the second photoresist is removed, for example, using a suitable ashing process followed by a wet cleaning process.

[0025] After implanting suitable impurities into the first region 100A and the second region 100B, an anneal may be performed to activate the implanted p- and n-type impurities. The implantation process may form a p-well in the first region 100A and an n-well in the second region 100B. In some embodiments where the fins are epitaxially grown, the grown materials of the fins 56 may be doped in situ during the growth process.

[0026] In the Fig. 7A, Fig. 7B and Fig. 7C, the mask 62 (see the Fig. 6A and Fig. 6B) using suitable photolithography and etching techniques to form a mask 72 in the first region 100A and a mask 78 in the second region 100B. The pattern of the masks 72 and 78 can then be transferred to the dummy gate layer 60 using a suitable etching technique to form dummy gates 70 in the first region 100A and dummy gates 76 in the second region 100B. Optionally, the pattern of the masks 72 and 78 can be transferred to the dummy dielectric layer 58 in a similar manner. The pattern of the dummy gates 70 and 76 covers corresponding channel regions of the fins 56 while exposing the source / drain regions of the fins 56. The dummy gates 70 and 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective fins 56.A size of the dummy gates 70 and 76 and a pitch between the dummy gates 70 and 76 may depend on a region of a die in which the dummy gates are formed. In some embodiments, the dummy gates 70 and 76 may be larger and have a larger pitch when located in an input / output region of a die (where, for example, input / output circuitry is disposed) than when located in a logic region of a die (where, for example, logic circuitry is disposed). In some embodiments, the dummy gates 70 may have a height between about 135 nm and about 175 nm, and the dummy gates 76 may have a width between about 15 nm and about 27 nm.

[0027] In the Fig. 8A, Fig. 8B and Fig. 8C, a gate spacer layer 80 is formed on exposed surfaces of the dummy gates 70 and 76 (see the Fig. 8A and Fig. 8B) and / or the dummy dielectric layer 58 over the fins 56 (see Fig. 8C). Any suitable methods for forming the gate spacer layer 80 may be used. In some embodiments, deposition (such as CVD, ALD, or the like) may be used to form the gate spacer layer 80. In some embodiments, the gate spacer layer 80 may comprise one or more layers, for example, silicon nitride (SiN), silicon oxynitride, silicon carbonitride, silicon oxycarbonitride (SiOCN), a combination thereof, or the like. In some embodiments, the gate spacer layer 80 may comprise a first gate spacer layer 80A, a second gate spacer layer 80B over the first gate spacer layer 80A, and a third gate spacer layer 80C over the second gate spacer layer 80B.In one embodiment, the first gate spacer layer 80A comprises SiOCN, the second gate spacer layer 80B comprises SiOCN, and the third gate spacer layer 80C comprises SiN. In some embodiments, the first gate spacer layer 80A has a thickness between about 3 nm and about 5 nm, the second gate spacer layer 80B has a thickness between about 3 nm and about 5 nm, and the third gate spacer layer 80C has a thickness between about 4 nm and about 6 nm.

[0028] With further reference to the Fig. 8A, Fig. 8B and Fig. 8C, after forming the first spacer layer 80A, lightly doped source / drain (LDD) regions 75 and 79 may be formed in the substrate 50 in the first region 100A and the second region 100B, respectively. Similar to the implantation process described above with reference to the Fig. 7A, Fig. 7B and Fig. 7C, a mask (not shown), such as a photoresist, may be formed over the first region 100A, e.g., the NMOS region, while the second region 100B, e.g., the PMOS region, is exposed, and p-type impurities may be implanted into the exposed fins 56 in the second region 100B to form the LDD regions 79. During the implantation of the LDD regions 79, the dummy gate 76 may act as a mask to prevent dopants from being implanted into a channel region of the exposed fins 56 (or at least reduce them). Thus, the LDD regions 79 may be formed substantially in source / drain regions of the exposed fins 56. The mask may then be removed.Subsequently, a mask (not shown), such as a photoresist, may be formed over the second region 100B while the first region 100A is exposed, and n-type impurities may be implanted into the exposed fins 56 in the first region 100A to form the LDD regions 75. During the implantation of the LDD regions 75, the dummy gate 70 may act as a mask to prevent dopants from being implanted into a channel region of the exposed fins 56 (or at least to reduce them). Thus, the LDD regions 75 may be substantially formed in source / drain regions of the exposed fins 56. The second mask may then be removed. The n-type impurities may be any of the n-type impurities described above, and the p-type impurities may be any of the p-type impurities described above. The LDD regions 75 and 79 can each have an impurity concentration of about 10. 15 cm -3up to about 10 16 cm -3 An annealing process can be performed to activate the implanted impurities.

[0029] Referring to the Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B and Fig. 10C, a patterning process is performed to remove excess portions of the spacer layer 80 in the first region 100A. Any suitable patterning process may be used. Referring first to the Fig. 9A, Fig. 9B and Fig. 9C, in some embodiments, a three-layer mask 120 is formed over the first region 100A and the second region 100B. The three-layer mask 120 includes a bottom layer 120A, a middle layer 120B over the bottom layer 120A, and a top layer 120C over the middle layer 120B. In some embodiments, the bottom layer 120A may comprise an organic material, such as a spin-on carbon (SOC) material or the like, and may be formed using spin-on coating, CVD, ALD, or the like. The middle layer 120B may comprise an inorganic material, which may be a nitride (such as SiN, TiN, TaN, or the like), an oxynitride (such as SiON), an oxide (such as silicon oxide), or the like, and may be formed using CVD, ALD, or the like.The upper layer 120C may comprise an organic material such as a photoresist material and may be formed using spin coating or the like. In some embodiments, the upper layer 120C of the three-layer mask 120 is patterned to expose the first region 100A. The upper layer 120C may be patterned using suitable photolithography techniques.

[0030] Referring to the Fig. 10A, Fig. 10B and Fig. 10C, an etching process is performed using the patterned three-layer mask 120 as a mask. The etching process may be anisotropic. After performing the etching process, lateral portions of the first spacer layer 80A, the second spacer layer 80B, and the third spacer layer 80C above the LDD regions 75 and in the isolation regions 54 may be removed to expose upper surfaces of the fins 56 and the masks 72 for the dummy gate stacks 70. Portions of the first spacer layer 80A, the second spacer layer 80B, and the third spacer layer 80C along sidewalls of the dummy gates 70 and the fins 56 may remain and form spacers 122. In further embodiments, the spacer layer 80 may also be removed from the sidewalls of the fins 56.After patterning the spacer layer 80, the three-layer mask 120 may be removed using any suitable removal method.

[0031] The Fig. 11B to 21C show the formation of epitaxial source / drain regions 82 and 84 in the first region 100A and the second region 100B. In some embodiments, the epitaxial source / drain regions 82 (see the Fig. 21B and Fig. 21C) in the first region 100A before the epitaxial source / drain regions 84 (see the Fig. 21B and Fig. 21C) may be formed in the second region 100B. In further embodiments, the epitaxial source / drain regions 84 may be formed in the second region 100B prior to forming the epitaxial source / drain regions 82 in the first region 100A.

[0032] The Fig. 11B to 14C illustrate the formation of the epitaxial source / drain regions 82 in the first region 100A. During the formation of the epitaxial source / drain regions in the first region 100A, e.g., the NMOS region, the second region 100B, e.g., the PMOS region, may be masked (not shown).

[0033] Referring to the Fig. 11B and Fig. 11C, a first patterning process is performed on the fins 56 to form recesses 124 in the source / drain regions of the fins 56. The first patterning process may be performed such that the recesses 124 are formed between adjacent dummy gates 70 (in inner regions of the fins 56, see, for example, FIG. 13D) or between an isolation region 54 and the adjacent dummy gate 70 (in end regions of the fins 56, for example, as in the Fig. 11B). In some embodiments, the first patterning process may comprise a suitable anisotropic dry etching process while using the dummy gates 70, the spacers 122, and / or the isolation regions 54 as a combined mask. The suitable anisotropic dry etching process may comprise reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. In some embodiments where RIE is used in the first patterning process, process parameters such as a process gas mixture, a bias voltage, and an RF power may be selected such that the etching is performed predominantly using physical etching, such as ion bombardment, rather than chemical etching, such as radical etching through chemical reactions.In some embodiments, a bias voltage may be increased to increase the energy of ions used in the ion bombardment process and thus increase the physical etching rate. Since physical etching is anisotropic in nature and chemical etching is isotropic in nature, such an etching process has an etching rate in the vertical direction that is greater than an etching rate in the lateral direction. In some embodiments, the anisotropic etching process may be performed using a process gas mixture comprising CH3F, CH4, HBr, O2, Ar, a combination thereof, or the like.

[0034] In some embodiments, the first patterning process forms recesses 124 with U-shaped bottom surfaces. The recesses 124 may also be referred to as U-shaped recesses 124. In some embodiments, the U-shaped recesses 124 have a depth D1, measured from a top surface of the fins 56, between about 45 nm and about 65 nm. As a result of the first patterning process, the recesses 124 may have rough surfaces. In some embodiments, the etching process for forming the U-shaped recesses 124 may also etch a top surface of the isolation regions 54. The shape and profile of the U-shaped recesses 124 are described further below with respect to Fig. 13D following a thermal diffusion process.

[0035] The Fig. 12B and Fig. 12C illustrate the formation of an intermetal dopant film and the thermal diffusion of dopants into the fin 56 and the semiconductor stripes 52. A first intermetal dopant film 220 is formed over the device in the first region 100A and the second region 100B. The first intermetal dopant film 220 may also be referred to as a first dopant film 220. The first dopant film 220 may comprise a doped silicate glass. The dopant used may comprise any suitable n-type Group V impurity, for example, any of those previously described, such as phosphorus, arsenic, antimony, or bismuth, and so on, or combinations thereof. The first doping film 220 may be deposited by any suitable method such as ALD, CVD, plasma enhanced CVD (PECVD), etc. (shown by arrows 221) to form a thin film over the dummy gates 70 and 76 and in the U-shaped recesses 124.

[0036] A dopant concentration in the first doping film 220 can be adjusted by varying the ratio of gases in the process environment, such as a deposition chamber. For example, when phosphorus is used to produce phosphosilicate glass (PSG), process gases can include tetraethylorthosilicate (TEOS) or silane SiH4 as the source of the silicate and PH3 or POCl3 as the source of phosphorus and other process gases (such as oxygen, nitrogen, hydrogen, or argon). The ratio of the phosphorus dopant source can be adjusted to incorporate more or less phosphorus into the formed PSG. For example, a ratio of PH3 to SiH4 can be about 15% to about 45%. A ratio of the process gases can be adjusted similarly for other dopants. In some embodiments, the resulting dopant concentration in the first doping film 220 can be between about 3.5 × 10 19 cm -3 up to about 8.5 × 1019 cm -3 In some embodiments, the first doping film 220 may be deposited to a thickness between about 0.8 nm and about 2 nm. In further embodiments, the first doping film 220 may be deposited to a thickness of less than about 0.8 nm or more than about 2 nm.

[0037] Still referring to the Fig. 12B and Fig. 12C, after forming the first doping film 220, a thermal diffusion process (shown by arrows 223) may be performed to diffuse the dopant of the first doping film 220 into the fins 56 and semiconductor stripes 52 surrounding the recesses 224. The thermal diffusion process 223 may include any suitable thermal diffusion process, such as rapid thermal annealing (RTA), microwave annealing, furnace annealing, and the like. For example, an RTA may be performed at a temperature of between about 900°C to about 1000°C for about 3 to 6 seconds, for example, about 5 seconds.

[0038] In some embodiments, a mask (not shown) may be formed over the second region 100B to substantially prevent dopant from the first doping film 220 from diffusing into structures of the second region 100B. In some embodiments, one or more layers of the gate spacer layer 80 may serve to prevent dopant from diffusing into underlying structures of the second region 100B. A conformal liner (not shown, see the description in connection with Fig. 4A above) may be formed between the isolation region 54 and the semiconductor stripes 52 to act as a diffusion barrier to prevent diffusion of dopant from the first doping layer 220 into the isolation regions 54.

[0039] The diffusion of dopant from the first doping layer 220 into the surrounding fin 56 and the semiconductor stripes 52 provides an increased doping concentration to reduce the sheet resistance and improve the carrier mobility into the source / drain region of the device formed in the first region 100A. The concentration of the dopant in the dopant diffusion region 227 of the surrounding fin 56 and the semiconductor stripes 52 is higher than the concentration of the same dopant outside the dopant diffusion region 227, for example, in an outer diffusion region surrounding and adjacent to at least a portion of the dopant diffusion region 227 in the surrounding fin 56 and the semiconductor stripes 52. The concentration of the dopant diffused through the first doping layer 220 in the dopant diffusion region 227 (see the Fig. 13B, Fig. 13C and Fig. 13D) (such as an n-impurity), can be between about 1.2 × 10 19 cm -3 up to about 6.2 × 10 19 cm -3 The resulting carrier mobility can be between about 15 cm 2 / Vs up to about 35 cm 2 / Vs. The sheet resistance can be between about 200 Ω-cm and about 1200 Ω-cm.

[0040] Referring to the Fig. 13B, Fig. 13C and Fig. 13D, after the thermal diffusion process 223, the first dopant film 220 is removed by any suitable method, for example, by wet etching. The first dopant diffusion region 227 is formed in the fins 56 and the semiconductor stripes 52.

[0041] Fig. 13D shows an enlarged view of a part of Fig. 13B to show details of the dimensions of the opening 226 after doping by the intermetal dopant film. Fig. 13D shows the opening 226 arranged between two adjacent dummy gates 70. In some embodiments, the depth D3 of the dopant diffusion region 227 may be about 3 nm to about 18 nm. The depth D1, measured from a top surface of the fins 56, may be between about 45 nm and about 65 nm. The surfaces 228 of the opening 226, including along the sides and bottom of the opening 226, are smoothed by the intermetal dopant film process. A width W1 of the opening 226 is measured at the top of the opening. A width W2 of the opening 226 is measured at 50% of the depth (at the center) of the opening. A width W3 of the opening 226 is measured at 90% of the depth (90% from the top) of the opening. In some embodiments, a ratio of widths W1:W2 may be about 1.00:1.13-1.22; a ratio of widths W1:W3 may be about 1.00:1.01-1.52; and a ratio of widths W2:W3 may be about 1.13-1.22:1.01-1.52.In other words, the middle width W2 can be about 13 to 22 percent wider than the top width W1 and the bottom 90% width W3 can be about 1 to about 52 percent wider than the top width W1.

[0042] The dopant diffusion region 227 results in an increased dopant concentration in the semiconductor fins 56 and the semiconductor stripes 52, providing increased carrier mobility. In some embodiments, the dopant diffusion region 227 comprises a portion of the channel region beneath the dummy gate 60. In other words, in some embodiments, the dummy gate 60 is vertically aligned with a portion of the dopant diffusion region 227.

[0043] The smooth surfaces 228 of the opening 226 are advantageous for growing an epitaxial material therein, as described in more detail below. The smooth surfaces 228 result in an epitaxial structure of the source / drain regions with a correspondingly smooth surface and a greater height and width than the epitaxial structure of the source / drain regions would have without the thermal diffusion doping process.

[0044] The Fig. 14B, Fig. 14C and Fig. 14D show the formation of the epitaxial source / drain regions 82 in the first region 100A. In some embodiments, the epitaxial source / drain regions 82 are epitaxially grown in the doped U-shaped recesses 226 (see the Fig. 13B and Fig. 13C) using metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), vapor-phase epitaxy (VPE), selective epitaxial growth (SEG), a combination thereof, or the like. The epitaxial source / drain regions 82 may comprise any suitable material, such as any material suitable for n-type FinFETs. For example, if the fin 56 is made of silicon, the epitaxial source / drain regions 82 may comprise silicon, SiC, SiCP, SiP, or the like. The epitaxial source / drain regions 82 may have surfaces raised from respective surfaces of the fins 56 and may have facets. The epitaxial source / drain regions 82 are formed in the fins 56 such that each dummy gate 70 is disposed between a corresponding adjacent pair of the epitaxial source / drain regions 82.In some embodiments, the epitaxial source / drain regions 82 may extend beyond the fins 56 and into the semiconductor stripes 52, as shown in FIG. Fig. 14B is shown.

[0045] The material of the epitaxial source / drain regions 82 in the first region 100A may be implanted with dopants, similar to the previously described method for forming the LDD regions 75, followed by annealing (see the Fig. 8A, Fig. 8B and Fig. 8C and its associated description). The epitaxial source / drain regions 82 may have an impurity concentration in a range of about 10 19 cm -3 up to about 10 21 cm -3The n-type impurities for the source / drain regions in the first region 100A, e.g., the NMOS region, may be any of the previously described n-type impurities. In further embodiments, the material of the epitaxial source / drain regions 82 may be doped in situ during growth. In the embodiments shown, each of the source / drain regions 82 is spatially separated from other source / drain regions 82. In further embodiments, two or more adjacent source / drain regions 82 may be combined. Examples of such embodiments are shown in the Fig. 27C and Fig. 31C, two or three adjacent source / drain regions 82 are combined to form a common source / drain region. In some embodiments, more than two or three adjacent source / drain regions 82 may be combined.

[0046] Due to the film doping of the U-shaped depression 226 (see the Fig. 13B, Fig. 13C and Fig. 13D), which provides a smooth sidewall profile of the recess, the epitaxial source / drain regions 82 can be formed in a more uniform manner and produce a larger volume than would otherwise be produced without the film doping.

[0047] Fig. Figure 14D shows an enlarged portion of the cross-section shown in Fig. 14B. The epitaxial source / drain regions 82 may include one or more layers 82A and 82B. Layer 82A is a first set of one or more layers of the epitaxial source / drain regions 82. Layer 82B is a second set of one or more layers of the epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may be formed from a single continuous layer. The first layer 82A may be formed using methods and materials as described above with respect to Fig. 14B. The second layer 82B may also be formed using methods and materials as described above with respect to Fig. 14B. The first layer 82A provides a first growth of epitaxial material in the epitaxial source / drain regions 82. The second layer 82B provides a subsequent growth of epitaxial material in the epitaxial source / drain regions 82. The first layer 82A may have a first lattice constant. The second layer 82B may have a second lattice constant. In some embodiments, the first lattice constant is equal to the second lattice constant. In some embodiments, the first lattice constant is different from the second lattice constant.

[0048] In some embodiments, the depth D6 of the epitaxial source / drain 82, measured from the top surface of the fin 56, may be about 45 nm to about 65 nm. The depth D5 from a top point of the epitaxial source / drain material 82 to the top surface of the fin 56 may be about 0.5 nm to about 3.0 nm. The depth D4 from the top surface of the fin 56 to a bottom interface of the second layer 82B may be about 30 nm to about 50 nm. A width W4 of the second layer 82b of the epitaxial source / drain material is measured at the top of the opening. A width W5 of the second layer 82b of the epitaxial source / drain material is measured at 50% of the depth (the center) of the second layer 82B. A width W6 of the second layer 82b of the epitaxial source / drain material is measured at 90% of the depth (90% from the top) of the second layer 82B.In some embodiments, a ratio of widths W4:W5 may be about 1.00:0.8-0.9; a ratio of widths W4:W6 may be about 1.00:1.02-1.61; and a ratio of widths W5:W6 may be about 0.8-0.9:1.02-1.61. In other words, the middle width W5 may be about 80% to about 90% of the top width W4, and the bottom 90% width W6 may be about 2% to about 61% wider than the top width W4.

[0049] Referring to the Fig. 13D and the widths and ratios described in Fig. 14D, a ratio relationship between the opening 226 and the second layer 82B of epitaxial source / drain material may be described. A ratio of the upper width W1 of the opening 226 to the upper width W4 of the second layer 82B (W1:W4) may be about 1.14 to about 1.19:1. A ratio of the middle width W2 of the opening 226 to the upper width W5 of the second layer 82B (W2:W5) may be about 1.52 to about 1.61. A ratio of the bottom 90% width W3 of the opening 226 to the upper width W6 of the second layer 82B (W3:W6) may be about 1.02 to about 1.21. These ratios are examples of possible ratios in some embodiments. Other dimensions and ratios may be used.

[0050] Referring to the Fig. 15A, Fig. 15B, Fig. 15C, Fig. 16A, Fig. 16B and Fig. 16C, a patterning process is performed to remove excess portions of the spacer layer 80 in the second region 100B. Any suitable patterning process may be used.

[0051] Referring first to the Fig. 15A, Fig. 15B and Fig. 15C, in some embodiments, a three-layer mask 121 is formed over the first region 100A and the second region 100B. The three-layer mask 121 includes a lower layer 121A, a middle layer 121B over the lower layer 121A, and an upper layer 121C over the middle layer 121B. The three-layer mask 121 may be formed using methods and materials as described above with reference to the Fig. 9A, Fig. 9B and Fig. 9C, which will not be repeated. In some embodiments, the upper layer 121C of the three-layer mask 121 is patterned to expose the second region 100B. The upper layer 121C may be patterned using suitable photolithography techniques.

[0052] In some embodiments, a mask layer 230 may be formed over the first region 100A to protect the first region while the second region 100B is processed. Any suitable methods for forming the mask layer 230 may be used. In some embodiments, deposition (such as CVD, ALD, or the like) or spin coating may be used to form the mask layer 230. In some embodiments, the mask layer 230 may comprise one or more layers of, for example, a nitride (such as SiN, TiN, TaN, or the like), an oxynitride (such as SiON), a carbonitride (such as SiOCN), spin-on carbon, a combination thereof, or the like. Although prior to forming the three-layer mask 121 of the Fig. 15A, Fig. 15B and Fig. 15C, in some embodiments, the mask layer 230 may be formed after removing the three-layer mask 121.

[0053] Referring to the Fig. 16A, Fig. 16B and Fig. 16C, an etching process is performed using the patterned three-layer mask 121 as a mask. The etching process may be anisotropic. After performing the etching process, lateral portions of the first spacer layer 80A, the second spacer layer 80B, and the third spacer layer 80C above the LDD regions 75 and above the isolation regions 54 may be removed, exposing upper surfaces of the fins 56 and the masks 78 for the dummy gate stacks 76. Portions of the first spacer layer 80A, the second spacer layer 80B, and the third spacer layer 80C remain along the sidewalls of the dummy gate 78 and the fins 56, forming spacers 122. In further embodiments, the spacer layer 80 may also be removed from the sidewalls of the fins 56.After patterning the spacer layer 80, the three-layer mask 121 may be removed using any suitable removal method.

[0054] The Fig. 17B to 21C illustrate the formation of the epitaxial source / drain regions 84 in the second region 100B. During the formation of the epitaxial source / drain regions 84 in the second region 100B, e.g., the PMOS region, the first region 100A, e.g., the NMOS region, may be masked by the mask layer 230 or another type of mask.

[0055] Referring to the Fig. 17B and Fig. 17C, a second patterning process is performed on the fins 56 to form recesses 125 in source / drain regions of the fins 56. The recesses 125 in the second region 100B may be formed using similar methods and materials as the U-shaped recesses 124 in the first region 100A, as described above with reference to FIGS. Fig. 11B and Fig. 11C, and the description is not repeated.

[0056] In some embodiments, the second patterning process forms recesses 125 with U-shaped bottom surfaces in the second region 100B. The recesses 125 may also be referred to as U-shaped recesses 125. In some embodiments, the U-shaped recesses 125 have a depth D1, measured from a top surface of the fins 56, between about 45 nm and about 65 nm. As a result of the first patterning process, the recesses 125 may have rough surfaces. In some embodiments, the etching process for forming the U-shaped recesses 125 may also etch a top surface of the isolation regions 54.

[0057] The Fig. 18B and Fig. 18C illustrate the formation of a second intermetal dopant film and the thermal diffusion of dopants into the fin 56 and the semiconductor stripes 52. A second intermetal dopant film 240 is formed over the device in the first region 100A and the second region 100B. The second intermetal dopant film 240 may also be referred to as a second dopant film 240. The second dopant film 240 may comprise a doped silicate glass. The dopant used may comprise any suitable p-type Group III impurity, such as any of those previously described, for example, boron, aluminum, gallium, or indium, and so on, or combinations thereof. The second doping film 240 may be deposited by any suitable method such as CVD, spin coating, PECVD, etc. (shown by arrows 241) to form a thin layer over the dummy gates 70 and 76 and in the U-shaped recesses 125.

[0058] A concentration of the dopant in the second doping film 240 can be adjusted by varying the ratio of gases in the process environment. For example, when boron is used to produce borosilicate glass (BSG), the process gases can include silane SiH4 as the source of the silicate and B2H6 as the source of the boron. The ratio of the boron dopant source can be adjusted to incorporate more or less boron into the formed BSG. For example, a ratio of B2H6 to SiH4 can be about 15% to about 45%. A ratio of the process gases can be adjusted similarly for other dopants. In some embodiments, the resulting dopant concentration in the second doping film 240 can be between about 2.5 × 10 18 cm -3 up to about 7.5 × 10 18 cm -3In some embodiments, the thickness of the second doping film 240 may be between about 0.8 nm and about 2 nm. In some embodiments, the thickness of the second doping film 240 may be less than about 0.8 nm or thicker than about 2 nm.

[0059] Still referring to the Fig. 18B and Fig. 18C, after forming the second doping film 240, a thermal diffusion process (shown by arrows 243) may be performed to diffuse the dopant of the second doping film 240 into the fins 56 and the semiconductor stripes 52 surrounding the recesses 125. The thermal diffusion process 243 may be performed by methods described above with respect to the thermal diffusion process 223 of the Fig. 12B and Fig. 12C, which are not repeated.

[0060] The mask 230 substantially prevents dopant from the second doping film 240 from diffusing into the source / drain regions 82 of the first region 100A. A conformal liner (not shown, see the description in connection with Fig. 4A above) may be formed between the isolation region 54 and the semiconductor stripes 52 to act as a diffusion barrier to prevent diffusion of dopant from the second doping film 240 into the isolation regions 54.

[0061] The diffusion of dopant into the surrounding fin 56 and the semiconductor stripes 52 provides an increased doping concentration to reduce the sheet resistance and improve the carrier mobility in the source / drain region of the device formed in the second region 100B. The concentration of the dopant in the dopant diffusion region 247 is greater than the concentration of the same dopant outside the dopant diffusion region 247, for example, in an outer diffusion region surrounding and adjacent to at least a portion of the dopant diffusion region 227 in the surrounding fin 56 and the semiconductor stripes 52. The concentration of the dopant formed by the first doping layer 220 in the dopant diffusion region 227 (see the Fig. 19B and Fig. 19C) (such as a p-type impurity) can be between about 2.5 × 10 19 cm -3 up to about 7.5 × 10 19 cm-3 The resulting carrier mobility can be between about 8 cm 2 / Vs up to about 20 cm 2 / Vs. The sheet resistance can be between about 150 Ω-cm and about 190 Ω-cm.

[0062] With reference to the Fig. 19B and Fig. 19C, after the thermal diffusion process 243, the second dopant film 240 is removed by any suitable method, for example, by a wet etch. A second dopant diffusion region 247 is formed in the fins 56 and the semiconductor stripes 52.

[0063] The dimensions and characteristics of the opening 125 and the thermal diffusion region 247 are the same as those described above with respect to the opening 124 and the thermal diffusion region 227 of Fig. 13D and are not repeated.

[0064] The Fig. 20B and Fig. 20C illustrate the formation of epitaxial source / drain regions 84 in the second region 100B. In some embodiments, the epitaxial source / drain regions 84 in the second region 100B are epitaxially grown in the recesses using MOCVD, MBE, LPE, VPE, SEG, a combination thereof, or the like. The epitaxial source / drain regions 84 may comprise any suitable material, such as any material suitable for p-type FinFETs. For example, if the fin 56 is made of silicon, the epitaxial source / drain regions 84 may comprise SiGe, SiGeB, Ge, GeSn, or the like. The epitaxial source / drain regions 84 may have surfaces raised from respective surfaces of the fins 56 and may have facets.The epitaxial source / drain regions 84 are formed in the fins 56 such that each dummy gate 76 is disposed between a corresponding adjacent pair of the epitaxial source / drain regions 84. In some embodiments, the epitaxial source / drain regions 84 may extend beyond the fins 56 and into the semiconductor stripes 52, as shown in FIG. Fig. 20B is shown.

[0065] The material of the epitaxial source / drain regions 84 in the second region 100B may be implanted with dopants, similar to the previously described method for forming the LDD regions 79, followed by annealing (see the Fig. 8A, Fig. 8B and Fig. 8C). The source / drain regions 84 may have an impurity concentration in a range of about 10 19 cm -3 up to about 10 21 cm -3The p-type impurities for the source / drain regions 84 in the second region 100B, e.g., the PMOS region, may be any of the previously described p-type impurities. In other embodiments, the epitaxial source / drain regions 84 may be doped in situ during growth. In the embodiments shown, each of the source / drain regions 84 is spatially separated from other source / drain regions 84. In further embodiments, two or more adjacent source / drain regions 84 may be combined. Examples of such embodiments are shown in the Fig. 27C and Fig. 31C, two or three adjacent source / drain regions 84 are combined to form a common source / drain region. In some embodiments, more than two adjacent source / drain regions 84 may be combined.

[0066] Due to the film doping of the U-shaped recess 246 (see the Fig. 20B and Fig. 20C), which provides a smooth sidewall profile of the recess, the epitaxial source / drain regions 84 can be formed in a uniform manner and produce a larger volume than would be produced without the film doping.

[0067] The dimensions and characteristics of the epitaxial source / drain regions 84 may be similar to those described above with respect to the epitaxial source / drain regions 82 of Fig. 14D and are not repeated.

[0068] Referring to the Fig. 21A, Fig. 21B and Fig. 21C, the mask 230 protecting the first region 100A is removed using any suitable technique.

[0069] The Fig. 22A to 25C illustrate the replacement of dummy gates 70 in first region 100A and dummy gates 76 in second region 100B with a replacement gate structure. In some embodiments, the replacement gate structure may be a metal gate, as described below. As mentioned above, although a gate-last method has been shown and described, those skilled in the art will understand that a gate-first method may also be used.

[0070] Referring to the Fig. 22A, Fig. 22B and Fig. 22C, an etch stop layer 87 and an interlayer dielectric (ILD) 88 are deposited over the dummy gates 70 and 76 and over the source / drain regions 82 and 84. In one embodiment, the ILD 88 is a flowable film formed by flowable CVD. In some embodiments, the ILD 88 is formed from a dielectric such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method such as CVD, PECVD, a combination thereof, or the like. In some embodiments, the etch stop layer 87 is used as a stop layer while the ILD 88 is patterned to form openings for subsequently formed contacts.Accordingly, a material for the etch stop layer 87 may be selected such that the material of the etch stop layer 87 has a lower etch rate than the material of the ILD 88.

[0071] Referring to the Fig. 23A, Fig. 23B and Fig. 23C, a planarization process, such as a CMP, may be performed to level the top surface of the ILD 88 with the top surfaces of the dummy gates 70 and 76. After the planarization process, the top surfaces of the dummy gates 70 and 76 are exposed through the ILD 88. In some embodiments, the CMP may also remove the masks 72 and 78, or portions thereof, on the dummy gates 70 and 76.

[0072] Referring to the Fig. 24A, Fig. 24B and Fig. 24C, remaining portions of the masks 72 and 78 and the dummy gates 70 and 76 are removed in one or more etching steps to form recesses 90. Each of the recesses 90 exposes a channel region of a corresponding fin 56. Each channel region is disposed between an adjacent pair of the epitaxial source / drain regions 82 in the first region 100A or between an adjacent pair of the epitaxial source / drain regions 84 in the second region 100B. In some embodiments, during the removal, the dummy dielectric layer 58 may be used as an etch stop layer and exposed when the dummy gates 70 and 76 are etched. The exposed dummy dielectric layer 58 may then be removed after the removal of the dummy gates 70 and 76. In some embodiments, portions of the dummy dielectric layer 58 that were not exposed by the process of removing the dummy gates 70 and 76 may remain, as shown in 。 Fig. 24B shown.

[0073] Referring to the Fig. 25A, Fig. 25B and Fig. 25C, gate dielectric layers 92 and 96 and gate electrodes 94 and 98 for the replacement gates are formed in the first region 100A and the second region 100B, respectively. The gate dielectric layers 92 and 96 are formed in the recesses 90, for example, on the top surfaces and sidewalls of the fins 56, on sidewalls of the gate spacers 122 and 130, respectively, and on a top surface of the ILD 88. In some embodiments, the gate dielectric layers 92 and 96 are deposited in a blanket layer. In some embodiments, the gate dielectric layers 92 and 96 comprise silicon oxide, silicon nitride, or multilayers thereof.In other embodiments, the gate dielectric layers 92 and 96 comprise a high-k dielectric, and in these embodiments, the gate dielectric layers 92 and 96 may have a k value greater than about 7.0 and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The fabrication methods of the gate dielectric layers 92 and 96 may include molecular beam deposition (MBD), ALD, CVD, PECVD, a combination thereof, or the like. In some embodiments, the formation may result in a conformally deposited layer having horizontal portions and vertical (or non-horizontal) portions of substantially the same thickness, for example, where the vertical thickness of the vertical portions of the dielectric layers 92 and 96 and the horizontal thickness of the horizontal portions of the dielectric layers 92 and 96 have a difference of less than 20 percent.In some embodiments, the gate dielectric layers 92 and 96 may be thermally grown as described above with respect to the dummy dielectric layer 58.

[0074] Next, gate electrodes 94 and 98 are deposited over gate dielectric layers 92 and 96, respectively, filling the remaining portions of recesses 90. Gate electrodes 94 and 98 may be made of a metal-containing material such as TiN, TaN, TaC, TiC, TiO, Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, combinations thereof, or multilayers thereof. After filling gate electrodes 94 and 98, a planarization process such as CMP may be performed to remove the excess portions of gate dielectric layers 92 and 96 and gate electrodes 94 and 98, which excess portions overlie the top surface of ILD 88. The resulting remaining material portions of gate electrodes 94 and 98 and gate dielectric layers 92 and 96 thus form replacement gates of the resulting FinFETs.

[0075] Although not shown, the gate electrodes 94 and 98 may comprise a sequence of one or more stacked layers (not shown). The stacked layers may be deposited in the recesses 90 over sidewalls and bottoms of the gate electrodes 94 and 98 and over the top surface of the ILD 88. The stacked layers may be formed by a blanket deposition process such as ALD or CVD and have a substantially uniform thickness within process variances. In some embodiments, forming the gate electrodes 94 and 98 may result in conformally deposited layers having horizontal portions and vertical (or non-horizontal) portions that have substantially the same thickness, for example, where the vertical thickness of the vertical portions of the layers and the horizontal thickness of the horizontal portions have a difference of less than 20 percent.The stacked layers may include a diffusion barrier layer and one or more work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN) or thallium nitride. The one or more work function layers determine the work function of the gate and may include at least one layer or a plurality of layers made of different materials. The specific material of the work function layer may be selected depending on whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, if the FinFET is an n-type FinFET, the work function layer may include an AlTiC layer. If the FinFET is a p-type FinFET, the work function layer may include an AlTiN and / or an AlTiC layer. After deposition of the one or more work function layers, a barrier layer (not shown), which may be another TiN layer, may be formed.

[0076] In some embodiments, the formation of the gate dielectric layers 92 and 96 may occur simultaneously such that the gate dielectric layers 92 and 96 are made of the same materials, and the formation of the gate electrodes 94 and 98 may occur simultaneously such that the gate electrodes 94 and 98 are made of the same materials. However, in other embodiments, the gate dielectric layers 92 and 96 may be formed by different processes such that the gate dielectric layers 92 and 96 may be made of different materials, and the gate electrodes 94 and 98 may be formed by different processes such that the gate electrodes 94 and 98 may be made of different materials. Different masking steps may be used to mask and expose appropriate areas if separate processes are used.

[0077] The Fig. 26A, Fig. 26B and Fig. 26C show the FinFET device after forming contacts to the source / drain regions 82 and 84 and the gates 94 and 96. A second ILD 102 is deposited over the ILD 88, contacts 104 and 106 are formed through the ILD 102 and the ILD 88, and contacts 108 and 110 are formed through the ILD 102. In one embodiment, the ILD 102 is formed using similar materials and processes as the ILD 88 described above with reference to the Fig. 22A, Fig. 22B and Fig. 22C, and the description will not be repeated. In some embodiments, the ILD 102 and the ILD 88 are formed from the same material. In other embodiments, the ILD 102 and the ILD 88 are formed from different materials.

[0078] Openings for contacts 104 and 106 are formed through ILDs 88 and 102 and etch stop layer 87. Openings for contacts 108 and 110 are formed through ILD 102 and etch stop layer 87. These openings can all be formed simultaneously in a single process or in separate processes. The openings can be formed using suitable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess materials from a top surface of ILD 102.Remaining liner and conductive material form contacts 104, 106, 108, and 110 in the openings. An annealing process may be performed to form a silicide (not shown) at the interface between epitaxial source / drain regions 82 and 84 and contacts 104 and 105, respectively. Contacts 104 are spatially and electrically connected to epitaxial source / drain regions 82, contacts 106 are spatially and electrically connected to epitaxial source / drain regions 84, contact 108 is spatially and electrically connected to gate electrode 94, and contact 110 is spatially and electrically connected to gate electrode 98.

[0079] Fig. Figure 27C shows a cross-sectional view of a FinFET device similar to that shown in Fig. 26A, Fig. 26B and Fig. 26C, wherein like elements are designated by like reference numerals. In some embodiments, the FinFET device of Fig. 27C using similar materials and processes as the FinFET device of Fig. 26A, Fig. 26B and Fig. 26C, which are described above with reference to the Fig. 1-26C, and the description will not be repeated. In the illustrated embodiment, two adjacent source / drain regions 82 and two adjacent source / drain regions 84 are combined to form respective common source / drain regions. In further embodiments, more than two adjacent source / drain regions 82 and more than two adjacent source / drain regions 84 may be combined (see, for example, Fig. 29C).

[0080] The Fig. 28C and Fig. 29C show enlarged portions of a cross-section of an epitaxial source / drain region of a device, showing various arrangements of the epitaxial materials according to some embodiments. The cross-sectional views of Fig. 28C and Fig. 29C correspond to a FinFET device similar to that shown in the Fig. 26A, Fig. 26B and Fig. 26C, wherein like elements are designated by like reference numerals. In some embodiments, the FinFET devices of Fig. 28C and Fig. 29C using similar materials and processes as the FinFET device of Fig. 26A, Fig. 26B and Fig. 26C, which are described above with reference to the Fig. 1-26C, and the description is not repeated.

[0081] In Fig. 28C, a single epitaxial source / drain region 82 / 84 may be part of a FinFET with a single fin or may be a single fin of a FinFET with a plurality of fins. Due to the dopant diffusion process ( Fig. 13B, Fig. 13C, Fig. 13D, Fig. 19B and Fig. 19C), the shape of the epitaxial materials in the source / drain regions 82 / 84 may be smoother, larger, and more defined than without the doping. The epitaxial source / drain 82 / 84 may include a first epitaxial structure 82Y / 84Y and a final layer of epitaxial material 82Z / 84Z formed on the first epitaxial structure 82Y / 84Y, which may be formed using methods and materials similar to those described above with respect to the Fig. 14B, Fig. 14C, Fig. 14D, Fig. 20B and Fig. 20C. The first epitaxial structure 82Y / 84Y may consist of multiple layers of epitaxial material. A width W7 corresponds to the width of the first epitaxial structure 82Y / 84Y. In some embodiments, the width W7 may be about 29 nm to about 39 nm. A width W8 corresponds to the width of the epitaxial source / drain region 82 / 84 comprising the final layer of epitaxial material 82Z / 84Z. In some embodiments, the width W8 may be about 38 nm to about 50 nm. A pitch D7 corresponds to the height of the first epitaxial structure 82Y / 84Y. In some embodiments, the pitch D7 may be about 36 nm to about 48 nm. A pitch D8 corresponds to the height of the epitaxial source / drain regions 82 / 84 comprising the final layer of epitaxial material 82Z / 84Z. In some embodiments, D8 may be about 43 nm to about 54 nm.A distance D9 corresponds to the thickness of the final layer of epitaxial material 82Z / 84Z. In some embodiments, D9 may be about 3.5 nm to about 7.5 nm.

[0082] The profile of the epitaxial source / drain regions 82 / 84 may have a larger volume and height with better defined facets as a result of the intermetal dopant diffusion process described here (see the Fig. 12B, Fig. 12C, Fig. 18B and Fig. 18C and the accompanying description).

[0083] In Fig. 29C, a triple epitaxial source / drain region 82 / 84 may be part of the fins of a FinFET, showing a crown-shaped structure with a combined epitaxial structure. Due to the dopant diffusion process ( Fig. 13B, Fig. 13C, Fig. 13D, Fig. 19B and Fig. 19C), the shape of the epitaxial materials in the source / drain regions 82 / 84 may be smoother, larger, and more defined than without the doping. The epitaxial source / drain regions 82 / 84 may include a first combined epitaxial structure 82Y / 84Y and a final layer of epitaxial material 82Z / 84Z formed on the first combined epitaxial structure 82Y / 84Y using methods and materials such as those described above with reference to the Fig. 14B, Fig. 14C, Fig. 14D, Fig. 20B and Fig. 20C. The first epitaxial structure 82Y / 84Y may consist of multiple layers of epitaxial material. A distance D 10 corresponds to the height of the first epitaxial structure 82Y / 84Y. In some embodiments, the distance D 10 about 51 nm to about 58 nm. A distance D 11corresponds to the height of the epitaxial source / drain regions 82 / 84 comprising the final layer of epitaxial material 82Z / 84Z. In some embodiments, the distance D 11 about 53 nm to about 64 nm. The distance D9 corresponds to the thickness of the final layer of epitaxial material 82Z / 84Z. In some embodiments, the distance D g about 3.5 nm to about 7.5 nm.

[0084] Embodiments of the present invention provide an increased concentration of dopant impurities in the source / drain regions of an n-type FinFET, p-type FinFET, or both (as in a complementary configuration). The increased dopant concentration provides improved carrier mobility and reduces sheet resistance in the source / drain regions. An additional advantage of the method of using thermal diffusion of a doped silicate glass to provide the dopant is that the profile of the recessed fin in the source / drain regions (prior to forming an epitaxial source / drain region) has smoother surfaces. The smoother surfaces provide an epitaxial structure in the source / drain regions (the epitaxial source / drain regions described above) that has a more defined faceted profile with greater height, width, and volume.

[0085] One embodiment is a method comprising etching a substrate to form a first semiconductor stripe. A first dummy gate structure is formed over a first channel region of the first semiconductor stripe, the first dummy gate being perpendicular to the first semiconductor stripe. A first recess is etched into the first semiconductor stripe on a first side of the first dummy gate. A second recess is etched into the first semiconductor stripe on a second side of the first dummy gate. A first intermetal doping film is formed in the first recess and the second recess. A first dopant of the intermetal doping film is diffused into the first semiconductor stripe proximate the first recess and into the first semiconductor stripe proximate the second recess. A source / drain region is epitaxially grown in the first recess and the second recess.

[0086] Another embodiment is a method comprising etching a first set of recesses in a source / drain region of a first region of a FinFET device and depositing a first intermetal doping film in the first set of recesses. The first intermetal doping film is annealed to diffuse the dopant of the first intermetal doping film adjacent to the first set of recesses. A first epitaxial source / drain region is grown in one or more recesses of the first set of recesses. The method also comprises etching a second set of recesses in a source / drain region of a second region of a FinFET device and depositing a second intermetal doping film in the second set of recesses, wherein the second intermetal doping film is different from the first intermetal doping film.The second intermetal dopant film is annealed to diffuse the dopant of the second intermetal dopant film adjacent to the second set of recesses. A second epitaxial source / drain region is grown in one or more recesses of the second set of recesses.

[0087] One embodiment is a semiconductor device comprising a plurality of semiconductor stripes and an isolation region formed between the plurality of semiconductor stripes, the isolation region having a top surface that is lower than a top surface of the plurality of semiconductor stripes. The device also comprises a plurality of gate stacks formed over a first channel region of the plurality of semiconductor stripes, the plurality of gate stacks being perpendicular to the plurality of semiconductor stripes. A first epitaxial source / drain region is arranged between a first two of the plurality of gate stacks, the first epitaxial source / drain region being formed in a first opening in a first stripe of the plurality of semiconductor stripes. A first dopant diffusion region surrounds the first epitaxial source / drain region and has a first concentration of the first dopant.A first outer diffusion region surrounds and adjoins at least a portion of the first dopant diffusion region and has a second concentration of the first dopant. The first concentration of the first dopant is greater than the second concentration of the first dopant.

Claims

[1] Method comprising: Etching a substrate (50) to form a first semiconductor stripe (52); Forming a first dummy gate structure (70) over a first channel region of the first semiconductor stripe (52), the first dummy gate structure (70) being perpendicular to the first semiconductor stripe (52); Etching a first recess (124, 226) in the first semiconductor stripe (52) on a first side of the first dummy gate structure (70); Etching a second recess (124, 226) in the first semiconductor stripe (52) on a second side of the first dummy gate structure (70); Forming a first intermetal doping film (220) in the first recess (124, 226) and the second recess (124, 226); Diffusing a first dopant of the first intermetal doping film (220) into the first semiconductor stripe (52) near the first recess (124, 226) and into the first semiconductor stripe (52) near the second recess (124, 226); epitaxially growing a source / drain region (82) in the first recess (124, 226); and epitaxially growing a source / drain region (82) in the second recess (124, 226), where: the epitaxial growth of the source / drain regions (82) in the first recess (124, 226) and in the second recess (124, 226) each comprises a first growth of a first layer (82A) of epitaxial material and a subsequent growth of a second layer (82B) of epitaxial material, the second layer (82B) has an upper width W4 at the top of the corresponding recess (124, 226), a middle width W5 at 50% of the depth of the second layer (82B) and a lower width W6 at 90% of the depth of the second layer (82B), and the middle width W5 is 80% to 90% of the upper width W4 and the lower width W6 is 2% to 61% wider than the upper width W4. [2] The method of claim 1, wherein the first dopant is selected from a group consisting of phosphorus, arsenic, antimony, bismuth, or a combination of two or more thereof. [3] The method of claim 1, wherein the first dopant is selected from a group consisting of boron, aluminum, gallium, indium, or a combination of two or more thereof. [4] The method of any preceding claim, wherein diffusing the first dopant comprises thermally annealing the first intermetal dopant film (220) between 900 and 1000 degrees Celsius for 3 to 6 seconds. [5] The method of any preceding claim, wherein forming the first intermetal doping film (220) comprises: Providing a first process gas having a first concentration, wherein the first process gas is a source of silicon, and Providing a second process gas having a second concentration, wherein the second process gas is a source of the first dopant, wherein a ratio of the second concentration to the first concentration determines a concentration of the first dopant in the first intermetal dopant film (220). [6] The method of claim 5, wherein the first process gas comprises: tetraethylorthosilicate or silane, and wherein the second process gas includes: PH3, POCl3 or B2H6. [7] Method according to one of the preceding claims, further comprising: Forming a second dummy gate structure (76) over a second channel region of the first semiconductor strip (52), wherein the first channel region is separated from the second channel region by an isolation structure; Etching a third recess (125, 246) into the first semiconductor stripe (52) on a first side of the second dummy gate structure (76); Etching a fourth recess (125, 246) into the first semiconductor stripe (52) on a second side of the second dummy gate structure (76); Forming a second intermetal doping film (240) in the third recess (125, 246) and the fourth recess (125, 246); Diffusing a second dopant of the second intermetal doping film (240) into the first semiconductor strip (52) near the third recess (125, 246) and into the first semiconductor strip (52) near the fourth recess (125, 246), wherein the second dopant is different from the first dopant; and epitaxially growing a source / drain region (84) in the third recess (125, 246) and a source / drain region (84) in the fourth recess (125, 246). [8] The method of claim 7, further comprising: Etching the substrate (50) to form a second semiconductor stripe (52) parallel to the first semiconductor stripe (52), wherein the first dummy gate structure (70) is formed over a first channel region of the second semiconductor stripe (52) and wherein the second dummy gate structure (76) is formed over a second channel region of the second semiconductor stripe (52); Depositing an insulating material (54) between the first and second semiconductor strips (52); Diffusing the first dopant of the first intermetal doping film (220) into the second semiconductor strip (52); and Diffusing the second dopant of the second intermetal doping film (240) into the second semiconductor strip (52). [9] Method comprising: Etching a first set of recesses (124, 226) into a source / drain region of a first region (100A) of a FinFET device; depositing a first intermetal dopant film (220) in the first set of recesses (124, 226); annealing the first intermetal doping film (220) to diffuse the dopant of the first intermetal doping film (220) adjacent to the first set of recesses (124, 226); Removing the first intermetal doping film (220); Growing a first epitaxial source / drain region (82) in one or more recesses of the first set of recesses (124, 226); Etching a second set of recesses (125, 246) into a source / drain region of a second region (100B) of a FinFET device; depositing a second intermetal doping film (240) different from the first intermetal doping film (220) in the second set of recesses (125, 246); annealing the second intermetal doping film (240) to diffuse the dopant of the second intermetal doping film (240) adjacent to the second set of recesses (125, 246); removing the second intermetal doping film (240); and Growing a second epitaxial source / drain region (84) in one or more recesses of the second set of recesses (125, 246), where: growing the first epitaxial source / drain region (82) comprises a first growth of a first layer (82A) of epitaxial material and a subsequent growth of a second layer (82B) of epitaxial material, the second layer (82B) in each of the one or more recesses of the first set of recesses (124, 226) has an upper width W4 at the top of the corresponding recess, a middle width W5 at 50% of the depth of the second layer (82B) and a lower width W6 at 90% of the depth of the second layer (82B), and the middle width W3 is 80% to 90% of the upper width W4 and the lower width W6 is 2% to 61% wider than the upper width W4. [10] The method of claim 9, wherein the dopant of the first intermetal doping film (220) is selected from a list consisting of phosphorus, arsenic, antimony, bismuth, or a combination of two or more thereof, and wherein the dopant of the second intermetal doping film (240) is selected from a list consisting of boron, aluminum, gallium, indium, or a combination of two or more thereof. [11] The method of claim 9, wherein the first intermetal doping film (220) is a first doped silicate glass and wherein the second intermetal doping film (240) is a second doped silicate glass. [12] The method of claim 11, wherein annealing the first intermetal dopant film (220) comprises annealing the first doped silicate glass between 900 and 1000 degrees Celsius for 3 to 6 seconds. [13] Method according to one of the preceding claims 9 to 12, further comprising: Forming a first dummy gate structure (70) perpendicular to and above one or a plurality of semiconductor fins (56), wherein the first set of recesses (124, 226) is etched in the one or more semiconductor fins (56) on opposite sides of the first dummy gate structure (70). [14] The method of any one of the preceding claims 9 to 13, wherein the first epitaxial source / drain region (82) comprises a plurality of epitaxial structures combined into a single faceted structure. [15] The method of claim 13, further comprising: Replacing the first dummy gate structure (70) with a first replacement gate structure, the first replacement gate structure comprising a gate electrode (94); Forming a first dielectric layer (102) over the first replacement gate structure (94); and Forming a contact (108) through the first dielectric layer (102) to the gate electrode (94). [16] A method according to any one of the preceding claims 9 to 15, wherein: the deposition of the first intermetal doping film (220) comprises: Providing a first process gas having a first concentration, wherein the first process gas is a source of silicon, and Providing a second process gas having a second concentration, wherein the second process gas is a source of the first dopant; and depositing the second intermetal doping film (240) comprises: Providing a third process gas having a third concentration, wherein the third process gas is a source of silicon, and Providing a fourth process gas having a fourth concentration, wherein the fourth process gas is a source of the second dopant. [17] A semiconductor device comprising: a plurality of semiconductor strips (52); an isolation region (54) formed between the plurality of semiconductor strips (52), the isolation region (54) having an upper surface lower than an upper surface of the plurality of semiconductor strips (52); a plurality of gate stacks (70, 76, 92-98) formed over respective channel regions of the plurality of semiconductor stripes (52), the plurality of gate stacks (70, 76, 92-98) being perpendicular to the plurality of semiconductor stripes (52); a first epitaxial source / drain region (82) formed between the first two (70, 92, 94) of the plurality of gate stacks (70, 76, 92-98), wherein the first epitaxial source / drain region (82) is formed in a first opening (124, 226) in a first strip of the plurality of semiconductor strips (52); a first dopant diffusion region (227) surrounding the first epitaxial source / drain region (82), the first dopant diffusion region (227) having a first concentration of a first dopant; and a first outer diffusion region surrounding and adjacent to at least a portion of the first dopant diffusion region (227), the first outer diffusion region having a second concentration of the first dopant, the first concentration of the first dopant being greater than the second concentration of the first dopant, where: the first epitaxial source / drain region (82) comprises a first layer (82A) of epitaxial material and a second layer (82B) of epitaxial material, the second layer (82B) has an upper width W4 at the top of the first opening (124, 226), a middle width W5 at 50% of the depth of the second layer (82B) and a lower width W6 at 90% of the depth of the second layer (82B), and the middle width W3 is 80% to 90% of the upper width W4 and the lower width W6 is 2% to 61% wider than the upper width W4. [18] The semiconductor device of claim 17, wherein the first opening (124, 226) has a lower surface that is lower than the upper surface of the isolation region (54). [19] A semiconductor device according to claim 17 or 18, further comprising: a second epitaxial source / drain region (84) disposed between second two (76, 96, 98) of the plurality of gate stacks (70, 76, 92-98), the second epitaxial source / drain region (84) being formed in a second opening (125, 246) in the first strip of the plurality of semiconductor strips (52); and a second dopant diffusion region (247) surrounding the second epitaxial source / drain region (84), the second dopant diffusion region (247) having a first concentration of a second dopant; and a second outer diffusion region surrounding and adjacent to at least a portion of the second dopant diffusion region (247), the second outer diffusion region having a second concentration of the second dopant, the first concentration of the second dopant being greater than the second concentration of the second dopant, and the first dopant being an n-type impurity and the second dopant being a p-type impurity. [20] A semiconductor device according to any one of the preceding claims 17 to 19, further comprising: a third epitaxial source / drain region (82) disposed between the first two (70, 92, 94) of the plurality of gate stacks (70, 76, 92-98), the third epitaxial source / drain region (82) being formed in a third opening (124, 226) in a second stripe of the plurality of semiconductor stripes (52), the second stripe being adjacent to the first stripe, the third epitaxial source / drain region (82) being joined to the first epitaxial source / drain region (82), the joined epitaxial source / drain region having a faceted epitaxial structure with a top surface that is at least about 2 nm higher than a top surface of the first stripe.

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