Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device (10), wherein the method comprises: Preparing an n-type semiconductor substrate (12) having a first region (X) and a second region (Y) in an upper surface (12a) of the semiconductor device (12), wherein the second region (Y) surrounds the first region (X), Forming a Schottky electrode (16) at least on the first region (X) of the upper surface (12a) of the semiconductor substrate (12), such that the Schottky electrode (16) is in Schottky contact with the upper surface (12a) of the semiconductor substrate (12); Etching of the second region (Y) of the upper surface (12a) of the semiconductor substrate (12) such that the first region (X) becomes higher than the second region (Y), forming a rising surface (Z) between the first region (X) and the second region (Y) and having an outer circumferential edge (16d) of the Schottky electrode (16) localized on the first region (X), Forming an insulating film (20) on the upper surface (12a) of the semiconductor substrate (12), wherein the insulating film (20) extends in a ring shape along the rising surface (Z), an inner circumferential edge (20c) of the insulating film (20) is located on the Schottky electrode (16) and an outer circumferential edge of the insulating film (20) is located on the second region (Y) and Forming a field plate electrode (18f), wherein the field plate electrode (18f) is electrically connected to the Schottky electrode (16) and points towards the upper surface (12a) of the semiconductor substrate (12) over the insulating film (20) within a region extending from the outer circumferential edge (16d) of the Schottky electrode (16) to the second region (Y) over the rising surface (Z), characterized in that the semiconductor substrate (12), which is prepared during preparation, has an n-type drift layer (34) and an n-type layer (36) with high resistivity, which has a lower carrier density than the drift region (34). the layer (36) with high specific resistance surrounds the drift area (34) in the upper surface (12a), a boundary of the first region (X) and the second region (Y) is located in the layer (36) with high resistivity, and the preparation of the semiconductor substrate (12) exhibits: Formation of the drift layer (34) by epitaxial growth, Etching a part of the drift layer (34) to form a groove (36c) at a position where the layer (36) with high resistivity is to be formed, and Formation of the layer (36) with high resistivity within the groove (36c) by epitaxial growth.

Description

TECHNICAL FIELD

[0001] The teaching disclosed here relates to a method for manufacturing a semiconductor device BACKGROUND

[0002] JP 2013-102081 A describes a semiconductor device. This semiconductor device comprises a semiconductor substrate and a Schottky electrode provided on a surface of the semiconductor substrate. The surface of the semiconductor substrate is provided with a so-called mesa structure. This means that the upper surface of the semiconductor substrate has a first region and a second region surrounding the first region, and the first region is located higher than the second region, with a rising surface provided between the first region and the second region. The Schottky electrode is provided at the first region, and a high-resistivity layer facing an outer peripheral edge of the Schottky electrode is provided at an outer peripheral portion of the first region.According to such a structure, a concentration of the electric field in a vicinity of the outer peripheral edge of the Schottky electrode is reduced, which improves the breakdown voltage of the semiconductor device.

[0003] JP 2013-102081 A further describes another semiconductor device that does not have such a mesa structure. In this semiconductor device, an outer peripheral portion of the Schottky electrode faces the semiconductor substrate via an insulating film. According to such a configuration, the outer peripheral portion of the Schottky electrode functions as a field plate electrode, and the concentration of the electric field near the outer peripheral edge within a region forming the Schottky contact is reduced by a field plate effect. Due to this, the breakdown voltage of the semiconductor device is improved.

[0004] US 2016 / 0 254 392 A1 discloses a semiconductor device and a method for its manufacture according to the preamble of claim 1 and claim 2. The subsequently published WO 2017 / 134 509 A1 also teaches a related semiconductor device and a method for its manufacture. SUMMARY

[0005] The teaching herein provides a new structure that further improves the breakdown voltage of a semiconductor device and claims a manufacturing method therefor.

[0006] A structure of a semiconductor device disclosed herein may include a semiconductor substrate, in an upper surface of which a first region and a second region surrounding the first region are provided. The first region may be located higher than the second region, and the surface of the semiconductor substrate may further include a rising surface between the first region and the second region. A Schottky electrode in Schottky contact with the upper surface of the semiconductor substrate may be provided at the first region. An outer peripheral edge of the Schottky electrode may be located at the first region, and the rising surface may not be covered by the Schottky electrode. An insulating film may further be provided at the upper surface of the semiconductor substrate.The insulating film may extend annularly along the rising surface, and an inner peripheral edge of the insulating film may be located at the Schottky electrode, and an outer peripheral edge of the insulating film may be located at the second region. A field plate electrode may be provided on the insulating film. The field plate electrode may be electrically connected to the Schottky electrode and may face the upper surface of the semiconductor substrate via the insulating film within a region extending from the outer peripheral edge of the Schottky electrode to the second region across the rising surface.

[0007] In the above-mentioned structure, the upper surface of the semiconductor substrate has a mesa structure, and the field plate electrode is provided in the region extending from the outer peripheral edge of the Schottky electrode, across the rising surface, and reaching the second region. According to such a structure, when an inverted bias voltage is applied between the semiconductor device and the Schottky electrode, a depletion layer easily develops from the outer peripheral edge of the Schottky electrode, across the rising surface, and into the second region. Due to this, the concentration of the electric field in the vicinity of the outer peripheral edge of the Schottky electrode is reduced, and the breakdown voltage of the semiconductor device is further improved.

[0008] The teaching here discloses a method for manufacturing the aforementioned semiconductor device. This method has the features listed in claim 1 or claim 2. Advantageous further developments are the subject of the dependent claims. According to this manufacturing method, the semiconductor device with a superior breakdown voltage can be manufactured as described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a semiconductor device 10. Fig. 2 is a cross-sectional view along a line II-II of Fig. 1 and schematically shows a structure related to the breakdown voltage of the semiconductor device 10. Fig. 3 is a flowchart showing a flow of a manufacturing method of a semiconductor device 10 of a first embodiment. Fig. 4 is a diagram explaining a process in preparing a semiconductor substrate 12 (S12) and shows an initial state of the semiconductor device 12. Fig. 5 is a diagram explaining a process in preparing the semiconductor substrate 12 (S12), and shows the semiconductor device 12 in which a drift layer 34 is formed. Fig. 6 is a diagram explaining a process in preparing the semiconductor substrate 12 (S12), and shows the semiconductor substrate 12 in which a groove 36c is formed at a position corresponding to a high resistivity layer 36. Fig. 7 is a diagram explaining a process in preparing the semiconductor substrate 12 (S12), and shows the semiconductor substrate 12 in which the high resistivity layer 36 is formed by epitaxial growth. Fig. 8 is a diagram explaining a process in preparing the semiconductor substrate 12 (S12), and shows the semiconductor substrate 12 in which an excessive portion of the high resistivity layer 36 is removed. Fig. 9 is a diagram explaining the formation of a Schottky electrode 16 (S14). Fig. 10 is a diagram explaining the etching of a second region Y (S16). Fig. 11 is a diagram explaining a process of forming an insulating film 20 (S18), and shows the semiconductor substrate 12 in which the insulating film 20 is formed over an entirety of an upper surface 12a. Fig. 12 is a diagram explaining a process of forming the insulating film 20 (S18), and shows the semiconductor substrate 12 in which the insulating film 20 is formed. Fig. 13 is a diagram explaining a process of forming a contact electrode 18 (S20), and shows the semiconductor substrate 12 in which the contact electrode 18 is formed over the entirety of an upper surface 12a. Fig. 14 is a diagram explaining a process of forming the contact electrode 18 (S20), and shows the semiconductor substrate 12 in which the contact electrode 18 is formed. Fig. 15 is a diagram explaining a process of forming a protective film 22 (S22), and shows the semiconductor substrate 12 in which the protective film 22 is formed over the entirety of the upper surface 12a. Fig. 16 is a diagram explaining a process of forming the protective film 22 (S22), and shows the semiconductor substrate 12 in which the protective film 22 is formed. Fig. 17 is a flowchart showing a flow of a manufacturing method of the semiconductor device 10 of a second embodiment. Fig. 18 is a diagram explaining the preparation of a semiconductor substrate 12 (S112). Fig. 19 is a diagram explaining the formation of a Schottky electrode 16 (S114). Fig. 20 is a diagram explaining etching of a second region Y (S116). Fig. 21 is a diagram explaining how to perform ion implantation of impurities (S117). Fig. 22 is a diagram explaining a process of forming an insulating film 20 (S118), and shows the semiconductor substrate 12 in which the insulating film 20 is formed over an entirety of an upper surface 12a. Fig. 23 is a diagram explaining a process of forming the insulating film 20 (S118), and shows the semiconductor substrate 12 in which the insulating film 20 is formed. DETAILED DESCRIPTION

[0009] A structure and a manufacturing method of the present disclosure can be applied to a semiconductor device using a semiconductor in which formation of a p-type region is difficult. In general, a guard ring structure having a p-type guard ring region is known as one of the structures that can improve the breakdown voltage of a semiconductor device. However, use of the guard ring structure with a semiconductor in which a p-type region cannot be easily formed is difficult. In this regard, the structure and manufacturing method of the present disclosure do not require the formation of a p-type region, which can be said to be effective for a semiconductor in which formation of a p-type region is difficult.As a semiconductor in which the formation of a p-type region is difficult, oxide semiconductors such as gallium oxide (Ga2O3) can be cited as examples. Particularly, with an oxide semiconductor in which a conductivity band minimum (CBM) of the oxide semiconductor is lower than -4.0 eV and a valence band maximum (VBM) of the oxide semiconductor is lower than -6.0 eV, with a vacuum level as a reference, the formation of the p-type region is difficult. However, the structure and manufacturing method of the present disclosure can be further suitably applied to a semiconductor device employing other semiconductors, for example, gallium nitride (GaN).

[0010] In one embodiment, the formation of an insulating film may be performed by a mist CVD (chemical vapor deposition) method. The insulating film is formed over both a first region and a second region, between which a rising surface is provided. Generally, it is difficult to uniformly form the insulating film on a front surface having such a surface level difference. In this regard, the mist CVD method is suitable for film deposition on such a front surface having the surface level difference, and thus, it can be effectively used in the formation of the insulating film in the present disclosure.

[0011] In one embodiment, the formation of a Schottky electrode may also form the Schottky electrode on the second region. In this case, etching the second region may preferably remove the Schottky electrode also formed on the second region. According to such a configuration, the formation of the Schottky electrode and the formation of a mesa structure of a semiconductor substrate are performed in a single step, so that a manufacturing error (i.e., a difference from the intended design) that may occur in a positional relationship between the Schottky electrode and the mesa structure of the semiconductor substrate is suppressed.

[0012] In one embodiment, the preparation of the semiconductor substrate may include a semiconductor substrate having an n-type drift layer and an n-type high-resistivity layer, the latter having a lower carrier density than the drift region. This semiconductor substrate may have the drift layer and the high-resistivity layer as part of its upper surface, the high-resistivity layer surrounding the drift region in the upper layer, and a boundary of the first region and the second region may be located on the high-resistivity layer. According to such a configuration, an outer peripheral edge of the Schottky barrier electrode contacts the high-resistivity layer, and a semiconductor device with greater superiority in breakdown voltage can be manufactured.

[0013] In the above-mentioned embodiment, the preparation of the semiconductor substrate may include forming the drift layer by epitaxial growth, etching a portion of the drift layer to form a groove at a position where the high-resistivity layer is to be formed, and forming the high-resistivity layer within the groove by epitaxial growth. In this case, although not particularly limited thereto, the epitaxial growth of the high-resistivity layer may be performed by a mist CVD method. By using the mist CVD method, an epitaxial growth layer free of voids or gaps can be formed even within the groove having corners.

[0014] Alternatively, as another embodiment, ion implantation of impurities may be further included at the upper surface of the semiconductor substrate between the etching of the second region and the formation of the insulating film. Here, the ion implantation may be performed using a Schottky electrode as a mask, and the impurities may have a property of reducing the carrier density of the semiconductor substrate. In this case, the impurities may be implanted along a direction angled with respect to a normal direction of the first region of the semiconductor substrate to be implanted below the Schottky electrode. According to such a configuration, the above-mentioned high-resistivity layer can be formed by the ion implantation.Since the Schottky electrode can be used as a mask for this, a manufacturing error (i.e., a difference from the intended design) that may occur in a positional relationship between the Schottky electrode and the high resistivity layer can be suppressed.

[0015] Representative, non-limiting examples of the present invention will now be described in detail with reference to the accompanying drawings. This detailed description is merely intended to inform a person skilled in the art of further details for practicing the preferred aspects of the present teachings and is not intended to limit the scope of protection. Furthermore, each of the additional features and teachings disclosed below may be used separately or in conjunction with other features or teachings to provide an improved semiconductor device, and methods of using and manufacturing the same.

[0016] Furthermore, combinations of features and steps disclosed in the following detailed description may not be necessary for practicing the invention in its broadest sense, and are provided merely to particularly describe representative examples of the invention. Furthermore, various features of the representative examples described above and below, as well as various independent and dependent claims, may be combined in a manner that is not specifically and explicitly recited to provide additional useful embodiments of the present disclosure.

[0017] All features disclosed in the description and / or claims are intended to be disclosed separately and independently of one another for the purpose of original written disclosure and for the purpose of limiting the claimed subject matter, regardless of the combinations of features in the embodiments and / or the claims. Furthermore, all ranges of values ​​or indications of groups of units are intended to disclose every possible intermediate value or unit for the purpose of original written disclosure and for the purpose of limiting the claimed subject matter.

[0018] (First Embodiment) A semiconductor device 10 and a manufacturing method thereof of a first embodiment will be described with reference to the drawings. The semiconductor device 10 is a type of power semiconductor device and can be used in a circuit for supplying power to a motor that drives wheels in an electrically powered vehicle, such as an electric vehicle, a hybrid vehicle, and a fuel cell vehicle. Note that technical elements disclosed in this embodiment are not limited to the semiconductor device 10 and the manufacturing method thereof, and can be applied to various other semiconductor devices and manufacturing methods thereof. Hereinafter, a configuration of the semiconductor device 10 will be described first, and then the manufacturing method of the semiconductor device 10 will be described.

[0019] As it is in the Fig. 1 and Fig. As shown in Fig. 2, the semiconductor device 10 includes a semiconductor substrate 12, an upper electrode 14, an insulating film 20, a protective film 22, and a lower electrode 24. The upper electrode 14, the insulating film 20, and the protective film 22 are provided on an upper surface 12a of the semiconductor substrate 12, and the lower electrode 24 is provided on a lower surface 12b of the semiconductor substrate 12. The upper electrode 14 includes a Schottky electrode 16 and a contact electrode 18. The contact electrode 18 is provided on the Schottky electrode 16 and is electrically connected to the Schottky electrode 16. An outer peripheral portion 18f of the contact electrode 18 faces the semiconductor substrate 12 via the insulating film 20 and functions as a field plate electrode. This field plate electrode 18f faces the upper surface 12a of the semiconductor substrate 12 on an outer side than the outer peripheral edges 16d (one of which is on the right side in Fig. 2) of the Schottky electrode 16 over the insulating film 20.

[0020] The upper surface 12a of the semiconductor substrate 12 has a mesa structure. More specifically, the upper surface 12a of the semiconductor substrate 12 includes a first region X and a second region Y surrounding the first region X, and has the first region X at a higher level than the second region Y. In other words, the first region X protrudes upward with respect to the second region Y. The first region X and the second region Y are parallel to each other and are also parallel to the lower surface 12b of the semiconductor substrate 12. Rising surfaces Z are provided between the first region X and the second region Y. The rising surfaces Z are inclined surfaces or vertical surfaces connecting the first region X and the second region Y, which have a height difference, and are surfaces that form angles with respect to the first region X and the second region Y.

[0021] The semiconductor substrate 12 is an n-type semiconductor substrate. Although not specifically limited to this, the semiconductor substrate 12 of the present embodiment is a gallium oxide (Ga2O3) substrate. The semiconductor layer 12 includes an n-type ohmic contact layer 32, a drift layer 34 having a lower carrier density than the ohmic contact layer 32, and a high-resistivity layer 36 having a lower carrier density than the drift layer 34. The ohmic contact layer 32 is located in a lower layer of the semiconductor substrate 12 and forms the lower surface 12b of the semiconductor substrate 12. The drift layer 34 and the high-resistivity layer 36 are provided on the ohmic contact layer 32 and form the upper surface 12a of the semiconductor substrate 12.In the upper surface 12a of the semiconductor substrate 12, the high-resistivity layer 36 surrounds the drift layer 34, and the rising surfaces Z between the first region X and the second region Y are located on the high-resistivity layer 36. In other words, the high-resistivity layer 36 is provided in a region extending from the first region X to the second region Y via the rising surfaces Z. In this embodiment, the high-resistivity layer 36 makes direct contact with the ohmic contact layer 32, but in other embodiments, the drift layer 34 may be interposed between the high-resistivity layer 36 and the ohmic contact layer 32. Alternatively, the high-resistivity layer 36 is not a required constituent feature and may be omitted as needed.

[0022] The Schottky electrode 16 is provided on the first region X and is in Schottky contact with the upper surface 12a of the semiconductor substrate 12. The outer peripheral edges 16d of the Schottky electrode 16 are located on the first region X. This means that the rising surfaces Z are not covered by the Schottky electrode 16. A material of the Schottky electrode 16 can simply be a material that establishes Schottky contact with the upper surface 12a of the semiconductor substrate 12, and this is not particularly limited, but it can be, for example, platinum (Pt).

[0023] The insulating film 20 extends annularly along the rising surfaces Z. Inner peripheral edges 20c of the insulating film 20 are located on the Schottky electrode 16, and outer peripheral edges 20d of the insulating film 20 are located on the second region Y. Although this is an example, the insulating film 20 of the embodiment reaches side surfaces 12d of the semiconductor substrate 12 and covers an entirety of the second region Y. A material of the insulating film 20 may simply be a material having desired insulation, and this is not particularly limited, but may be, for example, alumina (Al2O3).

[0024] An outer peripheral portion of the contact electrode 18 is located on the insulating film 20 and, as described above, functions as the field plate electrode 18f. On the other hand, a central portion of the contact electrode 18 is in direct contact with the Schottky electrode 16 through an opening defined by the peripheral edges 20c of the insulating film 20. Due to this, the field plate electrode 18f is electrically connected to the Schottky electrode 16. The field plate electrode 18f faces the upper surface 12a of the semiconductor substrate 12 above the insulating film 20 in a vicinity of the outer peripheral edges 16d of the Schottky electrode 16. More specifically, the field plate electrode 18f faces the upper surface 12a of the semiconductor substrate 12 via the insulating film 20 in a region extending from the outer peripheral edges 16d of the Schottky electrode 16, via the rising surfaces Z, reaching the second region Y.The material of the contact electrode 18 (i.e., the field plate electrode 18f) is not particularly limited, but it may be gold (Au), for example. Alternatively, the contact electrode 18 may have a laminate structure with layers of titanium (Ti), nickel (Ni), and gold.

[0025] The protective film 22 extends annularly along edges of the semiconductor substrate 12 and covers an outer peripheral portion of the upper electrode 14 and the insulating film 20. An outer peripheral edge 22c of the protective film 22 defines an opening through which the upper electrode 14 can be exposed. A material of the protective film 22 simply needs to be an insulating material, and this is not particularly limited, but may be, for example, a polymer material such as polyimide.

[0026] The lower electrode 24 is in ohmic contact with the lower surface 12b of the semiconductor substrate 12. A material of the lower electrode 24 can simply be a material that can make ohmic contact with the lower surface 12b of the semiconductor substrate 12, and thus is not particularly limited. The lower electrode 24 of the present embodiment makes contact with the entire lower surface 12b of the semiconductor substrate 12; however, as other embodiments, the lower electrode 24 may make contact with only a part of the lower surface 12b of the semiconductor substrate 12.

[0027] According to the above structure, the semiconductor device 10 of the present embodiment is provided with a Schottky barrier diode (hereinafter referred to simply as a diode) that uses the upper electrode 14 as an anode and the lower electrode 12b as a cathode. In this electrode, the upper surface 12a of the semiconductor substrate 12 has the mesa structure, and the field plate electrode 18f is provided in the region extending from the outer peripheral edges 16d of the Schottky electrode 16 across the rising surfaces Z and reaching the second region Y. According to such a structure, when an inverted bias voltage is applied between the semiconductor substrate 12 and the Schottky electrode 16, a depletion layer can easily spread from the outer peripheral edges 16d of the Schottky electrode 16 across the rising surfaces Z and to the second region Y.As a result, the concentration of the electric field near the outer peripheral edges 16d of the Schottky electrode 16 is greatly facilitated, and the breakdown voltage of the semiconductor device 10 is greatly improved. In particular, when the semiconductor device 12 uses the high-resistivity layer 36 and the outer peripheral edges 16d of the Schottky electrode 16 are located on the high-resistivity layer 36, as in the semiconductor device 10 of the present embodiment, this allows the aforementioned depletion layer to spread more easily, and the breakdown voltage of the semiconductor device 10 is further improved.

[0028] Next, a manufacturing method of a semiconductor device 10 will be described. Fig. Fig. 3 is a flow chart showing a flow of the manufacturing method of the present embodiment. First, in step S12, a semiconductor substrate 12 is prepared. In this step, although not specifically limiting, the semiconductor substrate 12 provided with an ohmic contact layer 32, a drift layer 34, and a high resistivity layer 36 as shown in Fig. 8, according to processes described in the Fig. 4 to 8 are shown.

[0029] First, as it is in Fig. 4, the semiconductor substrate 12, which has only the ohmic contact layer 32, is prepared. As previously described, the semiconductor substrate 12 may be a gallium oxide substrate. Washing and other processes are performed on the semiconductor substrate 12 as required. Next, as shown in Fig. 5, the drift layer 34 is formed on the ohmic contact layer 32. The drift layer 34 is formed over the entirety of the ohmic contact layer 32. This drift layer 34 is not particularly limited but can be formed by epitaxial growth of gallium oxide. This epitaxial growth can be performed, for example, by an MOCVD (Metal Organic Chemical Vapor Deposition) method or an HVPE (Hydride Vapor Phase Epitaxy) method. Alternatively, the epitaxial growth of the drift layer 34 can be performed by a mist CVD method.

[0030] Next, as it is in Fig. 6, a part of the drift layer 34 is etched so that a groove 36c is formed at a position where the high resistivity layer 36 is to be formed. Then, as shown in Fig. 7, the high-resistivity layer 36 is formed within the groove 36c. At this stage, the high-resistivity layer 36 may be formed over the entirety of an upper surface 12a of the semiconductor substrate 12, instead of being formed only within the groove 36c. The high-resistivity layer 36 may be formed by epitaxial growth of gallium oxide. Further, although not particularly limited, this epitaxial growth may be performed by the mist CVD method. When the mist CVD method is used, a raw material thereof (here, gallium oxide) is transferred in a mist form, so that an epitaxial growth layer without voids or gaps can be formed within a short period of time even in the groove 36c having corners.

[0031] In the epitaxial growth of the high-resistivity layer 36, compared to the epitaxial growth of the drift layer 34, impurities of iron (Fe) and / or magnesium (Mg) may be preferentially added. Addition of these impurities suppresses a carrier density of the high-resistivity layer 36 that is lower than that of the drift layer 34 and increases the resistivity thereof. It should be noted that the impurities are not limited to specific types of substances and can be any substance that can suppress the carrier density of the n-type drift layer 34 to low. Alternatively, a concentration of n-type impurities to be added may simply be lowered. Next, as shown in Fig. 8, an excessive high-resistivity layer 36 is removed to flatten the surface 12a of the semiconductor substrate 12. Although not particularly limiting, this flattening may be performed by a CMP (Chemical Mechanical Polishing) method. The flattened upper surface 12a of the semiconductor substrate 12 has the drift layer 32 and the high-resistivity layer 34 exposed there, and the high-resistivity layer 34 surrounds the drift layer 32. According to the above, the semiconductor substrate 12 including the ohmic contact layer 32, the drift layer 34, and the high-resistivity layer 36 is prepared.

[0032] It will be Fig. 3, wherein in step S14 a Schottky electrode 16 is formed on the upper surface 12a of the semiconductor substrate 12. As shown in Fig. 9, at this stage, the Schottky electrode 16 is formed over the entirety of the upper surface 12a having a first region X and a second region Y. In other embodiments, the Schottky electrode 16 may be selectively formed only on the first region X. In such cases, the Schottky electrode 16 simply needs to make Schottky contact with the upper surface 12a of the semiconductor substrate 12 at least in the first region X. As mentioned above, a material of the Schottky electrode 16 may be, for example, platinum.

[0033] In step S16 of Fig. 3, the second region Y of the upper surface 12a of the semiconductor substrate is etched. To do this, as shown in Fig. 10, the first region X in the upper surface 12a of the semiconductor substrate 12 is higher than the second region Y therein, and rising surfaces Z are formed between the first region X and the second region Y. In this step, not only the semiconductor substrate 12 is removed into the second region Y, but also the Schottky electrode 16 on the second region Y is also removed. As described above, when the formation of the Schottky electrode 16 and the formation of the mesa structure of the semiconductor substrate 12 are carried out in one step, a manufacturing error (i.e., a deviation from the intended design) that may occur in a positional relationship between the Schottky electrode 16 and the mesa structure of the semiconductor substrate 12 can be suppressed.

[0034] In step S18 of Fig. 3, an insulating film 20 is formed on the upper surface 12a of the semiconductor substrate 12. The formation of the insulating film 20 is not particularly affected by processes described in Fig. 11 and Fig. 12. First, as shown in Fig. 11, the insulating film 20 is formed on the upper surface 12a of the semiconductor substrate 12. The formation of the insulating film 20 can be carried out, for example, by a mist CVD method. According to the mist CVD method, the material of the insulating film 20 (e.g., aluminum oxide) is transferred into a mist form, so that the insulating film 20, which is free of gaps or voids, can be formed on the upper surface 12a of the semiconductor substrate 12, which has corners with rising areas Z. Then, as shown in Fig. As shown in Figure 12, the central portion 20g of the insulating film 20 is removed by etching to form the insulating film 20 into a ring shape. As a result, the insulating film 20 is provided with an opening through which the Schottky electrode 16 can be accessed.

[0035] In the present embodiment, the insulating film 20 is formed after the Schottky electrode 16 is formed. In other words, the Schottky electrode 16 is formed before the formation of the insulating film 20. According to such a procedure, the Schottky electrode can be formed on the upper surface 12a of the semiconductor substrate 12 without the risk of the upper surface 12a of the semiconductor substrate 12 receiving influences (such as damage and contamination) that may be caused by the formation and etching of the insulating film 20. Due to this, a stable Schottky junction interface can be achieved between the upper surface 12a of the semiconductor substrate 12 and the Schottky electrode 16.

[0036] In step S20 of Fig. 3, a contact electrode 18 is formed above the upper surface 12a of the semiconductor substrate 12. The formation of the contact electrode 18 is not particularly limited, but it can be carried out by processes described in Fig. 13 and Fig. 14. First, as shown in Fig. 13, the contact electrode 18 is formed over the entire upper surface 12a of the semiconductor substrate 12. As previously described, the material of the contact electrode 18 may be, for example, gold. Alternatively, the material of the contact electrode 18 may be a laminate structure of different types of metals. Then, as shown in Fig. 14, a portion 18e of the contact electrode 18 is removed by etching. As a result, the contact electrode 18 is shaped to have its desired form. Part of the contact electrode 18 is a field plate electrode 18f, and this process is therefore also a process for forming a field plate electrode 18f.

[0037] In step S22 of Fig. 3, a protective film 22 is formed on the upper surface 12a of the semiconductor substrate 12. The formation of the protective film 22 is not particularly limited, but it can be carried out by processes described in the Fig. 15 and Fig. 16. First, as shown in Fig. 15, the protective film 22 is formed over the entire upper surface 12a of the semiconductor substrate 12. As previously described, the material of the protective film 22 is the insulating material and may be, for example, polyimide. Then, as shown in Fig. As shown in Figure 16, a central portion 22g of the protective film 22 is removed by etching. As a result, the protective film 22 is formed into a ring shape.

[0038] In step S24 of Fig. 3, a lower electrode 24 is formed on the lower surface 12b of the semiconductor substrate 12. Due to this, the structure of the semiconductor device 10 shown in the Fig. 1 and Fig. 2 is completed. Normally, a plurality of semiconductor devices 10 are manufactured on a piece of semiconductor wafer at the same time, and dicing is performed to separate the semiconductor wafer into a plurality of semiconductor devices 10.

[0039] The structure of the semiconductor device 10 and the manufacturing method thereof described in this embodiment are not limited to semiconductor devices using gallium oxide as a material, but can be suitably applied to other types of semiconductor materials. It should be noted that gallium oxide is known as a substance in which a p-type region cannot be easily formed, so it is difficult to employ a guard ring structure requiring a p-type guard ring region in the semiconductor device 10 using the gallium oxide semiconductor substrate 12. In this regard, according to the structure and manufacturing method of the present embodiment, the breakdown voltage of the semiconductor device 10 can be improved without requiring the formation of the p-type region.Thus, the structures and manufacturing method of the present embodiment can be suitably used, especially in a semiconductor device using semiconductor materials with which the formation of the p-type region is difficult. Examples of such semiconductor materials include oxide semiconductors with a conductivity band minimum (CBM) lower than -4.0 eV and a valence band maximum (VBM) lower than -6.0 eV, with a vacuum level as a reference.

[0040] (Second Embodiment) Another embodiment of a manufacturing method of a semiconductor device 10 will be described. Fig. Fig. 17 is a flow chart showing a flow of the manufacturing method of the present embodiment. First, in step S112, a semiconductor substrate 12 is prepared. In this step, unlike S12 of the first embodiment, a semiconductor substrate 12 having an ohmic resistance layer 32 and a drift layer 34, but not having a high-resistivity layer 36, as shown in Fig. 18. Such a semiconductor substrate 12 can be prepared, for example, according to the Fig. 4 and Fig. 5 of the first embodiment. Step S112 of the second embodiment corresponds to step S12 of the first embodiment, but differs from step S12 of the first embodiment in that the semiconductor substrate 12 does not have the high-resistivity layer 36.

[0041] In step S114 of Fig. 17, a Schottky electrode 16 is formed on an upper surface 12a of the semiconductor substrate 12. As Fig. 19, at this stage, the Schottky electrode 16 is formed over an entirety of the upper surface 12a including a first region X and a second region Y. However, in other embodiments, the Schottky electrode 16 may be selectively formed only in the first region X. In such cases, the Schottky electrode 16 only needs to make Schottky contact with the upper surface 12a of the semiconductor substrate 12 at least in the region X. As described above, a material of the Schottky electrode may be, for example, platinum. Step S114 of the second embodiment corresponds to S14 of the first embodiment, and thus it can be carried out in a manner like step S14 of the first embodiment.

[0042] In step S116 of Fig. 17, the second region Y of the upper surface 12a of the semiconductor substrate 12 is etched. Due to this, as shown in Fig. 20, the first region X in the upper surface 12a of the semiconductor substrate 12 is higher than the second region Y therein, and rising surfaces Z are formed between the first region X and the second region Y. In this step, not only the semiconductor substrate 12 in the second region Y but also the Schottky electrode 16 on the second region Y are removed. Due to this, as described in the first embodiment, a manufacturing error (i.e., a difference from the intended design) that may occur in a positional relationship between the Schottky electrode 16 and a mesa structure of the semiconductor substrate 12 can be suppressed. Here, some parts of the Schottky electrode located in the first region X may be further removed, so that outer peripheral edges 16d of the Schottky electrode 16 separate from the rising surfaces Z.Step S116 of the second embodiment corresponds to step S16 of the first embodiment and thus can be executed in the same manner as step S16 of the first embodiment.

[0043] In step S117 of Fig. 17, impurities are ion-implanted with respect to the upper surface 12a of the semiconductor substrate 12. In this ion implantation, as shown in Fig. 21, the Schottky electrode 16 is used as a mask so that the impurity is implanted into the rising areas Z and the second area Y, which are not covered by the Schottky electrode 16. Arrows shown in Fig. 21, labeled "ION," schematically illustrate impurity ion implantation. The impurities to be implanted are impurities that suppress the carrier density in the n-type semiconductor substrate 12 (which is the drift layer 34 here) and are not particularly limited, but may be, for example, iron (Fe) and / or magnesium (Mg). Furthermore, the impurities are implanted along a direction that is at an angle to a normal direction of the first region X (up and down direction in Fig. 21) so that an implantation takes place under the Schottky electrode 16. Due to this, the high-resistivity layer 36, which is lower than the drift region 34 at the carrier density, is formed in the semiconductor substrate 12. Since the Schottky electrode 16 is used as the mask, a manufacturing error (i.e., a difference with respect to the intended design) that may occur in a positional relationship between the Schottky electrode 16 and the high-resistivity layer 36 can be suppressed. In a Fig. In the example shown in Figure 17, the drift layer 34 is sandwiched between the ohmic contact layer 32 and the high-resistivity layer 36, but in other embodiments, the high-resistivity layer 36 may reach the ohmic contact layer 32. Step S117 of the second embodiment is a step that cannot be seen in the manufacturing method of the first embodiment.

[0044] In step S118 of Fig. 17, an insulating film 20 is formed on the upper surface 12a of the semiconductor substrate 12. The formation of the insulating film 20 is not particularly limited, but can be carried out by processes described in the Fig. 22 and Fig. 23. First, as shown in Fig. 22, the insulating film 20 is formed over the entire upper surface 12a of the semiconductor substrate 12. The formation of the insulating film 20 can be carried out, for example, by the mist CVD method, similar to the first embodiment. Then, as shown in Fig. As shown in Figure 23, a central portion 20g of the insulating film 20 is removed by etching to form the insulating film 20 into a ring shape. As a result, the insulating film 20 is provided with an opening through which the Schottky electrode 16 can be reached. Step S118 of the second embodiment corresponds to step S18 of the first embodiment and thus can be performed in a similar manner to step S18 of the first embodiment.

[0045] In step S120 of Fig. 17, a contact electrode 18 is formed on the upper surface 12a of the semiconductor substrate 12. The formation of the contact electrode 18 can be achieved by processes described in the Fig. 13 and Fig. 14 are executed similarly to step S20 of the first embodiment. In step S122 of Fig. 17, a protective film 22 is formed on the upper surface 12a of the semiconductor substrate 12. The formation of the protective film 22 can be carried out by processes described in the Fig. 15 and Fig. 16, similar to step S22 of the first embodiment. Then, in step S124 of Fig. 17, a lower electrode 24 is formed on a lower surface 12b of the semiconductor substrate 12 similarly to step S24 of the first embodiment. Due to this, the structure of the semiconductor device 10 shown in Fig. 1 and Fig.2 (except that the ohmic contact layer 32 and the high resistivity layer 36 are in direct contact).

Claims

[1] A method of manufacturing a semiconductor device (10), the method comprising: Preparing an n-type semiconductor substrate (12) having a first region (X) and a second region (Y) in an upper surface (12a) of the semiconductor device (12), the second region (Y) surrounding the first region (X), Forming a Schottky electrode (16) at least on the first region (X) of the upper surface (12a) of the semiconductor substrate (12) such that the Schottky electrode (16) is in Schottky contact with the upper surface (12a) of the semiconductor substrate (12); Etching the second region (Y) of the upper surface (12a) of the semiconductor substrate (12) so that the first region (X) becomes higher than the second region (Y), wherein a rising surface (Z) is formed between the first region (X) and the second region (Y), and an outer peripheral edge (16d) of the Schottky electrode (16) is located at the first region (X), Forming an insulating film (20) on the upper surface (12a) of the semiconductor substrate (12), wherein the insulating film (20) extends annularly along the rising surface (Z), an inner peripheral edge (20c) of the insulating film (20) is located on the Schottky electrode (16) and an outer peripheral edge of the insulating film (20) is located on the second region (Y) and Forming a field plate electrode (18f), wherein the field plate electrode (18f) is electrically connected to the Schottky electrode (16) and faces the upper surface (12a) of the semiconductor substrate (12) via the insulating film (20) within a region extending from the outer peripheral edge (16d) of the Schottky electrode (16) to the second region (Y) via the rising surface (Z), characterized by , that the semiconductor substrate (12) prepared during preparation has an n-type drift layer (34) and an n-type high-resistivity layer (36) having a lower carrier density than the drift region (34) the high resistivity layer (36) surrounds the drift region (34) in the upper surface (12a), a boundary of the first region (X) and the second region (Y) is located in the high resistivity layer (36), and preparing the semiconductor substrate (12) comprises: Forming the drift layer (34) by epitaxial growth, Etching a part of the drift layer (34) to form a groove (36c) at a position where the high resistivity layer (36) is to be formed, and Forming the high resistivity layer (36) within the groove (36c) by epitaxial growth. [2] A method of manufacturing a semiconductor device (10), the method comprising: Preparing an n-type semiconductor substrate (12) having a first region (X) and a second region (Y) in an upper surface (12a) of the semiconductor device (12), the second region (Y) surrounding the first region (X), Forming a Schottky electrode (16) at least on the first region (X) of the upper surface (12a) of the semiconductor substrate (12) such that the Schottky electrode (16) is in Schottky contact with the upper surface (12a) of the semiconductor substrate (12); Etching the second region (Y) of the upper surface (12a) of the semiconductor substrate (12) so that the first region (X) becomes higher than the second region (Y), wherein a rising surface (Z) is formed between the first region (X) and the second region (Y), and an outer peripheral edge (16d) of the Schottky electrode (16) is located at the first region (X), Forming an insulating film (20) on the upper surface (12a) of the semiconductor substrate (12), wherein the insulating film (20) extends annularly along the rising surface (Z), an inner peripheral edge (20c) of the insulating film (20) is located on the Schottky electrode (16) and an outer peripheral edge of the insulating film (20) is located on the second region (Y) and Forming a field plate electrode (18f), wherein the field plate electrode (18f) is electrically connected to the Schottky electrode (16) and faces the upper surface (12a) of the semiconductor substrate (12) via the insulating film (20) within a region extending from the outer peripheral edge (16d) of the Schottky electrode (16) to the second region (Y) via the rising surface (Z), characterized by performing ion implantation of impurities on the upper surface (12a) of the semiconductor substrate (12), wherein the ion implantation is performed between the etching of the second region (Y) and the formation of the insulating film (20), wherein the ion implantation is carried out using the Schottky electrode (16) as a mask, wherein the impurities have a property of reducing the carrier density of the semiconductor substrate (12) and the impurities are implanted along a direction which is arranged at an angle to a normal direction of the first region (X) of the semiconductor substrate (12) in order to be implanted under the Schottky electrode (16). [3] The method according to claim 1 or 2, wherein the semiconductor substrate (12) is a substrate made of oxide semiconductor and with a vacuum level as a reference, a conduction band minimum (CBM) of the oxide semiconductor is lower than -4.0 eV and a valence band maximum (VBM) of the oxide semiconductor is lower than -6.0 eV. [4] The method according to any one of claims 1 to 3, wherein the semiconductor substrate (12) is a gallium oxide substrate. [5] The method according to any one of claims 1 to 4, wherein the forming of the insulating film (20) is carried out by a mist CVD method. [6] The method according to any one of claims 1 to 5, wherein the Schottky electrode (16) is formed on the second region (Y) of the upper surface (12a) during formation of the Schottky electrode (16) and a part of the Schottky electrode (16) formed on the second region (Y) of the upper surface (12a) is also removed during etching of the second region (Y) of the upper surface (12a) of the semiconductor substrate (12). [7] The method of claim 1, wherein the epitaxial growth of the high resistivity layer (36) is carried out by a mist CVD process.

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