Method for controlling electrical and / or electronic components of a vehicle module and such a vehicle module with automatic module addressing via powerline

Abstract

Auto-addressing method for assigning bus node addresses within a data bus system with a communication bus with n bus nodes (BK1, BK2, BK3, ..... BKn-1, BKn), where n is a positive integer greater than zero, and a bus master (ECU) - wherein the bus nodes are supplied with electrical energy via a supply voltage line (Vbat) and - wherein the communication bus (DB) is connected to the bus master (ECU) and - wherein each bus node (BK1, BK2, ..... BKn-1, BKn) is connected to the communication bus (DB) and - wherein within each bus node (BK1 to BKn) a measuring resistor (Rmj) assigned to the respective bus node (BKj) of the n bus nodes (BK1 to BKn) is inserted into the supply voltage line (Vbat), i.e. the data bus system has n measuring resistors (Rm1 to Rmn).and- wherein the measuring resistors (Rm1 to Rmn) of the bus nodes (BK1 to BKn) thus divide the supply voltage line (Vbat) into n supply voltage line sections and- wherein each bus node (BKj) of the bus nodes (BK1 to BKn) has an addressing current source (Iqj) and- wherein each bus node (BKj) of the bus nodes (BK1 to BKn) has means (D2, D3, Rmj) to detect the current through the measuring resistor (Rmj) of this bus node (BKj) of the bus nodes (BK1 to BKn) and- wherein the addressing current source (Iqj) of each bus node (BKj) of the bus nodes (BK1 to BKn) injects an addressing current towards the power supply (SUP) into the supply voltage line (Vbat) into the terminal of the measuring resistor (Rmj) of this bus node (BKj), which runs along the The supply voltage line (Vbat) is furthest from the power supply (SUP), and – with the following steps – signaling of an addressing state,hereinafter referred to as the power-line addressing state, to all bus nodes (BK1 to BKn), thereby setting them to an addressing state for performing an auto-addressing procedure using the power supply line (Vbat); - Performing an initialization sequence, comprising the following steps, for each bus node (BKj) of the n bus nodes (BK1, BK2, ..... BKn-1, BKn) that does not yet have a valid bus node address until all bus nodes of the n bus nodes (BK1, BK2, ..... BKn-1, BKn) have a valid bus node address: • Signaling a bus address to be assigned to all bus nodes of the n bus nodes (BK1, BK2, ..... BKn-1, BKn); • Parallel execution of the following steps for each bus node (BKj) of the bus nodes of the n bus nodes (BK1, BK2, ..... BKn-1, BKn), hereinafter referred to as the respective Bus junction (BKj) is designated,which does not have a valid bus node address: • Reception of the aforementioned auto-addressing command from the bus master (ECU) by the relevant bus node (BKj); • Reception of the bus address to be assigned from the bus master (ECU) by the relevant bus node (BKj); • Reception of a start signal for the assignment of the bus address to be assigned from the bus master (ECU) by the relevant bus node (BKj) and start of a timer at a start time (t0=0s) by the relevant bus node (BKj); • Detection of the voltage drop across the measuring resistor (Rmj) of the relevant bus node (BKj) as a base voltage value (Vm0) using measuring instruments (Rmj, D2,D3);• At a fourth time (t4) after the start time (t0): switching on the addressing current source (Iqj) of the relevant bus node (BKj) and adjusting the voltage drop across the measuring resistor (Rmj) of the relevant bus node (BKj) with the help of the addressing current source (Iqj) as a function of the voltage drop across the measuring resistor (Rmj) by means of a control signal (rwj) which is generated by measuring instruments (D2, D3, Rmj) and / or control instruments (F) of the bus node (BKj), to a total target voltage value which corresponds to a target voltage value as plus the previously measured base voltage value (Vm0),• wherein the addressing current of the auto-addressing current source (Iqj) of the relevant bus node (BKj) is increased by a first time constant (Δ1) and • wherein the addressing current of the auto-addressing current source (Iqj) of the relevant bus node (BKj) is decreased by a second time constant (Δ2); • At a fifth time (t5) after the start time (t0) and after the fourth time (t4): the value of the control signal (rwj) or a signal derived therefrom is detected and this value is compared with a threshold value and • the bus node address to be assigned is used as the valid bus node address of the bus node (BKj) if the magnitude of this value is above the threshold value and the addressing current source (Iqj) is switched off at least until the bus node (BKj) leaves the addressing state.

Description

The invention relates to a device for controlling electrical and / or electronic components of a vehicle module, in particular an interior light and / or exterior light such as a rear light module of a vehicle. Furthermore, the invention relates to a vehicle module with several electrical and / or electronic components, in particular an interior light and / or exterior light such as a rear light module of a vehicle. State of the art Regarding document DE 10 2017 100 718 A1 Document DE 10 2017 100 718 A1, which is a prior art document, describes a method for the secure authentication and integration of mobile devices into stationary computer systems via wireless networks. The focus is on controlling and managing device registration with a base station, proposing mechanisms for identity verification and protection against unauthorized access. Manual authentication and consistent access restrictions ensure a high level of operational reliability. The focus is on protecting the base station and maintaining the stability of the wireless connection between the device and the point-of-sale system. The specific technical problem addressed by the technical teaching presented here, and not addressed by DE 10 2017 100 718 A1, is the fully automated, system-based management and addressing of all system nodes in the network without time-consuming manual interaction.In particular, the assignment, modification, and control of bus addresses and the adaptation of devices in the network are achieved through self-optimizing, software-supported processes, enabling the efficient correction of errors, failures, or system changes without user intervention. The technical teaching of DE 10 2017 100 718 A1 does not offer an automated solution for addressing and integrating a large number of nodes; rather, the steps of device integration, testing, and approval remain manual and therefore error-prone and less scalable. Regarding document DE 10 2008 044 777 A1 The technical teaching of document DE 10 2008 044 777 A1, which is part of the prior art, deals with a method for managing communication addresses within a bus system, particularly in motor vehicles. The application describes how individual electronic control units (ECUs) are assigned addresses within a vehicle data bus. A system is recommended in which initialization and address assignment occur after the power supply is switched on. Using an addressing process and unique identifiers, such as a hardware ID or stored identification data, each participant is assigned an address. The bus nodes or ECUs participate in the process by synchronizing themselves and actively registering for assignment. The aim is to ensure error-free and rapid address assignment and to avoid collisions in the address space, with particular attention paid to efficiency in device assignment and bus communication. In contrast to the technical teaching presented in this document, which provides for an auto-addressing procedure and claims a fully automated system, the approach of DE 10 2008 044 777 A1 retains the problem of manual or software-supported detection and management of new or replaced bus nodes. The technical teaching of DE 10 2008 044 777 A1 does not offer a technical solution that guarantees automated, user-independent integration and reassignment of system nodes. For example, manual intervention may be necessary in the event of a node replacement or failure, and the automated reassignment of addresses after topology changes is not performed with hardware support and system autonomy. Regarding document US 2016 / 0 259 747 A1 The prior art US document US 2016 / 0259747A1 describes a method for automatically addressing devices (nodes) in a serial bus network, such as those typically found in decentralized automation systems or vehicle architectures. The core approach is that each node is identified and assigned an address within the network after being powered on. For this purpose, individual nodes are activated in addressing mode by a specific, action-based trigger (for example, an operator action, a sensor pulse, or similar). Following this activation, the bus master initiates an address assignment and assigns a unique address to each affected node. This allows new devices to be integrated into the existing network relatively easily and user-friendly, without the need for complex manual configurations.The process is designed so that the operator can address individual devices step by step through targeted actions, and these devices are then recognized and integrated by the system as new participants. However, unlike the technical teaching presented here, the technical teaching of US 2016 / 0 259 747 A1 leaves unresolved the problem of ensuring a completely system-autonomous, user-independent update and management of the device list when there are dynamic changes to the network's device inventory—for example, when bus nodes are replaced or automatically detected by the system. The technical teaching of US 2016 / 0 259 747 A1 deliberately requires human or sensor-based intervention for address assignment.A continuously monitored, autonomous address assignment and management system for all bus nodes is lacking, where the system reacts independently in the background, resolves conflicts, and keeps the device status up-to-date without maintenance. This problem of automatic, real-time address management without any user activity remains unaddressed in US 2016 / 0259747A1. The electrical and electronic components of vehicle modules, such as the various lighting modules, are becoming increasingly complex. Particularly in the area of ​​lighting, there has been a recent trend towards the use of dynamic functions, such as sweeping turn signals or the "coming home" function. This approach takes advantage of the fact that the individual exterior and interior lighting functions of a vehicle are each implemented using multiple LEDs or OLEDs. Dynamic effects can now be achieved in a relatively simple way from a hardware perspective by controlling the numerous light sources within such a vehicle lighting module in different ways. The numerous components of a vehicle module, such as the many LEDs or OLEDs assigned to the individual lighting functions of, for example, a taillight module, are advantageously connected to a control unit of the module via a communication bus, or rather, they communicate with the control unit via this bus. Typically, the control unit also includes a voltage converter to supply power, in particular, to the LED drivers of a lighting module. Differential two-wire communication bus systems have proven effective in terms of transmission speed and robustness. Information signals are transmitted between the control unit and the devices as a voltage difference between the two bus lines, resulting in greater signal reliability, higher transmission speed, and reduced susceptibility to interference. Such two-wire bus systems are generally known. The problem is that the hardware requirements for such two-wire bus systems and their components are considerable. A particular disadvantage in terms of cost is the fact that the components must have relatively precise clocks that operate synchronously. Furthermore, the light modules must be able to determine their physical position during installation and connection at the vehicle factory and convert it into a logical address. This allows identical light modules to be used without pre-programming a bus node address for each module, which significantly reduces the potential for errors and simplifies logistics in production. From NN: “High-Brightness LED Matrix Manager for Automotive Headlight Systems”, February 1, 2016 (2016-02-01), pages 1-53, XP055348745, Dallas, Texas (found on the Internet: URL:http: / / www.ti.com / lit / ds / symlink / tps92661-q1.pdf on 2017-02-23) a vehicle headlight control system is known whose bus has two lines to which no differential signals are applied. In MONAL GIRADKAR ET AL: “Design and Implementation of Adaptive Front Light System of Vehicle Using FPGA Based LIN Controller”, EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET), 2011 4TH INTERNATIONAL CONFERENCE ON, IEEE, November 18, 2011 (2011-11-18), pages 258-261, XP032087461, DOI: 10.1109 / ICETET.2011.67; ISBN: 978-1-4577-1847-2, a bit timing logic for a CAN bus is described. A device for controlling an adaptive automotive front light with an FPGA-based LIN controller is described in GUO JINYAN ET AL: “The design and realization of CAN bit timing logic”, MICROELECTRONICS AND ELECTRONIS (PRIMEASIA), 2010 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN, IEEE, PISCATAWAY, NJ, USA, September 22, 2010 (2010-09-22), pages 333-337, XP031777603, ISBN: 978-1-4244-6735-8. Finally, ZENG WEIYING ET AL: “In-Vehicle Networks Outlook: Achievements and Challenges”, IEEE COMMUNICATIONS SURVEYS & TUTORIALS, Vol. 18, No. 3, February 27, 2016 (2016-02-27), pages 1552-1571, XP011620858, DOI: 10.1109 / COMST.2016.2521642; [accessed 2016-08-19] provides an overview of vehicle communication systems. The object of the invention is to create a device for controlling electrical and / or electronic components of a vehicle module and such a vehicle module which is reduced in terms of hardware effort. The scope of application is determined by the claims. The description specifies the claims and places them in an overall context. To solve this problem, the invention proposes a device for controlling electrical and / or electronic components of a vehicle module, in particular an interior light and / or exterior light such as a rear light module of a vehicle, wherein the device is provided with: • a differential two-wire communication bus, • several components connected to the two-wire communication bus, and • a control unit that receives control commands for the components from external sources and converts these control commands into bit streams to be sent to the components via the two-wire communication bus, as well as receiving bit streams generated by the components, • wherein each component has an asynchronous, digital, serial interface,a microcontroller and a clock generator for generating a sampling signal for sampling bitstreams transmitted via the two-wire communication bus, and • wherein at least the bitstreams transmitted by the control unit contain synchronization information for synchronizing the clock generators of the components to the clock with which the control unit transmits the bits of the bitstreams via the two-wire communication bus, and • wherein each component is configured to determine and then use a logical bus node address correlated with its physical position by means of one or more auto-addressing methods. Furthermore, to solve the problem according to the invention, a vehicle module with several electrical and / or electronic components, in particular an interior light and / or exterior light such as a rear light module of a vehicle, serves, wherein the vehicle module is provided with: • a differential two-wire communication bus, • wherein the components are connected to the two-wire communication bus, and • a control unit that receives control commands for the components from external sources and converts these control commands into bit streams to be sent to the components via the two-wire communication bus, as well as receiving bit streams generated by the components, • wherein each component has an asynchronous, digital, serial interface,comprising a microcontroller and a clock generator for generating a sampling signal for sampling bitstreams transmitted via the two-wire communication bus, and wherein at least the bitstreams transmitted by the control unit contain synchronization information for synchronizing the clock generators of the components to the clock with which the control unit transmits the bits of the bitstreams via the two-wire communication bus, and wherein, before commencing normal operation, the components switch from a normal state to an addressing state and perform a procedure for determining bus node addresses that depend on the physical position of the bus nodes in the chain of bus nodes, and then exit the addressing state again. The proposed approach combines the advantages of a differential two-wire communication bus with auto-addressing capability with the advantages of using asynchronous digital serial interfaces to connect individual participants or components to the two-wire communication bus. The use of Universal Asynchronous Receiver Transmitters (UARTs) requires that the bitstream received via such a digital serial interface contains synchronization information for the clock of the bus participant (the respective bus node). However, such synchronization information (e.g., synchronization bits) can now also be easily integrated via a differential two-wire communication bus, for example, in the header of a data frame representing the bitstream.Thus, the protocol of the differential two-wire communication bus used according to the invention includes elements such as those known from single-wire buses whose participants have standardized and cost-effective UARTs. The invention is particularly applicable in the context of digital interfaces for robust and high-speed data transmission via a two-wire cable connection between circuit boards equipped with LEDs, for example, for the rear light and interior light within a luminaire, at a data rate of up to 500 kbit / s. Symmetrical transmission using a differential high-speed two-wire bus system is employed for the purpose of transmitting a simple serial protocol, thereby reducing the hardware digital complexity. Figure 1 shows an example of a taillight module (BLM) for a vehicle. The taillight module (BLM) comprises a bus master (ECU) and a serial, bidirectional, differential two-wire communication bus (DB). The serial, bidirectional, differential two-wire communication bus (DB) consists of a first single-wire bus (DBa) and a second single-wire bus (DBb). The TXD and RXD lines of the bus master (ECU) lead to a level converter (TR) to convert the signal level for operation of the two-wire communication bus DB. The bus master (ECU) receives various control commands externally, for example, for the functions taillight, turn signal, rear fog light, dynamic effects, etc., and / or information via a digital bus. The bus master (ECU) converts these commands into bit streams, which include, among other things, bits of a synchronization field for the corresponding data frames (bit stream packet (BP)).Level converter and bus master (ECU) are in the following also considered as a unit and referred to collectively as bus master (ECU). Various components or devices are connected to the communication bus (DB) as bus nodes BK1 to BK6. For example, the first and second bus nodes (BK1 and BK2) are responsible for the turn signal function, the third bus node (BK3) for the taillight function, the fourth and sixth bus nodes (BK4 and BK6) for the brake light function, and the fifth bus node (BK5) for the reverse light function. Each of these devices or components has a number of LEDs (LED1 to LED6) controlled by their respective LED drivers. Each bus node is also equipped with a digital interface (IF1 to IF6) in the form of a UART. Furthermore, each bus node may include a microcontroller (µC1 to µC6) and a clock generator (CLKG1 to CLKG6) to read messages on the differential two-wire communication bus (DB) synchronously with the transmission of bit streams, or to place such bit streams on the two-wire communication bus (DB) synchronously for reading by other participants or the bus master (ECU). Furthermore, simplifying the hardware of the inventive control system for the components of a vehicle module is facilitated by the use of fixed sampling points at the component or two-wire communication bus participant level, instead of dynamic adjustment of the sampling points. The latter is considerably more complex. Clock signal acquisition for each participant is achieved by reading the synchronization information from the bit streams, which is advantageously transmitted at the beginning of a bit stream. Fig. 2 shows a two-wire communication bus (DB), such as those known from the prior art. The serial, bidirectional, differential two-wire communication bus (DB) consists of a first single-wire bus (DBa) and a second single-wire bus (DBb). The serial, bidirectional, differential two-wire communication bus (DB) connects the bus master (ECU) to several bus nodes (BK1 to BKn). The bus master (ECU) has a first driver (TRa) with which it can bring the first single-wire bus (DBa) into a first state (Z1) or a second state (Z2) or a third state (Z3). A first driver, acting as a CAN driver, can preferably assume two of three allowed states: In a first state, it places a first logical level (Z1) on the first single-wire bus (DBa). In a second state, it places a third logical level (Z3) on the first single-wire bus (DBa). The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes (BK1 to BKn) as the first current sink for the first addressing currents of the first addressing current sources (Iq1 to Iqn) of the bus nodes (BK1 to BKn) and their first quiescent currents. Preferably, the first driver of a bus node (BK1 to BKn) or of the bus master (ECU) assumes the first state (Z1) when the second driver (TRb) of the respective bus node (BK1 to BKn) assumes the second state (Z2). This causes the signal to be differentially impressed with a first differential level (z1). Preferably, the first driver of a bus node (BK1 to BKn) or...The bus master (ECU) outputs the third state (Z3) when the second driver (TRb) of the relevant bus node (BK1 to BKn) assumes the third state (Z3). This differentially induces a third differential level (z3) in the signal. The first driver, also an RS485 driver, can preferably assume two of two allowed states: In a first state, it places a first logic level (Z1) on the first single-wire bus (DBa). In a second state, it places a second logic level (Z2) on the first single-wire bus (DBa). The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes (BK1 to BKn) as the first current sink for the first addressing currents of the first addressing current sources (Iq1 to Iqn) of the bus nodes (BK1 to BKn) and their first quiescent currents. Preferably, the first driver of a bus node (BK1 to BKn) or of the bus master (ECU) assumes the first state (Z1) when the second driver (TRb) of the respective bus node (BK1 to BKn) assumes the second state (Z2). This causes the signal to be differentially impressed with a first differential level (z1). Preferably, the first driver of a bus node (BK1 to BKn) or...The bus master (ECU) outputs the second state (Z2) when the second driver (TRb) of the relevant bus node (BK1 to BKn) assumes the first state (Z1). This differentially induces a second differential level (z2) in the signal. Furthermore, the first driver typically has a sub-device for detecting and avoiding a bus collision in the event of simultaneous access to the first single-wire bus (DBa) by a first driver of another bus node (BK1bis BKn) or the bus master (ECU). A second driver, acting as a CAN driver, can preferably assume two of three allowed states: In a first state, it places a second logical level (Z2) on the second single-wire bus (DBb). In a second state, it places a third logical level (Z3) on the second single-wire bus (DBb). The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes (BK1 to BKn) as a second current sink for the second addressing currents of the second addressing current sources (Iq'1 to Iq'n) of the bus nodes (BK1 to BKn) and their second quiescent currents. Preferably, the second driver of a bus node (BK1 to BKn) or of the bus master (ECU) assumes the second state (Z2) when the first driver (TRa) of the respective bus node (BK1 to BKn) assumes the first state (Z1). This causes the signal to be differentially impressed with a first differential level (z1). Preferably, the second driver of a bus node (BK1 to BKn) or...The bus master (ECU) outputs the third state (Z3) when the first driver (TRa) of the relevant bus node (BK1 to BKn) assumes the third state (Z3). This differentially induces a third differential level (z3) in the signal. The second driver, also an RS485 driver, can preferably assume any two of its two allowed states: In a first state, it places a second logic level (Z2) on the first single-wire bus (DBa). In a second state, it places a first logic level (Z1) on the second single-wire bus (DBb). The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes (BK1 to BKn) as a second current sink for the second addressing currents of the second addressing current sources (Iq'1 to Iq'n) of the bus nodes (BK1 to BKn) and their second quiescent currents. Preferably, the second driver of a bus node (BK1 to BKn) or of the bus master (ECU) assumes the second state (Z2) when the first driver (TRa) of the respective bus node (BK1 to BKn) assumes the first state (Z1). This causes the signal to be differentially impressed with a first differential level (z1). Preferably, the second driver of a bus node (BK1 to BKn) or...The bus master (ECU) enters the first state (Z1) when the first driver (TRa) of the relevant bus node (BK1 to BKn) assumes the second state (Z2). This differentially induces a second differential level (z2) in the signal. Furthermore, the first driver typically has a sub-device for detecting and avoiding a bus collision in the event of simultaneous access to the first single-wire bus (DBa) by a first driver of another bus node (BK1bis BKn) or the bus master (ECU). Each of the bus nodes (BK1 to BKn) and the bus master (ECU) preferably has a receiver (Rec). The respective receiver (Rec) extracts the data (DATA) contained in the bit stream packets (BP) on the serial, bidirectional, differential two-wire communication bus (DB) and preferably outputs this data, along with error information, via an output (out) of the receiver (Rec). The receiver (Rec) typically checks whether the check information (CHKD) within the data information (DATA) of a bit stream packet (BP) indicates error-free reception by the receiver (Rec). If a bit stream packet (BP) was not received correctly by the receiver (Rec), the receiver (Rec) preferably signals this. The actual user circuitry at the receiver output (out) is not shown in Fig. 2 for clarity.These process the information received by the receiver (Rec) (out) and control the drivers (TRa, TRb) for the respective transmission process of a bus node (BK1bis BKn) or the bus master (ECU). The data bus system has a common supply voltage line (Vbat) and typically a common reference potential (GND), which is not shown in Fig. 2. Note that despite the serial arrangement of the bus nodes (BK1 to BKn), Fig. 2 shows a star topology for the data bus. For clarity, the diagram in Fig. 2 ends at the third bus node (BK3). In one embodiment, a device for controlling electrical and / or electronic bus nodes (BK1 to BKn), particularly within a vehicle module, an interior light, and / or an exterior light such as a vehicle's taillight module, is proposed. This device features a serial, bidirectional, differential two-wire communication bus (DB) with n bus nodes (BK1 to BKn), where n is a positive integer greater than 1. Furthermore, the proposed device includes a bus master (ECU). The serial, bidirectional, differential communication bus (DB) consists of a first single-wire bus (DBa) and a second single-wire bus (DBb). Each of the n bus nodes (BK1 to BKn) has a differential serial interface (IFj) compatible with the serial, bidirectional, differential communication bus (DB).Each bus node (BKj) of the n bus nodes (BK1 to BKn) preferably has a clock generator (CLKGj), a scanning device (ATj), an address recognition unit (ADRj), and a bus node address register (BKADRj). The serial, bidirectional, differential communication bus (DB) is designed such that it can preferably be in at least a first logical state (High, Z1), a second logical state (Low, Z2), and optionally a third logical state (Idle, Z3). Firstly, levels of the high-speed CAN protocol (HS-CAN) can be used. This will be explained first. For this purpose, the serial, bidirectional, differential communication bus (DB) in the transmitters (TXa, TXb) of the respective bus node (BKj) is preferably connected via a high-impedance voltage divider per transmitter (TXa, TXb) to a preferably zero differential voltage difference between the first single-wire bus (DBa) and the second single-wire bus (DBb), corresponding to the third logical state (Idle, Z3). Each transmitter (TXa, TXb) preferably includes a switch which, when activated, allows the first single-wire bus (DBa) of the serial, bidirectional, differential communication bus (DB) to be set to the first logical state (High, Z1) by the first driver (TRa), and the second single-wire bus (DBb) of the serial, bidirectional, differential communication bus (DB) to be set to a second logical state (Low, Z2) by the second driver (TRb). This is shown in Fig. 3 below.When the switches of the drivers (TRa, TRb) are switched off (IDLE), the serial, bidirectional, differential communication bus (DB) again assumes the third logical state (Idle, Z3). Secondly, levels from the RS484 protocol can be used. This will be explained second. For this purpose, the serial, bidirectional, differential communication bus (DB) in the transmitters (TXa, TXb) of the respective bus node (BKj) is preferably connected to a differential voltage difference corresponding to the third logical state (Idle, Z3) via a high-impedance voltage divider in each transmitter (TXa, TXb). Each transmitter (TXa, TXb) preferably comprises a half-bridge, which, by inversely controlling the half-bridges, can bring the serial, bidirectional, differential communication bus (DB) to the first logical state (High, Z1) and to a second logical state (Low, Z2). When the half-bridges are switched off (IDLE), the serial, bidirectional, differential communication bus (DB) again assumes the third logical state (Idle, Z3). The serial interface (IFj) of at least one of the n bus nodes (BK1 to BKn) is connected to the serial, bidirectional, differential communication bus (DB) to send and / or receive data via this bus. It typically includes the aforementioned transmitters (TXa, TXb) and a receiver (Rec) for each bus node (BKj). For the sake of simplicity, the clock and data extraction within the bus nodes (BK1 to BKn) from the bit packets (BP) is not shown in the diagrams, as it is known from the prior art. The bus master (ECU) receives control commands for the n bus nodes (BK1 to BKn) from an external source and converts these commands into bit streams to be sent to the bus nodes (BK1 to BKn) via the serial, bidirectional, differential communication bus (DB).The bus master (ECU) transmits the bits of the bitstreams to be sent by the bus master (ECU) via the serial, bidirectional, differential communication bus (DB), depending on a clock signal (CLK) within the bus master (ECU). The bus master (ECU) receives bitstreams generated in the opposite direction by the bus nodes (BK1 to BKn) via the serial, bidirectional, differential communication bus (DB). Clock generators (CLKGj) within each of the n bus nodes (BK1 to BKn) generate a corresponding sampling signal (CLKAj) within each of these bus nodes (BK1 to BKn). The scanning device (ATj) of this respective bus node (BKj) of the n bus nodes (BK1 to BKn) then samples the bit streams transmitted via the serial, bidirectional, differential communication bus (DB) depending on the scanning signal (CLKAj) of this bus node (BKj).This can involve bitstreams from the bus master (ECU) to the bus nodes (BK1 to BKn), as well as bitstreams from other bus nodes (BK1 to BKn) to the bus master (ECU) or to other bus nodes (BK1 to BKn). The relevant bus node (BKj) extracts a local bitstream within itself from the signals on the serial, bidirectional, differential communication bus (DB), from the output of the receiver (Rec) by sampling the receiver's output signal (Rec) or a derived signal. The bus master (ECU) sends the bitstreams to be transmitted as sequences in bitstream packets (frames, BP). The bus nodes also preferably transmit their bitstreams as sequences in bitstream packets (frames, BP), which preferably correspond in structure to those of the bus master (ECU). For the sake of simplicity, only the bit stream packets (frames, BP) of the bus master (ECU) are discussed here.The same applies to the bit stream packets (BP) of the bus nodes (BK1 to BKn). As previously explained, this setup means that when neither the bus master (ECU) nor any of the n bus nodes (BK1 to BKn) is transmitting data over the serial, bidirectional, differential two-wire communication bus (DB), the DB assumes the first logical state (Z1) (dashed in Fig. 3) or the third logical state (Z3) - which is preferred. The proposed preferred structure of the bit stream packets (BP) sent by the bus master (ECU) is explained with the aid of Fig. 3. The signal designated Vdiff is intended to represent the differential level on the serial, bidirectional, differential communication bus (DB), i.e., the voltage difference between the first single-wire bus (DBa) and the second single-wire bus (DBb). The diagram labeled HS-CAN describes the corresponding levels when CAN drivers (TRa, TRb) are used. The diagram labeled RS485 represents the corresponding levels when RS485 drivers (TRa, TRb) are used. The drivers (TRa, TRb) provide three voltage levels in the HS-CAN scheme, but only two differential voltage levels. The drivers (TRa, TRb) provide two voltage levels and only two differential voltage levels in the RS485 scheme. It is proposed here that at least some of the bit stream packets (BP) sent by the bus master (ECU) contain the following: 1. a start signal (START) in the form of i bits, where i is a positive integer with i-1 ≤ m / 3, with a second logical differential state (z2) on the serial, bidirectional, differential two-wire communication bus (DB); 2. synchronization information (SYNC) for synchronizing the sampling signal (CLKAj) of the clock generators (CLKGj) of the bus nodes (BKj) with the clock (CLK) of the bus master (ECU); 3. data information (DATA) from the remaining bits of the mik bits of the m bits of the respective bit stream packet (BP), where the data information (DATA) includes address information (ADRD) and user information (INFO). The address recognition units (Adr1 to Adrn) of the bus nodes (BK1 to BKn) and, if applicable, also of the bus master (ECU), evaluate the address information (ADRD) of the bit stream packets (BP). The address recognition units (Adr1 to Adrn) of the bus nodes (BK1 to BKn) only allow the use of the contained payload information (INFO) if the content of the address information (ADRD) corresponds to the content of the bus node address register (BKADRj) of the bus node (BKj). Preferably, the bus nodes (BKj) of the n bus nodes (BK1 to BKn) have means to perform an auto-addressing procedure for a two-wire data bus in order to populate the bus node address register (BAKDRj) with a logical bus node address that corresponds to the physical position of that bus node (BKj) of the n bus nodes (BK1 to BKn) within the serial, bidirectional, differential two-wire communication bus (DB). This is an essential step that is not solved in the prior art. In a refinement of the method, each bus node (BKj) of the n bus nodes (BK1 to BKn) has a microcontroller (µCj) that can perform some of the previously mentioned tasks, such as the address recognition unit (ADRj) and / or the scanning device (ATj) of the respective bus node (BKj), via a software program. It is now proposed that preferably at least one bus node (BKj) of the n bus nodes (BK1 to BKn) also has at least one light source (LEDj) and at least one power supply (EVj). The at least one power supply (EVj) of the at least one bus node (BKj) of the n bus nodes (BK1 to BKn) is then provided for the power supply of the at least one light source (LEDj) of the at least one bus node (BKj) of the n bus nodes (BK1 to BKn). As before, the clock generator (CLKGj) of each of the n bus nodes (BK1 to BKn) generates a sampling signal (CLKAj) within that respective bus node (BKj). The sampling device (ATj) of preferably each of the n bus nodes (BK1 to BKn) again samples bit streams transmitted via the serial, bidirectional, differential two-wire communication bus (DB) based on the sampling signal (CLKAj) of that bus node (BKj) in order to obtain a local bit stream within that bus node (BKj). The bit stream packets (BP) preferably consist of a temporal sequence of m individual bits of equal time length tB, where m is a positive integer whose time length tBum does not vary by more than a factor of + / - (0.4 / m)*tBund / or better + / - (0.2 / m)*tBund / or better + / - (0.1 / m)*tBund / or better + / - (0.05 / m)*tB within a bit stream packet (BP).At least some of the bit stream packets (BP) sent by the bus master (ECU) preferably contain the following (see Fig. 3): 1. A start signal (START) in the form of i bits, where i is a positive integer with i-1 ≤ m / 3, with a second differential logic state (z2) on the serial, bidirectional, differential two-wire communication bus (DB); 2. Synchronization information (SYNC) consisting of k bits, where k is a positive integer, in particular with k <i, zur Phasensynchronisation des Abtastsignals (CLKAj) der Taktgeber (CLKGj) der Busknoten (BKj) auf die Phase des Takts (CLK) des Busmasters (ECU) aufweisen und zur Frequenzsynchronisation des Abtastsignals (CLKAj) der Taktgeber (CLKGj) der Busknoten (BKj) auf die Frequenz des Takts (CLK) des Busmasters (ECU); 3.Data information (DATA) from the remaining bits of the mik bits of the m bits of the respective bit stream packet (BP), wherein the data information (DATA) includes address information (ADRD), user information (INFO), and check information (CHKD). At least some of the user information (INFO) includes lighting information (ILD) for controlling the power supply to the lights (LEDs) of the bus node (BKj) by the bus node's power supply unit (EVj) based on this lighting information. Typically, a lighting register within the power supply unit (EVj) is written with a value dependent on the received lighting information (ILD), which determines the emission characteristics such as color, color temperature, and brightness of the connected lights (LEDs). For this data to be accepted by the relevant bus node (BKj), the logical content of the address information (ADRD) must match the content of the bus node's address register (BKADRj). If this is not the case, the data information (DATA) is ignored.The same applies if the integrity check of the received data information (DATA) using the also received check data (CHKD) reveals that the reception was faulty. The respective address recognition unit (ADRj) of each bus node (BKj) evaluates the address information (ADRD) of a received bit stream packet (BP) and only allows the use of the contained user information (INFO) by the rest of the bus node devices of the bus node (BKj) if the content of the received address information (ADRD) corresponds to the content of the bus node address register (BKADRj) of the bus node (BKj) and is error-free. In contrast to the prior art, bus nodes (BK1 to BKn) have means to perform an auto-addressing procedure for a serial, bidirectional, and differential communication bus (DB).As a result of such an auto-addressing procedure, the bus node address register (BAKDRj) of these bus nodes (BK1 to BKn) is filled with a logical bus node address that corresponds to the physical position of this bus node (BKj) of the n bus nodes (BK1 to BKn) within the serial, bidirectional, differential two-wire communication bus (DB). The tests described above can still be used. In a first variant of the device, the bus master (ECU) and / or bus nodes (BK1 to BKn) are equipped with means to conclude, based on the evaluation of the test information (CHKD), that a clock generator (CLKGj) of one or more bus nodes (BKj) is not functioning correctly. The following describes various exemplary auto-addressing methods and other variants that can be used as examples: Asymmetrical auto-addressing with bus shunt resistors that are not subject to the addressing current. It is typically desirable for the bus nodes (BK1 to BKn) to automatically determine their physical position within the data bus system in the serial, bidirectional, differential two-wire communication bus (DB) and receive a corresponding bus node address, so that the logical address corresponds to the physical address. This has the advantage that, for identically constructed bus nodes (BK1 to BKn), only one type of bus node needs to be kept in production, which improves error handling and logistics. To implement such auto-addressing, one could consider incorporating an auto-addressing mechanism. This is illustrated in Fig. 4. As an example, a first bus shunt resistor (R2) is inserted into the first single-wire bus (DBa) for each bus node (BK1 to BKn). A second differential amplifier (D2) is used to measure the initial current through the first single-wire bus (DBa) using the first shunt resistor (R2).The output of the second differential amplifier (D2), which measures the first current through the first single-wire bus (DBa), is connected to a third comparator (D3) that compares the output value of the second differential amplifier (D2) with a first reference value (Ref). This is equivalent to comparing the first current in the first single-wire bus (DBa) through the first bus shunt resistor (R2) with a first reference current (Iref). The data bus system, with its bus nodes (BK1 to BKn), can now be switched between an addressing state and a normal state by the bus master (ECU) using a special bus signal. During the addressing state, an auto-addressing procedure is performed. When the data bus system is in the addressing state, the bus nodes (BK1 to BKn) that can perform the auto-addressing procedure are in the corresponding addressing state.The first addressing current source (Iqj) (with 1≤j≤n) of the respective bus node (BKj) is switched off in the normal state or fulfills another function, such as supplying power to a light source (LEDj). The first addressing current source (Iqj) (with 1≤j≤n) of the respective bus node (BKj) is switched off in the addressing state when the respective bus node (BKj) detects, using these first means (R2, D2, D3), a first current through its first bus shunt resistor (R2) that is above this threshold value. In the example of Fig.4. The first addressing current source (Iqj) of each bus node (BKj) injects its first addressing current from the bus master (ECU) into the first single-wire bus (DBa) upstream of the first bus shunt resistor (R2) of the respective bus node (BKj) when the bus node (BKj) determines, using the previously described first means (R2, D2, D3), that only a first current below this threshold value flows through its first bus shunt resistor (R2) towards the bus master (ECU). This has the disadvantage that a self-test of the bus node (BKj) is not possible at this injection point of the first addressing current. Furthermore, the first driver (TRa) of the bus master (ECU) can be overloaded during the power-up process. Therefore, the first addressing current of the first addressing current sources (Iq1 to Iqn) must be limited to an nth part of the maximum current value that the first driver (TRa) can still accept.This limits the resistance value of the first bus shunt resistor (R2) from below, because otherwise the voltage drop across the first bus shunt resistor (R2) of a bus node (BKj) would be too small for detection by the first means (R2, D2, D3) of that bus node (BKj). This leads to increased sensitivity to electromagnetic interference, which should be avoided. Furthermore, the asymmetry between the first single-wire bus (DBa) and the second single-wire bus (DBb) of Fig. 4 leads to common-mode interference being coupled into the differential signal on the serial, bidirectional, differential two-wire communication bus (DB), which should also be avoided.If a bus node (BKj) in addressing state, after a certain predetermined waiting period following the entry into addressing state, detects that its first addressing current source (Iqj) is not yet switched off, it is the last bus node (BKj) not yet assigned a valid bus node address. It then adopts a bus node address typically offered by the bus master (ECU) as its new valid bus node address. Since it now has a valid bus node address, it switches off its addressing current source (Iqj) and waits for the end of the data bus system's addressing state without switching its addressing current source (Iqj) back on before this end.The next bus node (BKj-1) that determines in the next initialization run that its addressing current source (Iqj) is not switched off then adopts the next available bus node address offered by the bus master (ECU) as its valid bus node address, and so on. This continues until all bus nodes (BK1 to BKn) of the data bus system have received a valid bus node address in this way. The bus master then typically returns the data bus system and its bus nodes (BK1 to BKn) to their normal state, retaining the valid bus node addresses. This recommended retention of valid bus node addresses during the transition from the addressing state to the normal state is preferred throughout this document. Symmetrical auto-addressing with bus shunt resistors that are not subject to the addressing current. One problem that arises with auto-addressing, as mentioned, is that of symmetry. Since the serial, bidirectional, differential two-wire communication bus (DB) is a differential bus, the two single-wire buses (DBa and DBb) should be designed as symmetrically as possible to avoid common-mode interference. The data bus system should therefore include bus nodes (BKj) for the serial, bidirectional, differential two-wire communication bus (DB), which consists of a first single-wire bus (DB1) and a second single-wire bus (DB2), a first bus shunt resistor (R2) inserted into the first single-wire bus (DB1), and a second bus shunt resistor (R2') inserted into the second single-wire bus (DB2). A corresponding proposal based on Fig. 4 is shown in Fig. 5.The two bus shunt resistors (R2, R2') per bus node (BKj) of the bus nodes (BK1 to BKn) are preferably monolithically integrated and matched and manufactured with a relative resistance value deviation within the respective bus node (BKj) of less than 10% and / or better less than 5% and / or better less than 2% and / or better less than 1% and / or better less than 0.5%. Each bus node (BKj) of the bus nodes (BK1 to BKn) is now equipped with second means (R2', D2', D3') for detecting the second current through the first bus shunt resistor (R2) in the first single-wire bus (DBa), in addition to the first means (R2, D2, D3) for detecting the first current through the first bus shunt resistor (R2) in the second single-wire bus (DBb). As an example, a second bus shunt resistor (R2') is inserted into the second single-wire bus (DBb) for each bus node (BK1 to BKn). A further second differential amplifier (D2') measures the second current through the second single-wire bus (DBb) using the second shunt resistor (R2') of the respective bus node (BKj). The output of this second differential amplifier (D2'), which measures the second current through the second single-wire bus (DBb), is connected to a third comparator (D3'). This comparator compares the output value of the second differential amplifier (D2') with a further reference value (Ref'), which is typically equal to the first reference value (Ref).This is equivalent in effect to comparing the second current in the second single-wire bus (DBb) through the second bus shunt resistor (R2') with a second reference current (I'ref), which is typically chosen to be equal to the aforementioned first reference current (Iref). The second addressing current source (Iq'j) (with 1≤j≤n) of the respective bus node (BKj) is switched off when the respective bus node (BKj) detects, using these second means (R2', D2', D3'), a first current through its second bus shunt resistor (R2') that is above this threshold value. In the example of Fig.5. The respective second addressing current source (Iq'j) of a bus node (BKj) feeds the second addressing current from the bus master (ECU) into the second single-wire bus (DBb) upstream of the respective second bus shunt resistor (R2') of the respective bus node (BKj) if the bus node (BKj) determines, using the previously described second means (R2', D2', D3'), that only a second current below this threshold value flows through its second bus shunt resistor (R2') towards the bus master (ECU). As before, this has the disadvantage that a self-test of the bus node (BKj) is not possible. Furthermore, an overload of the second driver (TRb) of the bus master (ECU) can also occur here during the power-on process. Therefore, the second addressing current of the second addressing current sources (Iq'1 to Iq'n) must be limited to an nth part of the maximum current value that the second driver (TRb) can still accept.This limits the resistance value of the second bus shunt resistor (R2') from below, as otherwise the voltage drop across the second bus shunt resistor (R2') of a bus node (BKj) would be too small for detection by the second means (R2', D2', D3'). This leads to increased sensitivity to electromagnetic interference, which should be avoided. However, the symmetry between the first single-wire bus (DBa) of Fig. 5 and the second single-wire bus (DBb) of Fig. 5 already results in reduced coupling of common-mode interference into the differential signal on the serial, bidirectional, differential two-wire communication bus (DB), which is an advantage. Preferably, both addressing current sources (Iqj, Iq'j) of a bus node (BKj) are always switched off when the bus node (BKj) determines, using the first means described above (R2, D2, D3), that a first current above the threshold is flowing through its first bus shunt resistor (R2) towards the bus master (ECU), or, using the second means described above (R2', D2', D3'), that only a second current above this threshold is flowing through its second bus shunt resistor (R2') towards the bus master (ECU). Symmetrical auto-addressing with bus shunt resistors flowing through the addressing current. Fig. 6 now shows another proposal based on Fig. 5. The essential difference from Fig. 5 is that, from the perspective of the bus master (ECU), the respective first addressing current sources (Iq1 to Iqn) inject the first addressing current downstream of the first bus shunt resistors (R2) during the addressing phase, when the respective bus node (BKj) is in an addressing state. This occurs when the respective bus node (BKj) detects, using the first means (R2, D2, D3), a current value of the first current through the first bus shunt resistor (R2) that is smaller than a predetermined first reference current value (Iref). The third comparator (D3) is preferably a third differential amplifier (D3). In contrast to the proposal in Fig.In Figure 5, the first addressing current of the respective first addressing current source (Iqj) of the respective bus node (BKj) is now adjusted until the first current through the first bus shunt resistor (R2) corresponds to the predefined first reference current (Iref). Similarly, and in deviation from Figure 5, the respective second addressing current sources (Iq'1 to Iq'n), as seen from the bus master (ECU), also feed the respective second addressing current downstream of the corresponding second bus shunt resistors (R2') during the addressing phase, when the respective bus node (BKj) is in an addressing state, if the respective bus node (BKj) detects, by means of the second means (R2', D2', D3'), a current value of the second current through the second bus shunt resistor (R2) that is less than a predefined second reference current value (I'ref), which is preferably equal to the first reference current value (Iref).The third comparator (D3') is preferably another third differential amplifier (D3'). In contrast to the proposal in Fig. 5, the second addressing current of the respective second addressing current source (Iq'j) of the respective bus node (BKj) is now also adjusted until the second current through the second bus shunt resistor (R2') corresponds to the specified second reference current (I'ref). Of course, in the configuration shown in Fig. 6, it is possible to switch the addressing current sources (Iq1 to Iqn, Iq'1 to Iq'n) instead of regulating them. The proposed bus node (BKj) is thus equipped with a first addressing current source (Iqj) for determining the bus position of the bus node (BKj) in the serial, bidirectional, differential two-wire communication bus (DB). This first addressing current can be regulated and additionally fed into the first single-wire bus (DBa) of the serial, bidirectional, differential two-wire communication bus (DB) such that the first total current (ij) through the first bus shunt resistor (R2) of the bus node (BKj) corresponds to a predetermined, calculated, or otherwise determined first total current (Iref). Preferably, the first addressing current flows through the first bus shunt resistor (R2).Preferably, each bus node (BKj) is equipped with a second addressing current source (Iq'j) for determining the bus position of the bus node (BKj) in the serial, bidirectional, differential two-wire communication bus (DB). This second addressing current can be additionally fed into the second single-wire bus (DBb) of the serial, bidirectional, differential two-wire communication bus (DB) in such a way that the second total current (ij) through the second bus shunt resistor (R2') of the bus node (BKj) corresponds to a predefined, calculated, or otherwise determined second total current (I'ref). The second addressing current then flows through the second bus shunt resistor (R2'). For symmetry, it is advantageous if the two addressing current sources (Iqj, Iq'j) are implemented in a matching configuration.Furthermore, all measuring and controlling components of the control loop should be implemented matchingly for these two addressing current sources (Iqj, Iq'j) to achieve full symmetry. Figures 7, 8 to 9 illustrate the proposed advantageous properties of the control system. The control system is explained using the example of the control of the first addressing current sources (Iq1 to Iqn), but it also applies analogously to the second addressing current sources (Iq'1 to Iq'n). The control characteristic for the first addressing current source (Iqj) of a bus node (Bkj) is preferably generated by a first filter (F) that generates a first control signal (rwj) of the respective bus node (BKj) from the output signal of the third differential amplifier (D3), with which the first addressing current source (Iqj) of the respective bus node (BKj) is controlled.The control characteristic for the second addressing current source (Iq'j) of a bus node (Bkj) is preferably generated by a second filter or a second controller (F'), which generates a second control signal (rw'j) of the relevant bus node (BKj) from the output signal of the further third differential amplifier (D3'), with which the second addressing current source (Iq'j) of the relevant bus node (BKj) is controlled. Figure 7 shows, by way of example, the waveforms of the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2), and the output current (i3) of the third bus node (BK3) in an exemplary data bus system with n=3 bus nodes (BK1 to BK3). It also shows the first addressing current (I1_intern) of the first addressing current source (Iq1) of the first bus node (BK1), the first addressing current (I2_intern) of the first addressing current source (Iq2) of the second bus node (BK2), and the first addressing current (I3_intern) of the first addressing current source (Iq3) of the third bus node (BK3). Here, the time constants for the ramp-up and ramp-down of the first addressing current of the first addressing current sources are approximately equal. This results in an overshoot.It is clearly visible that the first addressing current (11_intern) of the first addressing current source (Iq1) of the first bus node (BK1) and the first addressing current (I2_intern) of the first addressing current source (Iq2) of the second bus node (BK2) are regulated down by the controllers of these first auto-addressing bus nodes, while the first addressing current (I3_intern) of the first addressing current source (Iq3) of the third bus node (BK3) is regulated to the reference value (Iref). The settling time is determined by a first time constant (τ1) for increasing the first addressing current of the first addressing current sources (Iq1 to Iq3). Fig. 8 shows the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2), and the output current (i3) of the third bus node (BK3). It also shows the current (I1_intern) of the first addressing current source (Iq1) of the first bus node (BK1), the current (I2_intern) of the first addressing current source (Iq2) of the second bus node (BK2), and the current (I3_intern) of the first addressing current source (Iq3) of the third bus node (BK3). Here, the first time constants (τ1) for increasing the first addressing current of the first addressing current sources are approximately ten times longer than the second time constants (τ2) for decreasing the first addressing current of the first addressing current sources. Only a minimal overshoot occurs. Fig. 9 shows the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2), and the output current (i3) of the third bus node (BK3). It also shows the first addressing current (I1_intern) of the first addressing current source (Iq1) of the first bus node (BK1), the first addressing current (I2_intern) of the first addressing current source (Iq2) of the second bus node (BK2), and the first addressing current (I3_intern) of the first addressing current source (Iq3) of the third bus node (BK3). Here, the first time constants (τ1) for increasing the first addressing current of the first addressing current sources are approximately one hundred times longer than the second time constants (τ2) for decreasing the first addressing current of the first addressing current sources. No overshoot occurs. Preferably, the bus node (BKj) includes first means (R2, D2) to detect the current through the first bus shunt resistor (R2) and / or second means (R2', D2') to detect the current through the second bus shunt resistor (R2'). If the data bus system is configured such that the first and second addressing currents of the two addressing current sources (Iqj, Iq'j) are always injected downstream of the bus shunt resistors (R2, R2') from the bus master (ECU), the current detected through the first bus shunt resistor (R2) and / or through the second bus shunt resistor (R2') can be used for a self-test. With perfect symmetry, the voltage drops across both bus shunt resistors (R2, R2') should ideally be equal. A cold solder joint, for example, can thus be easily detected. For fault detection, it is advantageous to equip the bus node (BKj) with a first detection device (DET) that checks the plausibility of the bus node's (BKj's) internal signals (ds1, ds3). These internal signals are preferably control signals within the bus node (BKj). In the case of bus symmetry, the symmetry of these signals can be checked, for example. However, checks per channel are also possible. Reference is made to the unpublished German patent application DE 10 2017 122 365.7 for further information. Fig. 10 illustrates the principle of such a detection. Fig. 10 shows the control loop of a bus node (BKj). Here, j represents a position in the bus chain of bus nodes (BK1 to BKn) in the form of a positive, integer, natural number. This is a j-th bus node (BKj) that is capable of: • firstly, detecting a swapping of its bus inputs with its bus outputs, and • secondly, in this case as an exemplary countermeasure: • positioning the injection point for the first addressing current of its regulated first addressing current source (Iqj) before or after its first bus shunt resistor (R2) so that auto-addressing is possible depending on the circuit configuration, and • positioning the injection point for the second addressing current of its regulated second addressing current source (Iq'j) before or after its second bus shunt resistor (R2') so that auto-addressing is possible depending on the circuit configuration. Figure 10 illustrates, by way of example, only the repositioning of the injection point of the first addressing current of the first addressing current source (Iqj) of the bus node (BKj) under consideration. The same applies to the repositioning of the injection point of the second addressing current of the second addressing current source (Iq'j) of the bus node (BKj) under consideration. The j-th auto-addressing bus node (BKj) shown as an example in Fig. 10 has a first detection device (DET) for repositioning the injection point of the first addressing current of the first addressing current source (Iqj) of the bus node under consideration (BKj). This detection device is capable of detecting a swap of the bus input of the j-th bus node (BKj) for the first single-wire bus (DBa) with the bus output of the j-th bus node (BKj) for the first single-wire bus (DBa). For this purpose, the exemplary first detection device (DET) checks the plausibility of internal signals of the j-th bus node (BKj). If the internal signals of the j-th bus node (BKj) allow for a reliable conclusion that the bus input of the j-th bus node (BKj) for the first single-wire bus (DBa) has been interchanged with the bus output of the j-th bus node (BKj) for the first single-wire bus (DBa), then the first detection device (DET) can potentially take various exemplary measures: a.a. Signaling the fault to a user; b. Signaling the fault to the bus master (ECU) by responding to a diagnostic request (broadcast message) or via an interrupt line; c. Using a predetermined fault address as a valid bus node address; d. Reconfiguring the internal topology to neutralize the fault; e. Reparameterizing internal sub-devices such as power sources to neutralize the fault. Further measures are conceivable. In the example shown in Fig. 10, a reconfiguration of the internal topology is provided to neutralize the error. In Fig. 10, the first detection device (DET) changes the injection point for the first addressing current of the regulated first addressing current source (Iqj) of the j-th bus node (BKj), for example, using a first analog multiplexer (X3), and reverses the polarity of the inputs or output of the second differential amplifier (D2) by means of the polarity signal (pol). For clarity, the analog device for the second single-wire bus (DBb) is not shown, as it is constructed similarly. The j-th auto-addressing bus node (BKj), shown in simplified form in Fig. 11, has a second detection device (DET') for repositioning the injection point of the second addressing current of the second addressing current source (Iq'j) of the bus node under consideration (BKj). This second detection device is capable of detecting a swap between the bus input of the j-th bus node (BKj) for the second single-wire bus (DBb) and the bus output of the j-th bus node (BKj) for the second single-wire bus (DBb). To this end, the exemplary second detection device (DET') checks further internal signals of the j-th bus node (BKj) for plausibility.If the internal signals of the j-th bus node (BKj) reliably indicate a swap of the bus input of the j-th bus node (BKj) for the second single-wire bus (DBb) with the bus output of the j-th bus node (BKj) for the second single-wire bus (DBb), the second detection device (DET') can potentially take various exemplary measures: a. Signaling the fault to a user; b. Signaling the fault to the bus master (ECU) by responding to a diagnostic request (broadcast message) or via an interrupt line; c. Using a fault address as a bus node address; d. Reconfiguring the internal topology to neutralize the fault; e. Reparameterizing internal sub-devices such as power sources to neutralize the fault. Further measures are conceivable. Here too, a reconfiguration of the internal topology can be provided to neutralize the error. For example, the second detection device (DET') can also change the injection point for the second addressing current of the regulated second addressing current source (Iq'j) of the j-th bus node (BKj) using a second multiplexer (X3') and reverse the polarity of the inputs or output of the further second differential amplifier (D2') by means of a second polarity signal (pol'). As an alternative to the preceding example in Fig. 10 and Fig. 11, reparameterization of internal sub-devices such as current sources to neutralize the error is possible if, instead of a first addressing current source (Iqj) of the j-th bus node (BKj) and a first multiplexer (X3), a first addressing current source (Iqj1) of the j-th bus node (BKj) and, for example, another first addressing current source (Iqj2) of the j-th bus node (BKj) are used, of which the first addressing current source (Iqj1) of the j-th bus node (BKj) feeds its first addressing current before the first bus shunt resistor (R2) and the other first addressing current source (Iqj2) of the j-th bus node (BKj) feeds its other first addressing current after the first bus shunt resistor (R2).In that case, the first detection device (DET) would set the first addressing current of one of the two first addressing current sources (Iqj1, Iqj2) to zero, so that the equivalent effect is achieved as when combining a first addressing current source (Iqj) of the j-th bus node (BKj) with switching by a first multiplexer (X3). For the second single-wire bus (DBb), instead of a second addressing current source (Iq'j) of the j-th bus node (BKj) and another second multiplexer (X3'), a second addressing current source (Iq'j1) of the j-th bus node (BKj) and, for example, another second addressing current source (Iq'j2) of the j-th bus node (BKj) would be used, of which the second addressing current source (Iq'j1) of the j-th bus node (BKj) feeds its second addressing current before the second bus shunt resistor (R2') and the other second addressing current source (Iq'j2) of the j-th bus node (BKj) feeds its other second addressing current after the second bus shunt resistor (R2').In that case, the second detection device (DET') would set the second addressing current of one of the two second addressing current sources (Iq'j1, Iq'j2) to zero, so that the equivalent effect is achieved as when combining a second addressing current source (Iq'j) of the j-th bus node (BKj) with switching by another second multiplexer (X3'). For example, the first detection device (DET) can recognize that the first control value of the first control signal (rwj) of the j-th bus node (BKj) maximizes the first addressing current of the first addressing current source (Iqj). With a suitable design, this can be achieved, for instance, by comparing the first control value of the first control signal (rwj) with a tenth threshold (Ref10). If the derivative of the first addressing current of the first auto-addressing current source (Iqj) with respect to the first control value of the first control signal (rwj) is positive, this means that the first control value of the first control signal (rwj) is above the tenth threshold (Ref10). Furthermore, the first detection device (DET) can simultaneously compare the output (ds2) of the second differential amplifier (D2) with an eleventh threshold (Ref11).If the output value (ds2) of the second differential amplifier (D2) is below the eleventh threshold (Ref11), the first detection device (DET) can infer a negative voltage drop across the first bus shunt resistor (R2) or a voltage drop close to zero across the first bus shunt resistor (R2). This condition is illegal because the first auto-addressing current source (Iqj) provides a positive first addressing current, which, if correctly installed, should flow through the first bus shunt resistor (R2), but this obviously does not happen. For example, the second detection device (DET') can also detect that the second control value of the second control signal (rw'j) of the j-th bus node (BKj) maximizes the second addressing current of the second addressing current source (Iq'j). This can be achieved, for example, with a suitable design, by comparing the second control value of the second control signal (rw'j) with a further tenth threshold (Ref10'), which is preferably equal to the tenth threshold (Ref10). If the derivative of the second addressing current of the second auto-addressing current source (Iq'j) with respect to the second control value of the second control signal (rw'j) is positive, this means that the second control value of the second control signal (rw'j) is above the further tenth threshold (Ref10'), which is preferably equal to the tenth threshold (Ref10).Furthermore, the second detection device (DET') can simultaneously compare the further output (ds2') of the further second differential amplifier (D2') with a further eleventh threshold (Ref11'). The further eleventh threshold (Ref11') is preferably equal to the eleventh threshold (Ref11). If the value of the further output (ds2') of the further second differential amplifier (D2') is below the further eleventh threshold (Ref11), the second detection device (DET') can conclude that there is a negative voltage drop across the second bus shunt resistor (R2') or that the voltage drop across the second bus shunt resistor (R2') is close to zero. This condition is illegal because the second auto-addressing current source (Iq'j) provides a positive second addressing current which, if correctly assembled, should flow through the second bus shunt resistor (R2'), but this obviously does not happen. Preferably, the first detection device (DET) and the second detection device (DET') form a unit. A switch in bus detection, as described above, preferably only occurs if both detection devices (DET, DET') detect a swap of the bus connections. The detection devices (DET, DET') can signal a detected error, for example, via a respective error signal (er, er') to a bus node, internal computer, or suitable control system. The test results can be used by the bus node (BKj) or a sub-device (DET, DET') of the bus node (BKj) to initiate and take predetermined actions if one or more of the detection devices (DET, DET') detect implausible internal signals within the bus node (BKj). For example, the bus node (BKj) might assume an input / output swap. To compensate for this, it is advantageous if the bus node (BKj) has a first sub-device (X3) that can change the injection point of the first addressing current of the first addressing current source (Iqj) and / or if the bus node (BKj) has a second sub-device (X3') that can change the injection point of the second addressing current of the second addressing current source (Iq'j).Preferably, the changes for controlling the first single-wire bus (DBa) and the first bus shunt resistor (R2) are made synchronously with the analogous changes for controlling the second single-wire bus (DBb) and the second bus shunt resistor (R2'). Instead of switching the input point of the addressing current sources (Iqjj and Iqj'j) using the aforementioned multiplexers (X3, X3'), it is also conceivable to use two different first addressing current sources (Iqj1 and Iqj2) instead of a single first addressing current source (Iqj), which transforms the switching using the multiplexer (X3) into switching between these two first addressing current sources (Iqj1 and Iqj2).Such a bus node (BKj) therefore has, instead of a first addressing current source (Iqj), a first addressing current source (Iqj1) and a second first addressing current source (Iqj2), wherein the first addressing current source (Iqj1) injects its first addressing current into a node connected to the first terminal of the first bus shunt resistor (R2) when it injects current, and wherein the second first addressing current source (Iqj1) injects its first addressing current into a node connected to the second terminal of the first bus shunt resistor (R2) when it injects current. The two first addressing current sources (Iqj1, Iqj2) preferentially inject their addressing currents such that the resulting total addressing current flows through the first bus shunt resistor (R2), thus ensuring self-test capability.In contrast to the prior art, the bus node (BKj) has, instead of a second addressing current source (Iq'j), a second addressing current source (Iq'j1) and a further second addressing current source (Iq'j2), wherein the second addressing current source (Iq'j1) feeds its addressing current into a node connected to the first terminal of the second bus shunt resistor (R2') when it supplies current, and wherein the further second addressing current source (Iq'j1) feeds its addressing current into a node connected to the second terminal of the second bus shunt resistor (R2') when it supplies current. These two second addressing current sources (Iq'j1, Iq'j2) also preferentially supply their addressing currents such that the addressing current flows through the second bus shunt resistor (R2') to ensure self-test capability. When multiple bus nodes are connected to a data bus, it is essential to prevent dangerous overcurrent situations caused by overshoot of the bus sum current. Therefore, it has proven advantageous for the first addressing current source (Iqj) to increase the first addressing current with a first time constant (τ1) and decrease it with a second time constant (τ2) that is smaller than the first time constant (τ1), and / or for the second addressing current source (Iq'j) to increase the second addressing current with a third time constant (τ3) and decrease it with a fourth time constant (τ4) that is smaller than the third time constant (τ3). Preferably, the third time constant (τ3) and the first time constant (τ1) are chosen to have the same magnitude to ensure bus symmetry even dynamically.For the same reason, the fourth time constant (τ4) and the second time constant (τ2) are preferably chosen to have the same absolute value in order to dynamically ensure bus symmetry here as well. Reference is again made here to Figures 7, 8 to 9. REDUCTION OF BUS RESISTANCE IN NORMAL OPERATION Reference is made here to Fig. 12. It has now been shown that the bus shunt resistors (R2, R2') degrade the properties of the single-wire buses (DBa, DBb) and thus of the serial, bidirectional, differential two-wire communication bus (DB). Therefore, it was recognized that it is advantageous to use a first bus shunt bypass switch (S4) for each bus node (BKj) to bypass the corresponding first bus shunt resistor (R2) of the bus node (BKj) during normal operation, i.e., in the normal state of the bus node (BKj), and to open this first bus shunt bypass switch (S4) only during addressing, thus allowing the first bus shunt resistor (R2) to become effective only during addressing.To avoid disturbing the bus symmetry, it is therefore also advisable to use a second bus shunt bypass switch (S4') for each bus node (BKj) to bridge the corresponding second bus shunt resistor (R2') of the bus node (BKj) during normal operation, i.e., in the normal state of the bus node (BKj), and to open this second bus shunt bypass switch (S4') only in the addressing state, thus allowing the second bus shunt resistor (R2') to become effective only in the addressing state. The bus node (BKj) described above is thus a bus node (BKj) capable of executing a procedure for assigning bus addresses to bus nodes of a serial, bidirectional, differential two-wire communication bus (DB). This procedure for assigning bus addresses to bus nodes (BK1, BK2, BK3, ... BKn-1, BKn) of a serial, bidirectional, differential two-wire communication bus (DB) is carried out using first bus shunt resistors (R2) and second bus shunt resistors (R2') in the individual bus nodes (BK1, BK2, BK3, ... BKn-1, BKn) during an assignment period in which the bus nodes (BK1 to BKn) are in an addressing state. This significantly distinguishes this procedure from the prior art. After carrying out the procedure for assigning bus addresses to the bus hubs (BK1, BK2, BK3, ......Following the assignment period of the serial, bidirectional, differential two-wire communication bus (DB) (BKn-1, BKn), an operating period ensues in which the bus nodes operate normally, i.e., are in a normal state. The bus node (BKj) is thus preferably characterized, compared to the prior art, by such a first bus shunt resistor (R2) and such a second bus shunt resistor (R2'). Preferably, the bus node (BKj) is each equipped with a first bus shunt bypass switch (S4) that is open before a bus address is assigned to the bus node (BKj) during the assignment period, and that is closed after a bus address is assigned to the bus node during the assignment period, and that remains closed during the operating period.Similarly, for symmetry reasons, a second bus shunt bypass switch (S4') is preferably provided in the bus node (BKj). This switch is open during the assignment period before a bus address is assigned to the bus node (BKj) and closed during the assignment period after a bus address has been assigned to the bus node (BKj), and closed during the operating period. These bus shunt bypass switches (S4, S4') significantly reduce the bus resistance and decrease the sensitivity to electromagnetic interference. They thus improve the EMC performance. Differential symmetrical common-mode and differential-mode based auto-addressing: Instead of a first addressing current from a first addressing current source (Iqj) of a bus node (BKj) and a second addressing current from a second addressing current source (Iq'j) of a bus node (BKj), a common-mode current source (GLIqj) of a bus node (BKj) with two outputs can also be used. Both outputs inject the same magnitude common-mode current into the first single-wire bus (DBa) and the second single-wire bus (DBb) of the serial bidirectional differential communication bus (DB) with the same sign. The first output of these two outputs thus corresponds to the first addressing current source (Iqj). The second output then corresponds to the second addressing current source (Iq'j). The first addressing current of the first addressing current source (Iqj) is then equal in magnitude to the second addressing current of the second addressing current source (Iq'j).The use of a single common-mode addressing current source (GLIqj) has the advantage that only one control system is required. Instead of a first addressing current from a first addressing current source (Iqj) of a bus node (BKj) and a second addressing current from a second addressing current source (Iq'j) of a bus node (BKj), a differential-mode current source (GGIqj) of a bus node (BKj) with two outputs can also be used. Both outputs feed the same magnitude differential-mode current into the first single-wire bus (DBa) and the second single-wire bus (DBb) of the serial bidirectional differential communication bus (DB), but with different signs. The first output of these two outputs corresponds to the first addressing current source (Iqj). The second output then corresponds to the second addressing current source (Iq'j). The first addressing current of the first addressing current source (Iqj) is then equal in magnitude but not in sign to the second addressing current of the second addressing current source (Iq'j).The use of a single push-pull addressing current source (GLIqj) also has the advantage that only one control system is required. Mixed solutions using common-mode and differential-mode addressing current sources are conceivable. Accordingly, a bus node (BKj) for a serial, bidirectional, differential two-wire communication bus (DB) with a bus master (ECU) is proposed here, in which the serial, bidirectional, differential two-wire communication bus (DB) comprises a first single-wire bus (DB1) and a second single-wire bus (DB2). A first bus shunt resistor (R2), inserted into the first single-wire bus (DB1), and a second bus shunt resistor (R2'), inserted into the second single-wire bus (DB2), are part of the bus node (BKj). The bus node also includes a differential first common-mode addressing current source (GLIqj) for determining the bus position of the bus node (BKj) in the serial, bidirectional, differential two-wire communication bus (DB).The differential first common-mode addressing current source (GLIqj) can additionally feed a first common-mode addressing current component into the first single-wire bus (DBa) of the serial, bidirectional, differential two-wire communication bus (DB) in such a controlled manner that the first total current (ij) through the first bus shunt resistor (R2) of the bus node (BKj) corresponds to a predetermined, calculated, or otherwise determined first total current (Iref).Simultaneously, the differential first common-mode addressing current source (GLlqj) can feed a second common-mode addressing current component, identical in magnitude and sign, into the second single-wire bus (DBb) of the serial, bidirectional, differential two-wire communication bus (DB). This second component is regulated with the same sign as the first differential-mode addressing current component, so that the second total current (i'j) through the second bus shunt resistor (R2') of the bus node (BKj) also corresponds to the specified, calculated, or otherwise determined first total current (Iref). The first common-mode addressing current component of the common-mode addressing current source (GLlqj) of the bus node (BKj) flows through the first bus shunt resistor (R2) of the bus node (BKj) towards the bus master (ECU).The second common-mode addressing current component of the common-mode addressing current source (GLlqj) of the bus node (BKj) flows through the second bus shunt resistor (R2') of the bus node (BKj) towards the bus master (ECU). Complementary to common-mode control, differential-mode control is also possible. Therefore, a bus node (BKj) for a serial, bidirectional, differential two-wire communication bus (DB) with a bus master (ECU) is proposed, in which the serial, bidirectional, differential two-wire communication bus (DB) comprises a first single-wire bus (DB1) and a second single-wire bus (DB2), and in which a first bus shunt resistor (R2) is inserted into the first single-wire bus (DB1) and a second bus shunt resistor (R2') is inserted into the second single-wire bus (DB2).The bus node (BKj) then has a differential first push-pull addressing current source (GGlqj) for determining the bus position of the bus node (BKj) in the serial, bidirectional, differential two-wire communication bus (DB), which can additionally feed a first push-pull addressing current component into the first single-wire bus (DBa) of the serial, bidirectional, differential two-wire communication bus (DB) in such a controlled manner that the first total current (ij) through the first bus shunt resistor (R2) of the bus node (BKj) corresponds to a predetermined or calculated or otherwise determined first sum current (Iref).The differential-mode addressing current source (GGlqj) of the bus node (BKj) feeds the second differential-mode addressing current component, of equal magnitude, into the second single-wire bus (DBb) of the serial, bidirectional, differential two-wire communication bus (DB), regulated with the opposite sign to the first differential-mode addressing current component, so that the second total current (i'j) through the second bus shunt resistor (R2') of the bus node (BKj) also corresponds to the specified, calculated, or otherwise determined first total current (Iref). The first differential-mode addressing current component of the differential-mode addressing current source (GGIqj) of the bus node (BKj) flows through the first bus shunt resistor (R2) of the bus node (BKj) towards the bus master (ECU).The second differential-mode addressing current component of the differential-mode addressing current source (GGIqj) of the bus node (BKj) flows through the second bus shunt resistor (R2') of the bus node (BKj) towards the bus master (ECU). For control purposes, the bus node (BKj) preferably has first means (R2, D2) to detect the current through the first bus shunt resistor (R2), and / or second means (R2', D2') to detect the current through the second bus shunt resistor (R2'). As previously explained, the ability to detect the voltage drop across the respective bus shunt resistor (R2, R2') can also be used for a self-test. Therefore, a bus node (BKj) is proposed where the detected current through the first bus shunt resistor (R2) is used for a self-test and / or where the detected current through the second bus shunt resistor (R2') is used for a self-test. Here, the detected voltage drop across the bus shunt resistor is compared with an expected value. If the detected voltage deviates from the expected value by more than a predefined amount, an error has occurred, which can be signaled. Preferably, the proposed bus node (BKj) comprises at least one detection device (DET) that checks the plausibility of internal signals (ds1, ds3) of the bus node (BKj). Preferably, the bus node (BKj) or a sub-device (DET) of the bus node (BKj) takes action when the detection device (DET) detects implausible internal signals within the bus node (BKj). One possible action can be initiated by a first sub-device (X3) of the bus node (BKj) and / or a second sub-device (X3') of the bus node (BKj) such that the injection points of the first common-mode addressing currents of the common-mode addressing current source (GLIqj) are changed by the first sub-device (X3) of the bus node (BKj) and / or the second sub-device (X3') of the bus node (BKj) upon detection of a predetermined error. Another possible measure can be initiated by a first sub-device (X3) of the bus node (BKj) and / or a second sub-device (X3') of the bus node (BKj) in such a way that the injection points of the first differential-mode addressing currents of the differential-mode addressing current source (GGlqj) are changed by the first sub-device (X3) of the bus node (BKj) and / or the second sub-device (X3') of the bus node (BKj) upon detection of a predetermined fault. Here too, regulating the addressing currents with specific time constants is desirable and recommended. Therefore, a bus node (BKj) is proposed where the common-mode addressing current source (GLIqj) increases the common-mode addressing current with a first time constant (τ1) and decreases it with a second time constant (τ2) that is smaller than the first time constant (τ1). Similarly, a bus node (BKj) is proposed in which the differential-mode addressing current source (GGlqj) increases the differential-mode addressing current with a first time constant (τ1) and decreases it with a second time constant (τ2) that is smaller than the first time constant (τ1). AUTO ADDRESSING VIA INTERRUPT LINE Figure 13 is based on Figure 2. In addition to the addressing method described above, the bus node (BKj) described above, which is intended for a data bus system with a serial, bidirectional, differential two-wire communication bus (DB), can be prepared for a different auto-addressing method (see Figure 13). The bus node in question (BKj) is then again intended to participate in a method for assigning logical bus node addresses to the bus nodes (BK1 to BKn) of the data bus system. The corresponding data bus system then has a bus master (ECU) with an address input (Adri0). The data bus system is again intended to have n bus nodes (BK1 to BKn), including this bus node (BKj) itself, where n is a positive integer.The bus node (BKj) is connected to the bus master (ECU) for data transmission via a data line section (DB1 to DBn) or the serial, bidirectional, differential two-wire communication bus (DB) consisting of data line sections (DB1 to DBn) and further bus nodes (BK2 to BKn). Within the data bus system, a line (L1 to Ln) originates from an address input (Adri0) of the bus master (ECU) and is looped through all bus nodes (BK1 to BKn) of the data bus system, including this bus node (BKj) itself, such that it is divided into n line sections (L1 to Ln) by the individual bus nodes (BK1 to BKn), including this bus node (BKj) itself. Each bus node (BKj) comprises an associated address input (Adrij) and an address output (Adroj) associated with that bus node (BKj).Each bus node (BKj) with 1≤j≤n-1, if it is not the nth bus node (BKn), is configured to have its address input (Adrij) connected to the address output (Adro(j+1)) of a subsequent bus node (BKj+1) with 1≤j≤n-1 via a line segment (Lj+1) belonging to the subsequent bus node (BKj+1). Each bus node (BKj), if it is not the first bus node (BK1), has its address output (Adroj) connected to the address input (Adri(j-1)) of a preceding bus node (BKj-1) with 2≤j≤n via a line segment (Lj) belonging to the bus node (BKj). The first bus node (BK1) is (j=1), with its address output (Adroj) connected to the address input (Adri0) of the bus master (ECU) via a line segment (L1) belonging to the bus node (BKj). The bus node address of the bus node (BKj) in its bus node address register (BKADRj) can be valid or invalid, as is discussed throughout this document.The proposed bus node now provides means and methods to set its bus node address and to make its bus node address valid or invalid. These can be, for example, specific data contents (DATA) from bit packets (BP) of the bus master (ECU), which the bus master (ECU) can use to force one, several, or all bus nodes (BK1 to BKn) to invalidate the addresses in their bus node address registers. The proposed bus node (BKj) can assume an addressing state and a second operating state (or normal state) different from the addressing state. The bus node (BKj) preferably has means to switch between the addressing state and the second operating state depending on instructions from the bus master (ECU).The bus node (BKj) then has means to, when it is in the addressing state and its bus node address is invalid, in this case to set the logical state at the address input (Adri(j-1)) of a preceding bus node (BKj-1) to a first logical value by overwriting, or to, when it is in the addressing state and its bus node address is invalid, in this case to set the logical state at the address input (Adri0) of a preceding bus master (ECU) to a first logical value by overwriting.The bus node (BKj) also preferably has means to set the logical state at its address input (Adrij) to a second logical value in the addressing state if this second logical value is not overwritten by a subsequent bus node (BKj+1) with a first logical value, and means to adopt a bus node address signaled by the bus master (ECU) as its valid future bus node address if its bus node address is invalid and if it is in the addressing state and if its address input (Adrij) has a second logical value, and to mark this future bus node address as "valid" in this case. In a refinement of this proposal, the address input (Adrij) of the bus node (BKj) can be used in the second operating state as the input of an interrupt signal from a subsequent bus node (BKj-1). In this way, an interrupt line can be used for the auto-addressing of bus nodes of a serial, bidirectional, differential two-wire communication bus (DB). Preferably, the address output (Adroj) of the bus node (BKj) can be used in the second operating state as the output of an interrupt signal from a subsequent bus node (BKj-1) and / or from the bus node (BKj) itself. Fig. 14 illustrates the basic sequence of the preferred address allocation procedure described here. After the address allocation procedure is started (START), the bus master (BM) signals, in a first step (1), preferably to one bus node or preferably to all or at least a subset of the bus nodes (BK1 to BKn) by means of a preferred first broadcast command, that such a procedure for allocating bus node addresses for these bus nodes is being initiated. This preferably results in all these bus nodes (BK1 to BKn) invalidating or deleting any valid bus node addresses that may already exist in these bus nodes. If addressing is to be carried out using an interrupt line (L1 to Ln) looped through all bus nodes as shown in Fig.In this preferred version of the proposal, if interrupt lines (L1 to Ln) are to be used for the duration of the addressing process, they lose their function and are split into the aforementioned point-to-point connections between the bus nodes (BK1 to BKn) and the point-to-point connection between the first LED bus node (BK1) and the bus master (BM). In a second process step (2), the bus master (ECU) informs the bus nodes (BK1 to BKn) that a bus node address is to be assigned and specifies which logical bus node address this is.The bus node, arbitrarily designated here as the j-th bus node (BKj) for clarity, whose address input (Adrij) contains a second logical value, then accepts the bus node address offered by the bus master (BM) in this step and sets its address output (Adroj) such that it no longer overwrites the address input (Adri(j-1)) of a preceding bus node (BKj-1) with the first logical value, but instead allows a second logical value at the address input (Adri(j-1)) of a preceding bus node (BKj-1). This second logical value is then preferentially imprinted at its address input (Adri(j-1)) by the preceding bus node (BKj-1) itself. In a further third step (3), the bus master (ECU) checks whether the logical value at its address input (Adri0) corresponds to a second logical value or not. If this is not the case (N), the bus master (ECU) repeats the second procedure step (2).If this logical value (J) is met, the bus master (ECU) terminates the process by executing a fourth process step (4). It may first perform a check to ensure the addresses were correctly assigned. Preferably, if all bus addresses have been successfully assigned, the bus master (ECU) sends a message to all bus nodes (BK1 to BKn) indicating that the bus node addresses have been assigned. This causes the bus nodes (BK1 to BKn) to return from the addressing state they entered in the first process step (1) to another operating state, preferably the normal operating state. In particular, after this fourth process step, the bus nodes (BK1 to BKn) resume using any looped interrupt line, possibly used for point-to-point connections, as an interrupt line. This concludes the proposed process (END). Symmetrical auto-addressing method via bus shunt resistors Here, a method for addressing the bus nodes (BK1 to BKn) of a data bus system using a symmetric method is discussed. This is an auto-addressing method for addressing the bus nodes (BK1 to BKn) of a data bus system based on a serial, bidirectional, differential two-wire communication bus (DB). The data bus system comprises a bus master (ECU), a serial, bidirectional, differential two-wire communication bus (DB) radiating from the bus master (ECU), and several addressable bus nodes (BK1 to BKn) connected to the serial, bidirectional, differential two-wire communication bus (DB). The serial, bidirectional, differential two-wire communication bus (DB) consists of the aforementioned first single-wire bus (DBa) and the aforementioned second single-wire bus (DBb). Each unaddressed bus node (BKj) of the bus nodes (BK1bis BKn) does not have a valid bus node address and therefore feeds a first addressing stream into the first single-wire bus (DBa) and a second addressing stream into the second single-wire bus (DBb) for identification purposes.All of these addressing streams flow through the serial, bidirectional, differential two-wire communication bus (DB) towards the bus master (ECU). Each unaddressed bus node (BKj) detects the first current flowing through the first single-wire bus (DBa) of the serial, bidirectional, differential two-wire communication bus (DB) and the second current flowing through the second single-wire bus (DBb) of the serial, bidirectional, differential two-wire communication bus (DB). Only those unaddressed bus nodes (BKj) that do not detect a first current, or only detect a first current that is lower than a predefined first threshold, and that simultaneously do not detect a second current, or only detect a second current that is lower than a predefined further first threshold, are identified as unaddressed bus nodes.The identified bus node is assigned an address for addressing purposes, thereby receiving a valid bus node address. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed. Preferably, the first threshold is equal to the next first threshold, and the value of the first addressing stream within a bus node is equal to the value of the second addressing stream within that bus node. In addition to addressed bus nodes (i.e., those with a valid bus node address), unaddressed bus nodes without a valid bus node address can also be connected to the serial, bidirectional, differential two-wire communication bus (DB). The unaddressed bus node injects a first quiescent current into the first single-wire bus (DBa) and a second quiescent current into the second single-wire bus (DBb). Each unaddressed bus node detects the first quiescent current flowing through the first single-wire bus (DBa) and the second quiescent current flowing through the second single-wire bus (DBb) before injecting the addressing currents. Only the unaddressed bus nodes with invalid bus node addresses inject the first addressing currents into the first single-wire bus (DBa) and the second addressing currents into the second single-wire bus (DBb).Only those unaddressed bus nodes that, when addressing currents are injected by all unaddressed bus nodes, detect no current difference between the first and second currents compared to the previous current detection, or only a current difference between the first and second currents that is smaller than a predefined second threshold, are identified as unaddressed bus nodes. An address is assigned to this identified bus node for addressing purposes, thereby giving it a valid bus node address. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed. The second threshold is preferably equal to the first threshold or to the subsequent first threshold. In another variant of the method, each addressable bus node injects a first quiescent current, which can be zero, into the first single-wire bus (DBa) and a second quiescent current, which can also be zero, into the second single-wire bus (DBb). Each unaddressed bus node without a valid bus node address injects a first quiescent current into the first single-wire bus (DBa) and a second quiescent current into the second single-wire bus (DBb). Each unaddressed bus node detects the first current flowing through the first single-wire bus (DBa) due to the quiescent current injection and the second current flowing through the second single-wire bus (DBb) due to the quiescent current injection.The process determines which of the unaddressed bus nodes detects a first current above a predefined third threshold, and which detects a second current above a predefined third threshold. Only those unaddressed bus nodes that detect a first current less than or equal to the third threshold when quiescent currents are applied feed first addressing currents into the first single-wire bus (DBa). Only those unaddressed bus nodes that detect a second current less than or equal to the third threshold when quiescent currents are applied preferentially feed second addressing currents into the second single-wire bus (DBb).It is preferred at this point if only those bus nodes that are not yet addressed, which detect a first current that is less than or equal to the third threshold when the quiescent currents are injected, and which simultaneously detect a second current that is less than or equal to the further third threshold when the quiescent currents are injected, inject first addressing currents into the first single-wire bus (DBa) and / or second addressing currents into the second single-wire bus (DBb). From the group of unaddressed bus nodes injecting these addressing streams, only the one that detects no first stream, or only a first stream lower than a predefined fourth threshold, and no second stream, or only a second stream lower than a predefined fourth threshold, is identified as an unaddressed bus node. An address is assigned to the bus node thus identified. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed. Preferably, the third and / or fourth threshold, and / or the further third and / or fourth threshold, and the first threshold are the same. In one variant of the method, in addition to the addressable bus nodes, non-addressable bus nodes are also connected to the serial, bidirectional, differential two-wire communication bus (DB). Such a non-addressable bus node injects a first quiescent current into the first single-wire bus (DBa) and a second quiescent current into the second single-wire bus (DBb). Before injecting the first addressing currents into the first single-wire bus (DBa), each unaddressed bus node determines the first current flowing in the first single-wire bus (DBa) due to the quiescent current injection from all non-addressable bus nodes by means of a first current detection. Each unaddressed bus node determines the second current flowing in the second single-wire bus (DBb) due to the quiescent current injection from all non-addressable bus nodes by means of a second current detection before injecting the second addressing currents into the second single-wire bus (DBb).Subsequently, each addressable bus node injects a first quiescent current into the first single-wire bus (DBa) and a second quiescent current into the second single-wire bus (DBb). The system then identifies which of the unaddressed bus nodes detects a first current in the first single-wire bus (DBa) that exceeds a predefined fifth threshold, and / or a second current in the second single-wire bus (DBb) that exceeds a predefined further fifth threshold. Only those unaddressed bus nodes that detect a first current less than or equal to the fifth threshold when the first quiescent currents are injected into the first single-wire bus (DBa) then inject initial addressing currents into the first single-wire bus (DBa).Only those bus nodes that have not yet been addressed and detect a second current less than or equal to the fifth threshold when the second quiescent currents are injected into the second single-wire bus (DBb) inject second addressing currents into the second single-wire bus (DBb). However, it is particularly preferred if only those bus nodes that detect a first current less than or equal to the fifth threshold when the first quiescent currents are injected into the first single-wire bus (DBa), and that simultaneously detect a second current less than or equal to the fifth threshold when the second quiescent currents are injected into the second single-wire bus (DBb), inject first addressing currents into the first single-wire bus (DBa) and second addressing currents into the second single-wire bus (DBb). From the group of unaddressed bus nodes feeding in these addressing streams, only those nodes that detect no current difference of the first current, or only a current difference of the first current less than a predefined sixth threshold, and that detect no current difference of the second current, or only a current difference of the second current less than a predefined sixth threshold, are identified as unaddressed. An address is then assigned to each of these identified bus nodes for addressing purposes. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed.The fifth threshold and / or the sixth threshold and / or the further fifth threshold and / or the further sixth threshold and / or the first threshold are preferably the same. The first current detection preferably takes place in the bus nodes via the first bus shunt resistors (R2) of the first single-wire bus (DBa) assigned to the addressable bus node, and the second current detection preferably takes place in the bus nodes via the second bus shunt resistors (R2') of the second single-wire bus (DBb) assigned to the addressable bus node. The first bus shunt resistors (R2) assigned to an addressable bus node preferably correspond, at least in value, to the second bus shunt resistors (R2') assigned to the respective addressable bus node. All first bus shunt resistors (R2) are preferably connected in series along the first single-wire bus (DBa), and all second bus shunt resistors (R2') are preferably connected in series along the second single-wire bus (DBb). Instead of current detection, voltage detection can also be performed in the bus nodes. The assignment of an address typically occurs by transmitting an address to the identified bus node, whereby all unaddressed bus nodes are each given the same address before the identification of a bus node, and only the subsequently identified bus node accepts this address as its bus node address. Preferably, an address is assigned after the initial identification of a bus node and / or the bus node address is verified after the identification of a bus node. Verification of the identification of a bus node can be carried out, for example, by re-identifying the bus node and / or by identifying the bus node using the other single-wire bus and comparing the second identification with the first identification. Verification of a participant's identification can also be achieved by re-identifying the participant using a different auto-addressing method and comparing the second identification with the first. Any errors that occur during this process are signaled. ASYMMETRIC AUTOADDRESSING METHOD VIA BUS SHUNT RESISTORS The data bus system comprises a bus master (ECU), a serial, bidirectional, differential two-wire communication bus (DB) radiating from the bus master (ECU), and several addressable bus nodes (BK1 to BKn) connected to the serial, bidirectional, differential two-wire communication bus (DB). The serial, bidirectional, differential two-wire communication bus (DB) itself consists of a first single-wire bus (DBa) and a second single-wire bus (DBb). In the first auto-addressing method discussed here, each unaddressed bus node (BKj) of the bus nodes (BK1 to BKn) injects an addressing current into at least one of the single-wire buses (DBa, DBb) for identification purposes. Each unaddressed bus node injects the addressing current into at least one single-wire bus, hereinafter referred to as the addressing single-wire bus. However, it is preferred if this addressing current is fed into both single-wire buses (DBa, DBb).All other unaddressed bus nodes also feed their respective addressing currents into the addressing single-wire bus. All addressing currents flow through the serial, bidirectional, differential two-wire communication bus (DB) towards the bus master (ECU). Each unaddressed bus node (BKj) detects the current flowing through the addressing single-wire bus of the serial, bidirectional, differential two-wire communication bus (DB). This detection is preferably performed via the bus shunt resistors (R2, R2') mentioned above. Only those unaddressed bus nodes (BKj) that detect no current or only a current lower than a predefined first threshold are identified as unaddressed. An address is then assigned to this identified bus node for addressing purposes, thus giving it a valid bus node address.This is preferably determined by the bus master (ECU). The previously mentioned steps are repeated without the last addressed bus node, i.e., another initialization cycle is performed until all unaddressed bus nodes have been addressed. It can happen that, in addition to the addressed bus nodes, one or more unaddressed bus nodes are connected to the serial, bidirectional, differential two-wire communication bus (DB), and these unaddressed nodes inject quiescent currents into the addressing single-wire bus. In this case, the previously described procedure must be modified. This modification requires that each unaddressed bus node detects the quiescent current flowing through the addressing single-wire bus before injecting the addressing currents. Only the unaddressed bus nodes then inject the addressing currents into the addressing single-wire bus.Only the unaddressed bus node that, when addressing currents are injected by all unaddressed bus nodes, detects no current difference compared to the previous current detection, or only a current difference smaller than a predefined second threshold, is identified as an unaddressed bus node. An address is assigned to this identified bus node for addressing purposes, thus giving it a valid bus node address. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed. Preferably, the second threshold is equal to the first threshold. It is also possible that every addressable bus node injects a quiescent current into the addressing single-wire bus, and that every unaddressed bus node injects a quiescent current into the addressing single-wire bus. The procedure is then modified similarly to the one described above: Each unaddressed bus node again detects the current flowing through the addressing single-wire bus due to the quiescent current injection. A circuit within the bus nodes (BKj) then determines which of the unaddressed bus nodes detects a current that is above a predefined third threshold. Only those unaddressed bus nodes that detect a current less than or equal to the third threshold when the quiescent currents are injected feed addressing currents into the addressing single-wire bus.From the group of unaddressed bus nodes injecting addressing streams, only the node that detects no current or only a current less than a predefined fourth threshold is identified as an unaddressed bus node. This identified bus node is then assigned an address, thus receiving a valid bus node address. The aforementioned steps are repeated without the most recently addressed bus node until all unaddressed bus nodes have been addressed. Preferably, the third and / or fourth threshold is also equal to the first threshold. It can again occur that, in addition to the addressable bus nodes, at least one non-addressable bus node is connected to the serial, bidirectional, differential two-wire communication bus (DB), which injects a quiescent current into the addressing single-wire bus. Again, the procedure is appropriately modified: Before injecting the addressing currents, each unaddressed bus node determines the current flowing in the addressing single-wire bus due to the quiescent current injection from all non-addressable bus nodes by means of an initial current detection. Subsequently, each addressable bus node injects a quiescent current into the addressing single-wire bus. The system then determines which of the unaddressed bus nodes detects a current above a predefined fifth threshold.Only those unaddressed bus nodes that detect a current less than or equal to the fifth threshold when quiescent currents are injected feed addressing currents into the addressing single-wire bus. From this group of unaddressed bus nodes injecting addressing currents, only the node that detects no current difference compared to the first current detection, or only a current difference less than a predefined sixth threshold, is identified as an unaddressed bus node. An address is assigned to this identified bus node for addressing purposes, thus giving it a valid bus node address. The aforementioned steps are repeated without the most recently addressed bus node until all unaddressed bus nodes have been addressed.Again, the fifth threshold and / or sixth threshold is preferably equal to the first threshold. Current detection in the bus nodes is preferably achieved via the shunt resistors of the addressing single-wire bus assigned to the addressable bus nodes. In the other single-wire bus, which is not the addressing single-wire bus, further bus shunt resistors assigned to the addressable participants are preferably, but not necessarily, arranged in the participants. These shunt resistors preferably have values ​​corresponding to the shunt resistors in the addressing single-wire bus. Most preferably, the bus shunt resistors (R2, R2') in the two single-wire buses (DBa, DBb) are matched. All shunt resistors in the addressing single-wire bus along its length are preferably connected in series. All shunt resistors in the other single-wire bus along this other single-wire bus are also preferably connected in series. It is possible to perform voltage detection instead of current detection in the bus nodes. One variant of the procedure provides that the assignment of an address is carried out by transmitting an address to the identified bus node or by transmitting the same address to all bus nodes that have not yet been addressed before the identification of a bus node, and that only the subsequently identified bus node accepts this address as its bus node address. Another variant of the proposed procedure provides that the assignment of an address takes place after the initial identification of a bus node, or that verification of the bus node address takes place after the identification of a bus node. Another variant of the proposed procedure provides that the verification of the identification of a bus node is carried out by re-identifying the bus node and / or by identifying the bus node using the other single-wire bus and comparing the second identification with the first identification. Another variant of the proposed procedure involves verifying a participant's identification by re-identifying the participant using a different auto-addressing method and comparing the second identification with the first. Preferably, the bus node and / or the bus master then signal an error. Symmetrical auto-addressing method via bus shunt resistors with self-test capability and addressing current control Furthermore, a self-testable auto-addressing procedure for assigning bus node addresses within a data bus system is proposed. The data bus system comprises a serial, bidirectional, differential two-wire communication bus (DB) with a chain of n bus nodes (BK1, BK2, BK3, ..., BKn-1, BKn), where n is a positive integer greater than zero, and a bus master (ECU). The serial, bidirectional, differential two-wire communication bus (DB) is connected to the bus master (ECU). Each bus node (BK2, BK3, ..... BKn-1, BKn) has a preceding bus node (BK1, BK2, BK3, ..... BKn-1) if it is not the first bus node (BK1), and each bus node (BK2, BK3, ..... BKn-1, BKn) is connected to its preceding bus node (BK1, BK2, BK3, ..... BKn-1) by the serial, bidirectional, differential two-wire communication bus (DB) via a connecting section of the serial, bidirectional, differentialThe first bus node (BK1) is connected to the two-wire communication bus (DB) if it is not the first bus node (BK1). The serial, bidirectional, differential two-wire communication bus (DB) consists of a first single-wire bus (DBa) and a second single-wire bus (DBb). The first bus node (BK1) is connected to the bus master (ECU) via the serial, bidirectional, differential two-wire communication bus (DB) by means of a connecting section of the serial, bidirectional, differential two-wire communication bus (DB). Each bus node (BK2, BK3, ..... BKn-1, BKn) sends a first bus node output current (i2, i3, ...i(n-1), in) via the section (DB1) of the first single-wire bus (DBa), which is part of the connecting section between that bus node (BK2, BK3, ..... BKn-1, BKn) and its preceding bus node (BK1, BK3, ..... BKn-1, BKn-1), to its preceding bus node (BK1, BK2, BK3, ..... BKn-1) if it is not the first bus node (BK1). Each bus node (BK2, BK3, ..... BKn-1,BKn) sends a second bus node output current (i'2, i'3,...i'(n-1), i'n) via section (DB2) of the second single-wire bus (DBb), which is part of the connection section between this bus node (BK2, BK3, ..... BKn-1, BKn) and its preceding bus node (BK1, BK3, ..... BKn-1, BKn-1), to its preceding bus node (BK1, BK2, BK3, ..... BKn-1), if it is not the first bus node (BK1). The first bus node (BK1) sends a first bus node output current (i1) via section (DB1) of the first single-wire bus (DBa), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), to the bus master (ECU). The first bus node (BK1) sends a second bus node output current (i2) via section (DB2) of the second single-wire bus (DBb), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), to the bus master (ECU). The bus master (ECU) receives a first bus node input current (i1) via theSection (DB1) of the first single-wire bus (DBa), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), receives a second bus node input current (i'1) from its subsequent first bus nodes (BK1) via section (DB2) of the second single-wire bus (DBb), which is part of the connection section between the first bus node (BK1) and the bus master (ECU). Each bus node (BK1, BK2, ... BKn-1) receives a first bus node input stream (i2, i3, ... i(n-1), i) via the section (DB1) of the first single-wire bus (DBa), which is part of the connecting section between that bus node (BK2, BK3, ... BKn-1, BKn) and its preceding bus node (BK1, BK3, ... BKn-1, BKn-1), from its subsequent bus nodes (BK2, BK3, ... BKn-1, BKn), if it is not the last bus node (BKn). Each bus node (BK1, BK2, ... BKn-1) receives a secondThe bus node input current (i2, i3, ...i(n-1), in) is transmitted via the section of the second single-wire bus (DBb), which is part of the connection between this bus node (BK2, BK3, ..... BKn-1, BKn) and its preceding bus node (BK1, BK3, ..... BKn-1, BKn-1), from its subsequent bus nodes (BK2, BK3, ..... BKn-1, BKn), if it is not the last bus node (BKn). This method, unlike the one described previously, therefore uses both single-wire buses (DBa and DBb) for transmitting the addressing streams. First, a maximum addressing stream (Iamax) is determined. The following is the execution of an initialization sequence, which includes the following steps, for each auto-addressing bus node of the n bus nodes (BK1, BK2, ..... BKn-1, BKn) that does not yet have a valid bus node address, until all auto-addressing bus nodes of the n bus nodes (BK1, BK2, ..... BKn-1, BKn) have a valid bus node address: • Signaling a bus address to be assigned to allAuto-addressing bus node of the n bus nodes (BK1, BK2, ..... BKn-1, BKn); • Performing the following steps for each auto-addressing bus node (BKj) of the auto-addressing bus nodes of the n bus nodes (BK1, BK2, ..... BKn-1, BKn), hereinafter referred to as the respective auto-addressing bus node (BKj): ▪ Receipt of said auto-addressing command from the bus master (ECU) by the respective auto-addressing bus node (BKj); ▪ Receipt of the bus address to be assigned from the bus master (ECU) by the respective auto-addressing bus node (BKj); ▪ Receipt of a start signal for the assignment of the bus address to be assigned from the bus master (ECU) by the respective auto-addressing bus node (BKj) and start of a timer by the respective auto-addressing bus node (BKj); ▪ Feeding the data from the subsequent bus nodes (BKj+1, BKj+2... BKn-1, BKn) received first bus input current (i(j+1)) via the section (DB1) of the first single-wire bus (DBa), which is part of the connection section of theserial, bidirectional, differential two-wire communication bus (DB) between the relevant auto-addressing bus node (BKj) and the preceding (j-1)th bus node (BKj-1), as part of the first bus output current (ij) of the relevant auto-addressing bus node (BKj); • Injecting the second bus input current (i'(j+1)) received by the subsequent bus nodes (BKj+1, BKj+2...) via the section (DB2) of the second single-wire bus (DBb), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the relevant auto-addressing bus node (BKj) and the preceding (j-1)th bus node (BKj-1), as part of the second bus output current (i'j) of the relevant auto-addressing bus node (BKj); ▪ Capturing the first Value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) using first measuring instruments (R2, D2, D3); ▪ Acquisition of the second value of the secondBus node output current (i'j) of the relevant auto-addressing bus node (BKj) by means of second measuring devices (R2', D2', D3'); ▪ Generation of a first control signal (rwj) from the detected first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) by means of first control devices (F); ▪ Generation of a second control signal (rw'j) from the detected second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) by means of second control devices (F'); ▪ Regulation of the first bus node output current (ij) by the relevant auto-addressing bus node (BKj), by means of a first controlled auto-addressing current source (Iqj), whose first addressing current represents a portion of the first bus output current (ij), to a first predetermined total current value (Iref) depending on the generated first control signal (rwj), wherein an increase in the first addressing stream of the first regulatedAuto-addressing current source (Iqj) of the relevant auto-addressing bus node (BKj) with a first time constant (τ1) is used, and wherein the first addressing current of the first controlled auto-addressing current source (Iqj) of the relevant auto-addressing bus node (BKj) is reduced by a second time constant (τ2), and wherein the second time constant (τ2) is smaller than the first time constant (τ1); ▪ Control of the second bus node output current (i'j) by the relevant auto-addressing bus node (BKj) by means of a second controlled auto-addressing current source (Iq'j), whose second addressing current represents a portion of the second bus output current (i'j), to a second predetermined sum current value (I'ref) depending on the generated second control signal (rw'j), and wherein the second addressing current of the second controlled auto-addressing current source (Iq'j) of the relevant auto-addressing bus node is increased (BKj) with a thirdtime constant (τ3) and wherein a reduction of the second addressing current of the second controlled auto-addressing current source (Iq'j) of the relevant auto-addressing bus node (BKj) with a fourth time constant (τ4) is performed and wherein the fourth time constant (τ4) is smaller than the third time constant (τ3); ▪ comparison of the first control value (rj) of the first control signal (rwj) of the relevant auto-addressing bus node (BKj) with a first threshold value (SWj) of the relevant auto-addressing bus node (BKj); ▪ comparison of the second control value (r'j) of the second control signal (rw'j) of the relevant auto-addressing bus node (BKj) with a second threshold value (SW'j) of the relevant auto-addressing bus node (BKj); ▪ freezing of the control of the first addressing current source (Iqj) of the relevant auto-addressing bus node (BKj) at a first time point t1 after the start of the timer; ▪ Freezing of the control of the second addressing current source (Iq'j) of theThe relevant auto-addressing bus node (BKj) at a second time t2 after the start of the timer; ▪ Adoption of the bus node address to be assigned from the bus master (ECU) as the valid bus node address of the relevant auto-addressing bus node (BKj) if a minimum time has elapsed since the start of the timer and if the comparison of the first control value (rj) with the first threshold value (SWj) shows that the first addressing current of the first addressing current source (Iqj) of the relevant auto-addressing bus node (BKj) is above a current threshold value in magnitude and / or if the comparison of the second control value (r'j) with the second threshold value (SW'j) shows that the second addressing current of the second addressing current source (Iqj) of the relevant auto-addressing bus node (BKj) is above a current threshold value in magnitude and configuration of the relevant auto-addressing bus node (BKj) as a bus node without auto-addressing capability with the toThe assigned bus node address is recognized as the valid bus node address of the respective auto-addressing bus node (BKj) at a third time t3 after the first time t1 and after the second time t2, thereby preventing this auto-addressing bus node (BKj) from participating in subsequent initialization sequences until further notice. • Verification of successful address assignment by the bus master (ECU); • If necessary, deletion of the validity of the last assigned bus node address, causing the respective auto-addressing bus nodes (BKj) to behave again as auto-addressing bus nodes (BKj) without a valid bus node address; • Verification that all auto-addressing bus nodes have received a valid bus node address; • Execution of another initialization sequence if not all auto-addressing bus nodes have received a valid bus node address. This basic procedure can be supplemented with an additional step after or concurrently with the assignment of the bus node address. This step then involves bridging the first bus shunt resistor (R2) using a first bus shunt bypass switch (S4) and / or bridging the second bus shunt resistor (R2') using a second bus shunt bypass switch (S4') when transitioning from the addressing state with an invalid bus node address for the respective bus node (BKj) to the addressing state with a valid bus node address for the respective bus node (BKj), or when transitioning to the normal state. This approach has the advantage of reducing the bus resistance during operation (normal state after address assignment). When transitioning to auto-addressing mode (addressing state) or to normal mode, the bus shunt resistors (R2, R2') are re-bridged. This involves opening the first bus shunt bypass switch (S4) if the bus node address of the relevant auto-addressing bus node (BKj) is invalid, and / or opening the second bus shunt bypass switch (S4') if the bus node address of the relevant auto-addressing bus node (BKj) is invalid. The third time constant (τ3) is preferably chosen to be smaller than the first time constant (τ1) and the second time constant (τ2) by a factor greater than 10. In one variant of the method, the third time constant (τ3) preferably depends within the respective auto-addressing bus node (BKj) on the first value of the first bus node output current (ij) of the respective auto-addressing bus node (BKj), as measured by first measuring instruments (R2, D2, D3), and / or on the second value of the second bus node output current (i'j) of the respective auto-addressing bus node (BKj), as measured by second measuring instruments (R2', D2', D3'). Preferably, the first time constant (τ1) within the relevant auto-addressing bus node (BKj) depends on the first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) detected by means of first measuring means (R2, D1, D3) and / or the second time constant (τ2) within the relevant auto-addressing bus node (BKj) depends on the second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) detected by means of second measuring means (R2', D1', D3'). The first time constant (τ1) within the relevant auto-addressing bus node (BKj) can depend on the value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) as measured by first measuring instruments (R2, D2, D3) in such a way that the value of the first time constant (τ1) has a first value below a threshold and a second value above this threshold, and / or depend on the value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) as measured by second measuring instruments (R2', D2', D3') in such a way that the value of the second time constant (τ2) has a third value below a threshold and a fourth value above this threshold. It is important to note that the technology disclosed here enables a self-test. Therefore, it is advantageous to additionally check the plausibility of the recorded first value of the first bus node output current (ij) and / or the recorded second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) and, if necessary, to initiate measures if the recorded first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) and / or the recorded second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj), or their combination, are implausible. Preferably, the injection point of the first addressing current (ij) is recalculated if the detected first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) is implausible. Similarly, preferably, the injection point of the first addressing current (ij) and the injection point of the second addressing current (i'j) are recalculated analogously if the detected first value of the first bus node output current (ij) and / or the detected second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) and / or their combination are implausible. In one variant, a fault is preferably signaled via the serial bidirectional differential communication bus (DB) upon request by a bus master (ECU) if the detected first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) and / or the detected second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) or their combination are implausible. In one variant of the procedure, the step of acquiring the first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) using first measuring instruments (R2, D1, D3) is carried out as acquiring the first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) using first measuring instruments (R2, D1, D3) with a first sign if the acquired first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) is plausible, and acquiring the first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) using first measuring instruments (R2, D1, D3) with a second sign that is inverted to the first sign if the acquired first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) is not plausible. In another variant of the procedure, relating to the other single-wire bus, the step of acquiring the second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) using second measuring instruments (R2', D1', D3') is carried out as follows: The step comprises acquiring the second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) using second measuring instruments (R2', D1', D3') with a first sign if the acquired second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) is plausible, and acquiring the second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) using second measuring instruments (R2', D1', D3') with a second sign that is inverted to the first sign.if the detected second value of the second bus node output stream (i'j) of the relevant auto-addressing bus node (BKj) is not plausible. Another variant of the procedure additionally includes acquiring the second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) using second measuring instruments (R2', D1', D3') in the following manner: This step first comprises acquiring the second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) using second measuring instruments (R2', D1', D3') with a first sign if the previously acquired first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) is plausible and if the previously acquired second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) is plausible, and acquiring the second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) using second measuring instruments. (R2', D1', D3') with a second sign,which is inverted with respect to the first sign if the previously detected first value of the first bus node output stream (ij) of the relevant auto-addressing bus node (BKj) is implausible or if the previously detected second value of the second bus node output stream (i'j) of the relevant auto-addressing bus node (BKj) is implausible. For the purposes of this disclosure, two values ​​are plausible if they are the result of two different tests which, by their very design, should not necessarily produce identical results, but rather similar ones, and which are equal to each other. Equality here means that the magnitude of the norm of the results deviates by less than a predetermined threshold. Two values ​​are not plausible within the meaning of this disclosure if they are the result of two different tests which, due to their design, should not necessarily produce an identical, but rather a similar result, and which are not identical to each other. Furthermore, this variant includes performing the step of acquiring the first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) using first measuring instruments (R2, D1, D3) in the following manner: The step includes acquiring the first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) using first measuring instruments (R2, D1, D3) with a first sign if the previously acquired first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) is plausible and if the previously acquired second value of the second bus node output current (i'j) of the relevant auto-addressing bus node (BKj) is plausible, and acquiring the first value of the first bus node output current (ij) of the relevant auto-addressing bus node (BKj) using first measuring instruments (R2, D1, D3) with a second sign, which is inverted to the first sign,if the previously detected first value of the first bus node output stream (ij) of the relevant auto-addressing bus node (BKj) is not plausible, or if the previously detected second value of the second bus node output stream (i'j) of the relevant auto-addressing bus node (BKj) is not plausible. One variant of the plausibility check procedure involves using an error address as the valid bus node address of the relevant auto-addressing bus node (BKj) if the detected first value of the first bus node output stream (ij) of the relevant auto-addressing bus node (BKj) is not plausible or if the detected second value of the second bus node output stream (i'j) of the relevant auto-addressing bus node (BKj) is not plausible. AUTO ADDRESSING PROCEDURE VIA INTERRUPT LINE In addition to these bus shunt resistor (R2, R2')-based address assignment methods, the following auto-addressing procedure via an interrupt line is proposed: This is a method for assigning logical bus node addresses to the bus nodes (BK1 to BKn) of a data bus system with a serial, bidirectional, differential two-wire communication bus (DB), where the data bus system has a bus master (ECU) with one address input (Adri0) and n bus nodes (BK1 to BKn) (where n is a positive integer). Each of the n bus nodes (BK2 to BKn) is connected to the bus master (ECU) for data transmission via a data line segment (DB1 to DBn) or a serial, bidirectional, differential two-wire communication bus (DB).A line, typically an interrupt line, used here to signal auto-addressing information, is looped from an address input (Adri0) of the bus master (ECU) through all bus nodes (BK1 to BKn) in such a way that it is divided into n line segments (L1 to Ln) by each bus node (BK1 to BKn). Each bus node, referred to below for clarity as the j-th bus node (BKj) where 1 ≤ j ≤ n, has an address input (Adrij) and an address output (Adroj) associated with it. These are used as inputs and outputs to stimulate and transmit the auto-addressing information.Each bus node (BKj), unless it is the nth bus node (BKn), is connected via its address input (Adrij) (with 1≤j≤n-1) to the address output (Adro(j+1)) of a subsequent bus node (BKj+1) with 1≤j≤n-1 by a line segment (Lj+1) belonging to the subsequent bus node (BKj+1). Each bus node (BKj) with 2≤j≤n is connected via its address output (Adroj) to the address input (Adri(j_1)) of a preceding bus node (BKj-1) with 2≤j≤n by a line segment (Lj) belonging to the bus node (BKj). The first bus node (BK1) is connected via its address output (Adro1) to the address input (Adri0) of the bus master (ECU) by a line segment (L1) belonging to the first bus node (BK1). The respective bus node address of each bus node (BK1 to BKn) can be valid or invalid.As a first step in this process, it is proposed to invalidate all or at least some of the respective bus node addresses (BK1 to BKn) and to shift at least this portion of the bus nodes (BK1 to BKn) from, for example, a normal state to an addressing state. The first step serves to establish a defined initial state. The second step initiates address assignment in all bus nodes (BK1 to BKn). As long as the bus node is in the addressing state, the line in question is not used for its normal function, such as an interrupt request line, but rather for transporting the auto-addressing function. During this addressing state, the first step is to set the level of the address input (Adri0) of the bus master (ECU) to a second logical value if the level of this address input (Adri0) of the bus master (ECU) is not overwritten by the address output (Adro1) of the first bus node (BK1) of the bus nodes (BK1 to BKn). It is a characteristic that both the bus master (ECU) with its address input (Adri0) and the bus nodes (BK1 to BKn-1) with their address inputs (Adri1 to Adrin) can be overwritten by the address outputs (Adro1 to Adron) of the subsequent bus nodes (BK1 to BKn), since these are designed with lower impedance than the corresponding driver stages in the address inputs (Adri1 to Adrin) of the bus nodes (BK1 to BKn). Only the last bus node (BKn) is not connected to any other subsequent bus node via its address input (Adrin).Therefore, in this last bus node (BKn), the driver stage within the address input (Adrin) of the last bus node (BKn) determines the logical state at the address input (Adrin). This allows the last bus node to recognize that it is the last in the sequence of bus nodes that does not yet have a valid bus node address, and therefore, if it does not have a valid bus node address, it can accept the address offered by the bus master as a new valid bus node address, provided it possesses a valid bus node address by some means.Since it has obtained a valid bus node address in this way and now has it, this bus node (BKj) then switches off its address output (Adroj), whereby the driver stage of the preceding address input (Adri(j-1)) of the preceding bus node (BKjA-1) is no longer overwritten by the address output (Adroj) of the bus node (BKj), and the preceding bus node (BKj-1) can then recognize itself as the last bus node without a valid bus node address in the sequence of unaddressed bus nodes, and thus, during the next initialization process, the preceding bus node (BKj-1) can then adopt the newly assigned bus node address offered by the bus master (ECU) as its valid bus node address in the same way. Since the preceding bus node (BKj-1) receives a valid bus node address in the subsequent initialization run and then has access to it, this preceding bus node (BKj-1) then switches off its address output (Adro(j-1)), whereby the driver stage of the address input (Adri(j-2)) of the next preceding bus node (BKj-2) is no longer overwritten by the address output (Adro(j-1)) of the preceding bus node (BKj-1), and the next preceding bus node (BKj-2) can then recognize itself as the last bus node without a valid bus node address in the sequence of unaddressed bus nodes, and thus, in the next subsequent initialization process, the next preceding bus node (BKj-2) can then adopt the newly assigned bus node address offered by the bus master (ECU) as its valid bus node address in the same way. This continues at bus stop after bus stop. During the addressing state, in each bus node (BKj) of the bus nodes (BK2 to BKn), excluding the first bus node (BK1), the level at the address input (Adri(j-1)) of the preceding bus node (BKj) is overwritten by that respective bus node (BKj) with a first logical level if the bus node address of that respective bus node (BKj) is invalid and the level at the address input (Adrij) of that respective bus node (BKj) has a first logical value. Furthermore, the level of the address input (Adrij) of that bus node (BKj) is set to a second logical value if the level of this address input (Adrij) of that bus node (BKj) is not already set by the address output (Adro(j+1)) of the bus node (BKj+1) that may be following that respective bus node (BKj). Bus junction (BK3bis BKn) is overwritten.Similarly, while the addressing state exists in the first bus node (BK1), the level at the address input (Adri0) of the bus master (ECU) is overwritten by the first bus node (BK1) with a first logical level if the bus node address of the first bus node (BK1) is invalid and the level at the address input (Adro1) of this first bus node (BK1) has a first logical value, and the level of the address input (Adri1) of this first bus node (BK1) is set to a second logical value if the level of this address input (Adri1) of this first bus node (BK1) is not overwritten by the address output (Adro2) of the bus node (BK2) following the first bus node (BK1) of the bus nodes (BK2 to BKn).Furthermore, while the addressing state exists, the bus master (ECU) signals a bus node address to all bus nodes (BK1 to BKn). The bus node (BKj) whose address is invalid and whose address input (Adrij) has a second logical value then adopts this signaled bus node address as a valid bus node address. The bus master (ECU) repeats this signaling process until its address input (Adri0) also has a second logical value, meaning it is not overwritten. This addressing process is repeated until the bus master (ECU) is the last in the chain of unaddressed bus nodes.Therefore, the bus nodes (BK1 to BKn) are moved into a second operating state different from the addressing state - which is typically the normal state when the address input (Adri0) of the bus master (ECU) has a second logical value. As already mentioned, in some cases it is advantageous to use the line (L1bis Ln) as an interrupt line in the second operating state. AUTO ADDRESSING METHOD VIA BUS SHUNT RESISTORS IN THE SUPPLY VOLTAGE LINE Finally, an auto-addressing method for assigning bus node addresses within a data bus system with a communication bus, in particular a serial, bidirectional, differential two-wire communication bus (DB), with n bus nodes (BK1, BK2, BK3, ..... BKn-1, BKn), where n is a positive integer greater than zero, and a bus master (ECU), is proposed, in which the bus nodes are supplied with electrical energy via a supply voltage line (Vbat), the communication bus (DB) is connected to the bus master (ECU), each bus node (BK1, BK2, ..... BKn-1, BKn) is connected to the communication bus (DB), and within each of the bus nodes (BK1 to BKn) a measuring resistor (Rmj) assigned to the respective bus node (BKj) of the n bus nodes (BK1 to BKn) is inserted into the supply voltage line (Vbat). This case corresponds to Fig. 15. Thus, the data bus system proposed here has n measuring resistors (Rm1 to Rmn).The measuring resistors (Rm1 to Rmn) of the bus nodes (BK1 to BKn) thus divide the supply voltage line (Vbat) into n supply voltage line sections. Since, particularly in the case of data bus systems for controlling multiple groups of lights (LED1 to LEDn) (see also Fig. 16), considerable currents can flow through the supply voltage line (Vbat), the measuring resistors (Rm1 to Rmn) should preferably be chosen with the lowest possible resistance to minimize losses. It is therefore conceivable to use, instead of dedicated measuring resistors (Rm1 to Rmn), only conductor track constrictions or even just conductor sections of predefined length, width, and thickness, made of the same material and with a specific resistance other than 0 Ω / m, as measuring resistors (Rm1 to Rmn). These are only examples of how the measuring resistors (Rm1 to Rmn) can be implemented. Other implementations, such as thick-film technology, etc., are conceivable.Each bus node (BKj) of the bus nodes (BK1 to BKn) has an addressing current source (Iqj). Current sources that are normally used as a power source for a light-emitting diode (LED) or other light source (LEDj) can also be used as such addressing current sources (Iqj). Each bus node (BKj) of the bus nodes (BK1 to BKn) preferably has means (D2, D3, Rmj) to detect the current through the measuring resistor (Rmj) of that bus node (BKj). The second differential amplifier (D2) of a bus node (BKj) detects the voltage drop across the respective measuring resistor (Rmj) of that bus node (BKj). A third differential amplifier (D3) compares the value of the output signal of the second differential amplifier (D2) with a reference value (Ref) by calculating the difference.The third differential amplifier (D3) of the bus node (BKj), together with a controller or filter (F) of the bus node (BKj), generates a control signal (rwj) specific to that bus node (BKj), depending on the result of this comparison. The value of the addressing current of the addressing current source (Iqj) of the respective bus node (BKj) depends on the value of this control signal (rwj) after the bus node (BKj) has been switched from its normal state to the addressing state by the bus master (ECU). When the bus node is in its normal state, the addressing current source (Iqj) is typically switched off if it has no other function in that normal state.For example, it is also possible to use a power source that is normally used to supply energy to loads, such as light bulbs and / or LEDs (LEDj), as the addressing power source (Iqj) of the bus node (BKj) when it is in the addressing state. This is illustrated in Fig. 16, which, apart from the light bulbs (LED1 to LEDn), is identical to Fig. 15. A command from the bus master (ECU) puts the relevant bus node (BKj) into the addressing state, thereby activating its addressing power source (Iqj). A bus node (BKj) preferably only activates its addressing power source (Iqj) if it does not have a valid bus node address, which is typically stored in a bus node address register (BKADR) and marked as "valid" or "invalid" with a corresponding flag.This flag is typically also used to mark the node as "invalid". If its bus node address is invalid, a bus node (BKj) will preferentially participate in an auto-addressing sequence when initiated by the bus master (ECU). This also applies to the other auto-addressing methods. In this case, the addressing current source (Iqj) of each bus node (BKj) feeds an addressing current into the supply line (Vbat) at the terminal of the measuring resistor (Rmj) of that bus node (BKj) that is furthest from the supply line (Vbat) along the supply line (Vbat).The bus nodes (BK1 to BKj-1) located closer to the power supply (Sup) detect the additional voltage drop across their respective measuring resistors (Rm1 to Rmj-1) using their respective measuring devices (Rm1 to Rmj-1, D2, D3). Depending on the implementation of the method, they then reduce or switch off their addressing current sources (Iq1 to Iqj-1) in this addressing state of the bus nodes (BK1 to BKn). This reduction can be detected by a threshold comparison, for example, of the respective control signal (rwj) of a bus node (BKj). This allows the respective bus node (BKj) to determine whether it is the last bus node in the bus node chain without a valid bus node address or whether it is indeed the last bus node in the bus node chain without a valid bus node address. In the latter case, the bus node adopts the available bus node address offered by the bus master as its valid bus node address.Thus, this bus node – let's say the j-th bus node (BKj) – now has a valid bus node address and switches off its addressing current source (Iqj) for the duration of the addressing procedure. As always in this disclosure, the addressing procedure is typically terminated by a command from the bus master (ECU), which preferably causes all bus nodes (BK1 to BKn) to exit the addressing state and, for example, return to their normal state. The proposed method for addressing via voltage drops along the power supply line (Vbat) therefore includes the following specific steps: • Signaling an addressing state, hereinafter referred to as the power-line addressing state, to all bus nodes (BK1 to BKn), thereby enabling them to assume an addressing state for performing an auto-addressing procedure using the power supply line (Vbat); • If necessary, signaling to at least one bus node or a subset, preferably all, of the bus nodes (BK1 to BKn) to invalidate their bus node addresses; • Executing an initialization sequence, comprising the following steps, for each bus node (BKj) of the n bus nodes (BK1, BK2, ..... BKn-1, BKn) that does not yet have a valid bus node address, until all bus nodes of the n bus nodes (BK1, BK2, ..... BKn-1, BKn) have a valid bus node address: • Signaling a new address to be assigned Bus address to all bus nodes of the n bus nodes (BK1, BK2,..... BKn-1, BKn) (Typically, this signaling also includes the bus master's (ECU) command to the bus nodes to assume or, if necessary, maintain the addressing state.);◯ Performing the following steps in parallel for each bus node (BKj) of the n bus nodes (BK1, BK2, ..... BKn-1, BKn), hereinafter referred to as the respective bus node (BKj),which does not have a valid bus node address: ▪ Reception of the aforementioned auto-addressing command from the bus master (ECU) by the relevant bus node (BKj); ▪ Reception of the bus address to be assigned from the bus master (ECU) by the relevant bus node (BKj); ▪ Reception of a start signal for the assignment of the bus address to be assigned from the bus master (ECU) by the relevant bus node (BKj) and start of a timer at a start time (t0=0s) by the relevant bus node (BKj); ▪ Detection of the voltage drop across the measuring resistor (Rmj) of the relevant bus node (BKj) as a base voltage value (Vm0) using measuring instruments (Rmj, D2,D3);▪ At a fourth time (t4) after the start time (t0): switching on the addressing current source (Iqj) of the relevant bus node (BKj) and adjusting the voltage drop across the measuring resistor (Rmj) of the relevant bus node (BKj) using the addressing current source (Iqj) as a function of the voltage drop across the measuring resistor (Rmj) by means of a control signal (rwj) generated by measuring instruments (D2, D3, Rmj) and / or control instruments (F) of the bus node (BKj), to a total target voltage value which corresponds to a target voltage value as plus the previously measured base voltage value (Vm0), wherein an increase in the addressing current of the auto-addressing current source (Iqj) of the relevant bus node (BKj) occurs with a first time constant (τ1) and wherein a decrease in the addressing current of the auto-addressing current source (Iqj) of the relevant bus node (BKj) occurs with a second time constant (τ2) is performed (Note,that no statement is yet made here about the numerical relationship of the first time constant (τ1) compared to the second time constant (τ2).);▪ At a fifth time point (t5) after the start time (t0) and after the fourth time point (t4): Acquisition of the value of the control signal (rwj) or a signal derived from it and comparison of this value with a threshold value and▪ Use of the bus node address to be assigned as the valid bus node address of the bus node (BKj) if the magnitude of this value is above the threshold value and switching off the addressing current source (Iqj) at least until the bus node (BKj) leaves the addressing state;, It is advisable for the bus master (ECU) to perform a check of the successful address assignment after assigning a bus node address to a bus node (BKj). If this check returns an error, for example, if several bus nodes report a bus collision, it is useful to delete the validity of the last assigned bus node address, causing the affected bus nodes (BKj) to behave like bus nodes (BKj) without a valid bus node address. After all bus node addresses have been assigned to all bus nodes (BK1 to BKn) that should receive a bus node address, it should be checked whether all bus nodes (BK1 to BKn) that should receive a bus node address have received a valid bus node address. If all bus nodes have received a valid bus node address, the bus master (ECU) preferably signals to all bus nodes (BK1 to BKn) that they should exit the addressing state and enter a different state, preferably the normal state.Under normal conditions, the bus nodes (BK1 to BKn) switch off their addressing current sources (Iq1 to Iqn) or operate them in the function assigned to these addressing current sources (Iq1 to Iqn) in this operating state, here the normal state. Performing a further initialization sequence is advisable if not all bus nodes (BK1 to BKn) that should receive a bus node address have received a valid bus node address. Generally, it is advantageous if the second time constant (τ2) is smaller than the first time constant (τ1) by a factor greater than 10. At a minimum, however, the first time constant (τ1) should be larger than the second time constant (τ2).It is advantageous if the first time constant (τ1) within the relevant auto-addressing bus node (BKj) depends on the voltage drop across the measuring resistor (Rmj) of the relevant auto-addressing bus node (BKj), as measured by instruments (Rmj, D2, D3), and / or if the second time constant (τ2) within the relevant auto-addressing bus node (BKj) depends on the voltage drop across the measuring resistor (Rmj) of the relevant auto-addressing bus node (BKj), as measured by instruments (Rmj, D2, D3). This enables faster control of the voltage drop across the measuring resistor (Rmj) of the relevant bus node (BKj). In Fig. 17, second addressing current sources (Iq'j) of the respective bus nodes (BKj) are also used for auto-addressing via the power supply line (Vbat). Second measuring devices (D2', D3') are also used in addition to the first measuring devices (Rm1 to Rmn, D2, D3). This redundancy can be used for testing and monitoring purposes, as each auto-addressing pass should lead to the same result for both branches. If this is not the case, the offered bus node address is preferably not accepted, but instead, for example, a specially reserved and predetermined error address is assumed. If the bus master (ECU) addresses this error address using its data bus protocol, the bus node where the error occurred responds to the bus master (ECU), which it should not do if no error had occurred in that bus node.The test could, for example, involve calculating the difference between the value of the first control signal (rwj) of a bus node (BKj) and the value of the second control signal (rw'j) of the same bus node (BKj). If the magnitude of this difference exceeds a predetermined threshold, at least one of the circuits is malfunctioning. This can then be detected and used to prevent the bus node address offered by the bus master (ECU) from being accepted as a valid address. Instead, the predetermined error address is used as the valid address, which can then be verified by the bus master (ECU) by accessing this address. Simultaneous Use of Different Auto-Addressing Methods It is advantageous to be able to use several of the auto-addressing methods described here, since each method can confirm the success of the correct identification through redundancy. Furthermore, a fail-operational property can be achieved when using more than two auto-addressing methods. This means that, as a rule, the auto-addressing is carried out successfully, but an error is detected and can then be signaled. This is potentially of particular importance for safety-critical applications. Fig. 18 shows such a proposed device, which allows the execution of several auto-addressing methods and thus offers increased safety. Fig. 18 is a combination of Fig. 17, Fig. 13, Fig. 6, and Fig. 5.In the bus nodes (BK1 to BKn) a first multiplexer (X1) of the respective bus node (BKj) and a second multiplexer (X2) of this bus node (BKj) are used to switch the inputs of the second differential amplifier (D2) of this bus node (BKj) to the first bus shunt resistor (R2) of this bus node (BKj) or to the measuring resistor (Rmj) of this bus node (BKj). In the bus nodes (BK1 to BKn), a further first multiplexer (X1') of the respective bus node (BKj) and a further second multiplexer (X2') of this bus node (BKj) are used to switch the inputs of the further second differential amplifier (D2') of this bus node (BKj) to the second bus shunt resistor (R2') of this bus node (BKj) or to the measuring resistor (Rmj) of this bus node (BKj).Accordingly, the first addressing current source (Iqj) of this bus node (BKj) is connected either to a reference potential (GND) or to the first single-wire bus (DBa) via a third multiplexer (X3) of this bus node (BKj). The third multiplexer (X3) of this bus node (BKj) also determines whether the first addressing current of the first addressing current source (Iqj) of this bus node (BKj) is injected into the first single-wire bus (DBa) before or after the first bus shunt resistor (R2) of this bus node (BKj). Similarly, the second addressing current source (Iq'j) of this bus node (BKj) is connected either to a reference potential (GND) or to the second single-wire bus (DBb) via another third multiplexer (X3') of this bus node (BKj).The third multiplexer (X3') of this bus node (BKj) also determines whether the second addressing current of the second addressing current source (Iq'j) of this bus node (BKj) is fed into the second single-wire bus (DBb) before or after the second bus shunt resistor (R2') of this bus node (BKj). Low-impedance normal operation It is advantageous if the bus shunt resistors (R2, R2') in the first single-wire bus (DBa) and the second single-wire bus (DBb) are only active during the addressing state of the bus nodes (BK1 to BKn). Therefore, as soon as the addressing state is exited, it is advantageous, preferably in all bus nodes (BK1 to BKn), to short-circuit the first bus shunt resistor (R2) of each bus node (BKj) by means of a first bypass switch (S4) in preferably each bus node (BKj), and to short-circuit the second bus shunt resistor (R2') of each bus node (BKj) by means of a second bypass switch (S4') in that same bus node (BKj). This is illustrated in Fig. 19. Of course, this approach would also be conceivable for the measuring resistor (Rmj) of a bus node (BKj). However, the corresponding switches would generally occupy too much chip area. Furthermore, the voltage drop across the normal supply voltage line is usually sufficient, so in these cases, a dedicated measuring resistor (Rmj) is not inserted into the supply voltage line (Vbat), but rather a section of the supply voltage line (Vbat) can be used as the measuring resistor (Rmj) of this bus node (BKj). Swap detection Figure 20 additionally shows a fourth multiplexer (X4) for each of the exemplary bus nodes (BK1 to BKn), which allows a controller within that bus node (BKj) to swap the two inputs of the second differential amplifier (D2) of that bus node (BKj). Furthermore, Figure 20 also shows a further fourth multiplexer (X4') for each of the exemplary bus nodes (BK1 to BKn), which allows the controller within that bus node (BKj) to swap the two inputs of the second differential amplifier (D2') of that bus node (BKj). This can now be explained using Fig. 21 for the error case shown there: The second bus node (BK2) is installed incorrectly. This can be easily detected by controlling the second bus node (BK2) in a self-test, which is preferably performed at the beginning of the initialization procedure. Preferably, for example, the bus master (ECU) signals to the bus nodes (BK1 to BKn) that they should perform such a self-test. Other start scenarios, e.g., during a power-on phase, are conceivable.For example, the bus node (BKj) can use its measuring means (R2, R2', D2, D2', D3, D3', Iqj, Iq'j, X1, X1', X2, X2', X3, X3') to determine whether the first addressing current of its first addressing current source (Iqj) flows through its first bus shunt resistor (R2) when it is supposed to flow through its first bus shunt resistor (R2), and whether the second addressing current of its second addressing current source (Iq'j) flows through its second bus shunt resistor (R2') when it is supposed to flow through the second bus shunt resistor (R2').If the opposite is true, the control of the bus node can determine this based on the corresponding measurement results and, by means of a fourth multiplexer (X4) of this bus node (BKj) and the third multiplexer (X3) of this bus node (BKj), firstly swap the inputs of the second differential amplifier (D2) of this bus node (BKj) and secondly move the injection point for the first addressing current of the first addressing current source (Iqj) of this bus node (BKj) to the other side of the first bus shunt resistor (R2) of this bus node (BKj).In this case, controlling the bus node by means of a further fourth multiplexer (X4') of this bus node (BKj) and the further third multiplexer (X3') of this bus node (BKj) can, firstly, also swap the inputs of the further second differential amplifier (D2') of this bus node (BKj) and, secondly, move the injection point for the second addressing current of the second addressing current source (Iq'j) of this bus node (BKj) to the other side of the second bus shunt resistor (R2') of this bus node (BKj). Then the implementation of the auto-addressing procedure using the bus shunt resistors (R2, R2') is possible again. Also possible, but not shown here for clarity, is to move the feed point of the first addressing current source (Iqj) of this bus node (BKj) into the supply voltage line (Vbat) to the other side of the measuring resistor (Rmj) by means of a fifth multiplexer (X5) not shown.This is only practical, however, if the first addressing current source (Iqj) does not have to supply excessively high current under normal conditions. This is precisely the case if, for example, the first auto-addressing current source (Iqj) of the bus node (BKj) under normal conditions is the power source for the bus node's LEDs (LEDj). In that case, the transistors of the fifth multiplexer (X5), which is not shown, would be too large and therefore too expensive. Similarly, relocating the feed point of the second addressing current source (Iq'j) of this bus node (BKj) to the supply voltage line (Vbat) on the other side of the measuring resistor (Rmj) by means of another fifth multiplexer (X5'), which is not shown, is no longer depicted. The same considerations apply here. Likewise, it was not shown that the input of the address input (Adrij) of the relevant bus node (BKj) (here, for example, the second bus node (BK2)) can also be swapped with the output of the address output (Adroj) of the relevant bus node (BKj) by means of two multiplexers (X6, X7), if such a swap, as in Fig. 21, was detected by the control of the bus node (BKj), e.g., in the manner described above. These are examples of measures to compensate for the insertion of a bus node with connector swapping. Reference symbol list ADRD Address information within the data information (DATA) of a bit stream packet (BP); ADR1 Address recognition unit of the first bus node (BK1); ADR2 Address recognition unit of the second bus node (BK2); ADR3 Address recognition unit of the third bus node (BK3); ADR4 Address recognition unit of the fourth bus node (BK4); ADR5 Address recognition unit of the fifth bus node (BK5); ADR6 Address recognition unit of the sixth bus node (BK6); ADRj Address recognition unit of the j-th bus node (BKj); ADRn Address recognition unit of the n-th bus node (BKn); ADR1 Address input of the bus master (ECU); ADR1 Address input of the first bus node (BK1); ADR2 Address input of the second bus node (BK2); ADR3 Address input of the third bus node (BK3); Adri(j-1) Address input of the (j-1)th bus node (BK(j-1)); Adrij Address input of the j-th bus node (BKj); Adri(j+1) Address input of the (j+1)th bus node (BK(j+1)); Adrin Address input of the n-th bus node (BKn); Adro1 Address output of the first bus node (BK1);Adro2 Address output of the second bus node (BK2); Adro3 Address output of the third bus node (BK3); Adro(j-1) Address output of the (j-1)th bus node (BK(j-1)); Adroj Address output of the j-th bus node (BKj); Adro(j+1) Address output of the (j+1)th bus node (BK(j+1)); Adro Address output of the n-th bus node (BKn); AT1 Scan device of the first bus node (BK1); AT2 Scan device of the second bus node (BK2); AT3 Scan device of the third bus node (BK3); AT4 Scan device of the fourth bus node (BK4); AT5 Scan device of the fifth bus node (BK5); AT6 Scan device of the sixth bus node (BK6); ATj Scan device of the j-th bus node (BKj); ATn scanning device of the nth bus node (BKn); BK1 first bus node; BK2 second bus node; BK3 third bus node; BK4 fourth bus node; BK5 fifth bus node; BK6 sixth bus node; BKj-2(j-2) third bus node; BKj-1(j-1) third bus node; BKjj-th bus node, also referred to in this disclosure as the relevant bus node when making statements abouta single bus node of the bus nodes (BK1, BK2, .....BKn-1, BKn) can be accessed; BKj+1(j+1)th bus node; BKj+2(j+2)th bus node; BKn-2(n-2)th bus node; BKn-1(n-1)th bus node; BKnn-th bus node; BKADR1 Bus node address register of the first bus node (BK1); BKADR2 Bus node address register of the second bus node (BK2); BKADR3 Bus node address register of the second bus node (BK3); BKADR4 Bus node address register of the second bus node (BK4); BKADR5 Bus node address register of the second bus node (BK5); BKADR6 Bus node address register of the second bus node (BK6); BKADRj Bus node address register of the jth bus node (BKj); BKADRn Bus node address register of the nth bus node (BKn); BP Bit stream packet (frame), also referred to as data packet; CHKD Check information within the data information (DATA) of a bit stream packet (BP). Preferably a CRC checksum and / or parity bits, etc.; CLK Clock within the bus master (ECU); CLKA1 Sampling signal within thefirst bus node (BK1); CLKA2 sampling signal within the second bus node (BK2); CLKA3 sampling signal within the third bus node (BK3); CLKA4 sampling signal within the fourth bus node (BK4); CLKA5 sampling signal within the fifth bus node (BK5); CLKA6 sampling signal within the sixth bus node (BK6); CLKAj sampling signal within the j-th bus node (BKj); CLKAn sampling signal within the n-th bus node (BKn); CLKG1 clock of the first bus node (BK1); CLKG2 clock of the second bus node (BK2); CLKG3 clock of the third bus node (BK3); CLKG4 clock of the fourth bus node (BK4); CLKG5 clock of the fifth bus node (BK5); CLKG6 clock of the sixth bus node (BK6); CLKGj Clock of the j-th bus node (BKj); CLKGn Clock of the n-th bus node (BKn); D2 Second differential amplifier for measuring the first current through the first single-wire bus (DBa) using the first shunt resistor (R2) or for measuring the current through the supply voltage line (Vbat)D2' second differential amplifier for measuring the second current through the second single-wire bus (DBb) using the second shunt resistor (R2') or for measuring the current through the supply voltage line (Vbat) using the measuring resistor (RMj) within the relevant bus node (BKj). For clarity, the second differential amplifiers are not labeled with indices for the respective bus nodes. D3' third comparator or third differential amplifier for comparing the output of the second differential amplifier (D2), which is used to measure the current through the first single-wire bus (DBa) using the first shunt resistor (R2) or through the supply voltage line using the measuring resistor (RMj), with a threshold value (Ref) within the relevant bus node (BKj).For clarity, the third comparators and differential amplifiers are not labeled with indices for the respective bus nodes (BKj). D3' is the third comparator or differential amplifier for comparing the output of the second differential amplifier (D2'), which measures the current through the second single-wire bus (DBb) via the second shunt resistor (R2') or through the supply voltage line via the measuring resistor (RMj), with a further threshold value (Ref') within the respective bus node (BKj). For clarity, the third comparators and differential amplifiers are not labeled with indices for the respective bus nodes (BKj). DATA is data information within a bit stream packet; DB is a serial, bidirectional, differential two-wire communication bus; DBa is the first single-wire bus of the serial, bidirectional, differential two-wire communication bus (DB); DBaz is the second single-wire bus of the serial, bidirectional, differentialTwo-wire communication bus (DB); DB1: First, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the first bus node (BK1) and the bus master (ECU). It comprises one corresponding section each of the first single-wire bus (DBa) and the second single-wire bus (DBb); DB2: Second, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the second bus node (BK2) and the first bus node (BK1). It comprises one corresponding section each of the first single-wire bus (DBa) and the second single-wire bus (DBb); DB3: Third, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the third bus node (BK3) and the second bus node (BK2). It comprises a corresponding section of the first single-wire bus (DBa) and the second single-wire bus (DBb);DBjthird, bidirectional differential data line section of the bidirectional differential two-wire communication bus between the j-th bus node (BKj) and the (j-1)-th bus node (BKj-1). It comprises a corresponding section each of the first single-wire bus (DBa) and the second single-wire bus (DBb); DBnn-th, bidirectional differential data line section of the bidirectional differential two-wire communication bus between the n-th bus node (BKn) and the (n-1)-th bus node (BKn-1). It comprises a corresponding section each of the first single-wire bus (DBa) and the second single-wire bus (DBb); DET first detection device within a bus node (BKj); DET' second detection device within a bus node (BKj); ds2 output of the second differential amplifier (D2). This is an internal signal within a bus node (BKj); ds2' output of the second differential amplifier (D2'). It is aInternal signal within a bus node (BKj); ds3 Internal signal within a bus node (BKj); ECU bus master, also referred to here as the control unit; er First fault signal of the first detection device (DET); er' Second fault signal of the second detection device (DET'); EV1 Power supply means of the first bus node (BK1), which is provided for the power supply of the first light source (LED1) of the first bus node (BK1). EV2 Power supply means of the second bus node (BK2), which is provided for the power supply of the second light source (LED2) of the second bus node (BK2). EV3 Power supply means of the third bus node (BK3), which is provided for the power supply of the third light source (LED3) of the third bus node (BK3). EV4 Energy supply unit of the fourth bus junction (BK4), which is intended for the energy supply of the fourth light source (LED4) of the fourth bus junction (BK4). EV5 Energy supply unit of the fifthBus node (BK5) intended for the power supply of the fifth light source (LED5) of the fifth bus node (BK5). EV6 Power supply of the sixth bus node (BK6) intended for the power supply of the sixth light source (LED6) of the sixth bus node (BK6). EVj Power supply of the j-th bus node (BKj) intended for the power supply of the j-th light source (LEDj) of the j-th bus node (BKj). EVn Power supply of the n-th bus node (BKn) intended for the power supply of the n-th light source (LEDn) of the n-th bus node (BKn). F First filter; F' Second filter; GND Second supply voltage line (complementary to Vbat), also referred to as reference potential; i1 first bus node output current, which the first bus node (BK1) via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between thefirst bus node (BK1) and the bus master (ECU), which sends to the bus master (ECU) and which the bus master receives as the first bus master input current; i'1 second bus node output current, which the first bus node (BK1) sends to the bus master (ECU) via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the first bus node (BK1) and the bus master (ECU), and which the bus master receives as the second bus master input current; i2first bus node output current that the second bus node (BK2) sends to the first bus node (BK1) via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the second bus node (BK2) and the first bus node (BK1), and which the first bus node (BK1) receives as the first bus node input current; i'2secondBus node output current that the second bus node (BK2) sends to the first bus node (BK1) via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the second bus node (BK2) and the first bus node (BK1), and which the first bus node (BK1) receives as the second bus node input current; i3 first bus node output current that the third bus node (BK3) sends to the second bus node (BK2) via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the third bus node (BK3) and the second bus node (BK2), and which the second bus node (BK2) receives as the first bus node input current; i'3second bus node output current, which the third bus node (BK3) via the section of the second single-wire bus (DB2), which is part of the connecting section of theserial, bidirectional, differential two-wire communication bus (DB) between the third bus node (BK3) and the second bus node (BK2), sends to the second bus node (BK2) and which the second bus node (BK2) receives as the second bus node input current; ijerster bus node output current, which the j-th bus node (BKj) sends via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the j-th bus node (BKj) and the (j-1)-th bus node (BKj-1), to the (j-1)-th bus node (BKj-1) and which the (j-1)-th bus node (BK(j-1)) receives as the first bus node input current; i'jzweiter Busknotenausgangsstrom, den der der j-te Busknoten (BKj) über den Abschnitt des zweites Eindrahtbusse (DB2), der Teil des Verbindungsabschnitt des serial, bidirectional, differentialiell zweidrahtkommunikationsbus (DB) zwischen dem j-te Busknoten (BKj) und dem (j-1)-tebus node (BKj-1) is, which sends to the (j-1)th bus node (BKj-1) and which the (j-1)th bus node (BK(j-1)) receives as the second bus node input current; ij+1 first bus node output current, which the (j+1)th bus node (BKj+1) sends to the j-th bus node (BKj) via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the (j+1)th bus node (BKj+1) and the j-th bus node (BKj) and which the j-th bus node (BKj) receives as the first bus node input current; i'j+1 second bus node output current, which the (j+1)th bus node (BKj+1) sends to the j-th bus node (BKj) via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the (j+1)th bus node (BKj+1) and the j-th bus node (BKj), and which the j-th bus node (BKj) receives as the secondbus node input current received; first bus node output current that the (n-1)th bus node (BKn-1) sends to the (n-2)th bus node (BKn-2) via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the (n-1)th bus node (BKn-1) and the (n-2)th bus node (BKn-2), and which the (n-2)th bus node (BKn-2) receives as the first bus node input current; i'n-1 second bus node output current that the (n-1)th bus node (BKn-1) sends to the (n-2)th bus node (BKn-2) via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the (n-1)th bus node (BKn-1) and the (n-2)th bus node (BKn-2), and which the (n-2)th bus node (BKn-2) receives as the second bus node input current; inertial bus node output current that the nth bus node (BKn) sends viathe section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the n-th bus node (BKn) and the (n-1)-th bus node (BKn-1), sends to the (n-1)-th bus node (BKn-1) and which the (n-1)-th bus node (BKn-1) receives as the first bus node input current; i'nsecond bus node output current, which the nth bus node (BKn) sends to the (n-1)th bus node (BKn-1) via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the nth bus node (BKn) and the (n-1)th bus node (BKn-1), and which the (n-1)th bus node (BKn-1) receives as the second bus node input current; IF1 differential serial interface of the first bus node (BK1); IF2 differential serial interface of the second bus node (BK2); IF3 differential serial interface of the thirdBus node (BK3); IF4 differential serial interface of the fourth bus node (BK4); IF5 differential serial interface of the fifth bus node (BK5); IF6 differential serial interface of the sixth bus node (BK6); IF(j-1) differential serial interface of the (j-1)th bus node (BKj-1); IFj differential serial interface of the j-th bus node (BKj); IF(j+1) differential serial interface of the (j+1)th bus node (BKj+1); IF(n-1) differential serial interface of the (n-1)th bus node (BKn-1); IFn differential serial interface of the n-th bus node (BKn); ILD lighting information for controlling the power supply of the light sources (LEDj) of the bus node (BKj) by the power supply unit (EVj) of the bus node (BKj) depending on this lighting information; INFO is useful information within the data information (DATA) of a bitstream packet (BP). It is preferably illumination data for the respective...Bus node (BKj); Iq1 first addressing current source of the first bus node (BK1); Iq2 first addressing current source of the second bus node (BK2); Iq3 first addressing current source of the third bus node (BK3); Iqj first addressing current source of the j-th bus node (BKj); Iqj1 first addressing current source of the j-th bus node (BKj) when the first addressing current source (Iqj1) of the j-th bus node (BKj) is split into a first addressing current source that feeds in before the first bus shunt resistor (R2) and another first addressing current source that feeds in after the first bus shunt resistor (R2); Iqj2 further first addressing current source of the j-th bus node (BKj) when the first addressing current source (Iqj1) of the j-th bus node (BKj) is split into a first addressing current source that feeds in before the first bus shunt resistor (R2) and a first addressing current source that feeds in after the first bus shunt resistor (R2); Iq'j1 secondAddressing current source of the j-th bus node (BKj) when the second addressing current source (Iqj1) of the j-th bus node (BKj) is split into a second addressing current source that feeds in before the second bus shunt resistor (R2') and another second addressing current source that feeds in after the second bus shunt resistor (R2'); Iq'j2 further second addressing current source of the j-th bus node (BKj) when the second addressing current source (Iqj1) of the j-th bus node (BKj) is split into a second addressing current source that feeds in before the second bus shunt resistor (R2') and another second addressing current source that feeds in after the second bus shunt resistor (R2'); Iqj first addressing current source of the j-th bus node (BKj); Iq first addressing current source of the nth bus node (BKn); Irefest predefined sum current value within a bus node (BKj) for the first bus node output current (ij). The first sum current value should be for allThe second total current value within a bus node (BKj) is preferably the same for all bus nodes. However, it can also vary from bus node to bus node. I'ref is the second specified total current value within a bus node (BKj) for the second bus node output current (i'j). The second total current value should preferably be the same for all bus nodes. However, it can also vary from bus node to bus node. L1 is the first line segment from the first bus node (BK1) to the bus master (ECU); L2 is the second line segment from the second bus node (BK2) to the first bus node (BK1); L3 is the third line segment from the third bus node (BK3) to the second bus node (BK2); L4 is the fourth line segment from the fourth bus node (BK4) to the third bus node (BK3); Lj-1 is the (j-1)th line segment from the (j-1)th bus node (BKj-1) to the (j-2)th bus node (BKj-2). Ljj-th line section from the j-th bus node (BKj) to the (j-1)-th bus node (BKj-1); Lj+1(j+1)-th line section from the (j+1)-th bus node (BKj+1) to the j-th bus node (BKj); Ln-1(n-1)-th line section from(n-1)th bus node (BKn-1) to (n-2)th bus node (BKn-2); Lnn-th line segment from the nth bus node (BKn) to the (n-1)th bus node (BKn-1); µC1 microcontroller of the first bus node (BK1); µC2 microcontroller of the second bus node (BK2); µC3 microcontroller of the third bus node (BK3); µC4 microcontroller of the fourth bus node (BK4); µC5 microcontroller of the fifth bus node (BK5); µC6 microcontroller of the sixth bus node (BK6); µCj microcontroller of the jth bus node (BKj); µCn microcontroller of the nth bus node (BKn); LED1 light source of the first bus node (BK1). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of several LEDs.) LED2 Light source of the second bus node (BK2). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of several LEDs.) LED3 Light source of the third bus node (BK3). Light source groups andCircuits are included here. (These can be, for example, series and parallel circuits of multiple LEDs.) LED4: Light source of the fourth bus node (BK4). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of multiple LEDs.) LED5: Light source of the fifth bus node (BK5). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of multiple LEDs.) LED6: Light source of the sixth bus node (BK6). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of multiple LEDs.) LEDj: Light source of the j-th bus node (BKj). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of multiple LEDs.) LEDn: Light source of the n-th bus node (BKn). Light source groups and circuits areIncluded here. (These can be, for example, series and parallel circuits of several LEDs.) pol first polarity signal, which preferably controls the multiplexer (X4); pol second polarity signal, which preferably controls the further multiplexer (X4'); R2 first shunt resistor for measuring the current through the first single-wire bus (DBa) within the relevant bus node (BKj). The first shunt resistor is considered here as part of the bus node (BKj). It is preferably present in each of the auto-addressable bus nodes (BK1 to BKn). For clarity, the first shunt resistors have not been labeled with indices for the respective bus nodes. R2' second shunt resistor for measuring the current through the second single-wire bus (DBb) within the relevant bus node (BKj). The second shunt resistor is considered here as part of the bus node (BKj). It is preferentially present at each of the auto-addressable bus nodes (BK1 to BKn).For clarity, the second shunt resistors were not labeled with indices for the respective bus nodes. Rec Receiver. Each bus node (BK1 to BKn) and the bus master (ECU) preferably has a receiver. A receiver extracts the data (DATA) contained in the bit stream packets (BP) and preferably outputs it, along with error information, via an output (out). The receiver typically checks whether the check information (CHKD) within the data information (DATA) of a bit stream packet (BP) indicates error-free reception. If a bit stream packet (BP) was not received without errors, the receiver signals this. r1: first control value of the first control signal (rw1) of the first bus node (BK1); r'1: second control value of the second control signal (rw'1) of the first bus node (BK1); r2: first control value of the first control signal (rw2) of the second bus node (BK1). r'2second control value of the second control signal (rw'1) of the second bus node (BK1);r3first control value of the first control signal (rw3) of the third bus node (BK1); r'3second control value of the second control signal (rw'1) of the third bus node (BK1); rjfirst control value of the first control signal (rwj) of the jth bus node (BK1); r'jsecond control value of the second control signal (rw'1) of the jth bus node (BK1); rnfirst control value of the first control signal (rwn) of the nth bus node (BK1); r'nsecond control value of the second control signal (rw'1) of the nth bus node (BK1); Rm1measuring resistance in the supply voltage line for the first bus node (BK1); Rm2measuring resistance in the supply voltage line for the second bus node (BK2); Rm3measuring resistance in the supply voltage line for the third bus node (BK3); Rmj measuring resistance in the supply voltage line for the j-th bus node (BKj); Rmn measuring resistance in the supply voltage line for the n-th bus node (BKn); rw1 first control signal of the first bus node (BK1). The first control signal of the first bus node(BK1) is generated from the output signal of the third comparator (D3) of the first bus node (BK1) by means, preferably a first filter (F) of the first bus node (BK1), which can also form a unit with the third comparator (D3) of the first bus node (BK1), and serves to control the first auto-addressing current source (Iq1) of the first bus node (BK1); rw'1 second control signal of the first bus node (BK1). The second control signal of the first bus node (BK1) is generated from the output signal of the corresponding third comparator (D3') of the first bus node (BK1) by means, preferably a second filter (F) of the first bus node (BK1), which can also form a unit with the corresponding third comparator (D3') of the first bus node (BK1), and serves to control the second auto-addressing current source (Iq'1) of the first bus node (BK1); rw2 first control signal of the second bus node (BK2). The first control signal of the second bus node (BK2) is generated using means,preferably a first filter (F) of the second bus node (BK2), which can also form a unit with the third comparator (D3) of the second bus node (BK2), is generated from the output signal of the second comparator (D3) of the second bus node (BK2) and serves to control the first auto-addressing current source (Iq2) of the second bus node (BK2); rw'2 second control signal of the second bus node (BK2). The second control signal of the second bus node (BK2) is generated from the output signal of the corresponding third comparator (D3') of the second bus node (BK2) by means of, preferably a second filter (F) of the second bus node (BK2), which can also form a unit with the corresponding third comparator (D3') of the second bus node (BK2) and serves to control the second auto-addressing current source (Iq'2) of the second bus node (BK2); The first control signal of the third bus node (BK3) is generated using means, preferably aThe first filter (F) of the third bus node (BK3), which can also form a unit with the third comparator (D3) of the third bus node (BK3), is generated from the output signal of the third comparator (D3) of the third bus node (BK3) and serves to control the first auto-addressing current source (Iq3) of the third bus node (BK3); rw'3 is the second control signal of the third bus node (BK3). The second control signal of the third bus node (BK3) is generated from the output signal of the corresponding third comparator (D3') of the third bus node (BK3) by means of, preferably, a second filter (F) of the third bus node (BK3), which can also form a unit with the corresponding third comparator (D3') of the third bus node (BK3), and serves to control the second auto-addressing current source (Iq'3) of the third bus node (BK3). The first control signal of the j-th bus node (BKj). The first control signal of the j-th bus node (BKj) is filtered by means, preferably a first filter (F) of theThe second control signal of the j-th bus node (BKj) is generated from the output signal of the third comparator (D3) of the j-th bus node (BKj) and serves to control the first auto-addressing current source (Iqj) of the j-th bus node (BKj); rw'j is the second control signal of the j-th bus node (BKj). The second control signal of the j-th bus node (BKj) is generated from the output signal of the corresponding third comparator (D3') of the j-th bus node (BKj) by means of, preferably, a second filter (F) of the j-th bus node (BKj), which can also form a unit with the corresponding third comparator (D3') of the j-th bus node (BKj) and serves to control the second auto-addressing current source (Iq'j) of the j-th bus node (BKj). The first control signal of the nth bus node (BKn). The first control signal of the nth bus node (BKn) is filtered by means, preferably a first filter (F) of the nth bus node (BKn), which is connected to the thirdThe second control signal of the nth bus node (BKn) is generated from the output signal of the third comparator (D3) of the nth bus node (BKn) and serves to control the first auto-addressing current source (Iqn) of the nth bus node (BKn). The second control signal of the nth bus node (BKn) is generated from the output signal of the corresponding third comparator (D3') of the nth bus node (BKn) by means of, preferably, a second filter (F) of the nth bus node (BKn), which can also form a unit with the corresponding third comparator (D3') of the nth bus node (BKn) and serves to control the second auto-addressing current source (Iq'n) of the nth bus node (BKn). S4 is the first bypass switch – also called the first bus shunt bypass switch – for bypassing the first shunt resistor (R2) within a bus node (BKj). The first bypass switch can also be a transistor and / or aA more complex circuit of various electronic and other components can be implemented if the functionality of a switch results within the operating range; S4' second bypass switch - also called second bus shunt bypass switch - for bypassing the second shunt resistor (R2') within a bus node (BKj). The second bypass switch can also be implemented as a transistor and / or as a more complex circuit of various electronic and other components if the functionality of a switch results within the operating range; START start signal; SUP power supply; SW1 first threshold for comparison with the first control value (r1) of the first bus node (BK1) to decide whether the address data should be accepted as a valid bus node address; SW'1 second threshold for comparison with the second control value (r'1) of the first bus node (BK1) to decide whether the address data should be accepted as a valid bus node addressSW2 first threshold for comparison with the first rule value (r2) of the second bus node (BK2) to decide whether the address data should be accepted as a valid bus node address; SW'2 second threshold for comparison with the second rule value (r'2) of the second bus node (BK2) to decide whether the address data should be accepted as a valid bus node address; SW3 first threshold for comparison with the first rule value (r3) of the third bus node (BK3) to decide whether the address data should be accepted as a valid bus node address; SW'3 second threshold for comparison with the second rule value (r'3) of the third bus node (BK3) to decide whether the address data should be accepted as a valid bus node address; SWj first threshold for comparison with the first rule value (rj) of the j-th bus node (BKj) to decide whether the address data should be accepted as a valid bus node address; SW'second threshold toComparison with the second control value (r'j) of the j-th bus node (BKj) for the decision of whether the address data should be accepted as a valid bus node address; SWinnerst threshold for comparison with the first control value (rn) of the n-th bus node (BKn) for the decision of whether the address data should be accepted as a valid bus node address; SW'n2 threshold for comparison with the second control value (r'n) of the n-th bus node (BKn) for the decision of whether the address data should be accepted as a valid bus node address; SYNC synchronization information; τ1 first time constant by which the increment of the first addressing current of the first controlled auto-addressing current source (Iqj) of the respective bus node (BKj) is carried out; τ2 second time constant with which the first addressing current of the first regulated auto-addressing current source (Iqj) of the relevant auto-addressing bus node (BKj) is lowered; τ3 third time constant with which the increase of thesecond addressing stream of the second controlled auto-addressing stream source (Iq'j) of the relevant bus node (BKj); τ4 fourth time constant with which the reduction of the second addressing stream of the second controlled auto-addressing stream source (Iq'j) of the relevant auto-addressing bus node (BKj) occurs; t1 first time point after the start of the timer at which a freeze of the control of the first addressing stream source (Iqj) of the relevant auto-addressing bus node (BKj) occurs; t2 second time point after the start of the timer at which a freeze of the control of the second addressing stream source (Iq'j) of the relevant auto-addressing bus node (BKj) occurs; t3 third time point at which, under certain conditions, the bus node address to be assigned is accepted by the bus master (ECU) as a valid bus node address of the relevant auto-addressing bus node (BKj); tBLength of a single bit within a bit stream packet (BP); TRaersterThe driver is located in the bus master (ECU) or in a bus node (BK1 to BKn). Preferably, the driver is implemented as a CAN driver or an RS485 driver. A first driver, preferably a CAN driver, can assume two of three permitted states: In a first state, it places a first logical level (Z1) on the first single-wire bus (DBa). In a second state, it places a third logical level (Z3) on the first single-wire bus (DBa). The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes (BK1 to BKn) as the first current sink for the first addressing currents of the first addressing current sources (Iq1 to Iqn) of the bus nodes (BK1 to BKn) and their first quiescent currents. Preferably, the first driver of a bus node (BK1 to BKn) or the bus master (ECU) assumes the first state (Z1) when the second driver (TRb) of the respective bus node (BK1 to BKn) assumes the second state (Z2). This results in the signal being assigned a first state.The signal is differentially impressed with a third differential level (z1). Preferably, the first driver of a bus node (BK1 to BKn) or the bus master (ECU) assumes the third state (Z3) when the second driver (TRb) of the respective bus node (BK1 to BKn) assumes the third state (Z3). This differentially impresses the signal with a third differential level (z3). The first driver, also acting as an RS485 driver, can preferably assume two of the two allowed states: In a first state, it applies a first logic level (Z1) to the first single-wire bus (DBa). In a second state, it applies a second logic level (Z2) to the first single-wire bus (DBa). The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes (BK1 to BKn) as the first current sink for the first addressing currents of the first addressing current sources (Iq1 to Iqn) of the bus nodes (BK1 to BKn) and their first quiescent currents. The first driver preferentially uses the first addressing current source (Iq1 to Iqn) of the bus nodes (BK1 to BKn).The first driver of a bus node (BK1 to BKn) or the bus master (ECU) assumes the first state (Z1) when the second driver (TRb) of the respective bus node (BK1 to BKn) assumes the second state (Z2). This differentially induces the signal with a first differential level (z1). Preferably, the first driver of a bus node (BK1 to BKn) or the bus master (ECU) assumes the second state (Z2) when the second driver (TRb) of the respective bus node (BK1 to BKn) assumes the first state (Z1). This differentially induces the signal with a second differential level (z2). Furthermore, the first driver typically has a sub-device for detecting and avoiding a bus collision in the event of simultaneous access to the first single-wire bus (DBa) by a first driver of another bus node (BK1 to BKn) or the bus master (ECU). The second driver is located in the bus master (ECU) or in a bus node (BK1 to BKn). Preferably, theA second driver is implemented as a CAN driver or RS485 driver. A second driver, acting as a CAN driver, can preferably assume two of three allowed states: In a first state, it places a second logical level (Z2) on the second single-wire bus (DBb). In a second state, it places a third logical level (Z3) on the second single-wire bus (DBb). The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes (BK1 to BKn) as a second current sink for the second addressing currents of the second addressing current sources (Iq'1 to Iq'n) of the bus nodes (BK1 to BKn) and their second quiescent currents. Preferably, the second driver of a bus node (BK1 to BKn) or of the bus master (ECU) assumes the second state (Z2) when the first driver (TRa) of the respective bus node (BK1 to BKn) assumes the first state (Z1). This causes the signal to be differentially impressed with a first differential level (z1). Preferably, theThe second driver of a bus node (BK1 to BKn) or the bus master (ECU) sets the third state (Z3) when the first driver (TRa) of the respective bus node (BK1 to BKn) assumes the third state (Z3). This differentially applies a third differential level (z3) to the signal. The second driver, also acting as an RS485 driver, can preferentially assume two of two allowed states: In a first state, it applies a second logic level (Z2) to the first single-wire bus (DBa). In a second state, it applies a first logic level (Z1) to the second single-wire bus (DBb). The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes (BK1 to BKn) as a second current sink for the second addressing currents of the second addressing current sources (Iq'1 to Iq'n) of the bus nodes (BK1 to BKn) and their second quiescent currents. Preferably, the second driver of a bus node (BK1 to BKn) or of the bus master (ECU) takes over theThe second driver (TRa) of the relevant bus node (BK1 to BKn) assumes the first state (Z1) when the first driver (TRa) of the relevant bus node (BK1 to BKn) assumes the first state (Z1). This differentially induces the signal with a first differential level (z1). Preferably, the second driver of a bus node (BK1 to BKn) or the bus master (ECU) assumes the first state (Z1) when the first driver (TRa) of the relevant bus node (BK1 to BKn) assumes the second state (Z2). This differentially induces the signal with a second differential level (z2). Furthermore, the first driver typically has a sub-device for detecting and preventing a bus collision in the event of simultaneous access to the first single-wire bus (DBa) by a first driver of another bus node (BK1 to BKn) or the bus master (ECU). Vbat supply voltage line; X1 is the first multiplexer for connecting a first input of the second differential amplifier (D2) for measuring the current through thefirst single-wire bus (DBa) with a first connection of the first shunt resistor (R2) on the side of the bus master (ECU) or optionally with a second connection of the measuring resistor (Rmj) in the supply voltage line within the relevant bus node (BKj); X1' second multiplexer for connecting a first input of the second comparator (D2') for measuring the current through the second single-wire bus (DBb) with a first connection of the second shunt resistor (R2') on the side of the bus master (ECU) or optionally with a second connection of the measuring resistor (Rmj) in the supply voltage line within the relevant bus node (BKj); X2 is the first multiplexer for connecting a second input of the second differential amplifier (D2) for measuring the current through the first single-wire bus (DBa) to a second connection of the first shunt resistor (R2) on the opposite side of the bus master (ECU) or to a first connection of the measuring resistor (Rmj) in theSupply voltage line within the relevant bus node (BKj); X2' second multiplexer for connecting a second input of the second comparator (D2') for measuring the current through the second single-wire bus (DBb) to a second terminal of the second shunt resistor (R2') on the far side of the bus master (ECU) or to a first terminal of the measuring resistor (Rmj) in the supply voltage line within the relevant bus node (BKj); X3 first multiplexer for connecting a terminal of the first addressing current source (Iqj) of the bus node (BKj) to a first terminal of the first shunt resistor (R2) or to a second terminal of the first shunt resistor (R2) or to a reference potential within the relevant bus node (BKj); X3' second multiplexer for connecting a terminal of the second addressing current source (Iq'j) of the bus node (BKj) to a first terminal of the second shunt resistor (R2') or to asecond connection of the second shunt resistor (R2') or with a reference potential within the relevant bus node (BKj); X4 first multiplexer for swapping the inputs of the second differential amplifier (D2) of the bus node (BKj); X4' second multiplexer for swapping the inputs of the further second differential amplifier (D2') of the bus node (BKj); X5 multiplexer for swapping the connections of the measuring resistor (Rmj) of a bus node (BKj); X6 first multiplexer for swapping the connections of the address input (Adrij) and the stress output (Adroj) of a bus node (BKj); X7 second multiplexer for swapping the connections of the address input (Adrij) and the stress output (Adroj) of a bus node (BKj); Z1 first logical state in which the first single-wire bus (DBa) or the second single-wire bus (DBb) can be. This is also referred to as High in this disclosure. z1 first differential state in which the serial, bidirectional,Z2 is the second logical state in which the first single-wire bus (DBa) or the second single-wire bus (DBb) can be located. This is also referred to as High in this disclosure. Z2 is the second differential state in which the serial, bidirectional, differential two-wire communication bus (DB) can be located. This is also referred to as Low in this disclosure. Z3 is the third logical state in which the first single-wire bus (DBa) or the second single-wire bus (DBb) can be located. This is also referred to as Idle in this disclosure. Preferably, but not necessarily, the corresponding physical level of the first single-wire bus (DBa) or the second single-wire bus (DBb) has a value around a common mean value. Z3 is the third differential state in which the serial, bidirectional, differential two-wire communication bus (DB)This can be located in an idle state. This is also referred to as "Idle" in this disclosure. Preferably, but not necessarily, the corresponding differential physical level has a value around zero.

Claims

Auto-addressing method for assigning bus node addresses within a data bus system with a communication bus with n bus nodes (BK1, BK2, BK3, ..... BKn-1, BKn), where n is a positive integer greater than zero, and a bus master (ECU) - wherein the bus nodes are supplied with electrical energy via a supply voltage line (Vbat) and - wherein the communication bus (DB) is connected to the bus master (ECU) and - wherein each bus node (BK1, BK2, ..... BKn-1, BKn) is connected to the communication bus (DB) and - wherein within each bus node (BK1 to BKn) a measuring resistor (Rmj) assigned to the respective bus node (BKj) of the n bus nodes (BK1 to BKn) is inserted into the supply voltage line (Vbat), i.e. the data bus system has n measuring resistors (Rm1 to Rmn).and- wherein the measuring resistors (Rm1 to Rmn) of the bus nodes (BK1 to BKn) thus divide the supply voltage line (Vbat) into n supply voltage line sections and- wherein each bus node (BKj) of the bus nodes (BK1 to BKn) has an addressing current source (Iqj) and- wherein each bus node (BKj) of the bus nodes (BK1 to BKn) has means (D2, D3, Rmj) to detect the current through the measuring resistor (Rmj) of this bus node (BKj) of the bus nodes (BK1 to BKn) and- wherein the addressing current source (Iqj) of each bus node (BKj) of the bus nodes (BK1 to BKn) injects an addressing current towards the power supply (SUP) into the supply voltage line (Vbat) into the terminal of the measuring resistor (Rmj) of this bus node (BKj), which runs along the The supply voltage line (Vbat) is furthest from the power supply (SUP), and – with the following steps – signaling of an addressing state,hereinafter referred to as the power-line addressing state, to all bus nodes (BK1 to BKn), thereby setting them to an addressing state for performing an auto-addressing procedure using the power supply line (Vbat); - Performing an initialization sequence, comprising the following steps, for each bus node (BKj) of the n bus nodes (BK1, BK2, ..... BKn-1, BKn) that does not yet have a valid bus node address until all bus nodes of the n bus nodes (BK1, BK2, ..... BKn-1, BKn) have a valid bus node address: • Signaling a bus address to be assigned to all bus nodes of the n bus nodes (BK1, BK2, ..... BKn-1, BKn); • Parallel execution of the following steps for each bus node (BKj) of the bus nodes of the n bus nodes (BK1, BK2, ..... BKn-1, BKn), hereinafter referred to as the respective Bus junction (BKj) is designated,which does not have a valid bus node address: • Reception of the aforementioned auto-addressing command from the bus master (ECU) by the relevant bus node (BKj); • Reception of the bus address to be assigned from the bus master (ECU) by the relevant bus node (BKj); • Reception of a start signal for the assignment of the bus address to be assigned from the bus master (ECU) by the relevant bus node (BKj) and start of a timer at a start time (t0=0s) by the relevant bus node (BKj); • Detection of the voltage drop across the measuring resistor (Rmj) of the relevant bus node (BKj) as a base voltage value (Vm0) using measuring instruments (Rmj, D2,D3);• At a fourth time (t4) after the start time (t0): switching on the addressing current source (Iqj) of the relevant bus node (BKj) and adjusting the voltage drop across the measuring resistor (Rmj) of the relevant bus node (BKj) with the help of the addressing current source (Iqj) as a function of the voltage drop across the measuring resistor (Rmj) by means of a control signal (rwj) which is generated by measuring instruments (D2, D3, Rmj) and / or control instruments (F) of the bus node (BKj), to a total target voltage value which corresponds to a target voltage value as plus the previously measured base voltage value (Vm0),• wherein the addressing current of the auto-addressing current source (Iqj) of the relevant bus node (BKj) is increased by a first time constant (τ1) and • wherein the addressing current of the auto-addressing current source (Iqj) of the relevant bus node (BKj) is decreased by a second time constant (τ2); • At a fifth time point (t5) after the start time (t0) and after the fourth time point (t4): the value of the control signal (rwj) or a signal derived therefrom is detected and this value is compared with a threshold value and • the bus node address to be assigned is used as the valid bus node address of the bus node (BKj) if the magnitude of this value is above the threshold value and the addressing current source (Iqj) is switched off at least until the bus node (BKj) leaves the addressing state. Method according to the preceding claim 1 .- wherein the communication bus (DB) is a serial, bidirectional, differential two-wire communication bus (DB). Method according to the preceding claim 1 or 2 comprising the steps of signaling an addressing state, hereinafter referred to as power-line addressing state, to all bus nodes (BK1 to BKn), whereby these assume an addressing state for carrying out an auto-addressing procedure by means of the supply voltage line (Vbat) and signaling to bus nodes (BK1 to BKn) to invalidate their bus node addresses. Method according to the preceding claim 1 or 2 or 3 with the additional step:- verification of the successful address assignment by the bus master (ECU) after assignment of a bus node address to a bus node (BKj). Method according to the preceding claim 4 with the additional steps: - Deletion of the validity of the last assigned bus node address, whereby the relevant bus nodes (BKj) behave again as bus nodes (BKj) without a valid bus node address. Method according to the preceding claims 1 to 5 with the additional steps: - after assigning all bus node addresses to all bus nodes (BK1 to BKn) that should receive a bus node address: • Check whether all bus nodes (BK1 to BKn) that should receive a bus node address have received a valid bus node address; • Perform a further initialization sequence if not all bus nodes (BK1 to BKn) that should receive a bus node address have received a valid bus node address. Method according to one or more of the preceding claims 1 to 6,- wherein the second time constant (τ2) is smaller than the first time constant (τ1) by a factor greater than 10. Method according to one or more of the preceding claims 1 to 7,- wherein the second time constant (τ2) is smaller than the first time constant (τ1). Method according to one or more of the preceding claims 1 to 8, wherein the first time constant (t1) within the relevant auto-addressing bus node (BKj) depends on the value of the voltage drop across the measuring resistor (Rmj) of the relevant auto-addressing bus node (BKj) as measured by means of measuring instruments (Rmj, D2, D3) and / or wherein the second time constant (τ2) within the relevant auto-addressing bus node (BKj) depends on the value of the voltage drop across the measuring resistor (Rmj) of the relevant auto-addressing bus node (BKj) as measured by means of measuring instruments (Rmj, D2, D3).

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