IMAGE SENSOR WITH A SURFACE STRUCTURE WITH IMPROVED QUANTUM YIELD

Abstract

Semiconductor image sensor device (100) with: a semiconductor layer (104, 404) having a first surface and a second surface opposite the first surface; a connection structure arranged on the first surface of the semiconductor layer (104, 404); multiple radiation scanning regions (106A, 106B, 106C) fabricated in the semiconductor layer (104, 404), wherein the multiple radiation scanning regions (106A, 106B, 106C) are configured to detect radiation entering the semiconductor layer (104, 404) from the second surface; several trenches (306A, 306B, 306C, 306D), each trench (306A, 306B, 306C, 306D) being arranged between two radiation scanning regions (106A, 106B, 106C) of the multiple radiation scanning regions (106A, 106B, 106C) and having a depth greater than half the thickness of the semiconductor layer (104, 404), wherein the trenches (306A, 306B, 306C, 306D) are filled by a gap filling (902), the gap filling being made of a dielectric material; and several groove structures (408) that are produced on the second surface of the semiconductor layer (104, 404), wherein the gap filling (902) fills the groove structures (408).

Description

Background of the invention

[0001] Solid-state image sensors are used to detect radiation, such as light. CMOS (complementary metal oxide semiconductor) image sensors (CIS; IS) and CCD (charge-coupled device) sensors are used in various applications, such as digital cameras or camera applications in mobile phones. These devices use an array of pixels (which may include photodiodes and transistors) in a substrate to absorb (e.g., detect) radiation projected to the pixels and convert the sensed radiation into electrical signals. An example of an image sensor is a back-illuminated image sensor (BSI), which detects light from the back of a substrate.

[0002] Semiconductor image sensors and corresponding manufacturing processes are known, for example, from US 2005 / 0040440 A1, US 2016 / 0363673 A1, US 2005 / 0184353 A1, and US 2015 / 0287761 A1. Further semiconductor image sensors are known from US 2017 / 0110493 A1 and US 7759755 B2. Short description of the drawings

[0003] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. The Fig. 1 to 9 are cross-sectional views of an exemplary image sensor device having a quantum efficiency enhanced surface structure, according to some embodiments. The Fig. 10 and Fig. 11 are flow diagrams of example methods for fabricating an image sensor device having a quantum efficiency enhanced surface structure, according to some embodiments. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the component in use or operation, in addition to the orientation illustrated in the figures. The component may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] As used herein, the term "nominal" refers to a nominal or target value of a property or parameter for a component or process step, established during the design phase of a product or process, along with a range of values ​​above and / or below the nominal value. This range of values ​​may be due to variations in manufacturing processes or tolerances.

[0007] The term “substantially” used here indicates that the value of a given quantity may vary by ±5%.

[0008] The term "about" as used herein indicates the value of a given quantity, which may vary due to a particular technology node associated with the semiconductor device according to the invention. Depending on the specific technology node, the term "about" may indicate a value of a given quantity that varies within a range of, for example, 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0009] A BSI image sensor device comprises a silicon substrate or semiconductor material layer in which light-sensing pixels are fabricated. The quantum efficiency of a BSI image sensor may depend on its ability to absorb incident light in a radiation-sensing region. BSI image sensors may have a planarized silicon surface, which is compatible with process integration and control in semiconductor processes. However, the planarized surface may cause light to be reflected from the radiation-sensing region, resulting in a reduced quantum efficiency of BSI image sensors.

[0010] Various embodiments according to the present invention describe the fabrication of a BSI image sensor with improved quantum efficiency. By modifying the surface topography of the incident light region, the effective area of ​​the incident light region is increased without increasing the device dimensions. The modified surface topography also provides a material with an equivalent gradient refractive index (GRIN), which further improves light input power by reducing reflections. In addition, the BSI image sensors with improved quantum efficiency have a backside deep trench isolation (BDTI) structure with a greater depth embedded in a thick silicon layer to improve device isolation and reduce crosstalk in the silicon layer.The BDTI with the greater depth enables improved isolation between pixel sensors (e.g., between adjacent pixel sensors) because the trench depth of the BDTI is more than 50% of the thickness of the silicon layer. In some embodiments of the present invention, the BSI image sensor enables improved quantum efficiency by using at least the following components: (I) a modified surface topography having a periodic groove pattern / structure to increase the effective area of ​​the incident light region; (II) a material with an equivalent GRIN created by the modified surface topography to improve light input power; and (III) a BDTI structure with a greater depth embedded in a thick silicon layer to improve device isolation and reduce crosstalk.

[0011] Fig. Figure 1 is a cross-sectional view of a partially fabricated image sensor device 100 having improved quantum efficiency after pixels have been formed in a semiconductor layer, according to some embodiments of the present invention. The image sensor device 100 is a semiconductor image sensor device. The partially fabricated image sensor device 100 in Fig. 1 comprises a substrate 102, a semiconductor layer 104 and pixels 106A to 106C.

[0012] The substrate 102 may be a p-type substrate, such as a silicon material, doped with a p-type dopant such as boron. In some embodiments, the substrate 102 may be an n-type substrate, such as a silicon material, doped with an n-type dopant such as phosphorus or arsenic. In some embodiments, the substrate 102 may comprise germanium, diamond, a compound semiconductor, an alloy semiconductor, a silicon-on-insulator (SOI) structure, other suitable materials, or combinations thereof. The substrate 102 may have an initial thickness of about 100 µm to about 3000 µm. The substrate 102 has a backside 103.

[0013] The semiconductor layer 104 is formed on the substrate 102 and comprises a semiconductor material, such as silicon, germanium, a compound semiconductor, an alloy semiconductor, another suitable semiconductor material, or combinations thereof. In some embodiments, the semiconductor layer 104 may be an epitaxial material that is strained to improve performance. The semiconductor layer 104 has a front side 105. In some embodiments, the semiconductor layer 104 has a thickness greater than 2 µm. In some embodiments, the semiconductor layer 104 has a thickness greater than 3 µm. In some embodiments, the thickness of the semiconductor layer 104 may be in the range of about 3 µm to about 10 µm (e.g., 3 µm to 10 µm). The thickness of the semiconductor layer 104 may be determined by various factors.For example, in some embodiments, a greater thickness may improve the absorption of invisible light. In some embodiments, a greater thickness may increase manufacturing costs.

[0014] Radiation sensing regions are formed in the semiconductor layer 104, for example, pixels 106A to 106C. The pixels 106A to 106C are configured to detect radiation (or radiation waves), such as incident light waves. The pixels 106A to 106C each comprise a photodiode structure. In some embodiments, the pixels 106A to 106C may comprise pinned layer photodiodes, photogates, reset transistors, source follower transistors, transfer transistors, other suitable structures, or combinations thereof. The pixels 106A to 106C may also be referred to as “radiation detection devices” or “light sensors.” For simplicity, Fig. 1 illustrates three pixels 106A to 106C, but any number of pixels may be implemented in the semiconductor layer 104. In some embodiments, the pixels 106A to 106C are created by performing an implantation process on the semiconductor layer 104 from the front side 105. The implantation process may include doping the semiconductor layer 104 with a p-dopant such as boron. In some embodiments, the implantation process may include doping the semiconductor layer 104 with an n-dopant such as phosphorus or arsenic. In some embodiments, the pixels 106A to 106C may also be created using a diffusion process.

[0015] Fig. 2 is a cross-sectional view of a partially fabricated image sensor device 100 having improved quantum efficiency after an interconnect structure has been formed, according to some embodiments of the present invention. The partially fabricated image sensor device 100 is flipped, and the semiconductor layer 104 is wafer bonded to a carrier wafer 201 on the front side 105. In some embodiments, the carrier wafer 201 is bonded to the semiconductor layer 104 using a suitable bonding technique, such as fusion bonding, hybrid bonding, anodic bonding, or direct bonding, or other suitable bonding techniques or combinations thereof. The carrier wafer 201 may include an interlayer dielectric 202, conductive vias 204, conductive lines 206, a buffer layer 208, and a support substrate 210.

[0016] The interlayer dielectric 202 is arranged at (e.g., beneath) the front side 105 of the semiconductor layer 104. Embedded in the interlayer dielectric 202 are conductive layers and structures that provide connections (e.g., wiring) between various doped structural elements, circuits, and inputs / outputs of the image sensor device 100. The conductive layers and structures may be parts of a multilayer interconnect (MLI) structure that includes contacts, vias, and / or metal lines. As shown in Fig. 2, the vias 204 and the conductive lines 206 are embedded in the interlayer dielectric 202. The vias 204 and the conductive lines 206 are provided as examples, but other conductive structures may be used, and the positioning and configuration of the MLI structure may vary depending on the design requirements. The vias 204 and the conductive lines 206 may be made of conductive materials such as copper, aluminum, tungsten, doped polysilicon, other conductive materials, or combinations thereof. The MLI structure may be electrically connected to the pixels 106A-106C. Other circuitry and devices (not shown for simplicity) used to detect and process received light may also be embedded in the interlayer dielectric 202.

[0017] Buffer layer 208 may be formed using a dielectric material, such as silicon oxide, silicon nitride, another suitable material, or combinations thereof. Buffer layer 208 may be formed using suitable deposition techniques, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), another suitable technique, or combinations thereof. Buffer layer 208 may be planarized using a planarization process (e.g., chemical mechanical polishing) to create a smooth surface. In some embodiments, buffer layer 208 provides electrical isolation between substrate 102 and support substrate 210.

[0018] The support substrate 210 provides mechanical support for the partially fabricated image sensor device 100 so that processes can be performed on the backside 103. In some embodiments, the support substrate 210 may be fabricated using a material similar to the material of the substrate 102. For example, the support substrate 210 comprises a silicon material. In some embodiments, the support substrate 210 is a glass substrate. In some embodiments, the interlayer dielectric 202 is fabricated on the semiconductor layer 104, and the support substrate 210 is bonded to the interlayer dielectric 202 via the buffer layer 208.

[0019] Fig. Figure 3 is a cross-sectional view of an image sensor device 100 having improved quantum efficiency after trenches have been formed in a semiconductor layer, according to some embodiments of the present invention. The partially fabricated image sensor device 100 includes a patterned semiconductor layer 304 and trenches 306A through 306D.

[0020] The substrate 102 is removed, and the semiconductor layer 104 may be thinned before the trenches are formed. Any suitable method for removing the substrate 102 may be used, such as planarization (e.g., chemical mechanical polishing), wet etching or dry etching, or other suitable methods or combinations thereof.

[0021] After the substrate 102 has been removed, the semiconductor layer 104 is thinned and patterned to create trenches 306A to 306D between the pixels. Any suitable method for thinning the semiconductor layer 104 may be used, such as planarization (e.g., chemical mechanical polishing), wet etching or dry etching, or other suitable methods or combinations thereof. After the semiconductor layer 104 has been thinned and patterned, the patterned semiconductor layer 304 is formed. In some embodiments, the trenches 306A to 306D are formed in the semiconductor layer 104 without further thinning the semiconductor layer 104. As shown in Fig. 3, the patterned semiconductor layer 304 has a thickness T that may range from about 2 μm to about 10 μm. In some embodiments, a depth D of the trenches 306A-306D may be greater than half the thickness T of the semiconductor layer 104. In some embodiments, the trenches may have a high aspect ratio, for example, greater than 6. The etch process for the trenches 306A-306D may be a timed etch process that continues until nominal depths of the trenches are reached, such as a nominal depth greater than half the thickness of the semiconductor layer. In some embodiments, the depth of the trenches may be substantially equal to the thickness of the semiconductor layer 104.

[0022] Fig. 4 is a cross-sectional view of an image sensor device 100 having improved quantum efficiency after grooves are formed on a top surface of a patterned semiconductor layer, according to some embodiments of the present invention.

[0023] First, pins 402 are deposited to form the trenches 306A to 306D of Fig. 3. A suitable material, such as a dielectric material, may be used for the pins 402. In some embodiments, the pins 402 may comprise an epoxy-based polymer. In some embodiments, the pins 402 may comprise a resin material. The material for the pins is deposited by protective deposition, followed by a planarization process such that top surfaces of the deposited pin material in the trenches are coplanar with a top surface of the patterned semiconductor layer 304 of Fig. 3. The pins 402 are used to fill the trenches so that after the planarization process, a coplanar top surface of the pins 402 and the patterned semiconductor layer 304 is ready for deposition of a hard mask layer.

[0024] A hardmask material is deposited on the planar top surfaces of the pins 402, which is patterned into a patterned hardmask layer 406, exposing portions of the patterned semiconductor layer 304. In some embodiments, the hardmask material is made of a dielectric material, such as silicon nitride. The hardmask material may be deposited using any suitable deposition method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), or other suitable methods, or combinations thereof.

[0025] Exposed portions of the patterned semiconductor layer 304 that are not covered by the patterned hard mask layer 406 are etched to form a periodic pattern of groove structures, such as grooves 408. After the etching process, the patterned semiconductor layer 304 becomes a grooved semiconductor layer 404. As shown in Fig. 4, the grooves 408 form a periodic groove pattern on top of the grooved semiconductor layer 404 and between the pins 402. As a result, the grooves 408 change the surface topography of the semiconductor material between the pins 402, such that an additional surface area of ​​the semiconductor material is exposed between the pins 402 compared to a planar surface of the semiconductor layer. In other words, in some embodiments, the grooves 408 enable an increase in the exposed area per unit horizontal area, which can be achieved without adjusting the spacing between the pins 402. By increasing the exposed area, the effective area of ​​the incident light of the semiconductor material is increased, which in turn increases the intensity of the incident light received by the pixels 106A to 106C. This improves the quantum efficiency of the pixels.Furthermore, various groove configurations of the present invention can enable multiple reflections of incident light within the grooves, which in turn increases the likelihood that incident light will be absorbed by pixels 106A through 106C. For example, by appropriately selecting a nominal sidewall angle of the groove, light can be reflected multiple times from the sidewalls without leaving the groove, thus increasing the proportions of light absorbed by the semiconductor material. Furthermore, the sidewall angles can change from an upper part to a lower part of the groove structure. According to Fesnel's equations, the reflection coefficient and the transmission factor of light propagating between media with different refractive indices can change with respect to the angle of incidence of the light.As light propagates into the semiconductor layer 304, the groove structure may exhibit a gradient change in equivalent refractive index from the top to the bottom of the groove structure due to the gradient change in the sidewall angles of the groove structure. Therefore, the groove structure may provide a material with an equivalent gradient refractive index (GRIN), which reduces Fresnel reflection by creating a region with an equivalent gradient refractive index. Thus, the quantum efficiency can be improved by reducing Fresnel reflection at the interface of the semiconductor layer 304.

[0026] As in Fig. 4, each groove 408 of the periodic pattern of groove structures may have a triangular cross-sectional profile. In some embodiments, other cross-sectional profile shapes may be achieved and used with suitable etching processes and material properties of the grooved semiconductor layer 404. In some embodiments, the triangular cross-sectional profile of the grooves 408 may be created by first performing an anisotropic dry etch followed by a wet etch. With the anisotropic dry etch, groove structures with a triangular cross-sectional profile may be created. With the chemical wet etch, the rectangular semiconductor layer 404 may be etched due to the chemical properties of the etchant and the crystal orientation of the etched semiconductor material, so that different etch profiles may be created (e.g., resulting in the triangular cross-sectional profile).

[0027] In some embodiments, the grooved semiconductor layer 404 may be made of silicon with a (111) orientation. In some embodiments, the grooved semiconductor layer 404 may be made of silicon with, for example, crystal orientations (100), (110), or other suitable orientations. In some embodiments, the dry etch process may be a fluorine-based etch process, a chlorine-based etch process, another suitable process, or a combination thereof. In some embodiments, the wet etch process may use a fluoric acid-based etch chemistry, a nitric acid-based etch chemistry, another suitable etchant, or a combination thereof. In some embodiments, the wet etch process may etch the semiconductor layer 304 isotropically, and a portion of the patterned semiconductor layer 304 under the patterned hard mask layer 406 is also etched.Further details on the different etch profiles are given below with reference to the . Fig. 6 to 8 discussed.

[0028] Fig. 5 is a cross-sectional view of an image sensor device 100 having improved quantum efficiency after removing the studs and the patterned hard mask layer, according to some embodiments of the present invention. The studs 402 and the patterned hard mask layer 406 may be removed using a suitable method, such as planarization (e.g., chemical mechanical polishing), wet etching, or dry etching, or other suitable removal methods or combinations thereof. The removal method may be selected such that the grooved semiconductor layer 404 is not etched during removal.

[0029] After the removal process, the trenches 306A to 306D reappear in the image sensor device 100. In some embodiments, after removing the patterned hard mask layer, a second wet etch process may be performed on the grooved semiconductor layer to create a nominal cross-sectional profile for the grooves. In some embodiments, substantially the same etching chemistries may be used for the second wet etch process as for the wet etch process described with reference to Fig. 4. In some embodiments, other etching chemicals may be used for the second wet etching process. In some embodiments, the second wet etching process may be used to refine the etch profile, and it may be performed for a shorter duration than the second wet etching process described with reference to Fig. 4 may be performed. For example, the second wet etching process may be used to create substantially planar surfaces between the grooves 408.

[0030] The Fig. 6 to 8 are cross-sectional views of various groove configurations for an image sensor device 100 having improved quantum efficiency after the studs and patterned hard mask layer have been removed, according to some embodiments of the present invention.

[0031] Fig. 6 is a sectional view of grooves 408 having a triangular cross-sectional profile. As in Fig. 6, each groove 408 has a depth d1, a width w1, and an angle α with respect to the sidewall surface, and is parallel to a top surface 602 of the grooved semiconductor layer 404. The angle α is measured at various locations in the groove. A distance between adjacent grooves 408 may be measured from a center point of the triangle and is denoted by l1. In some embodiments, the depth d1 may be about 20 nm to about 500 nm (e.g., 20 nm to 500 nm), the pitch l1 may be about 0.1 μm to about 0.5 μm (e.g., 0.1 μm to 0.5 μm), and the angle α may be about 45° to about 60° (e.g., 45° to 60°). By appropriately selecting a nominal sidewall angle (e.g., angle α) of the groove, light can be reflected multiple times from the sidewalls without leaving the grooves 408.With each reflection, light is absorbed in the semiconductor material, so the quantum efficiency increases by increasing the amount of light absorbed and processed by pixels 106A to 106C.

[0032] Fig. 7 is a sectional view of grooves 408 having a rectangular cross-sectional profile. As in Fig. 7, each groove 408 has a depth d2 and a width w2. A distance between adjacent grooves 408 may be measured from a center point of the rectangle and is denoted by l2. In some embodiments, the depth d2 and the width w2 may each be about 20 nm to about 500 nm (e.g., 20 nm to 500 nm), and the distance l2 may be about 0.1 µm to about 0.5 µm (e.g., 0.1 µm to 0.5 µm). Similar to the angle α shown in Fig. 6, the angle α can be Fig. 7 at various points on the side wall in the grooves 408.

[0033] Fig. 8 is a sectional view of grooves 408 having a semi-oval cross-sectional profile. As in Fig. 8, each groove 408 has a depth d3 and a width w3. A distance between adjacent grooves 408 may be measured from a center point of the semi-oval shape and is denoted by l3. In some embodiments, the depth d3 and the width w3 may each be about 20 nm to about 500 nm (e.g., 20 nm to 500 nm), and the distance l3 may be about 0.1 µm to about 0.5 µm (e.g., 0.1 µm to 0.5 µm). Similar to the angle α shown in Fig. 6, the angle α can be Fig. 8 at various points on the side wall in the grooves 408.

[0034] For grooves 408 having a triangular, rectangular, or semi-oval cross-sectional profile, or other suitable cross-sectional profiles, the angle α is an angle measured at a given position on the groove sidewall relative to the sidewall surface and a direction parallel to the top surface 602. In some embodiments, the angle α may change from an upper portion to a lower portion of the grooves 408, and the grooves may act like a material with an equivalent GRIN, reducing Fresnel reflection by creating a region with an equivalent gradient refractive index, which in turn enables better quantum efficiency.

[0035] Fig. Figure 9 is a cross-sectional view of an image sensor device 100 having improved quantum efficiency after a passivation layer and other structures have been formed, according to some embodiments of the present invention. The image sensor device 100 may include a gap fill 902, a buffer layer 904, grating structures 906, and a passivation layer 908.

[0036] The gap fill 902 is formed by a protective deposition over the grooved semiconductor layer 404, followed by a planarization process. The gap fill 902 fills the trenches 306A to 306D, the grooves 408, and other exposed surfaces of the grooved semiconductor layer 404. The gap fill 902 may be formed using a suitable dielectric material, such as silicon oxide or silicon nitride, or other suitable dielectric materials, or combinations thereof. In some embodiments, a cap layer (not shown) is formed between the grooved semiconductor layer 404 and the gap fill 902. The cap layer may be formed using a high-k dielectric material, such as hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), or another high-k material, or combinations thereof.The material for the gap fill 902 may be deposited using a suitable deposition method, such as atomic layer deposition (ALD), molecular beam epitaxy (MBE), high-density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma CVD (RPCVD), plasma enhanced chemical vapor deposition (PECVD), plating, or other suitable methods, or combinations thereof. After the gap fill material is deposited, a planarization process, such as chemical mechanical polishing, is performed on the deposited gap fill material to achieve a planar top surface of the gap fill 902. In some embodiments, the gap fill 902 is deposited into the trenches 306A-306D to establish BDTI and avoid crosstalk between pixels (e.g., neighboring pixels). As described above with reference to FIG. Fig. 3, the trenches 306A to 306D may have a high aspect ratio with depths greater than half the thickness T of the patterned semiconductor layer 304.

[0037] In some embodiments, a buffer layer 904 may be formed on top of the gap fill 902. A buffer material is deposited by protective deposition, followed by a planarization process to form the buffer layer 904 and provide a planar top surface for one or more subsequent manufacturing processes. In some embodiments, the buffer layer 904 may be made of the same dielectric material as the gap fill 902. In some embodiments, the buffer layer 904 may be made of a different dielectric material.

[0038] Grating structures 906 are formed on the buffer layer 904. In some embodiments, the grating structures 906 may be formed by depositing a metal layer on the buffer layer 904 and performing a patterning process. The grating structures 906 may be used to reduce crosstalk between pixels (e.g., between neighboring pixels) and may include a metal grid used to reflect light to corresponding pixels 106A-106C. In some embodiments, the grating structures 906 are formed using a metal, such as copper, tungsten, aluminum, or another suitable metal, or a combination thereof. In some embodiments, the grating structures 906 are formed using a material that has high reflectivity.In some embodiments, the grating structures 906 may have a stacked structure in which additional dielectric grating structures are fabricated on top of the grating structures 906. In some embodiments, the grating structures 906 may each have a height of about 200 nm to about 300 nm (e.g., 200 nm to 300 nm). For example, the grating structures 906 may have a height of about 250 nm.

[0039] A passivation layer 908 is formed on the buffer layer 904 and the grating structures 906. The passivation layer 908 may be formed by protectively depositing a dielectric layer on the buffer layer 904 and the grating structures 906. In some embodiments, the passivation layer 908 may have a thickness of about 400 nm to about 600 nm. For example, the passivation layer 908 may have a thickness of about 500 nm.

[0040] Pixels 106A through 106C are configured to detect radiation (or radiation waves), such as incident light 910 projected toward passivation layer 908. Incident light 910 enters image sensor device 100 through the backside and may be detected by one or more of pixels 106A through 106C. In some embodiments, image sensor device 100 may be used not only to detect visible light but also to detect invisible light due to the greater depth of the grooved semiconductor material and reduced crosstalk between pixels.

[0041] Fig. 10 is a flowchart of an exemplary method 1000 for fabricating an image sensor device with improved quantum efficiency, according to some embodiments of the present invention. Different steps than in the exemplary method 1000 may be performed, and steps of the method 1000 may be performed in a different order and / or may differ.

[0042] In step 1002, in some embodiments, pixels are formed in a semiconductor layer and over a substrate. The substrate may be a p-type substrate or an n-type substrate. The substrate may have an initial thickness of about 100 μm to about 3000 μm. A semiconductor layer may be formed on the substrate. In some embodiments, the semiconductor layer may be an epitaxial material that may be strained to improve performance. In some embodiments, the semiconductor layer has a thickness greater than 2 μm. The pixels may be formed in the semiconductor layer and configured to detect radiation, such as incident light waves. In some embodiments, the pixels are capable of sensing invisible light. The pixels may each comprise a photodiode structure. Examples of the substrate, the semiconductor layer, and the pixels may include the substrate 102, the semiconductor layer 104, and the substrate 102, respectively.the pixels 106A to 106C described above with reference to . Fig. 1 have been described.

[0043] In step 1004, in some embodiments, an interconnect structure is fabricated. A carrier wafer with the interconnect structure may be bonded to the semiconductor layer. The semiconductor layer may be bonded to the carrier wafer using a suitable bonding method, such as fusion bonding or hybrid bonding, or other suitable bonding methods, or combinations thereof. The carrier wafer may include an interlayer dielectric, conductive vias, conductive lines, a buffer layer, and a carrier substrate. An example of the carrier wafer and its components may be the carrier wafer 201 and its corresponding components, which were described above with reference to Fig. 2. The interlayer dielectric may be formed on the semiconductor layer. Conductive layers and structures may be embedded in the interlayer dielectric, providing connections between various structural elements, circuits, and inputs / outputs of the image sensor device. Examples of the conductive layers and structures may be the vias 204 and the conductive lines 206 described above with reference to Fig. 2 have been described.

[0044] In step 1006, in some embodiments, trenches are created in the semiconductor layer. The substrate is removed, and the semiconductor layer may be thinned before the trenches are created. The trenches are created between pixels, and the depth of the trenches may be greater than half the thickness of the semiconductor layer. In some embodiments, the semiconductor layer may have a thickness in the range of about 2 μm to about 10 μm. Examples of the trenches may be trenches 306A to 306D described above with reference to Fig. 3 have been described.

[0045] In step 1008, in some embodiments, grooves are created on a top surface of the semiconductor layer. Studs are deposited to fill the trenches (created in step 1006) so that, after a planarization process, a coplanar top surface of the stud material and the semiconductor layer is ready for deposition of a hard mask layer. Then, a hard mask material is deposited on the planar top surface and patterned into a patterned hard mask layer, exposing portions of the semiconductor layer. Examples of the studs and the patterned hard mask layer may be the studs 402 and the patterned hard mask layer 406 described above with reference to Fig. 4 have been described.

[0046] Exposed portions of the semiconductor layer not covered by the patterned hard mask layer are etched to create a periodic pattern of groove structures. The grooves form a periodic depression pattern on top of the semiconductor layer, with the depressions located between pins. As a result, the grooves change the surface topography of the semiconductor material between the pins, exposing additional surface area of ​​the semiconductor material between the pins compared to a planar surface. This additional surface area is achieved without increasing the spacing between the pins. By increasing the exposed surface area, the effective area of ​​the incident light of the semiconductor material is increased, which in turn increases the intensity of the incident light received by the pixels. This improves the quantum efficiency of the pixels.Furthermore, various groove configurations of the present invention can enable multiple reflections of incident light within the grooves. These multiple reflections increase the probability that incident light is absorbed by the pixels, which also improves quantum efficiency. The modified surface topography can also provide a material with an equivalent gradient refractive index (GRIN), further improving light input power by reducing reflections.

[0047] In some embodiments, nominal groove profiles can be achieved with an anisotropic dry etching process followed by a wet etching process. The anisotropic dry etching process can create groove structures with a rectangular cross-sectional profile. A chemical wet etching process can etch the rectangular semiconductor layer due to the chemical properties of the etchant and the crystal orientation of the etched semiconductor material. The etch rate and etch direction are based on the chemical nature of the selected etchant and the crystal orientation of the etched semiconductor material, so that different etch profiles can be achieved. Examples of the different cross-sectional profiles of the recesses and the corresponding etching methods and material compositions are described above in the Fig. 4 to 8 can be found.

[0048] In step 1010, in some embodiments, a passivation layer and other structures are formed on the semiconductor layer. A gap fill material is deposited over the semiconductor layer to fill the trenches and grooves. In some embodiments, a cap layer is formed between the semiconductor layer and the gap fill material using a high-k dielectric material. After the gap fill material is deposited, a planarization process may be performed on the deposited gap fill material to achieve a planar top surface. The gap fill material deposited into the trenches forms a BDTI, which may prevent crosstalk between pixels (e.g., between neighboring pixels).Since the trenches can have a high aspect ratio with depths greater than half the thickness of the semiconductor layer, the gap fill material provides a depth coverage greater than half the thickness of the semiconductor layer, creating separation between pixels and avoiding crosstalk between pixels (e.g., between neighboring pixels).

[0049] Fig. 11 is a flowchart of an exemplary method 1100 for fabricating an image sensor device with improved quantum efficiency, according to some embodiments of the present invention. Different steps than in the exemplary method 1100 may be performed, and steps of the method 1100 may be performed in a different order and / or may differ.

[0050] In step 1102, in some embodiments, pixels are formed in a semiconductor layer and over a substrate. In step 1104, in some embodiments, an interconnect structure is formed. In some embodiments, steps 1102 and 1104 may be similar to steps 1002 and 1004, respectively, described above in the exemplary method 1000 of Fig. 10. In some embodiments, steps 1102 and 1104 may be different from steps 1002 and 1004.

[0051] In step 1106, in some embodiments, grooves are created on a top surface of the semiconductor layer. A hard mask material is deposited on a planar top surface of the semiconductor layer and patterned into a patterned hard mask layer, exposing portions of the semiconductor layer. The exposed portions of the semiconductor layer not covered by the patterned hard mask layer are etched to form a periodic pattern of groove structures. The grooves form a periodic groove pattern on the top surface of the semiconductor layer, with the grooves located between the posts. As a result, the grooves change the surface topography of the semiconductor material between the posts, exposing an additional surface area of ​​the semiconductor material compared to a planar surface. The additional surface area is achieved without increasing the spacing between the posts.The additional surface area can improve the quantum efficiency of the pixels in a manner similar to the enhanced quantum efficiency effect discussed above with reference to . Fig. 4. Furthermore, various groove configurations of the present invention can enable multiple reflections of the incident light in the groove. The multiple reflections increase the probability that incident light is absorbed by the pixels, which also improves the quantum efficiency. The modified surface topography also provides a material with an equivalent gradient refractive index (GRIN), so that the light input power is further improved by reducing reflections. In some embodiments, nominal groove profiles can be achieved with an anisotropic dry etching process followed by a wet etching process. The anisotropic dry etching process and the chemical wet etching process can be similar to the etching processes described above with reference to Fig. 4. Examples of the different cross-sectional profiles of the grooves and the corresponding etching processes and material compositions are described above in the Fig. 4 to 8 can be found.

[0052] In step 1108, in some embodiments, trenches are created in the semiconductor layer. The substrate is removed, and the semiconductor layer may be thinned before the trenches are created. The trenches are created between pixels, and the depth of the trenches may be half the thickness of the semiconductor layer. In some embodiments, the semiconductor layer may have a thickness in the range of about 2 µm to about 10 µm. In some embodiments, the depth of the trenches may be substantially equal to the thickness of the semiconductor layer. Studs are deposited to fill the trenches to create a coplanar top surface of the stud material and the semiconductor layer after a planarization process.

[0053] In step 1110, in some embodiments, a passivation layer and other structures are formed on the semiconductor layer. In some embodiments, step 1110 may be similar to step 1010 described above with reference to Fig. 10. In some embodiments, step 1110 may be different from step 1010.

[0054] A buffer layer and grating structures may be fabricated over the top of the gap fill material. The buffer layer may be fabricated using a dielectric material and may provide a planar top surface for one or more subsequent fabrication processes. The grating structures may be fabricated on the buffer layer and may reduce crosstalk between pixels (e.g., between neighboring pixels). The grating structures may include a metal grid used to reflect light to corresponding pixels, and they may also include dielectric grid structures fabricated on the metal grid. A passivation layer may be fabricated on the buffer layer and the grating structures.

[0055] The present invention describes the fabrication of a BSI image sensor with improved quantum efficiency. The effective area of ​​the incident light region is increased without increasing the device dimensions by modifying the surface topography of the incident light region. The modified surface topography also provides a material with an equivalent gradient refractive index (GRIN), which further improves the light input power by reducing reflections. In addition, the BSI image sensors with improved quantum efficiency have a backside deep trench isolation (BDTI) structure with a greater depth embedded in a thick silicon layer to improve device isolation and reduce crosstalk in the silicon layer. The greater depth BDTI enables improved isolation between pixel sensors (e.g.,between adjacent pixel sensors), since the trench depth of the BDTI is more than 50% of the silicon layer thickness. The BSI image sensor enables improved quantum efficiency at least by using a modified surface topography that has a periodic groove pattern / structure to increase the effective area of ​​the incident light region. A BDTI structure with greater depth can be embedded in a thick silicon layer to improve device isolation and reduce crosstalk.

[0056] In some embodiments, a semiconductor image sensor device comprises a semiconductor layer having a first surface and a second surface opposite the first surface. An interconnect structure is formed on the first surface of the semiconductor layer. The semiconductor image sensor device comprises a plurality of trenches, each trench being arranged between two radiation sensing regions of the plurality of radiation sensing regions and having a depth greater than half a thickness of the semiconductor layer, the trenches being filled by a gap filling, the gap filling being made of a dielectric material. A plurality of radiation sensing regions are formed in the semiconductor layer and are configured to detect radiation entering the semiconductor layer from the second surface.The semiconductor image sensor device further comprises a plurality of groove structures formed on the second surface of the semiconductor layer, wherein the gap filling fills the groove structures.

[0057] In some embodiments, a semiconductor image sensor device comprises a semiconductor layer having a front side and a back side opposite the front side. The back side of the semiconductor layer comprises a plurality of groove structures. A plurality of pixels are formed in the semiconductor layer and are configured to detect light entering the semiconductor layer at least through the plurality of groove structures. The semiconductor image sensor device further comprises a plurality of separation structures, wherein at least one of the separation structures is arranged between two pixels of the plurality of pixels and has a depth of at least half a thickness of the semiconductor layer, wherein the separation structures comprise trenches filled by a gap filling, and the gap filling is made of a dielectric material and fills the groove structures.

[0058] In some embodiments, a method of fabricating a semiconductor image sensor device comprises forming a plurality of pixels in a semiconductor layer. The semiconductor layer has a first surface and a second surface opposite the first surface. The method further comprises disposing an interconnect structure on the second surface of the semiconductor layer and depositing and patterning a hard mask layer over the first surface of the semiconductor layer. The patterned hard mask layer exposes portions of the first surface over the plurality of pixels. A first etch process is performed on the exposed portions of the semiconductor layer. A second etch process is performed on the exposed portions of the semiconductor layer. The first and second etch processes create a plurality of grooves in the first surface of the semiconductor layer.The method further comprises creating a plurality of trenches in the semiconductor layer, wherein each trench of the plurality of trenches is created between pixels of the plurality of pixels, wherein after creating the plurality of trenches, a gap filling is deposited and the plurality of trenches and the grooves are filled with the gap filling such that the gap filling fills the trenches and the grooves.

Claims

[1] A semiconductor image sensor device (100) comprising: a semiconductor layer (104, 404) having a first surface and a second surface opposite the first surface; an interconnection structure disposed on the first surface of the semiconductor layer (104, 404); a plurality of radiation sensing regions (106A, 106B, 106C) formed in the semiconductor layer (104, 404), the plurality of radiation sensing regions (106A, 106B, 106C) configured to detect radiation entering the semiconductor layer (104, 404) from the second surface; a plurality of trenches (306A, 306B, 306C, 306D), each trench (306A, 306B, 306C, 306D) being arranged between two radiation scanning regions (106A, 106B, 106C) of the plurality of radiation scanning regions (106A, 106B, 106C) and having a depth greater than half a thickness of the semiconductor layer (104, 404), the trenches (306A, 306B, 306C, 306D) being filled by a gap filling (902), the gap filling being made of a dielectric material; and a plurality of groove structures (408) formed on the second surface of the semiconductor layer (104, 404), wherein the gap filling (902) fills the groove structures (408). [2] The semiconductor image sensor device (100) according to claim 1, wherein a groove structure of the plurality of groove structures (408) has a triangular cross-sectional profile. [3] The semiconductor image sensor device (100) according to claim 2, wherein a side wall of the groove structure forms an angle of 45° to 60° with the second surface of the semiconductor layer (104, 404). [4] The semiconductor image sensor device (100) according to claim 1, wherein a groove structure of the plurality of groove structures (408) has a rectangular cross-sectional profile. [5] The semiconductor image sensor device (100) according to claim 1, wherein a groove structure of the plurality of groove structures (408) has a semi-oval cross-sectional profile. [6] The semiconductor image sensor device (100) according to any one of the preceding claims, wherein a distance between the individual groove structures (408) of the plurality of groove structures (408) is about 0.1 micrometers (µm) to about 0.5 µm. [7] The semiconductor image sensor device (100) of any preceding claim, wherein a groove structure of the plurality of groove structures (408) has a depth of about 20 nanometers (nm) to about 500 nm. [8] The semiconductor image sensor device (100) according to any one of the preceding claims, wherein a groove structure of the plurality of groove structures (408) has a width of about 20 nm to about 500 nm. [9] A semiconductor image sensor device (100) according to any one of the preceding claims, wherein the depth (D) of the trenches (306A, 306B, 306C, 306D) is substantially equal to the thickness (T) of the semiconductor layer (104, 404). [10] The semiconductor image sensor device (100) according to any one of the preceding claims, wherein an angle between a side wall of a groove structure of the plurality of groove structures (408) with respect to the second surface of the semiconductor layer (104, 404) changes from an upper part to a lower part of the groove structure. [11] A semiconductor image sensor device (100) comprising: a semiconductor layer (104, 404) having a front side and a back side opposite the front side, wherein the back side of the semiconductor layer (104, 404) has a plurality of groove structures (408); a plurality of pixels formed in the semiconductor layer (104, 404), the plurality of pixels configured to detect light entering the semiconductor layer (104, 404) at least through the plurality of groove structures (408); and a plurality of separation structures, wherein at least one of the separation structures is arranged between two pixels of the plurality of pixels and has a depth of at least half a thickness of the semiconductor layer (104, 404), wherein the separation structures have trenches (306A, 306B, 306C, 306D) filled by a gap filling, and the gap filling (902) is made of a dielectric material and fills the groove structures (408). [12] The semiconductor image sensor device (100) according to claim 11, wherein the thickness of the semiconductor layer (104, 404) is greater than 3 µm. [13] A semiconductor image sensor device (100) according to claim 11 or 12, wherein the depth (D) of the trenches (306A, 306B, 306C, 306D) is substantially equal to the thickness (T) of the semiconductor layer (104, 404). [14] The solid-state image sensor device (100) of any one of claims 11 to 13, further comprising a cap layer between the gap guide (902) and the semiconductor layer (104, 404), the cap layer comprising a high-k material. [15] The semiconductor image sensor device (100) according to any one of claims 11 to 14, wherein a groove structure of the plurality of groove structures (408) has a triangular cross-sectional profile. [16] A method of manufacturing a semiconductor image sensor device (100), comprising the following steps: forming a plurality of pixels in a semiconductor layer (104, 404) having a first surface and a second surface opposite the first surface; Arranging an interconnect structure on the second surface of the semiconductor layer (104, 404); depositing and patterning a hard mask layer over the first surface of the semiconductor layer (104, 404), the patterned hard mask layer exposing portions of the first surface over the plurality of pixels; performing a first etching process on the exposed parts of the semiconductor layer (104, 404); and Performing a second etching process on the exposed parts of the semiconductor layer (104, 404), wherein the first and the second etching process produce a plurality of grooves (408) in the first surface of the semiconductor layer (104, 404), the method further comprising producing a plurality of trenches (306A, 306B, 306C, 306D) in the semiconductor layer (104, 404), each trench (306A, 306B, 306C, 306D) of the plurality of trenches (306A, 306B, 306C, 306D) being produced between pixels of the plurality of pixels, wherein after producing the plurality of trenches (306A, 306B, 306C, 306D), a gap filling (902) is deposited and the plurality of trenches (306A, 306B, 306C, 306D) and the grooves (408) are filled with the gap filling (902) so that the gap filling (902) fills the trenches (306A, 306B, 306C, 306D) and the grooves (408). [17] The method of claim 16, wherein after the deposition of the gap filling (902), the gap filling (902) is planarized. [18] The method of claim 16 or 17, wherein a depth of the plurality of trenches (306A, 306B, 306C, 306D) is greater than half a thickness of the semiconductor layer (104, 404). [19] The method of any one of claims 16 to 18, wherein the first and second etching processes are selected based on a crystal orientation of the semiconductor layer (104, 404). [20] The method of any one of claims 16 to 19, wherein at least one groove of the plurality of grooves has an angle between a sidewall of the at least one groove with respect to the second surface of the semiconductor layer (104, 404), the angle changing in the at least one groove.

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