NEGATIVE CAPACITY SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF IT

Abstract

Method for producing a structure with negative capacitance, the method comprising: forming a ferroelectric dielectric layer (105, 115) over a first conductive layer arranged over a substrate (100); and forming a second conductive layer (106, 116) over the ferroelectric dielectric layer (105, 115), wherein the ferroelectric dielectric layer (105, 115) comprises an amorphous layer (120) and crystals (123, 125), wherein the crystals (123, 125) are nanocrystals distributed in the amorphous layer (120), wherein an average size of the nanocrystals is in the range of 0.5 nm to 5 nm, wherein the amorphous layer (120) and the crystals (123, 125) are made of the same material, including HfO2 and an oxide of a metallic element, wherein the metallic element is one or more selected from the group consisting of Zr, Al, La, Y, G and Sr.

Description

[0001] This application claims priority from the preliminary US patent application No. 62 / 552,900, filed on August 31, 2017, the entire contents of which are incorporated herein by reference. TECHNICAL AREA

[0002] The disclosure concerns integrated semiconductor circuits and especially semiconductor devices that are field-effect transistors with negative capacitance ( NCFET ) include. BACKGROUND

[0003] The subthreshold swing is a feature of a transistor's current-voltage characteristic. In the subthreshold region, the drain current behavior is similar to the exponentially increasing current of a forward-biased diode. A graphical representation of a logarithmic drain current versus the gate voltage with fixed drain, source, and bulk voltages will show approximately logarithmic linear behavior in this metal-oxide-semiconductor FET (MOSFET) operating region. To improve the subthreshold characteristics, a field-effect transistor with negative capacitance ( NCFET ) using a ferroelectric material. List of characters

[0004] The aspects of this disclosure will be best understood with the help of the following detailed description and the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be enlarged or reduced arbitrarily for the clarity of the discussion. The Fig. 1A and Fig. 1B shows sectional views of NCFET of the metal-insulator-semiconductor FET type (MIS-FET type) and Fig. 1C shows a sectional view of a NCFET of the metal-insulator-metal-insulator-semiconductor FET type (MIMIS-FET type). The Fig. 2A, Fig. 2B and Fig. Figures 2C show various structures of a ferroelectric layer according to embodiments of the present disclosure. The Fig. 3A, Fig. 3B, Fig. 3C and Fig. 3D images show various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. The Fig. 4A, Fig. 4B, Fig. 4C and Fig. Figure 4D shows various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. The Fig. 5A and Fig. Figure 5B shows various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. The Fig. 5C and Fig. Figure 5D shows various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. The Fig. 6A, Fig. 6B, Fig. 6C and Fig. Figure 6D shows various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. The Fig. 7A, Fig. 7B, Fig. 7C and Fig. Figure 7D shows various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. The Fig. 8A and Fig. Figure 8B shows various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. The Fig. 8C and Fig. Figure 8D shows various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. Fig. Figure 9 shows a schematic view of a film-forming device according to an embodiment of the present disclosure. The Fig. 10A and Fig. Figure 10B shows one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. The Fig. 11A and Fig. Figure 11B shows one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. The Fig. 12A and Fig. Figure 12B shows one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. The Fig. 13A and Fig. Figure 13B shows one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. The Fig. 14A, Fig. 14B and Fig. Figure 14C shows one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. The Fig. 15A, Fig. 15B and Fig. Figure 15C shows one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. The Fig. 16A, Fig. 16B and Fig. Figure 16C shows one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. The Fig. 17A, Fig. 17B and Fig. Figure 17C shows one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. The Fig. 18A, Fig. 18B and Fig. 18C shows one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. Fig. Figure 19 shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. Fig. Figure 20 shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. Fig. Figure 21 shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. The Fig. 22A and Fig. Figure 22B shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. Fig. Figure 23 shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. The Fig. 24A and Fig. Figure 24B shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. The Fig. 25A and Fig. Figure 25B shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. The Fig. 26A and Fig. Figure 26B shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. The Fig. 27A and Fig. Figure 27B shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. The Fig. 28A and Fig. Figure 28B shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. The Fig. 29, Fig. 29B and Fig. Figure 29C shows one of several stages of manufacturing work steps for a NCFET and one FET according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0005] It is understood that the following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values ​​but may depend on process conditions and / or desired properties of the component.Furthermore, the formation of a first feature over or on top of a second feature, as described below, can include embodiments in which the first and second features are in direct contact, and can also include embodiments in which additional features can be inserted between the first and second features, so that the first and second features may not be in direct contact. For the sake of simplicity and clarity, various features are arbitrarily drawn at different scales. In the accompanying drawings, some layers / features may be omitted for the sake of simplicity.

[0006] Furthermore, spatial reference terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for the sake of simplicity to describe the relationship of an element or feature to one or more other elements or features, as illustrated in the figures. These spatial reference terms are intended to encompass different orientations of the component in use or operation, in addition to the orientation shown in the figures. The component may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial reference descriptors used herein may be interpreted accordingly. Moreover, the term "made of" may mean either "comprising" or "consisting of."Furthermore, the following manufacturing process may include one or more additional work steps in / between the described work steps, and the sequence of the work steps may be changed.

[0007] To control the subthreshold swing (S.-S.) of a field-effect transistor ( FET To reduce ) a negative capacitance (NC) technology, such as integrating ferroelectric (FE) materials, provides a feasible solution to significantly reduce VDD (power supply) and achieves a FET with a steep slope for operation with low energy consumption.

[0008] In a NCFET A capacitor (e.g., a ferroelectric (FE) capacitor) with a negative capacitance is connected in series with the gate of a MOSFET. In some embodiments, the ferroelectric negative capacitor can be a separate capacitor connected to the gate of the MOSFET by a conductive layer (e.g., wire / contact). In other embodiments, one of the electrodes of the negative capacitor is a gate electrode of the MOSFET.

[0009] In conventional electronic devices, dielectric materials with high k-values, such as HfO2, are usually an amorphous layer. However, undoped HfO2 is amorphous and paraelectric, exhibiting no negative capacitance effect. This disclosure provides a ferroelectric layer containing grains of a stabilized crystalline phase and its production methods. The correct combinations of stress and composition can maintain a stabilized ferroelectric phase (e.g., a metastable orthorhombic phase of HfO2). The stabilized crystalline phase includes, for example, nanocrystals and / or columnar crystals.

[0010] The Fig. 1A-1C show sectional views of various NCFET . The Fig. 1A and Fig. 1B shows sectional views of NCFET from metal-insulator-semiconductor- FET -Type (MIS- FET -Type) and Fig. 1C shows a sectional view of a NCFET from metal-insulator-metal-insulator-semiconductor- FET -Type (MIMIS- FET -type). Although the Fig. 1A-1C NCFET with a planar MOS transistor structure, Fin- FET and / or Gate-All-Around- FET be used.

[0011] As in Fig. Shown in 1A, it includes a MIS- NCFET a substrate 100 , a canal 101 and a source and drain 102 The Source and Drain 102 is appropriately doped with impurities. Furthermore, the source, drain, and channel (active regions) are surrounded by an insulating layer (not shown), such as trench insulation (STI), made, for example, of silicon dioxide.

[0012] A boundary layer 103 In some embodiments, it is located above the channel layer. 101 formed. The interface layer 103In some embodiments, it is made from silicon dioxide with a thickness in the range of about 0.5 nm to about 1.5 nm.

[0013] A ferroelectric dielectric layer 105 is above the interface layer 103 arranged. The ferroelectric dielectric layer 105 includes a mixture of HfO2 and an oxide of one or more metallic elements from the group consisting of Zr, Al, La, Y , Gd and Sr is selected (hereinafter referred to as HXO or HfO2:XO2, where X Zr, Al, La, Y , Gd and / or Sr is, denoted). In some embodiments, the ferroelectric dielectric layer includes 105 HfO2 doped with Si and / or Zr. In certain embodiments, the ferroelectric dielectric layer includes 105 Hf1-xZrxO2 (0 < x <1). In some embodiments, the ferroelectric dielectric layer includes 105an amorphous layer and crystals. In other embodiments, the ferroelectric dielectric layer includes 105 a compressed hafnium oxide and a metal element X , whereby X which is one or more of the group consisting of Zr, Al, La, Y , Gd and Sr are selected. The thickness of the ferroelectric dielectric layer. 105 In some embodiments, the wavelength lies in a range of approximately 1.0 nm to approximately 10 nm.

[0014] A gate electrode layer 106 is applied above the ferroelectric dielectric layer 105 arranged. The gate electrode layer 106 It includes one or more metallic layers. In some embodiments, the gate electrode layer includes... 106 a first conductive layer (a cover layer) that is applied to the ferroelectric dielectric layer 105is arranged, a second layer (a boundary layer) arranged on the first conductive layer, a third conductive layer (a working function setting layer) arranged on the second conductive layer, a fourth conductive layer (an adhesive layer) arranged on the third conductive layer, and / or a fifth conductive layer (a main gate metal layer) arranged on the fourth conductive layer.

[0015] The top layer comprises a TiN-based material, such as TiN and TiN doped with one or more additional elements. In some embodiments, the TiN layer is doped with Si. The boundary layer comprises TaN in some embodiments. In certain embodiments, the top layer is not used.

[0016] The working function setting layer comprises one or more layers of conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For the n-channel fin- FET One or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as the working function setting layer and for the p-channel fin- FET One or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as the working function setting layer.

[0017] In some embodiments, the adhesive layer contains Ti, TiN, and / or TaN. The main gate metal layer contains a metal selected from a group consisting of W, Cu, Ti, Al, and Co.

[0018] Furthermore, side wall spacers are used. 109 formed on opposite side surfaces of the gate structure, as in Fig. Shown in 1A. The side wall spacers. 109 include one or more layers of insulating material, such as silicon oxide, silicon nitride and silicon oxynitride.

[0019] Fig. 1B shows a sectional view of a NCFET from metal-insulator-semiconductor- FET -Type (MIS- FET -type) according to another embodiment. In Fig. 1B indicates the interface layer 103 a flat shape and the ferroelectric dielectric layer 105 is conformally formed in the gate space and has a height that is essentially equal to the height of the gate electrode layer 106 is.

[0020] In Fig. 1C, similar to the Fig. 1A and / or 1B will be a channel 101 and a source and drain 102 on a substrate 100 formed. A first-gate dielectric layer 113 is formed over the channel 101 arranged. The first gate dielectric layer113 In some embodiments, it includes one or more dielectric layers with a high k-value (e.g., with a dielectric constant greater than 3.9). The one or more gate dielectric layers can, for example, comprise one or more layers of a metal oxide or silicate of Hf, Al, Zr, combinations thereof, and multiple layers thereof. Other suitable materials include La, Mg, Ba, Ti, Pb, and Zr in the form of metal oxides, metal alloy oxides, and combinations thereof. Exemplary materials include MgOx, SiN (Si3N4), Al2O3, La2O3, Ta2O3, Y2O3, HfO2, ZrO2, GeO2, HfxZ1-xO2, Ga2O3, Gd2O3, TaSiO2, TiO2, HfSiON, YGexOy, YSixOy, and LaAlO3, and the like. In certain embodiments, HfO2, ZrO2 and / or HfxZr1-xO2 are used. The formation methods for the first gate dielectric layer 113These include molecular beam deposition (MBD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like. In some embodiments, the first gate dielectric layer has 113 a thickness of approximately 1.0 nm to approximately 10.0 nm.

[0021] In some embodiments, an interface layer (not shown) can be placed above the channel. 101 be formed before the first gate dielectric layer 113 is formed, and the first gate dielectric layer 113 is formed above the interface layer.

[0022] A first gate electrode 114 as an internal electrode on the first gate dielectric layer 113 arranged. At the first gate electrode 114It can be one or more metals, such as W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt and Zr. In some embodiments, the first gate electrode includes 114 One or more of TiN, WN, TaN, and Ru. Metal alloys such as Ti-Al, Ru-Ta, Ru-Zr, Pt-Ti, Co-Ni, and Ni-Ta can be used, and / or metal nitrides such as WNx, TiNx, MoNx, TaNx, and TaSixNy can also be used. In some embodiments, at least one of W, Ti, Ta, TaN, and TiN can be used as the first gate electrode. 114 can be used. In some embodiments, the first gate electrode includes 114 a work function setting layer.

[0023] A ferroelectric dielectric layer 115 is applied to the first gate electrode 114 formed. The ferroelectric dielectric layer 115exhibits the same or a similar composition / structures as the ferroelectric layer 105 on.

[0024] Furthermore, a second gate electrode is used. 116 as an external gate on the ferroelectric dielectric layer 115 arranged. At the second gate electrode 116 It can be a metal selected from a group consisting of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. The second gate electrode 116 is made of the same material as, or of a different material than, the first gate electrode 114 manufactured. Furthermore, side wall spacers are produced. 119 formed on opposite side surfaces of the gate structure, as in Fig. Shown in 1C. The side wall spacers 119include one or more layers of insulating material, such as silicon oxide, silicon nitride and silicon oxynitride.

[0025] As in the Fig. 1A Fig. As shown in Figure 1C, the ferroelectric dielectric layers exhibit 105 and 115 and the first gate dielectric layer 113 In cross-section, it has a "U" shape with a thin middle section and thick side sections in the vertical direction.

[0026] The ferroelectric dielectric layers 105 and 115These nanocrystals can be formed using various methods. In some embodiments, laminated layers of amorphous HfO2 / XO2 can be deposited using ALD at a low temperature in the range of approximately 100 °C to approximately 300 °C. In other embodiments, the temperature is in the range of approximately 100 °C to approximately 175 °C. The thickness of the amorphous matrix (each layer) is in some embodiments in the range of approximately 1 nm to approximately 10 nm. A tempering process is then carried out to create the HfO2:XO2 nanocrystals within the amorphous matrix.

[0027] In other embodiments, an amorphous HfO2 layer is formed using ALD, and then a metal layer containing one or more metal elements from the group consisting of Zr, Al, La, Y , Gd and Sr are selected (element XThe metal elements are deposited over the amorphous HfO2 layer. A tempering process is then carried out to drive the metal elements into the amorphous HfO2 layer to create a compressed HfO2:XO2 layer. The tempering can be performed in an oxidizing gas such as O2.

[0028] Furthermore, in other embodiments, an oxygen-deficient amorphous HfO2 layer containing one or more metallic elements from the group consisting of Zr, Al, La, Y , Gd and Sr are selected (element X ), is deposited via ALD over a conductive layer (e.g., a channel layer). A tempering step is then performed in an oxygen-containing atmosphere (e.g., O2) to induce lattice expansion and / or compression of more than 20%. The process is repeated to deposit a ferroelectric layer. 105 or 115to train, maximize stress effects and stabilize a ferroelectric phase.

[0029] In other embodiments, ferroelectric dielectric layers can be used. 105 and 115 HfO2:XO2 are formed from HfO2 by high-pressure synthesis to produce stress effects in order to stabilize ferroelectric phases.

[0030] The Fig. Figures 2A-2C show various structures of a ferroelectric layer according to embodiments of the present disclosure. In the Fig. 2A-2C includes the ferroelectric dielectric layer 105 / 115 an amorphous layer 120 and crystals 123 , 125 In Fig. 2A are nanocrystals 123 from HXO in the amorphous layer 120distributed from HXO. In some embodiments, the average size of the nanocrystals ranges from approximately 0.5 nm to approximately 5 nm. When the crystals are formed by HfO2:XO2, they exhibit an orthorhombic structure. Fig. 2B and Fig. 2C are the crystals stem-shaped crystals 125 The stem-shaped crystals 125 They extend along a film stack direction (Z-direction) and are located in the amorphous layer 120 embedded. The average diameter of the stem-shaped crystals ranges from about 0.5 nm to about 5 nm, and the average length of the stem-shaped crystals ranges from about 1 nm to about 5 nm. In some embodiments, such as in Fig. As shown in 2B, the stem-shaped crystals are located closer to the underlying layer (e.g., a channel layer). 101 the Fig. 1A and Fig. 1B), so that the density of the crystals in the ferroelectric layer is greater in a region closer to the layer below than in a region closer to a layer above (e.g., a gate electrode layer). 106 the Fig. 1A and Fig. 1B). In other embodiments, such as in Fig. As shown in 2C, the stem-shaped crystals are located closer to the layer above, so that the density of the crystals in the ferroelectric layer is greater in a region closer to the layer above than in a region closer to the layer below.

[0031] The Fig. Figures 3A-3D show various stages of the manufacturing process for a structure with negative capacity according to an embodiment of the present disclosure. It is understood that additional processing steps may be performed before, during, and after the process described in the figures. Fig. The process shown in 3A-3D can be provided for, and some of the steps described below can be replaced or omitted for additional embodiments of the method. The sequence of steps / processes can be interchangeable. Materials, configurations, dimensions, and / or processes that are the same or similar to the embodiments described above, which are associated with the Fig. The components described in 1A-2C can be used in the following embodiments, and a detailed explanation of them can be omitted.

[0032] As in Fig. As shown in 3A, an interface layer is formed. 20 on a substrate 10 formed. In some embodiments, the substrate 10from a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as group IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), group III-V compound semiconductors (e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GalnP)), or the like. Furthermore, the substrate can be 10 may include an epitaxial layer (epi-layer) that can be exploited to improve performance, and / or may include a silicon-on-insulator (SOI) structure.

[0033] In some embodiments, the interface layer 20A silicon oxide that can be formed by chemical reactions. For example, a chemical silicon oxide can be formed using deionized water + ozone (DIO3), NH4OH + H2O2 + H2O (APM), or other methods. Other embodiments may utilize a different material or processes for the interface layer. In some embodiments, the interface layer exhibits 20 a thickness of approximately 0.5 nm to approximately 1.5 nm.

[0034] Then a ferroelectric dielectric layer is applied. 30 above the interface layer 20 formed. The ferroelectric dielectric layer 30 In some embodiments, it comprises an amorphous layer and crystals of HfO2 and an oxide of a metallic element, wherein the metallic element is one or more elements from the group consisting of Zr, Al, La, Y, G and Sr are selected. In other embodiments, the ferroelectric dielectric layer includes 30 a compressed hafnium oxide and a metal element X , whereby X which is one or more of the group consisting of Zr, Al, La, Y , Gd and Sr are selected. The ferroelectric dielectric layer 30 In some embodiments, it can be formed by the method described above.

[0035] In other embodiments, the formation methods for the dielectric layer include 30Molecular beam deposition (MBD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like. In some embodiments, Zr-doped HfO2 can be formed by ALD using HfCl4 and H2O as a first precursor and ZrCl4 and H2O as a second precursor at a temperature in the range of approximately 200 °C to 400 °C. In the case of Si-doped HfO2, SiH4, Si2H6, and / or SiH2Cl2, or another suitable silicon source gas, can be used. The thickness of the dielectric layer 30 In some embodiments, the wavelength lies in a range of approximately 1 nm to approximately 10 nm.

[0036] After the dielectric layer 30 has been formed, a top layer will be applied. 40 on the dielectric layer 30 trained, as in Fig. 3B shown. The top layer 40In some embodiments, it includes a TiN-based material, such as TiN and TiN doped with one or more additional elements. In some embodiments, the TiN layer is doped with Si. The top layer 40 The coating can be formed by ALD, CVD, or physical vapor deposition, including sputtering, or any other suitable method. When ALD is used, in some embodiments the process is carried out at a temperature in the range of approximately 400 °C to approximately 500 °C. The thickness of the coating layer 40 In some embodiments, the thickness lies in a range of approximately 1 nm to approximately 5 nm. After the top layer 40 Once trained, a tempering process is carried out, as described in Fig. Figure 3C shows the tempering process. The tempering step is carried out at a temperature in the range of approximately 600 °C to approximately 1000 °C in an inert ambient gas, such as N₂, Ar, and / or He. In some embodiments, the tempering period ranges from approximately 10 s to 1 min. Following tempering, a cooling step is performed. In some embodiments, the substrate is cooled to less than 100 °C or to room temperature (approximately 25 °C).

[0037] In some embodiments, the top layer 40 and the tempering step was not used.

[0038] Then a boundary layer will form 52 , which is made, for example, from TaN, above the top layer 40 trained, as in Fig. Shown in 3D. The boundary layer 52The interface can be formed by ALD, CVD, or physical vapor deposition, including sputtering, or any other suitable method. When ALD is used, in some embodiments it is performed at a temperature in the range of approximately 300 °C to approximately 400 °C. The thickness of the interface 52 In some embodiments, the thickness lies in a range of approximately 1 nm to approximately 5 nm. In some embodiments, the tempering step to transform the amorphous structure into the orthorhombic structure can be carried out after the boundary layer has been treated. 52 was trained.

[0039] Furthermore, a work function setting layer will be implemented. 54 on the boundary layer 52 trained. In some embodiments, the work function setting layer includes 54TiN for a p-type transistor and TiAl for an n-type transistor. Any other suitable metallic material can be used as the working function setting layer. 54 can be used. In some embodiments, a TiAl layer is also formed on a TiN working function setting layer for a p-transistor. The working function setting layer 54 The working function setting layer can be formed by ALD, CVD, or physical vapor deposition, including sputtering, or any other suitable method. When ALD is used, in some embodiments the ALD process is carried out at a temperature in the range of approximately 300 °C to approximately 400 °C. 54 In some embodiments, it lies in a range of approximately 1 nm to approximately 5 nm.

[0040] Furthermore, a main gate metal layer is used. 58 above the work function setting layer 54formed. The main gate metal layer 58 It includes one or more metals, such as tungsten (W), copper (Cu), titanium (Ti), aluminum (Al), and cobalt (Co), or another suitable material. In some embodiments, when the main gate metal layer is 58W, an adhesive layer is used. 56 on the work function setting layer 54 formed. In some embodiments, the adhesive layer 56 Ti. As in Fig. Shown in 3D, the gate electrode 50 a boundary layer 52 , which are on the top layer 40 is arranged, a work function setting layer 54 , which are located on the boundary layer 52 is arranged, an adhesive layer 56 , which are on the work function setting layer 54 is arranged, and a main gate metal layer 58 In some embodiments, the cover layer can be part of the gate electrode. 50 be viewed.

[0041] The Fig. Figures 4A-4D show various stages of manufacturing work steps for a structure with negative capacitance according to an embodiment of the present disclosure. It is understood that additional work steps may be performed before, during, and after the process described in the figures. Fig. The process shown in 4A-4D can be provided for, and some of the steps described below can be replaced or omitted for additional embodiments of the method. The sequence of steps / operations can be interchangeable. Materials, configurations, dimensions, and / or operations that are the same or similar to the embodiments described above, which are associated with the Fig. 1A Fig. 3D descriptions can be used in the following embodiments, and a detailed explanation of them can be omitted.

[0042] In this embodiment, at least the surface section of the substrate includes 10an epitaxial semiconductor layer 11 , which are made of the same or a different semiconductor material than the substrate 10 is manufactured. In certain embodiments, the epitaxial semiconductor layer includes 11 SiGe. The interface layer 20 is on the epitaxial semiconductor layer 11 trained. The remaining manufacturing steps are related to the Fig. 3A-3D explained it identically.

[0043] The Fig. 5A and Fig. Figure 5B shows various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. It is understood that additional work steps may be performed before, during, and after the process described in the Fig. 5A and Fig. The process shown in Figure 5B can be provided for, and some of the steps described below can be replaced or omitted for additional embodiments of the method. The sequence of steps / processes can be interchangeable. Materials, configurations, dimensions, and / or processes that are the same or similar to the embodiments described above, which are associated with the Fig. The components described in 1A-4D can be used in the following embodiments, and a detailed explanation of them can be omitted.

[0044] In this embodiment, the initial dielectric layer comprises one or more HfO2 layers stacked alternately. 30A and one or more XO2 layers 30B , whereby X which is one or more of the group consisting of Zr, Al, La, Y , Gd and Sr are selected above the interface layer 20 trained, as in Fig. 5A is shown. In some embodiments, the interface layer 20 not used. In certain embodiments, an epitaxial semiconductor layer is used. 11 in addition to or instead of the interface layer 20 used.

[0045] The stack layer can be formed using ALD at a temperature in the range of 100 °C to 300 °C. Each layer can be a monatomic layer or a multiatomic layer (e.g., two, three, or more monatomic layers). Although Fig. 5A four layers of HfO2 layers 30A and four layers of XO2 layers 30B This shows that the number of layers is not limited to four and can be two, three, five or more.

[0046] After the tempering steps, the stack layer is formed by HfO2 layers. 30A and XO2 layers 30B to a single amorphous layer of HfO2:XO2, in which nanocrystals39 are distributed by HfO2:XO2, as in Fig. 5B shown. In certain embodiments, X The temperature of the tempering process, in some embodiments, ranges from approximately 400 °C to approximately 800 °C.

[0047] The Fig. 5C and Fig. Figure 5D shows various stages of the manufacturing process for a structure with negative capacity according to an embodiment of the present disclosure. It is understood that additional processing steps may occur before, during, and after the process described above. Fig. 5C and Fig. The process shown in 5D can be provided for, and some of the work steps described below can be replaced or omitted for additional embodiments of the process. The sequence of work steps / processes can be interchangeable. Material, configuration, dimensions, and / or processes that are the same or similar to the embodiments described above, which are associated with the Fig. The components described in 1A-5B can be used in the following embodiments, and a detailed explanation of them can be omitted.

[0048] In these embodiments, the initial dielectric layer comprises one or more HfO2- layers stacked alternately. x -Layers 30C and one or more XO2- y -layers 30D, where 0 < x , y ≤ 0.8 and it is at X which is one or more of the group consisting of Zr, Al, La, Y , Gd and Sr are selected above the interface layer 20 trained, as in Fig. 5C shown. In some embodiments, the interface layer 20 not used. In certain embodiments, an epitaxial semiconductor layer is used. 11 in addition to or instead of the interface layer 20 used.

[0049] The stacking layer can be formed using ALD. Each layer can be a monoatomic layer or a multiatomic layer (e.g., two or three monoatomic layers). Although Fig. 5C four layers of HfO2- x -Layers 30C and four layers of XO2- y -Layers 30D shows that the number of layers is not limited to four and can be two, three, five or more.

[0050] After the tempering steps in the oxidizing atmosphere (ozone and / or oxygen), the stack layer of HfO2- x -Layers 30C and XO2- y -Layers 30D to a single amorphous layer of HfO2:XO2, in which nanocrystals 39 are distributed by HfO2:XO2, as in Fig. 5D shown. In certain embodiments, X Zr.

[0051] The Fig. Figures 6A-6D show various stages of manufacturing work steps for a structure with negative capacitance according to an embodiment of the present disclosure. It is understood that additional work steps may be performed before, during, and after the process described in the figures. Fig. The process shown in Figures 6A-6D can be provided for, and some of the steps described below can be replaced or omitted for additional embodiments of the method. The sequence of steps / operations can be interchangeable. Materials, configurations, dimensions, and / or operations that are the same or similar to the embodiments described above, which are associated with the Fig. The components described in 1A-5D can be used in the following embodiments, and a detailed explanation of them can be omitted.

[0052] In Fig. 6A, similar Fig. 3A, a boundary layer will be formed 20 on a substrate 10formed and a dielectric layer 30 is located on the interface layer 20 formed. In some embodiments, the substrate includes 10 an epitaxial layer 11 , similar Fig. 4A. The dielectric layer 30 In some embodiments, it includes amorphous HfO2 formed using ALD.

[0053] Then, as in Fig. As shown in 6B, a metal layer is applied. 45 , which contains one or more metallic elements from the group consisting of Zr, Al, La, Y , Gd and Sr are selected (element X ), deposited above the amorphous HfO2 layer. Then, as in Fig. As shown in Figure 6C, an annealing step is performed to drive the metal elements into the amorphous HfO2 layer to form a compressed HfO2:XO2 layer 31. The annealing temperature (substrate temperature) in some embodiments is in the range of approximately 400 °C to approximately 800 °C. The annealing can be carried out in an oxidizing gas such as O2.

[0054] In some embodiments, only a portion of the initial dielectric layer is removed. 30 to the compressed layer 31 , as in Fig. 6D shown. In some embodiments, the initial dielectric layer can 30 oxygen-depleted hafnium oxide (HfO2- x , where 0 < x ≤ 0.8).

[0055] The Fig. Figures 7A-7D show various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. It is understood that additional work steps may be performed before, during, and after the process described in the figures. Fig. The process shown in Figures 7A-7D can be provided for, and some of the steps described below can be replaced or omitted for additional embodiments of the method. The sequence of steps / operations can be interchangeable. Materials, configurations, dimensions, and / or operations that are the same or similar to the embodiments described above, which are associated with the Fig. The components described in 1A-6D can be used in the following embodiments, and a detailed explanation of them can be omitted.

[0056] As in Fig. 7A shown, similar Fig. 3A, a boundary layer will be formed 20 on a substrate 10formed and a dielectric layer 32 is located on the interface layer 20 formed. In some embodiments, the substrate includes 10 an epitaxial layer 11 , similar Fig. 4A. The dielectric layer 30 In some embodiments, it includes amorphous HfO2 formed using ALD.

[0057] In this embodiment, the dielectric layer 32 an oxygen-deficient amorphous hafnium oxide layer containing one or more metallic elements from the group consisting of Zr, Al, La, Y , Gd and Sr are selected (element X ), deposited via ALD over a conductive layer (e.g., a channel layer). The oxygen-deficient hafnium oxide can be dissolved by HfO2- x , where 0 < x ≤ 0.8, can be represented.

[0058] Then, a tempering process is carried out in an oxygen-containing atmosphere (e.g., O2) to induce lattice expansion and / or compression of more than 20%, as described in Fig. 7B shown. The process is repeated as shown in the Fig. 7C and Fig. 7D shown to create a ferroelectric layer 33 to train. Subsequently, a gate electrode is trained.

[0059] The Fig. 8A and Fig. Figure 8B shows various stages of manufacturing work steps for a structure with negative capacity according to an embodiment of the present disclosure. It is understood that additional work steps may be performed before, during, and after the process described in the Fig. 8A and Fig. The process shown in Figure 8B can be provided for, and some of the steps described below can be replaced or omitted for additional embodiments of the method. The sequence of steps / processes can be interchangeable. Materials, configurations, dimensions, and / or processes that are the same or similar to the embodiments described above, which are associated with the Fig. The components described in 1A-7D can be used in the following embodiments, and a detailed explanation of them can be omitted.

[0060] In Fig. 8A will be a shift 36 , which contains stem-shaped crystals, above an epitaxial layer 11 formed. In some embodiments, the layer 36 , which contains stem-shaped crystals, above the substrate 10 without the epitaxial layer 11In some embodiments, the stem-shaped crystals can be formed by molecular beam epitaxy (MBE), metal-organic CVD (MOCVD), rapid melt growth and liquid-phase epitaxy (LPE), or any other epitaxial methods. Epitaxial growth allows stem-shaped crystals of, for example, HfO₂:XO₂ to form on the Si or SiGe surface. Then, an amorphous layer is formed. 37 above the layer 36 , which contains the stem-shaped crystals, formed as in Fig. 8B shown.

[0061] The Fig. 8C and Fig. Figure 8D shows various stages of the manufacturing process for a structure with negative capacity according to an embodiment of the present disclosure. Fig. 8C becomes a dielectric layer 30 above an epitaxial layer 11 formed. In some embodiments, the dielectric layer 30above the substrate 10 without the epitaxial layer 11 trained. Then a shift 36 , which contains stem-shaped crystals, above the dielectric layer 30 trained, as in Fig. Figure 8D shows that in some embodiments an additional amorphous oxide layer is applied over the layer. 36 trained.

[0062] Fig. Figure 9 shows a schematic view of a film-forming device according to embodiments of the present disclosure.

[0063] Fig. Figure 9 shows an integrated film deposition system 1500 The system includes a loading opening (airlock system). 1510 and a wafer handling system 1520 Several chambers 1610 - 1670 are accessible via the wafer handling system 1520 In some embodiments, a chamber for forming ferroelectric material (FE chamber) is provided. 1620provided for, which may be the MBE chamber, CVD chamber, ALD chamber, PVD chamber or the like. A pretreatment chamber 1610 is used to clean the surface of a wafer (substrate), an ALD chamber 1630 is used to form different oxide layers, a annealing chamber 1640 It is used for thermal processing steps. An inoculation layer can be applied in the pretreatment chamber. 1610 or in the ALD chamber 1630 be trained. Metal deposition chambers 1650 and 1660 are used to form metallic layers, such as TiN, TaN, Ti, Ta, W, Zr, Al, La, Y , Gd, Sc or any other metallic materials. Furthermore, in some embodiments a measuring chamber is included. 1670 , which is equipped with, for example, an X-ray diffraction measuring device (XRD measuring device) or any other measuring instruments.

[0064] By using the system 1500 , which in Fig. As shown in 9, multiple layers of a gate structure can be used for a NCFET and / or an ordinary one FET a dielectric layer with a high k-value, made from, for example, HfO2, for an ordinary FET can be trained, for example, through the work steps that involve pretreatment in the pretreatment chamber 1610 and ALD deposition of HfO2 in the ALD chamber 1630 , followed by optional tempering in the chamber 1640 , a cover / boundary layer deposition above the HfO2 layer in the chamber 1650 and a gate metal deposition in the chamber 1660 include a gate structure with a ferroelectric layer for a NCFET can be trained through the work steps that involve pretreatment in the pretreatment chamber 1610and the deposition of a ferroelectric layer in the FE chamber 1620 , followed by optional tempering in the chamber 1640 , a cover / boundary layer deposition above the HfO2 layer in the chamber 1650 and a gate metal deposition in the chamber 1660 include. In some embodiments, an additional oxide layer is incorporated into the ALD chamber. 1630 formed after the ferroelectric layer has formed.

[0065] Furthermore, a gate structure can be used for a NCFET with an internal gate (see Fig. 1C) are trained through the work steps that involve pretreatment in the pretreatment chamber 1610 , a deposition of a dielectric layer with a high k-value in the ALD chamber 1630 and training of an internal gatekeeper in the chamber 1660 and the deposition of a ferroelectric layer in the FE chamber 1620, followed by optional tempering in the chamber 1640 , a cover / boundary layer deposition above the HfO2 layer in the chamber 1650 and a gate metal deposition in the chamber 1660 include. In addition, a gate structure can be used for a NCFET with a diffusion boundary between two ferroelectric layers formed by the work steps that include pretreatment in the pretreatment chamber 1610 , a deposition of a dielectric layer with a high k-value in the ALD chamber 1630 , a diffusion boundary layer deposition in the ALD chamber 1660 and the deposition of ferroelectric layers in the chamber 1620 , followed by optional tempering in the chamber 1640 , a cover / boundary layer deposition above the HfO2 layer in the chamber 1650 and a gate metal deposition in the chamber 1660 include. Furthermore, a gate structure can be used for a NCFET with the diffusion boundary and the internal gate electrode are formed by the work steps that include pretreatment in the pretreatment chamber 1610 , a deposition of a dielectric layer in the ALD chamber 1620 , a diffusion boundary layer deposition in the ALD chamber 1630 , a training of an internal gate electrode in the chamber 1660 and the deposition of ferroelectric layers in the chamber 1620 , followed by optional tempering in the chamber 1640 , a cover / boundary layer deposition above the HfO2 layer in the chamber 1650 and a gate metal deposition in the chamber 1660 include.

[0066] In some embodiments, the nanocrystals and / or the columnar crystals of HfXO consist of an orthorhombic crystal phase. In other embodiments, the HfXO crystals are essentially formed from an orthorhombic crystal phase. In such a case, the orthorhombic crystal phase comprises about 0.1% or more of the HfXO crystals, and the remaining phases may be amorphous, monolithic, cubic, and / or tetragonal.

[0067] The Fig. Figures 10A-18C show one of several stages of manufacturing work steps for a NCFET according to one embodiment of the present disclosure. It is understood that additional work steps may be required before, during and after the process described by the Fig. 10A Fig. The process shown in Figure 18C can be provided for, and some of the steps described below can be replaced or omitted for additional embodiments of the method. The sequence of steps / operations can be interchangeable. Materials, configuration, dimensions, and / or operations that are the same or similar to the embodiments described above, which are associated with the Fig. The elements described in 1A-9 can be used in the following forms, and a detailed explanation of them can be omitted.

[0068] Fig. Figure 10A shows a perspective view and Fig. 10B is a sectional view along the X -Direction, which shows one of several stages of the manufacturing process according to an embodiment of the present disclosure. As in the Fig. 10A and Fig. As shown in 10B, a substrate 200 provided. In some embodiments, the substrate 200from a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as group IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), group III-V compound semiconductors (e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP)), or the like. Furthermore, the substrate can be 200 It may include an epitaxial layer (epi-layer) that can be utilized to improve performance, and / or it may include a silicon-on-insulator (SOI) structure. In the upper section of the substrate... 200 It could be multiple layers of Si and SiGe.

[0069] Fig. Figure 11A shows a perspective view and Fig. 11B is a sectional view along the X -Direction, which shows one of several stages of the manufacturing process according to an embodiment of the present disclosure. As in the Fig. 11A and Fig. As shown in 11B, rib structures are depicted 210 by etching the substrate 200 and forming an insulating layer 220 formed. The rib structures 210 They can be structured by any suitable method. The rib structures 210For example, they can be structured using one or more photolithography processes, including dual-structuring and multiple-structuring processes. Generally, dual-structuring or multiple-structuring processes combine photolithography and self-alignment processes, enabling the creation of structures with, for example, spacing smaller than would otherwise be obtainable using a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to form the rib structures. 210to structure. In some embodiments, the width of the rib structures is 210 in a range of approximately 4 nm to approximately 10 nm and the spacing of the rib structures 210 lies in a range of approximately 10 nm to approximately 50 nm.

[0070] Then a layer 220 The layer consists of insulating material formed over the rib structures, thus embedding the rib structures. 220 The insulating material can be made from suitable dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), dielectrics with low k-values, such as carbon-doped oxides, dielectrics with extremely low k-values, such as porous carbon-doped silicon dioxide, a polymer, such as polyimide, combinations of these, or the like. In some embodiments, the layer 220The insulating material is formed by a process such as CVD, flowable CVD (FCVD), or a spin-on-glass process, although any acceptable process can be used. Subsequently, sections of the layer are 220 made of insulating material that covers the upper surfaces of the rib structures 210 extend, using, for example, an etching process, chemical-mechanical polishing (CMP), or the like, as in the Fig. 11A and Fig. 11B shown.

[0071] Fig. Figure 12A shows a perspective view and Fig. 12B is a sectional view along the X -Direction, which shows one of several stages of the manufacturing process according to an embodiment of the present disclosure. Furthermore, as in the Fig. 12A and Fig. As shown in 1B, the layer 220made of insulating material, so that the upper sections of the rib structures 210 are exposed. The sunken layer 220 A layer of insulating material is called an insulating insulation layer or trench insulation (STI). The height of the exposed rib structures 210 , which are located on the upper surface of the insulating layer 220 The measured value lies in a range of approximately 30 nm to approximately 100 nm in some embodiments.

[0072] Fig. Figure 13A shows a perspective view and Fig. 13B is a sectional view along the X -Direction, which shows one of several stages of the manufacturing process according to an embodiment of the present disclosure. Subsequently, a dummy gate dielectric layer is applied. 215 over the upper sections of the rib structure 210 trained, as in the Fig. 13A and Fig. Shown in 13B. The dummy gate dielectric layer. 215 In some embodiments, this is a silicon oxide layer formed by CVD or ALD. The thickness of the dummy gate dielectric layer 215 In some embodiments, the wavelength lies in a range of approximately 1 nm to approximately 10 nm.

[0073] Then a polysilicon layer is applied. 230 above the dummy gate electrode layer 215 Furthermore, a hard mask layer is formed on the polysilicon layer. The hard mask layer is then transformed into a hard mask pattern through suitable lithographic and etching processes. 235 structured as in the Fig. Shown in 14A-14C. The hard mask pattern. 235 In some embodiments, it includes one or more layers of insulating material, such as silicon oxide and silicon nitride.

[0074] Fig. Figure 14A shows a perspective view, Fig.14B is a sectional view along the Y -direction and Fig. 14C is a sectional view along the X -Direction, which shows one of several stages of the manufacturing process according to an embodiment of the present disclosure. By using the hard mask pattern 235 The polysilicon layer is used as an etching mask to create dummy gate electrodes. 230 structured as in the Fig. shown in 14A-14C. In some embodiments, the width of the dummy gate electrode is 230 in a range of about 8 nm to about 20 nm.

[0075] Fig. Figure 15A shows a perspective view, Fig. 15B is a sectional view along the Y -direction and Fig. 15C is a sectional view along the X -Direction, which shows one of several stages of the manufacturing process according to an embodiment of the present disclosure. Sidewall spacer240 are applied to opposite sides of the dummy gate electrodes 230 trained. The side wall spacers 240 They include one or more layers of insulating material, such as silicon dioxide, silicon nitride, and silicon oxynitride. In addition, source / drain epitaxy layers are used. 250 about source / drain regions of the rib structures 210 formed. The source / drain epitaxic layers 250 include SiP, SiAs, SiGeP, SiGeAs, GeP, GeAs and / or SiGeSn or another suitable material for an n- FET and SiB, SiGa, SiGeB, SiGeGa, GeB, GeGa and / or SiGeSn or another suitable material for a p- FET The thickness of the source / drain epitaxy layers 250 In some embodiments, the thickness lies in a range of approximately 3 nm to approximately 8 nm. In some embodiments, an alloy layer, such as a silicide layer, is applied over the source / drain epitaxial layers. 250 trained.

[0076] Fig. Figure 16A shows a perspective view, Fig. 16B is a sectional view along the Y -direction and Fig. 16C is a sectional view along the X -Direction, which shows one of several stages of the manufacturing process according to an embodiment of the present disclosure. Subsequently, an etch stop layer (ESL) is applied. 245 and an intermediate dielectric layer 260 trained and a planarization step, such as a CMP step, is performed on exposed upper surfaces of the dummy gate electrodes 230 carried out as in the Fig. 16A-16C shown.

[0077] In some embodiments, the ESL layer 245 made from a silicon nitride-based material, such as SiN and SiON, and the interdielectric layer 260It is manufactured from a silicon oxide-based material, such as SiO2, or a material with a low k-value. In some embodiments, a tempering step is performed after the interdielectric layer has formed.

[0078] Fig. Figure 17A shows a perspective view, Fig. 17B is a sectional view along the Y -direction and Fig. 17C is a sectional view along the X -Direction, which shows one of several stages of the manufacturing process according to an embodiment of the present disclosure. Then the dummy gate electrodes are 230 and the dummy gate dielectric layer 215 removed by using dry and / or wet sets, thereby creating gate spaces 265 be trained, as in the Fig. 17A-17C is shown. Furthermore, the gate rooms will be... 265 a boundary layer 271 and a dielectric layer 270trained, as in the Fig. 17A-17C shown. As explained above, the interface layer 271 made from silicon dioxide and the dielectric layer 270 This is a ferroelectric layer formed by one of the methods mentioned above. Optionally, a top layer (not shown) can then be formed, and a tempering step can be performed optionally.

[0079] Fig. Figure 18A shows a perspective view, Fig. 18B is a sectional view along the Y -direction and Fig. 18C is a sectional view along the X -Direction, which shows one of several stages of the manufacturing process according to an embodiment of the present disclosure. A gate electrode 280 is trained as in the Fig. Figures 18A-18C are shown. The top layer and gate electrode can be formed using a suitable process such as ALD, CVD, PVD, electroplating, or combinations thereof. After the conductive materials for the gate electrode have been formed, a planarization step, such as CMP, is performed to remove excess material above the interdielectric layer. 260 to remove.

[0080] After forming the gate structures, further CMOS processes are carried out to form various features, such as additional interdielectric layers, contacts / vias, interconnect metal layers and passivation layers, etc.

[0081] The Fig. Figures 19-29C show other manufacturing steps for an NC fin- FET according to some embodiments of the present disclosure. Throughout the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. It is understood that additional work steps may be performed before, during, and after the processes described by the Fig. The processes shown in Figures 19-29C can be provided for, and some of the steps described below can be replaced or omitted for additional embodiments of the method. The sequence of steps / processes can be interchangeable. Materials, configuration, dimensions, and / or processes that are the same or similar to the embodiments described above, which are described in relation to the Fig. 1A Fig. The following embodiments, as described in 18C, can be used and a detailed explanation thereof can be omitted.

[0082] Fig. Figure 19 shows an exemplary perspective view after gate rooms 390 formed by removing the dummy gate electrode and the dummy gate dielectric layer. In Fig. 19 will define the structure for an NC- FET and the structure for an ordinary fin- FET adjacent to each other with a first ILD layer inserted in between 370 arranged. The structure for the NC- FET and the structure for the ordinary fin- FET They may not necessarily be arranged adjacent to each other.

[0083] After the dummy gate electrode and the dummy gate dielectric layer have been removed, upper sections are 324 the rib structures 320 , which become channels in the gate rooms 390 exposed, while lower sections 322 the rib structures 320 into the insulating insulating layer 330are embedded. In some embodiments, a first rib lining layer is used. 326 on the lower sections 322 the rib structures 320 formed and a second rib lining layer 328 is applied to the first rib lining layer 326 formed. In some embodiments, each of the lining layers has a thickness in the range of approximately 1 nm to approximately 20 nm. In some embodiments, the first rib lining layer includes 326 silicon oxide and has a thickness between approximately 0.5 nm and approximately 5 nm, and the second rib lining layer 328It contains silicon nitride and has a thickness between approximately 0.5 nm and 5 nm. The lining layers can be deposited by one or more processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), although any acceptable process can be used.

[0084] After the dummy gate electrode and the dummy gate dielectric layer have been removed, a gate dielectric layer is applied. 400 conforming to the upper sections 324 (Channels) of the rib structures, side surfaces of the insulating structure, including the ILD layer 370 , the side wall spacers 348 and the dielectric layer 372 trained, as in Fig. 20 shown. Fig. 20 is the section view that follows the line Y1-Y1 from Fig. 19 corresponds to a source / drain region. 360 is also located under the ILD layer370 trained using ion implantation and / or epitaxy growth methods.

[0085] In some embodiments, the gate dielectric layer includes 400 One or more dielectric layers with a high k-value (e.g., with a dielectric constant greater than 3.9). The one or more gate dielectric layers can, for example, comprise one or more layers of a metal oxide or silicate of Hf, Al, Zr, combinations thereof, and multiple layers thereof. Other suitable materials include La, Mg, Ba, Ti, Pb, and Zr in the form of metal oxides, metal alloy oxides, and combinations thereof. Exemplary materials include MgOx, BaTixOy, BaSrxTiyOz, PbTixOy, PbZrxTiyOz, SiCN, SiON, SiN, Al₂O₃, La₂O₃, Ta₂O₃, Y₂O₃, HfO₂, ZrO₂, GeO₂, ZrO₂, HfZrO₂, Ga₂O₃, Gd₂O₃, TaSiO₂, and TiO₂. HfSiON, YGexOy, YSixOy, LaAlO3, and the like. The formation processes for the gate dielectric layer. 400These include molecular beam deposition (MBD), ALD, PVD, and the like. In some embodiments, the gate dielectric layer has... 400 a thickness of approximately 0.5 nm to approximately 5 nm.

[0086] In some embodiments, an interface layer (not shown) can be placed over the channels. 324 be formed before the gate dielectric layer 400 is formed, and the gate dielectric layer 400The interface layer forms above the interface layer. This interface layer helps to buffer the subsequently formed high k-value dielectric layer from the underlying semiconductor material. In some embodiments, the interface layer is a chemical silicon dioxide, which can be formed by chemical reactions. For example, a chemical silicon dioxide can be formed using deionized water + ozone (DIO3), NH4OH + H2O2 + H2O (APM), or other methods. Other embodiments may use a different material or process for the interface layer. In one embodiment, the interface layer has a thickness of approximately 0.2 nm to approximately 1 nm.

[0087] A working function setting metal layer (WFM layer) is then applied. 410 above the gate dielectric layer 400 trained, as in Fig. 21 shown.

[0088] The WFM layer 410It consists of one or more layers of conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FinFET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as the working function setting layer, and for the p-channel FinFET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as the working function setting layer.

[0089] The thickness and material of the WFM layer 410 can be used for the types (p or n) of FET and operating voltages are selected. If the thickness of the WFM layer 410 with regard to the aspect ratio of the gate space 390 If the WFM layer is small, it can be used. 410 conforming to the floor and sides of the gate room 90 , on which the gate dielectric layer400 is trained, to be trained, so that the gate room 90 not with the WFM layer 410 is filled, as in Fig. 21 shown. If the thickness of the WFM layer 410 with regard to the aspect ratio of the gate space 390 The WFM layer is high. 410 the gate room 390 , on which the dielectric layer 400 is trained.

[0090] Then a first conductive layer is formed. 415 for a first gate electrode (internal gate) for the NC- FET and a metal-gate electrode for ordinary use FET above the WFM layer 410 trained, as in the Fig. 22A and Fig. 22B shown. Fig. 22B is the section view that follows the line Y1 - Y1 from Fig. 22A corresponds to the first conductive layer. 415 fills the gate room 390 and can form above the insulating structure.

[0091] The conductive material for the first conductive structure 415 It comprises one or more materials selected from a group including W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, Zr, TiN, WN, TaN, Ru, alloys such as Ti-Al, Ru-Ta, Ru-Zr, Pt-Ti, Co-Ni, WNx, TiNx, MoNx, TaNx, and TaSiNy. In one embodiment, W is designated as the first conductive layer. 415 used. In some embodiments, the first conductive layer can 415 trained using a suitable process such as ALD, CVD, PVD, electroplating or combinations thereof.

[0092] A planarization process, such as a CMP, is then performed to remove excess material, as in Fig. 23 shown. This step creates a metal gate structure for the ordinary FET formed (with the exception of an insulating gate cover layer).

[0093] Then the structures for the ordinary FET through a layer of masks 395 covered, as in Fig. 24A shown, and the first conductive layer 415 , the WFM layer 410 and the gate dielectric layer 400 for the NC- FET are sunk by using an etching step, creating a sunken gate space 392 is trained, as in the Fig. 24A and Fig. 24B shown. Fig. 24B is the section view that follows the line Y -Y1 of Fig. 24A corresponds to the mask layer. 395 It could be a photoresist pattern or a hard mask pattern.

[0094] In some embodiments, the height H11 the remaining first conductive layer 415 from the canal 324 In some embodiments, the WFM layer is in a range of approximately 5 nm to approximately 50 nm. In certain embodiments, the WFM layer is... 410due to different etching rates, more than the first conductive layer 415 etched and the remaining first conductive layer 415 protrudes from the WFM layer 410 before. In certain embodiments, the gate dielectric layer 400 Not etched. After the sinking process, the mask layer 395 removed.

[0095] Then the ferroelectric layer is successively 420 , a conductive lining layer 425 and a second conductive layer 430 in the sunken gate room 392 trained, as in the Fig. 25A and Fig. 25B shown. Fig. 25B is the section view that follows the line Y -Y1 of Fig. 25A is equivalent.

[0096] The ferroelectric layer 420 can be formed by one of the methods mentioned above. The thickness of the ferroelectric layer 420In some embodiments, the wavelength lies in a range of approximately 1 nm to approximately 20 nm. As in Fig. As shown in 25B, the ferroelectric layer 420 In some embodiments, it is designed to conform to the standard.

[0097] The conductive lining layer 425 This is a cover layer or adhesive layer for the second conductive layer and is made, for example, of Ti, Ta, TiN and / or TaN. The thickness of the conductive lining layer 425 In some embodiments, the thickness lies in a range of approximately 0.5 nm to approximately 10 nm and can be formed by a suitable process such as ALD, CVD, PVD, electroplating, or combinations thereof. As in Fig. Figure 25B shows the conductive lining layer. 425 In some embodiments, it is designed to conform to the standard.

[0098] The second conductive layer 430 is made from the same or a similar material as the first conductive layer 415It is manufactured and can be formed by a suitable process such as ALD, CVD, PVD, electroplating, or combinations thereof. In one embodiment, W is designated as the second conductive layer. 430 used.

[0099] After the second conductive layer 430 A tempering process is carried out, whereby the phase of the ferroelectric layer is transformed from a polycrystalline structure to a crystalline structure, for example, an orthorhombic structure, which exhibits ferroelectricity. In some embodiments, the tempering process includes rapid thermal annealing (RTA), which is performed at a temperature between approximately 400 °C and approximately 900 °C.

[0100] A planarization process, such as a CMP, is then performed to remove excess materials, as described in the Fig. 26A and Fig. 26B shown. Fig. 26B is the section view that follows the line Y-Y1 of Fig. 26A corresponds to this step. This step involves removing the upper sections of the side wall spacers. 348 , the ESL layer 362 and the dielectric layer 372 exposed. The ferroelectric layer 420 and the conductive lining layer 425 , which are in the region of the ordinary FET They are removed by the planarization step.

[0101] Then a countersinking operation is performed, which increases the height of the gate structure for the NC fin- FET and the height of the gate structure for the ordinary FET be reduced and a second sunken gate room 394 is trained, as in the Fig. 27A and Fig. 27B shown.

[0102] Furthermore, as in the Fig. 28A and Fig. As shown in 28B, a gate top layer is applied after the immersion etching step. 440 in the second gate room394 designed to protect the gate electrodes during subsequent processes. In some embodiments, the gate cover layer includes 440 SiO2, SiCN, SiON, SiN, Al2O3, La2O3, SiN, a combination thereof or the like; however, other suitable dielectric films may be used. The gate cover layer 440 It can be formed using, for example, CVD, PVD, spin-on-glass, or the like. Other suitable process steps can be used. A planarization process, such as CMP, can be performed to remove excess material. During the planarization process, in some embodiments, the dielectric layer is also removed. 372 removed, as in the Fig. 28A and Fig. 28B shown. The thickness of the gate cover layer. 440 After the planarization process, in some embodiments the thickness lies in a range of approximately 5 nm to approximately 50 nm.

[0103] Fig. Figure 29A shows an exemplary cross-sectional view of a semiconductor device along the X -Direction according to some embodiments of the present disclosure. Fig. Figure 29B shows an exemplary sectional view of the NC-Fin- FET -section along the Y -direction and Fig. Figure 29C shows an exemplary sectional view of the section of the ordinary fin- FET along the Y -Direction according to some embodiments of the present disclosure.

[0104] As in Fig. As shown in 29A, the NC fin includes FET -Section a MIM structure, which is separated from the second conductive layer 430 , the conductive lining layer 425 , the ferroelectric layer 420 and the first conductive layer 415 is formed, together with a MOS structure that is formed by the first conductive layer 415 , the WFM layer 410, the gate dielectric layer 400 and the canal 324 is formed, while the section of the ordinary fin- FET only includes the MOS structure.

[0105] In the NC-Fin- FET In this section, the upper surface of the MIM structure is essentially flat, as shown in Fig. 29B shown. In other words, a base of the insulating gate cover layer. 440 is essentially flat, meaning that the variation is less than 1.0 nm.

[0106] The thickness H21 the WFM layer 410 above the channel (upper section of the rib structure) 324 varies depending on the type of NC- FET (Conductivity type and / or operating voltage) and in some embodiments lies in a range of approximately 0.5 nm to approximately 20 nm. The thickness H22 the first conductive layer 415 above the canal 324In some embodiments, the thickness ranges from approximately 5 nm to approximately 50 nm. H23 the ferroelectric layer 420 The thickness above the first conductive layer (internal gate) 415 is in some embodiments in a range of approximately 2 nm to approximately 20 nm. H24 the conductive lining layer 425 The thickness above the first conductive layer (internal gate) 415 is in some embodiments in a range of approximately 0.5 nm to approximately 10 nm. H25 the second conductive layer 430 above the canal 324 In some embodiments, the value lies in a range of approximately 5 nm to approximately 50 nm. In certain embodiments, H22 is greater than or equal to H25, and in other embodiments, H22 is less than H25.

[0107] In the section of ordinary finance FET is the height H26 of the metal gate (the first conductive layer) 415 and the WFM layer 410) above the channel (upper section of the rib structure) 324 in some embodiments in a range of about 10 nm to about 110 nm.

[0108] As in the Fig. 29B and Fig. 29C shows the gate dielectric layer 400 and the WFM layer 410 a “U-shape” in cross-section in Y -direction with a thin middle section and thick side sections, and as in Fig. 29A shows the gate dielectric layer 400 and the WFM layer 410 a “U-shape” between adjacent canals 324 and / or between the side wall spacer 348 and the canal 324 in cross-section in X -Direction up.

[0109] Furthermore, as in Fig. As shown in 19B, the ferroelectric layer 420 , the conductive lining layer 425 and the second conductive layer 430 a “U-shape” in cross-section inY -direction up, as in Fig. 29A shows the ferroelectric layer 420 , the conductive lining layer 425 and the second conductive layer 430 exhibit a "U-shape" between the side wall spacers 348 in cross-section in X -direction on, although Fig. 29A shows only one end section of the U-shape.

[0110] After the formation of the gate top layer 440 , so that they are in direct contact with the second conductive layer 430 for the NC- FET and with the first conductive layer 415 for the ordinary FET If this is the case, further CMOS processes are carried out to form various features, such as additional interdielectric layers, contacts / vias, interconnect metal layers and passivation layers, etc.

[0111] It will be understood that not all advantages have necessarily been discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer other advantages.

[0112] In the present disclosure, for example, it is possible to maximize stress effects and stabilize a ferroelectric property, since the ferroelectric layer comprises a crystalline phase in an amorphous matrix. Furthermore, it is possible to optimize operational properties of NCFET to improve.

[0113] According to one aspect of the present disclosure, in a method for producing a structure with negative capacitance, a ferroelectric dielectric layer is formed over a first conductive layer arranged over a substrate. A second conductive layer is formed over the dielectric layer. The ferroelectric dielectric layer comprises an amorphous layer and crystals. In one or more of the preceding and following embodiments, the amorphous layer and the crystals are made of the same material, including HfO2 and an oxide of a metallic element, wherein the metallic element is one or more from the group consisting of Zr, Al, La, Y, Gd and Sr are selected. In one or more of the preceding and following embodiments, the ferroelectric dielectric layer is formed by an atomic layer deposition (ALD) process at a substrate temperature in the range of 100 °C to 300 °C. In one or more of the preceding and following embodiments, a tempering step is performed after the ferroelectric dielectric layer has been formed by an ALD process. In one or more of the preceding and following embodiments, the crystals are nanocrystals dispersed in the amorphous layer. In one or more of the preceding and following embodiments, the average size of the nanocrystals is in the range of 0.5 nm to 5 nm.In one or more of the preceding and following embodiments, the crystals have a stem-like shape extending along a film stack direction and embedded in the amorphous layer. In one or more of the preceding and following embodiments, the average diameter of the stem-like shape is in the range of 0.5 nm to 5 nm. In one or more of the preceding and following embodiments, the average length of the stem-like shape is in the range of 1 nm to 5 nm. In one or more of the preceding and following embodiments, the stem-like crystals are located closer to the first conductive layer, such that the density of the crystals in the ferroelectric layer is greater in a region closer to the first conductive layer than in a region closer to the second conductive layer.In one or more of the preceding and following embodiments, the ferroelectric dielectric layer is formed by the following method. The columnar-shaped crystals are formed over the first conductive layer, and the amorphous layer is formed over the columnar-shaped crystals. In one or more of the preceding and following embodiments, the columnar-shaped crystals are located closer to the second conductive layer, such that the crystal density in the ferroelectric layer is greater in a region closer to the second conductive layer than in a region closer to the first conductive layer. In one or more of the preceding and following embodiments, the ferroelectric dielectric layer is formed by the following method. A first amorphous layer is formed over the first conductive layer.The columnar-shaped crystals form over a first amorphous layer. A second amorphous layer forms after the columnar-shaped crystals have formed.

[0114] According to another aspect of the present disclosure, in a process for producing a structure with negative capacitance, a ferroelectric dielectric layer is formed over a first conductive layer arranged over a substrate. A second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer is formed by the following process. An amorphous oxide layer is formed over the first conductive layer. A metal layer is formed over the amorphous oxide layer. The substrate is annealed such that metal elements from the metal layer diffuse into the amorphous layer. In one or more of the preceding and following embodiments, the amorphous layer and the amorphous oxide layer comprise HfO2, and the metal element comprises one or more elements from the group consisting of Zr, Al, La, Y, Gd and Sr are selected. In one or more of the preceding and following embodiments, the tempering is carried out at a substrate temperature in the range of 300 to 600 °C.

[0115] According to another aspect of the present disclosure, in a method for producing a structure with negative capacitance, a ferroelectric dielectric layer is formed over a first conductive layer arranged over a substrate. A second conductive layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer is formed by the following method. An amorphous oxide layer is formed over the first conductive layer. The amorphous oxide layer is an oxygen-deficient oxide. The amorphous oxide layer is annealed in an oxygen-containing atmosphere. In one or more of the preceding and following embodiments, the amorphous oxide layer comprises HfO2- x , where 0 < x ≤ 0.8, and further contains one or more components from the group consisting of Zr, Al, La, Y, Gd and Sr are selected. In one or more of the preceding and following embodiments, the annealing is carried out at a substrate temperature in the range of 400 to 800 °C. In one or more of the preceding and following embodiments, the first conductive layer comprises SiGe.

[0116] According to another aspect of the present disclosure, a method for manufacturing a field-effect transistor with negative capacitance (NC- FET A ferroelectric dielectric layer is formed over the ferroelectric dielectric layer, and a gate electrode layer is formed over the ferroelectric dielectric layer. The ferroelectric dielectric layer comprises an amorphous layer and crystals.

[0117] According to one aspect of the present disclosure, a negative-capacitance structure comprises a first conductive layer, a ferroelectric dielectric layer arranged over the first conductive layer, and a second conductive layer arranged over the ferroelectric dielectric layer. The ferroelectric dielectric layer comprises an amorphous layer and crystals. In one or more of the preceding and following embodiments, the amorphous layer and the crystals are made of the same material, including HfO2 and an oxide of a metallic element, wherein the metallic element is one or more from the group consisting of Zr, Al, La, Y, Gd and Sr are selected. In one or more of the preceding and following embodiments, the crystals are nanocrystals distributed within the amorphous layer. In one or more of the preceding and following embodiments, the average size of the nanocrystals is in the range of 0.5 nm to 5 nm. In one or more of the preceding and following embodiments, the crystals have a columnar shape extending along a film stacking direction and embedded in the amorphous layer. In one or more of the preceding and following embodiments, the average diameter of the columnar shape is in the range of 0.5 nm to 5 nm. In one or more of the preceding and following embodiments, the average length of the columnar shape is in the range of 1 nm to 5 nm.In one or more of the preceding and following embodiments, the columnar-shaped crystals are located closer to the first conductive layer, such that the crystal density in the ferroelectric layer is greater in a region closer to the first conductive layer than in a region closer to the second conductive layer. In one or more of the preceding and following embodiments, the amorphous layer and the crystals are made of HfZrO₂.

[0118] According to another aspect of the present disclosure, a field-effect transistor with negative capacitance (NC- FET ) a channel layer made of a semiconductor, a ferroelectric dielectric layer arranged over the channel layer, and a gate electrode layer arranged over the ferroelectric dielectric layer. The ferroelectric dielectric layer comprises an amorphous layer and crystals. In one or more of the preceding and following embodiments, the amorphous layer and the crystals are made of the same material, including HfO2 and an oxide of a metallic element, wherein the metallic element is one or more from the group consisting of Zr, Al, La, Y, Gd and Sr are selected. In one or more of the preceding and following embodiments, the crystals are nanocrystals distributed within the amorphous layer. In one or more of the preceding and following embodiments, the crystals have a columnar shape extending along a film stacking direction and embedded in the amorphous layer. In one or more of the preceding and following embodiments, the columnar-shaped crystals are located closer to the channel layer, such that the density of the crystals in the ferroelectric layer is greater in a region closer to the channel layer than in a region closer to the gate electrode layer.In one or more of the preceding and following embodiments, the columnar-shaped crystals are located closer to the gate electrode layer, such that the crystal density in the ferroelectric layer is greater in a region closer to the gate electrode layer than in a region closer to the channel layer. In one or more of the preceding and following embodiments, the channel layer comprises SiGe. In one or more of the preceding and following embodiments, the gate electrode layer comprises a first conductive layer arranged on the ferroelectric dielectric layer, and the first conductive layer is made of TiN or TiN doped with one or more elements.In one or more of the foregoing and following embodiments, the gate electrode layer further comprises a second conductive layer arranged on top of the first conductive layer, and the second conductive layer is made of TaN.

[0119] According to another aspect of the present disclosure, a field-effect transistor with negative capacitance (NC- FET ) a channel layer made of a semiconductor, a first dielectric layer arranged over the channel layer, a first conductive layer arranged over the first dielectric layer, a second dielectric layer arranged over the first conductive layer, and a gate electrode layer arranged over the second dielectric layer. The second dielectric layer includes a compressed oxide of hafnium and a metallic element. X , whereby Xwhich is one or more of the group consisting of Zr, Al, La, Y , Gd and Sr are selected.

[0120] The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also understand that such equivalent designs do not deviate from the meaning and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications herein without deviating from the meaning and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62552900

[0001]

Claims

[1] Method for producing a structure with negative capacity, the method comprising: Forming a ferroelectric dielectric layer over a first conductive layer arranged over a substrate; and Formation of a second conductive layer above the ferroelectric dielectric layer, wherein the ferroelectric dielectric layer includes an amorphous layer and crystals. [2] Method according to claim 1, wherein the amorphous layer and the crystals are made from the same material, including HfO2 and an oxide of a metallic element, wherein the metallic element is one or more selected from the group consisting of Zr, Al, La, Y, G and Sr. [3] Method according to claim 1 or 2, wherein the ferroelectric dielectric layer is formed by an atomic layer deposition (ALD) process at a substrate temperature in a range of 100 °C to 300 °C. [4] Method according to claim 3, wherein a tempering work step is carried out after the ferroelectric dielectric layer has been formed by an ALD process. [5] Method according to any of the preceding claims, wherein the crystals are nanocrystals distributed in the amorphous layer. [6] Method according to claim 5, wherein the average size of the nanocrystals is in the range of 0.5 nm to 5 nm. [7] Method according to any of the preceding claims, wherein the crystals have a column shape extending along a film stacking direction and are embedded in the amorphous layer. [8] Method according to claim 7, wherein an average diameter of the stem shape is in a range of 0.5 nm to 5 nm. [9] Method according to claim 7 or 8, wherein the average length of the stem shape is in the range of 1 nm to 5 nm. [10] Method according to any one of the preceding claims 7 to 9, wherein the columnar-shaped crystals are located closer to the first conductive layer, such that the density of the crystals in the ferroelectric layer is greater in a region closer to the first conductive layer than in a region closer to the second conductive layer. [11] Method according to claim 10, wherein the ferroelectric dielectric layer is formed by: Formation of the crystals with a columnar shape above the first conductive layer and Formation of the amorphous layer over the crystals with a stem shape. [12] Method according to any one of the preceding claims 7 to 9, wherein the columnar-shaped crystals are located closer to the second conductive layer, such that the density of the crystals in the ferroelectric layer is greater in a region closer to the second conductive layer than in a region closer to the first conductive layer. [13] Method according to claim 12, wherein the ferroelectric dielectric layer is formed by: Formation of a first amorphous layer above the first conductive layer; Formation of the crystals with a columnar shape above a first amorphous layer and Formation of a second amorphous layer after the crystals have formed with a stem shape. [14] Method for producing a structure with negative capacity, the method comprising: Forming a ferroelectric dielectric layer over a first conductive layer arranged over a substrate; and Formation of a second conductive layer above the ferroelectric dielectric layer, the ferroelectric dielectric layer is formed by: Formation of an amorphous oxide layer over the first conductive layer; Formation of a metal layer over the amorphous oxide layer and Tempering the substrate so that metallic elements from the metal layer diffuse into the amorphous layer. [15] Method according to claim 14, wherein the amorphous layer and the amorphous oxide layer comprise HfO2 and an oxide and the metal element comprises one or more selected from the group consisting of Zr, Al, La, Y, G and Sr. [16] Method according to claim 14 or 15, wherein the tempering is carried out at a substrate temperature in a range of 300 °C to 600 °C. [17] Structure with negative capacity, comprising: a first conductive layer; a ferroelectric dielectric layer arranged above the first conductive layer; and a second conductive layer arranged above the ferroelectric dielectric layer, wherein the ferroelectric dielectric layer includes an amorphous layer and crystals. [18] Structure with negative capacity according to claim 17, wherein the amorphous layer and the crystals are made of the same material, including HfO2 and an oxide of a metal element, wherein the metal element is one or more selected from the group consisting of Zr, Al, La, Y, G and Sr. [19] Structure with negative capacity according to claim 17 or 18, wherein the crystals are nanocrystals distributed in the amorphous layer. [20] Structure with negative capacity according to any one of the preceding claims 17 to 19, wherein the crystals have a column shape extending along a film stacking direction and are embedded in the amorphous layer.

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